140 changes: 138 additions & 2 deletions llvm/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -322,7 +322,7 @@ body: |
...
---
name: ashr_v4i64
name: ashr_v2i64
alignment: 4
legalized: true
regBankSelected: true
Expand All @@ -336,7 +336,7 @@ body: |
bb.1:
liveins: $q0, $q1
; CHECK-LABEL: name: ashr_v4i64
; CHECK-LABEL: name: ashr_v2i64
; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
Expand Down Expand Up @@ -372,3 +372,139 @@ body: |
$d0 = COPY %2(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: lshr_v4i16
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $d0, $d1
; CHECK-LABEL: name: lshr_v4i16
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[NEGv4i16_:%[0-9]+]]:fpr64 = NEGv4i16 [[COPY1]]
; CHECK: [[USHLv4i16_:%[0-9]+]]:fpr64 = USHLv4i16 [[COPY]], [[NEGv4i16_]]
; CHECK: $d0 = COPY [[USHLv4i16_]]
; CHECK: RET_ReallyLR implicit $d0
%0:fpr(<4 x s16>) = COPY $d0
%1:fpr(<4 x s16>) = COPY $d1
%2:fpr(<4 x s16>) = G_LSHR %0, %1(<4 x s16>)
$d0 = COPY %2(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: lshr_v4i32
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
machineFunctionInfo: {}
body: |
bb.1:
liveins: $q0, $q1
; CHECK-LABEL: name: lshr_v4i32
; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[NEGv4i32_:%[0-9]+]]:fpr128 = NEGv4i32 [[COPY1]]
; CHECK: [[USHLv4i32_:%[0-9]+]]:fpr128 = USHLv4i32 [[COPY]], [[NEGv4i32_]]
; CHECK: $q0 = COPY [[USHLv4i32_]]
; CHECK: RET_ReallyLR implicit $q0
%0:fpr(<4 x s32>) = COPY $q0
%1:fpr(<4 x s32>) = COPY $q1
%2:fpr(<4 x s32>) = G_LSHR %0, %1(<4 x s32>)
$q0 = COPY %2(<4 x s32>)
RET_ReallyLR implicit $q0
...
---
name: lshr_v8i16
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $q0, $q1
; CHECK-LABEL: name: lshr_v8i16
; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[NEGv8i16_:%[0-9]+]]:fpr128 = NEGv8i16 [[COPY1]]
; CHECK: [[USHLv8i16_:%[0-9]+]]:fpr128 = USHLv8i16 [[COPY]], [[NEGv8i16_]]
; CHECK: $q0 = COPY [[USHLv8i16_]]
; CHECK: RET_ReallyLR implicit $q0
%0:fpr(<8 x s16>) = COPY $q0
%1:fpr(<8 x s16>) = COPY $q1
%2:fpr(<8 x s16>) = G_LSHR %0, %1(<8 x s16>)
$q0 = COPY %2(<8 x s16>)
RET_ReallyLR implicit $q0
...
---
name: ashr_v4i16
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $d0, $d1
; CHECK-LABEL: name: ashr_v4i16
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[NEGv4i16_:%[0-9]+]]:fpr64 = NEGv4i16 [[COPY1]]
; CHECK: [[SSHLv4i16_:%[0-9]+]]:fpr64 = SSHLv4i16 [[COPY]], [[NEGv4i16_]]
; CHECK: $d0 = COPY [[SSHLv4i16_]]
; CHECK: RET_ReallyLR implicit $d0
%0:fpr(<4 x s16>) = COPY $d0
%1:fpr(<4 x s16>) = COPY $d1
%2:fpr(<4 x s16>) = G_ASHR %0, %1(<4 x s16>)
$d0 = COPY %2(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: vashr_v4i16_imm
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $d0, $d1
; CHECK-LABEL: name: vashr_v4i16_imm
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[SSHRv4i16_shift:%[0-9]+]]:fpr64 = SSHRv4i16_shift [[COPY]], 5
; CHECK: $d0 = COPY [[SSHRv4i16_shift]]
; CHECK: RET_ReallyLR implicit $d0
%0:fpr(<4 x s16>) = COPY $d0
%1:gpr(s32) = G_CONSTANT i32 5
%2:fpr(<4 x s16>) = G_VASHR %0, %1
$d0 = COPY %2(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: vlshr_v4i16_imm
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $d0, $d1
; CHECK-LABEL: name: vlshr_v4i16_imm
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[USHRv4i16_shift:%[0-9]+]]:fpr64 = USHRv4i16_shift [[COPY]], 5
; CHECK: $d0 = COPY [[USHRv4i16_shift]]
; CHECK: RET_ReallyLR implicit $d0
%0:fpr(<4 x s16>) = COPY $d0
%1:gpr(s32) = G_CONSTANT i32 5
%2:fpr(<4 x s16>) = G_VLSHR %0, %1
$d0 = COPY %2(<4 x s16>)
RET_ReallyLR implicit $d0
...