32 changes: 16 additions & 16 deletions llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -1104,7 +1104,7 @@ define void @cmpxchg_i16_monotonic_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounw
; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: addi a4, a4, -1
; RV64IA-NEXT: sllw a5, a4, a0
; RV64IA-NEXT: and a1, a1, a4
; RV64IA-NEXT: sllw a1, a1, a0
Expand Down Expand Up @@ -1206,7 +1206,7 @@ define void @cmpxchg_i16_acquire_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin
; RV64IA-WMO-NEXT: andi a3, a0, -4
; RV64IA-WMO-NEXT: slli a0, a0, 3
; RV64IA-WMO-NEXT: lui a4, 16
; RV64IA-WMO-NEXT: addiw a4, a4, -1
; RV64IA-WMO-NEXT: addi a4, a4, -1
; RV64IA-WMO-NEXT: sllw a5, a4, a0
; RV64IA-WMO-NEXT: and a1, a1, a4
; RV64IA-WMO-NEXT: sllw a1, a1, a0
Expand All @@ -1230,7 +1230,7 @@ define void @cmpxchg_i16_acquire_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin
; RV64IA-TSO-NEXT: andi a3, a0, -4
; RV64IA-TSO-NEXT: slli a0, a0, 3
; RV64IA-TSO-NEXT: lui a4, 16
; RV64IA-TSO-NEXT: addiw a4, a4, -1
; RV64IA-TSO-NEXT: addi a4, a4, -1
; RV64IA-TSO-NEXT: sllw a5, a4, a0
; RV64IA-TSO-NEXT: and a1, a1, a4
; RV64IA-TSO-NEXT: sllw a1, a1, a0
Expand Down Expand Up @@ -1332,7 +1332,7 @@ define void @cmpxchg_i16_acquire_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind
; RV64IA-WMO-NEXT: andi a3, a0, -4
; RV64IA-WMO-NEXT: slli a0, a0, 3
; RV64IA-WMO-NEXT: lui a4, 16
; RV64IA-WMO-NEXT: addiw a4, a4, -1
; RV64IA-WMO-NEXT: addi a4, a4, -1
; RV64IA-WMO-NEXT: sllw a5, a4, a0
; RV64IA-WMO-NEXT: and a1, a1, a4
; RV64IA-WMO-NEXT: sllw a1, a1, a0
Expand All @@ -1356,7 +1356,7 @@ define void @cmpxchg_i16_acquire_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind
; RV64IA-TSO-NEXT: andi a3, a0, -4
; RV64IA-TSO-NEXT: slli a0, a0, 3
; RV64IA-TSO-NEXT: lui a4, 16
; RV64IA-TSO-NEXT: addiw a4, a4, -1
; RV64IA-TSO-NEXT: addi a4, a4, -1
; RV64IA-TSO-NEXT: sllw a5, a4, a0
; RV64IA-TSO-NEXT: and a1, a1, a4
; RV64IA-TSO-NEXT: sllw a1, a1, a0
Expand Down Expand Up @@ -1458,7 +1458,7 @@ define void @cmpxchg_i16_release_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin
; RV64IA-WMO-NEXT: andi a3, a0, -4
; RV64IA-WMO-NEXT: slli a0, a0, 3
; RV64IA-WMO-NEXT: lui a4, 16
; RV64IA-WMO-NEXT: addiw a4, a4, -1
; RV64IA-WMO-NEXT: addi a4, a4, -1
; RV64IA-WMO-NEXT: sllw a5, a4, a0
; RV64IA-WMO-NEXT: and a1, a1, a4
; RV64IA-WMO-NEXT: sllw a1, a1, a0
Expand All @@ -1482,7 +1482,7 @@ define void @cmpxchg_i16_release_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin
; RV64IA-TSO-NEXT: andi a3, a0, -4
; RV64IA-TSO-NEXT: slli a0, a0, 3
; RV64IA-TSO-NEXT: lui a4, 16
; RV64IA-TSO-NEXT: addiw a4, a4, -1
; RV64IA-TSO-NEXT: addi a4, a4, -1
; RV64IA-TSO-NEXT: sllw a5, a4, a0
; RV64IA-TSO-NEXT: and a1, a1, a4
; RV64IA-TSO-NEXT: sllw a1, a1, a0
Expand Down Expand Up @@ -1584,7 +1584,7 @@ define void @cmpxchg_i16_release_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind
; RV64IA-WMO-NEXT: andi a3, a0, -4
; RV64IA-WMO-NEXT: slli a0, a0, 3
; RV64IA-WMO-NEXT: lui a4, 16
; RV64IA-WMO-NEXT: addiw a4, a4, -1
; RV64IA-WMO-NEXT: addi a4, a4, -1
; RV64IA-WMO-NEXT: sllw a5, a4, a0
; RV64IA-WMO-NEXT: and a1, a1, a4
; RV64IA-WMO-NEXT: sllw a1, a1, a0
Expand All @@ -1608,7 +1608,7 @@ define void @cmpxchg_i16_release_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind
; RV64IA-TSO-NEXT: andi a3, a0, -4
; RV64IA-TSO-NEXT: slli a0, a0, 3
; RV64IA-TSO-NEXT: lui a4, 16
; RV64IA-TSO-NEXT: addiw a4, a4, -1
; RV64IA-TSO-NEXT: addi a4, a4, -1
; RV64IA-TSO-NEXT: sllw a5, a4, a0
; RV64IA-TSO-NEXT: and a1, a1, a4
; RV64IA-TSO-NEXT: sllw a1, a1, a0
Expand Down Expand Up @@ -1710,7 +1710,7 @@ define void @cmpxchg_i16_acq_rel_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin
; RV64IA-WMO-NEXT: andi a3, a0, -4
; RV64IA-WMO-NEXT: slli a0, a0, 3
; RV64IA-WMO-NEXT: lui a4, 16
; RV64IA-WMO-NEXT: addiw a4, a4, -1
; RV64IA-WMO-NEXT: addi a4, a4, -1
; RV64IA-WMO-NEXT: sllw a5, a4, a0
; RV64IA-WMO-NEXT: and a1, a1, a4
; RV64IA-WMO-NEXT: sllw a1, a1, a0
Expand All @@ -1734,7 +1734,7 @@ define void @cmpxchg_i16_acq_rel_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin
; RV64IA-TSO-NEXT: andi a3, a0, -4
; RV64IA-TSO-NEXT: slli a0, a0, 3
; RV64IA-TSO-NEXT: lui a4, 16
; RV64IA-TSO-NEXT: addiw a4, a4, -1
; RV64IA-TSO-NEXT: addi a4, a4, -1
; RV64IA-TSO-NEXT: sllw a5, a4, a0
; RV64IA-TSO-NEXT: and a1, a1, a4
; RV64IA-TSO-NEXT: sllw a1, a1, a0
Expand Down Expand Up @@ -1836,7 +1836,7 @@ define void @cmpxchg_i16_acq_rel_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind
; RV64IA-WMO-NEXT: andi a3, a0, -4
; RV64IA-WMO-NEXT: slli a0, a0, 3
; RV64IA-WMO-NEXT: lui a4, 16
; RV64IA-WMO-NEXT: addiw a4, a4, -1
; RV64IA-WMO-NEXT: addi a4, a4, -1
; RV64IA-WMO-NEXT: sllw a5, a4, a0
; RV64IA-WMO-NEXT: and a1, a1, a4
; RV64IA-WMO-NEXT: sllw a1, a1, a0
Expand All @@ -1860,7 +1860,7 @@ define void @cmpxchg_i16_acq_rel_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind
; RV64IA-TSO-NEXT: andi a3, a0, -4
; RV64IA-TSO-NEXT: slli a0, a0, 3
; RV64IA-TSO-NEXT: lui a4, 16
; RV64IA-TSO-NEXT: addiw a4, a4, -1
; RV64IA-TSO-NEXT: addi a4, a4, -1
; RV64IA-TSO-NEXT: sllw a5, a4, a0
; RV64IA-TSO-NEXT: and a1, a1, a4
; RV64IA-TSO-NEXT: sllw a1, a1, a0
Expand Down Expand Up @@ -1938,7 +1938,7 @@ define void @cmpxchg_i16_seq_cst_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin
; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: addi a4, a4, -1
; RV64IA-NEXT: sllw a5, a4, a0
; RV64IA-NEXT: and a1, a1, a4
; RV64IA-NEXT: sllw a1, a1, a0
Expand Down Expand Up @@ -2016,7 +2016,7 @@ define void @cmpxchg_i16_seq_cst_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind
; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: addi a4, a4, -1
; RV64IA-NEXT: sllw a5, a4, a0
; RV64IA-NEXT: and a1, a1, a4
; RV64IA-NEXT: sllw a1, a1, a0
Expand Down Expand Up @@ -2094,7 +2094,7 @@ define void @cmpxchg_i16_seq_cst_seq_cst(ptr %ptr, i16 %cmp, i16 %val) nounwind
; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: addi a4, a4, -1
; RV64IA-NEXT: sllw a5, a4, a0
; RV64IA-NEXT: and a1, a1, a4
; RV64IA-NEXT: sllw a1, a1, a0
Expand Down
182 changes: 91 additions & 91 deletions llvm/test/CodeGen/RISCV/atomic-rmw.ll
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22 changes: 11 additions & 11 deletions llvm/test/CodeGen/RISCV/atomic-signext.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -1207,7 +1207,7 @@ define signext i16 @atomicrmw_xchg_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: addi a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0
Expand Down Expand Up @@ -1281,7 +1281,7 @@ define signext i16 @atomicrmw_add_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: addi a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0
Expand Down Expand Up @@ -1355,7 +1355,7 @@ define signext i16 @atomicrmw_sub_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: addi a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0
Expand Down Expand Up @@ -1423,7 +1423,7 @@ define signext i16 @atomicrmw_and_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: addi a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: not a4, a4
; RV64IA-NEXT: and a1, a1, a3
Expand Down Expand Up @@ -1492,7 +1492,7 @@ define signext i16 @atomicrmw_nand_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: addi a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0
Expand Down Expand Up @@ -1748,7 +1748,7 @@ define signext i16 @atomicrmw_max_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: addi a4, a4, -1
; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: slli a1, a1, 48
; RV64IA-NEXT: srai a1, a1, 48
Expand Down Expand Up @@ -1904,7 +1904,7 @@ define signext i16 @atomicrmw_min_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: addi a4, a4, -1
; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: slli a1, a1, 48
; RV64IA-NEXT: srai a1, a1, 48
Expand Down Expand Up @@ -2057,7 +2057,7 @@ define signext i16 @atomicrmw_umax_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: addi a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0
Expand Down Expand Up @@ -2205,7 +2205,7 @@ define signext i16 @atomicrmw_umin_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: addi a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0
Expand Down Expand Up @@ -3969,7 +3969,7 @@ define signext i16 @cmpxchg_i16_monotonic_monotonic_val0(ptr %ptr, i16 signext %
; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: addi a4, a4, -1
; RV64IA-NEXT: sllw a5, a4, a0
; RV64IA-NEXT: and a1, a1, a4
; RV64IA-NEXT: sllw a1, a1, a0
Expand Down Expand Up @@ -4054,7 +4054,7 @@ define i1 @cmpxchg_i16_monotonic_monotonic_val1(ptr %ptr, i16 signext %cmp, i16
; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: addi a4, a4, -1
; RV64IA-NEXT: sllw a5, a4, a0
; RV64IA-NEXT: and a1, a1, a4
; RV64IA-NEXT: sllw a1, a1, a0
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -140,7 +140,7 @@ define i8 @atomicrmw_uinc_wrap_i8(ptr %ptr, i8 %val) {
; RV64IA-NEXT: srlw a5, a3, a0
; RV64IA-NEXT: sext.w a6, a3
; RV64IA-NEXT: andi a7, a5, 255
; RV64IA-NEXT: addiw a5, a5, 1
; RV64IA-NEXT: addi a5, a5, 1
; RV64IA-NEXT: sltu a7, a7, a1
; RV64IA-NEXT: negw a7, a7
; RV64IA-NEXT: and a5, a7, a5
Expand Down Expand Up @@ -304,7 +304,7 @@ define i16 @atomicrmw_uinc_wrap_i16(ptr %ptr, i16 %val) {
; RV64IA-NEXT: srlw a6, a4, a0
; RV64IA-NEXT: sext.w a7, a4
; RV64IA-NEXT: and t0, a6, a3
; RV64IA-NEXT: addiw a6, a6, 1
; RV64IA-NEXT: addi a6, a6, 1
; RV64IA-NEXT: sltu t0, t0, a1
; RV64IA-NEXT: negw t0, t0
; RV64IA-NEXT: and a6, a6, a3
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/bfloat-convert.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -404,7 +404,7 @@ define i32 @fcvt_wu_bf16_sat(bfloat %a) nounwind {
; CHECK64ZFBFMIN-NEXT: fcvt.wu.s a0, fa5, rtz
; CHECK64ZFBFMIN-NEXT: feq.s a1, fa5, fa5
; CHECK64ZFBFMIN-NEXT: seqz a1, a1
; CHECK64ZFBFMIN-NEXT: addiw a1, a1, -1
; CHECK64ZFBFMIN-NEXT: addi a1, a1, -1
; CHECK64ZFBFMIN-NEXT: and a0, a0, a1
; CHECK64ZFBFMIN-NEXT: slli a0, a0, 32
; CHECK64ZFBFMIN-NEXT: srli a0, a0, 32
Expand All @@ -420,7 +420,7 @@ define i32 @fcvt_wu_bf16_sat(bfloat %a) nounwind {
; RV64ID-NEXT: fcvt.wu.s a0, fa5, rtz
; RV64ID-NEXT: feq.s a1, fa5, fa5
; RV64ID-NEXT: seqz a1, a1
; RV64ID-NEXT: addiw a1, a1, -1
; RV64ID-NEXT: addi a1, a1, -1
; RV64ID-NEXT: and a0, a0, a1
; RV64ID-NEXT: slli a0, a0, 32
; RV64ID-NEXT: srli a0, a0, 32
Expand Down Expand Up @@ -1722,7 +1722,7 @@ define zeroext i32 @fcvt_wu_bf16_sat_zext(bfloat %a) nounwind {
; CHECK64ZFBFMIN-NEXT: fcvt.wu.s a0, fa5, rtz
; CHECK64ZFBFMIN-NEXT: feq.s a1, fa5, fa5
; CHECK64ZFBFMIN-NEXT: seqz a1, a1
; CHECK64ZFBFMIN-NEXT: addiw a1, a1, -1
; CHECK64ZFBFMIN-NEXT: addi a1, a1, -1
; CHECK64ZFBFMIN-NEXT: and a0, a0, a1
; CHECK64ZFBFMIN-NEXT: slli a0, a0, 32
; CHECK64ZFBFMIN-NEXT: srli a0, a0, 32
Expand All @@ -1738,7 +1738,7 @@ define zeroext i32 @fcvt_wu_bf16_sat_zext(bfloat %a) nounwind {
; RV64ID-NEXT: fcvt.wu.s a0, fa5, rtz
; RV64ID-NEXT: feq.s a1, fa5, fa5
; RV64ID-NEXT: seqz a1, a1
; RV64ID-NEXT: addiw a1, a1, -1
; RV64ID-NEXT: addi a1, a1, -1
; RV64ID-NEXT: and a0, a0, a1
; RV64ID-NEXT: slli a0, a0, 32
; RV64ID-NEXT: srli a0, a0, 32
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/bfloat.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -367,7 +367,7 @@ define bfloat @bfloat_add(bfloat %a, bfloat %b) nounwind {
; RV64ID-LP64-NEXT: addi sp, sp, -16
; RV64ID-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64ID-LP64-NEXT: lui a2, 16
; RV64ID-LP64-NEXT: addiw a2, a2, -1
; RV64ID-LP64-NEXT: addi a2, a2, -1
; RV64ID-LP64-NEXT: and a0, a0, a2
; RV64ID-LP64-NEXT: and a1, a1, a2
; RV64ID-LP64-NEXT: slli a1, a1, 16
Expand Down Expand Up @@ -409,7 +409,7 @@ define bfloat @bfloat_add(bfloat %a, bfloat %b) nounwind {
; RV64ID-LP64D-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64ID-LP64D-NEXT: fmv.x.w a0, fa0
; RV64ID-LP64D-NEXT: lui a1, 16
; RV64ID-LP64D-NEXT: addiw a1, a1, -1
; RV64ID-LP64D-NEXT: addi a1, a1, -1
; RV64ID-LP64D-NEXT: and a0, a0, a1
; RV64ID-LP64D-NEXT: fmv.x.w a2, fa1
; RV64ID-LP64D-NEXT: and a1, a2, a1
Expand Down Expand Up @@ -605,7 +605,7 @@ define void @bfloat_store(ptr %a, bfloat %b, bfloat %c) nounwind {
; RV64ID-LP64-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64ID-LP64-NEXT: mv s0, a0
; RV64ID-LP64-NEXT: lui a0, 16
; RV64ID-LP64-NEXT: addiw a0, a0, -1
; RV64ID-LP64-NEXT: addi a0, a0, -1
; RV64ID-LP64-NEXT: and a1, a1, a0
; RV64ID-LP64-NEXT: and a0, a2, a0
; RV64ID-LP64-NEXT: slli a0, a0, 16
Expand Down Expand Up @@ -652,7 +652,7 @@ define void @bfloat_store(ptr %a, bfloat %b, bfloat %c) nounwind {
; RV64ID-LP64D-NEXT: mv s0, a0
; RV64ID-LP64D-NEXT: fmv.x.w a0, fa0
; RV64ID-LP64D-NEXT: lui a1, 16
; RV64ID-LP64D-NEXT: addiw a1, a1, -1
; RV64ID-LP64D-NEXT: addi a1, a1, -1
; RV64ID-LP64D-NEXT: and a0, a0, a1
; RV64ID-LP64D-NEXT: fmv.x.w a2, fa1
; RV64ID-LP64D-NEXT: and a1, a2, a1
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/bittest.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -266,7 +266,7 @@ define i1 @bittest_constant_by_var_shr_i32(i32 signext %b) nounwind {
; RV64I-LABEL: bittest_constant_by_var_shr_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 301408
; RV64I-NEXT: addiw a1, a1, 722
; RV64I-NEXT: addi a1, a1, 722
; RV64I-NEXT: srlw a0, a1, a0
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: ret
Expand Down Expand Up @@ -296,7 +296,7 @@ define i1 @bittest_constant_by_var_shr_i32(i32 signext %b) nounwind {
; RV64XTHEADBS-LABEL: bittest_constant_by_var_shr_i32:
; RV64XTHEADBS: # %bb.0:
; RV64XTHEADBS-NEXT: lui a1, 301408
; RV64XTHEADBS-NEXT: addiw a1, a1, 722
; RV64XTHEADBS-NEXT: addi a1, a1, 722
; RV64XTHEADBS-NEXT: srlw a0, a1, a0
; RV64XTHEADBS-NEXT: andi a0, a0, 1
; RV64XTHEADBS-NEXT: ret
Expand All @@ -319,7 +319,7 @@ define i1 @bittest_constant_by_var_shl_i32(i32 signext %b) nounwind {
; RV64I-LABEL: bittest_constant_by_var_shl_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 301408
; RV64I-NEXT: addiw a1, a1, 722
; RV64I-NEXT: addi a1, a1, 722
; RV64I-NEXT: srlw a0, a1, a0
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: ret
Expand Down Expand Up @@ -349,7 +349,7 @@ define i1 @bittest_constant_by_var_shl_i32(i32 signext %b) nounwind {
; RV64XTHEADBS-LABEL: bittest_constant_by_var_shl_i32:
; RV64XTHEADBS: # %bb.0:
; RV64XTHEADBS-NEXT: lui a1, 301408
; RV64XTHEADBS-NEXT: addiw a1, a1, 722
; RV64XTHEADBS-NEXT: addi a1, a1, 722
; RV64XTHEADBS-NEXT: srlw a0, a1, a0
; RV64XTHEADBS-NEXT: andi a0, a0, 1
; RV64XTHEADBS-NEXT: ret
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/bswap-bitreverse.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -497,7 +497,7 @@ define i32 @test_bitreverse_i32(i32 %a) nounwind {
; RV64ZBB-NEXT: and a1, a1, a2
; RV64ZBB-NEXT: srli a0, a0, 28
; RV64ZBB-NEXT: lui a2, 986895
; RV64ZBB-NEXT: addiw a2, a2, 240
; RV64ZBB-NEXT: addi a2, a2, 240
; RV64ZBB-NEXT: and a0, a0, a2
; RV64ZBB-NEXT: sext.w a0, a0
; RV64ZBB-NEXT: or a0, a1, a0
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/calling-conv-half.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -396,7 +396,7 @@ define i32 @caller_half_on_stack() nounwind {
; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: lui a0, 1048565
; RV64IF-NEXT: addiw t0, a0, -1792
; RV64IF-NEXT: addi t0, a0, -1792
; RV64IF-NEXT: li a0, 1
; RV64IF-NEXT: li a1, 2
; RV64IF-NEXT: li a2, 3
Expand Down
20 changes: 10 additions & 10 deletions llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -58,7 +58,7 @@ define i8 @test_cttz_i8(i8 %a) nounwind {
; RV64NOZBB-NEXT: andi a1, a0, 255
; RV64NOZBB-NEXT: beqz a1, .LBB0_2
; RV64NOZBB-NEXT: # %bb.1: # %cond.false
; RV64NOZBB-NEXT: addiw a1, a0, -1
; RV64NOZBB-NEXT: addi a1, a0, -1
; RV64NOZBB-NEXT: not a0, a0
; RV64NOZBB-NEXT: and a0, a0, a1
; RV64NOZBB-NEXT: srli a1, a0, 1
Expand Down Expand Up @@ -308,7 +308,7 @@ define i32 @test_cttz_i32(i32 %a) nounwind {
; RV64M-NEXT: negw a1, a0
; RV64M-NEXT: and a0, a0, a1
; RV64M-NEXT: lui a1, 30667
; RV64M-NEXT: addiw a1, a1, 1329
; RV64M-NEXT: addi a1, a1, 1329
; RV64M-NEXT: mul a0, a0, a1
; RV64M-NEXT: srliw a0, a0, 27
; RV64M-NEXT: lui a1, %hi(.LCPI2_0)
Expand Down Expand Up @@ -567,7 +567,7 @@ define i8 @test_cttz_i8_zero_undef(i8 %a) nounwind {
;
; RV64NOZBB-LABEL: test_cttz_i8_zero_undef:
; RV64NOZBB: # %bb.0:
; RV64NOZBB-NEXT: addiw a1, a0, -1
; RV64NOZBB-NEXT: addi a1, a0, -1
; RV64NOZBB-NEXT: not a0, a0
; RV64NOZBB-NEXT: and a0, a0, a1
; RV64NOZBB-NEXT: srli a1, a0, 1
Expand Down Expand Up @@ -753,7 +753,7 @@ define i32 @test_cttz_i32_zero_undef(i32 %a) nounwind {
; RV64M-NEXT: negw a1, a0
; RV64M-NEXT: and a0, a0, a1
; RV64M-NEXT: lui a1, 30667
; RV64M-NEXT: addiw a1, a1, 1329
; RV64M-NEXT: addi a1, a1, 1329
; RV64M-NEXT: mul a0, a0, a1
; RV64M-NEXT: srliw a0, a0, 27
; RV64M-NEXT: lui a1, %hi(.LCPI6_0)
Expand Down Expand Up @@ -1315,10 +1315,10 @@ define i32 @test_ctlz_i32(i32 %a) nounwind {
; RV64M-NEXT: srli a1, a0, 4
; RV64M-NEXT: add a0, a0, a1
; RV64M-NEXT: lui a1, 61681
; RV64M-NEXT: addiw a1, a1, -241
; RV64M-NEXT: addi a1, a1, -241
; RV64M-NEXT: and a0, a0, a1
; RV64M-NEXT: lui a1, 4112
; RV64M-NEXT: addiw a1, a1, 257
; RV64M-NEXT: addi a1, a1, 257
; RV64M-NEXT: mul a0, a0, a1
; RV64M-NEXT: srliw a0, a0, 24
; RV64M-NEXT: ret
Expand Down Expand Up @@ -1969,10 +1969,10 @@ define i32 @test_ctlz_i32_zero_undef(i32 %a) nounwind {
; RV64M-NEXT: srli a1, a0, 4
; RV64M-NEXT: add a0, a0, a1
; RV64M-NEXT: lui a1, 61681
; RV64M-NEXT: addiw a1, a1, -241
; RV64M-NEXT: addi a1, a1, -241
; RV64M-NEXT: and a0, a0, a1
; RV64M-NEXT: lui a1, 4112
; RV64M-NEXT: addiw a1, a1, 257
; RV64M-NEXT: addi a1, a1, 257
; RV64M-NEXT: mul a0, a0, a1
; RV64M-NEXT: srliw a0, a0, 24
; RV64M-NEXT: ret
Expand Down Expand Up @@ -2558,10 +2558,10 @@ define i32 @test_ctpop_i32(i32 %a) nounwind {
; RV64M-NEXT: srli a1, a0, 4
; RV64M-NEXT: add a0, a0, a1
; RV64M-NEXT: lui a1, 61681
; RV64M-NEXT: addiw a1, a1, -241
; RV64M-NEXT: addi a1, a1, -241
; RV64M-NEXT: and a0, a0, a1
; RV64M-NEXT: lui a1, 4112
; RV64M-NEXT: addiw a1, a1, 257
; RV64M-NEXT: addi a1, a1, 257
; RV64M-NEXT: mul a0, a0, a1
; RV64M-NEXT: srliw a0, a0, 24
; RV64M-NEXT: ret
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -98,7 +98,7 @@ define signext i32 @ctz_dereferencing_pointer(i64* %b) nounwind {
; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: lbu a0, 0(a0)
; RV64I-NEXT: seqz a1, s0
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: andi a0, a0, 63
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
Expand Down Expand Up @@ -177,7 +177,7 @@ define i64 @ctz_dereferencing_pointer_zext(i32* %b) nounwind {
; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: lbu a0, 0(a0)
; RV64I-NEXT: seqz a1, s0
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: andi a0, a0, 31
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
Expand Down Expand Up @@ -252,7 +252,7 @@ define signext i32 @ctz1(i32 signext %x) nounwind {
; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: lbu a0, 0(a0)
; RV64I-NEXT: seqz a1, s0
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: andi a0, a0, 31
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
Expand Down Expand Up @@ -325,7 +325,7 @@ define signext i32 @ctz1_flipped(i32 signext %x) nounwind {
; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: lbu a0, 0(a0)
; RV64I-NEXT: seqz a1, s0
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: andi a0, a0, 31
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
Expand Down Expand Up @@ -561,7 +561,7 @@ define signext i32 @ctz4(i64 %b) nounwind {
; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: lbu a0, 0(a0)
; RV64I-NEXT: seqz a1, s0
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: andi a0, a0, 63
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
Expand Down Expand Up @@ -804,7 +804,7 @@ define signext i32 @ctz5(i32 signext %x) nounwind {
; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: lbu a0, 0(a0)
; RV64I-NEXT: seqz a1, s0
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: andi a0, a0, 31
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
Expand Down Expand Up @@ -877,7 +877,7 @@ define signext i32 @ctz6(i32 signext %x) nounwind {
; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: lbu a0, 0(a0)
; RV64I-NEXT: seqz a1, s0
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: andi a0, a0, 31
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
Expand Down Expand Up @@ -956,7 +956,7 @@ define signext i32 @globalVar() nounwind {
; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: lbu a0, 0(a0)
; RV64I-NEXT: seqz a1, s0
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: andi a0, a0, 31
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/div-by-constant.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,7 @@ define i32 @udiv_constant_no_add(i32 %a) nounwind {
; RV64: # %bb.0:
; RV64-NEXT: slli a0, a0, 32
; RV64-NEXT: lui a1, 838861
; RV64-NEXT: addiw a1, a1, -819
; RV64-NEXT: addi a1, a1, -819
; RV64-NEXT: slli a1, a1, 32
; RV64-NEXT: mulhu a0, a0, a1
; RV64-NEXT: srli a0, a0, 34
Expand All @@ -50,7 +50,7 @@ define i32 @udiv_constant_add(i32 %a) nounwind {
; RV64IM: # %bb.0:
; RV64IM-NEXT: slli a1, a0, 32
; RV64IM-NEXT: lui a2, 149797
; RV64IM-NEXT: addiw a2, a2, -1755
; RV64IM-NEXT: addi a2, a2, -1755
; RV64IM-NEXT: slli a2, a2, 32
; RV64IM-NEXT: mulhu a1, a1, a2
; RV64IM-NEXT: srli a1, a1, 32
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/div.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -69,7 +69,7 @@ define i32 @udiv_constant(i32 %a) nounwind {
; RV64IM: # %bb.0:
; RV64IM-NEXT: slli a0, a0, 32
; RV64IM-NEXT: lui a1, 838861
; RV64IM-NEXT: addiw a1, a1, -819
; RV64IM-NEXT: addi a1, a1, -819
; RV64IM-NEXT: slli a1, a1, 32
; RV64IM-NEXT: mulhu a0, a0, a1
; RV64IM-NEXT: srli a0, a0, 34
Expand Down Expand Up @@ -452,7 +452,7 @@ define i16 @udiv16(i16 %a, i16 %b) nounwind {
; RV64IM-LABEL: udiv16:
; RV64IM: # %bb.0:
; RV64IM-NEXT: lui a2, 16
; RV64IM-NEXT: addiw a2, a2, -1
; RV64IM-NEXT: addi a2, a2, -1
; RV64IM-NEXT: and a1, a1, a2
; RV64IM-NEXT: and a0, a0, a2
; RV64IM-NEXT: divuw a0, a0, a1
Expand Down
22 changes: 11 additions & 11 deletions llvm/test/CodeGen/RISCV/double-convert.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -394,7 +394,7 @@ define i32 @fcvt_wu_d_sat(double %a) nounwind {
; RV64IFD-NEXT: fcvt.wu.d a0, fa0, rtz
; RV64IFD-NEXT: feq.d a1, fa0, fa0
; RV64IFD-NEXT: seqz a1, a1
; RV64IFD-NEXT: addiw a1, a1, -1
; RV64IFD-NEXT: addi a1, a1, -1
; RV64IFD-NEXT: and a0, a0, a1
; RV64IFD-NEXT: slli a0, a0, 32
; RV64IFD-NEXT: srli a0, a0, 32
Expand All @@ -420,7 +420,7 @@ define i32 @fcvt_wu_d_sat(double %a) nounwind {
; RV64IZFINXZDINX-NEXT: fcvt.wu.d a1, a0, rtz
; RV64IZFINXZDINX-NEXT: feq.d a0, a0, a0
; RV64IZFINXZDINX-NEXT: seqz a0, a0
; RV64IZFINXZDINX-NEXT: addiw a0, a0, -1
; RV64IZFINXZDINX-NEXT: addi a0, a0, -1
; RV64IZFINXZDINX-NEXT: and a0, a1, a0
; RV64IZFINXZDINX-NEXT: slli a0, a0, 32
; RV64IZFINXZDINX-NEXT: srli a0, a0, 32
Expand Down Expand Up @@ -1891,20 +1891,20 @@ define signext i16 @fcvt_w_s_sat_i16(double %a) nounwind {
; RV64I-NEXT: lui s1, 1048568
; RV64I-NEXT: .LBB26_2: # %start
; RV64I-NEXT: lui a0, 4152
; RV64I-NEXT: addiw a0, a0, -1
; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: slli a1, a0, 38
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __gtdf2@plt
; RV64I-NEXT: blez a0, .LBB26_4
; RV64I-NEXT: # %bb.3: # %start
; RV64I-NEXT: lui s1, 8
; RV64I-NEXT: addiw s1, s1, -1
; RV64I-NEXT: addi s1, s1, -1
; RV64I-NEXT: .LBB26_4: # %start
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __unorddf2@plt
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: addiw a0, a0, -1
; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: and a0, a0, s1
; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srai a0, a0, 48
Expand Down Expand Up @@ -2074,7 +2074,7 @@ define zeroext i16 @fcvt_wu_s_sat_i16(double %a) nounwind {
; RV64I-NEXT: call __fixunsdfdi@plt
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lui a0, 8312
; RV64I-NEXT: addiw a0, a0, -1
; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: slli a1, a0, 37
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __gtdf2@plt
Expand Down Expand Up @@ -2298,7 +2298,7 @@ define signext i8 @fcvt_w_s_sat_i8(double %a) nounwind {
; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __unorddf2@plt
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: addiw a0, a0, -1
; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: and a0, a0, s1
; RV64I-NEXT: slli a0, a0, 56
; RV64I-NEXT: srai a0, a0, 56
Expand Down Expand Up @@ -2509,7 +2509,7 @@ define zeroext i32 @fcvt_wu_d_sat_zext(double %a) nounwind {
; RV64IFD-NEXT: fcvt.wu.d a0, fa0, rtz
; RV64IFD-NEXT: feq.d a1, fa0, fa0
; RV64IFD-NEXT: seqz a1, a1
; RV64IFD-NEXT: addiw a1, a1, -1
; RV64IFD-NEXT: addi a1, a1, -1
; RV64IFD-NEXT: and a0, a0, a1
; RV64IFD-NEXT: slli a0, a0, 32
; RV64IFD-NEXT: srli a0, a0, 32
Expand All @@ -2535,7 +2535,7 @@ define zeroext i32 @fcvt_wu_d_sat_zext(double %a) nounwind {
; RV64IZFINXZDINX-NEXT: fcvt.wu.d a1, a0, rtz
; RV64IZFINXZDINX-NEXT: feq.d a0, a0, a0
; RV64IZFINXZDINX-NEXT: seqz a0, a0
; RV64IZFINXZDINX-NEXT: addiw a0, a0, -1
; RV64IZFINXZDINX-NEXT: addi a0, a0, -1
; RV64IZFINXZDINX-NEXT: and a0, a1, a0
; RV64IZFINXZDINX-NEXT: slli a0, a0, 32
; RV64IZFINXZDINX-NEXT: srli a0, a0, 32
Expand Down Expand Up @@ -2735,13 +2735,13 @@ define signext i32 @fcvt_w_d_sat_sext(double %a) nounwind {
; RV64I-NEXT: call __gtdf2@plt
; RV64I-NEXT: blez a0, .LBB34_4
; RV64I-NEXT: # %bb.3: # %start
; RV64I-NEXT: addiw s1, s3, -1
; RV64I-NEXT: addi s1, s3, -1
; RV64I-NEXT: .LBB34_4: # %start
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __unorddf2@plt
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: addiw a0, a0, -1
; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: and a0, a0, s1
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -69,7 +69,7 @@ define void @_Z3foov() {
; CHECK-NEXT: vl2r.v v16, (a1) # Unknown-size Folded Reload
; CHECK-NEXT: vle16.v v16, (a0)
; CHECK-NEXT: lui a0, 1048572
; CHECK-NEXT: addiw a0, a0, 928
; CHECK-NEXT: addi a0, a0, 928
; CHECK-NEXT: vmsbc.vx v0, v8, a0
; CHECK-NEXT: vsetvli zero, zero, e16, m2, tu, mu
; CHECK-NEXT: csrr a0, vlenb
Expand Down
18 changes: 9 additions & 9 deletions llvm/test/CodeGen/RISCV/float-convert.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -243,7 +243,7 @@ define i32 @fcvt_wu_s_sat(float %a) nounwind {
; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz
; RV64IF-NEXT: feq.s a1, fa0, fa0
; RV64IF-NEXT: seqz a1, a1
; RV64IF-NEXT: addiw a1, a1, -1
; RV64IF-NEXT: addi a1, a1, -1
; RV64IF-NEXT: and a0, a0, a1
; RV64IF-NEXT: slli a0, a0, 32
; RV64IF-NEXT: srli a0, a0, 32
Expand All @@ -263,7 +263,7 @@ define i32 @fcvt_wu_s_sat(float %a) nounwind {
; RV64IZFINX-NEXT: fcvt.wu.s a1, a0, rtz
; RV64IZFINX-NEXT: feq.s a0, a0, a0
; RV64IZFINX-NEXT: seqz a0, a0
; RV64IZFINX-NEXT: addiw a0, a0, -1
; RV64IZFINX-NEXT: addi a0, a0, -1
; RV64IZFINX-NEXT: and a0, a1, a0
; RV64IZFINX-NEXT: slli a0, a0, 32
; RV64IZFINX-NEXT: srli a0, a0, 32
Expand Down Expand Up @@ -1528,13 +1528,13 @@ define signext i16 @fcvt_w_s_sat_i16(float %a) nounwind {
; RV64I-NEXT: blez a0, .LBB24_4
; RV64I-NEXT: # %bb.3: # %start
; RV64I-NEXT: lui s1, 8
; RV64I-NEXT: addiw s1, s1, -1
; RV64I-NEXT: addi s1, s1, -1
; RV64I-NEXT: .LBB24_4: # %start
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __unordsf2@plt
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: addiw a0, a0, -1
; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: and a0, a0, s1
; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srai a0, a0, 48
Expand Down Expand Up @@ -1874,7 +1874,7 @@ define signext i8 @fcvt_w_s_sat_i8(float %a) nounwind {
; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __unordsf2@plt
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: addiw a0, a0, -1
; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: and a0, a0, s1
; RV64I-NEXT: slli a0, a0, 56
; RV64I-NEXT: srai a0, a0, 56
Expand Down Expand Up @@ -2057,7 +2057,7 @@ define zeroext i32 @fcvt_wu_s_sat_zext(float %a) nounwind {
; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz
; RV64IF-NEXT: feq.s a1, fa0, fa0
; RV64IF-NEXT: seqz a1, a1
; RV64IF-NEXT: addiw a1, a1, -1
; RV64IF-NEXT: addi a1, a1, -1
; RV64IF-NEXT: and a0, a0, a1
; RV64IF-NEXT: slli a0, a0, 32
; RV64IF-NEXT: srli a0, a0, 32
Expand All @@ -2077,7 +2077,7 @@ define zeroext i32 @fcvt_wu_s_sat_zext(float %a) nounwind {
; RV64IZFINX-NEXT: fcvt.wu.s a1, a0, rtz
; RV64IZFINX-NEXT: feq.s a0, a0, a0
; RV64IZFINX-NEXT: seqz a0, a0
; RV64IZFINX-NEXT: addiw a0, a0, -1
; RV64IZFINX-NEXT: addi a0, a0, -1
; RV64IZFINX-NEXT: and a0, a1, a0
; RV64IZFINX-NEXT: slli a0, a0, 32
; RV64IZFINX-NEXT: srli a0, a0, 32
Expand Down Expand Up @@ -2238,13 +2238,13 @@ define signext i32 @fcvt_w_s_sat_sext(float %a) nounwind {
; RV64I-NEXT: call __gtsf2@plt
; RV64I-NEXT: blez a0, .LBB32_4
; RV64I-NEXT: # %bb.3: # %start
; RV64I-NEXT: addiw s1, s3, -1
; RV64I-NEXT: addi s1, s3, -1
; RV64I-NEXT: .LBB32_4: # %start
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __unordsf2@plt
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: addiw a0, a0, -1
; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: and a0, a0, s1
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -325,7 +325,7 @@ define dso_local void @inc_g_i32() nounwind {
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: lui a0, %hi(g_4_i32)
; RV64I-NEXT: lw a1, %lo(g_4_i32)(a0)
; RV64I-NEXT: addiw a1, a1, 1
; RV64I-NEXT: addi a1, a1, 1
; RV64I-NEXT: sw a1, %lo(g_4_i32)(a0)
; RV64I-NEXT: ret
;
Expand All @@ -334,7 +334,7 @@ define dso_local void @inc_g_i32() nounwind {
; RV64I-MEDIUM-NEXT: .Lpcrel_hi8:
; RV64I-MEDIUM-NEXT: auipc a0, %pcrel_hi(g_4_i32)
; RV64I-MEDIUM-NEXT: lw a1, %pcrel_lo(.Lpcrel_hi8)(a0)
; RV64I-MEDIUM-NEXT: addiw a1, a1, 1
; RV64I-MEDIUM-NEXT: addi a1, a1, 1
; RV64I-MEDIUM-NEXT: sw a1, %pcrel_lo(.Lpcrel_hi8)(a0)
; RV64I-MEDIUM-NEXT: ret
entry:
Expand Down
46 changes: 23 additions & 23 deletions llvm/test/CodeGen/RISCV/half-convert.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1703,7 +1703,7 @@ define i32 @fcvt_wu_h_sat(half %a) nounwind {
; RV64IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
; RV64IZFH-NEXT: feq.h a1, fa0, fa0
; RV64IZFH-NEXT: seqz a1, a1
; RV64IZFH-NEXT: addiw a1, a1, -1
; RV64IZFH-NEXT: addi a1, a1, -1
; RV64IZFH-NEXT: and a0, a0, a1
; RV64IZFH-NEXT: slli a0, a0, 32
; RV64IZFH-NEXT: srli a0, a0, 32
Expand All @@ -1723,7 +1723,7 @@ define i32 @fcvt_wu_h_sat(half %a) nounwind {
; RV64IDZFH-NEXT: fcvt.wu.h a0, fa0, rtz
; RV64IDZFH-NEXT: feq.h a1, fa0, fa0
; RV64IDZFH-NEXT: seqz a1, a1
; RV64IDZFH-NEXT: addiw a1, a1, -1
; RV64IDZFH-NEXT: addi a1, a1, -1
; RV64IDZFH-NEXT: and a0, a0, a1
; RV64IDZFH-NEXT: slli a0, a0, 32
; RV64IDZFH-NEXT: srli a0, a0, 32
Expand All @@ -1743,7 +1743,7 @@ define i32 @fcvt_wu_h_sat(half %a) nounwind {
; RV64IZHINX-NEXT: fcvt.wu.h a1, a0, rtz
; RV64IZHINX-NEXT: feq.h a0, a0, a0
; RV64IZHINX-NEXT: seqz a0, a0
; RV64IZHINX-NEXT: addiw a0, a0, -1
; RV64IZHINX-NEXT: addi a0, a0, -1
; RV64IZHINX-NEXT: and a0, a1, a0
; RV64IZHINX-NEXT: slli a0, a0, 32
; RV64IZHINX-NEXT: srli a0, a0, 32
Expand All @@ -1763,7 +1763,7 @@ define i32 @fcvt_wu_h_sat(half %a) nounwind {
; RV64IZDINXZHINX-NEXT: fcvt.wu.h a1, a0, rtz
; RV64IZDINXZHINX-NEXT: feq.h a0, a0, a0
; RV64IZDINXZHINX-NEXT: seqz a0, a0
; RV64IZDINXZHINX-NEXT: addiw a0, a0, -1
; RV64IZDINXZHINX-NEXT: addi a0, a0, -1
; RV64IZDINXZHINX-NEXT: and a0, a1, a0
; RV64IZDINXZHINX-NEXT: slli a0, a0, 32
; RV64IZDINXZHINX-NEXT: srli a0, a0, 32
Expand Down Expand Up @@ -1863,7 +1863,7 @@ define i32 @fcvt_wu_h_sat(half %a) nounwind {
; RV64ID-LP64-NEXT: fcvt.wu.s a0, fa5, rtz
; RV64ID-LP64-NEXT: feq.s a1, fa5, fa5
; RV64ID-LP64-NEXT: seqz a1, a1
; RV64ID-LP64-NEXT: addiw a1, a1, -1
; RV64ID-LP64-NEXT: addi a1, a1, -1
; RV64ID-LP64-NEXT: and a0, a0, a1
; RV64ID-LP64-NEXT: slli a0, a0, 32
; RV64ID-LP64-NEXT: srli a0, a0, 32
Expand Down Expand Up @@ -1893,7 +1893,7 @@ define i32 @fcvt_wu_h_sat(half %a) nounwind {
; RV64ID-NEXT: fcvt.wu.s a0, fa0, rtz
; RV64ID-NEXT: feq.s a1, fa0, fa0
; RV64ID-NEXT: seqz a1, a1
; RV64ID-NEXT: addiw a1, a1, -1
; RV64ID-NEXT: addi a1, a1, -1
; RV64ID-NEXT: and a0, a0, a1
; RV64ID-NEXT: slli a0, a0, 32
; RV64ID-NEXT: srli a0, a0, 32
Expand All @@ -1917,7 +1917,7 @@ define i32 @fcvt_wu_h_sat(half %a) nounwind {
; CHECK64-IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
; CHECK64-IZFHMIN-NEXT: feq.s a1, fa5, fa5
; CHECK64-IZFHMIN-NEXT: seqz a1, a1
; CHECK64-IZFHMIN-NEXT: addiw a1, a1, -1
; CHECK64-IZFHMIN-NEXT: addi a1, a1, -1
; CHECK64-IZFHMIN-NEXT: and a0, a0, a1
; CHECK64-IZFHMIN-NEXT: slli a0, a0, 32
; CHECK64-IZFHMIN-NEXT: srli a0, a0, 32
Expand All @@ -1939,7 +1939,7 @@ define i32 @fcvt_wu_h_sat(half %a) nounwind {
; CHECK64-IZHINXMIN-NEXT: fcvt.wu.s a1, a0, rtz
; CHECK64-IZHINXMIN-NEXT: feq.s a0, a0, a0
; CHECK64-IZHINXMIN-NEXT: seqz a0, a0
; CHECK64-IZHINXMIN-NEXT: addiw a0, a0, -1
; CHECK64-IZHINXMIN-NEXT: addi a0, a0, -1
; CHECK64-IZHINXMIN-NEXT: and a0, a1, a0
; CHECK64-IZHINXMIN-NEXT: slli a0, a0, 32
; CHECK64-IZHINXMIN-NEXT: srli a0, a0, 32
Expand All @@ -1961,7 +1961,7 @@ define i32 @fcvt_wu_h_sat(half %a) nounwind {
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.wu.s a1, a0, rtz
; CHECK64-IZDINXZHINXMIN-NEXT: feq.s a0, a0, a0
; CHECK64-IZDINXZHINXMIN-NEXT: seqz a0, a0
; CHECK64-IZDINXZHINXMIN-NEXT: addiw a0, a0, -1
; CHECK64-IZDINXZHINXMIN-NEXT: addi a0, a0, -1
; CHECK64-IZDINXZHINXMIN-NEXT: and a0, a1, a0
; CHECK64-IZDINXZHINXMIN-NEXT: slli a0, a0, 32
; CHECK64-IZDINXZHINXMIN-NEXT: srli a0, a0, 32
Expand Down Expand Up @@ -6551,13 +6551,13 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind {
; RV64I-NEXT: blez a0, .LBB32_4
; RV64I-NEXT: # %bb.3: # %start
; RV64I-NEXT: lui s1, 8
; RV64I-NEXT: addiw s1, s1, -1
; RV64I-NEXT: addi s1, s1, -1
; RV64I-NEXT: .LBB32_4: # %start
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __unordsf2@plt
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: addiw a0, a0, -1
; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: and a0, a0, s1
; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srai a0, a0, 48
Expand Down Expand Up @@ -7511,7 +7511,7 @@ define signext i8 @fcvt_w_s_sat_i8(half %a) nounwind {
; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __unordsf2@plt
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: addiw a0, a0, -1
; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: and a0, a0, s1
; RV64I-NEXT: slli a0, a0, 56
; RV64I-NEXT: srai a0, a0, 56
Expand Down Expand Up @@ -8128,7 +8128,7 @@ define zeroext i32 @fcvt_wu_h_sat_zext(half %a) nounwind {
; RV64IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
; RV64IZFH-NEXT: feq.h a1, fa0, fa0
; RV64IZFH-NEXT: seqz a1, a1
; RV64IZFH-NEXT: addiw a1, a1, -1
; RV64IZFH-NEXT: addi a1, a1, -1
; RV64IZFH-NEXT: and a0, a0, a1
; RV64IZFH-NEXT: slli a0, a0, 32
; RV64IZFH-NEXT: srli a0, a0, 32
Expand All @@ -8148,7 +8148,7 @@ define zeroext i32 @fcvt_wu_h_sat_zext(half %a) nounwind {
; RV64IDZFH-NEXT: fcvt.wu.h a0, fa0, rtz
; RV64IDZFH-NEXT: feq.h a1, fa0, fa0
; RV64IDZFH-NEXT: seqz a1, a1
; RV64IDZFH-NEXT: addiw a1, a1, -1
; RV64IDZFH-NEXT: addi a1, a1, -1
; RV64IDZFH-NEXT: and a0, a0, a1
; RV64IDZFH-NEXT: slli a0, a0, 32
; RV64IDZFH-NEXT: srli a0, a0, 32
Expand All @@ -8168,7 +8168,7 @@ define zeroext i32 @fcvt_wu_h_sat_zext(half %a) nounwind {
; RV64IZHINX-NEXT: fcvt.wu.h a1, a0, rtz
; RV64IZHINX-NEXT: feq.h a0, a0, a0
; RV64IZHINX-NEXT: seqz a0, a0
; RV64IZHINX-NEXT: addiw a0, a0, -1
; RV64IZHINX-NEXT: addi a0, a0, -1
; RV64IZHINX-NEXT: and a0, a1, a0
; RV64IZHINX-NEXT: slli a0, a0, 32
; RV64IZHINX-NEXT: srli a0, a0, 32
Expand All @@ -8188,7 +8188,7 @@ define zeroext i32 @fcvt_wu_h_sat_zext(half %a) nounwind {
; RV64IZDINXZHINX-NEXT: fcvt.wu.h a1, a0, rtz
; RV64IZDINXZHINX-NEXT: feq.h a0, a0, a0
; RV64IZDINXZHINX-NEXT: seqz a0, a0
; RV64IZDINXZHINX-NEXT: addiw a0, a0, -1
; RV64IZDINXZHINX-NEXT: addi a0, a0, -1
; RV64IZDINXZHINX-NEXT: and a0, a1, a0
; RV64IZDINXZHINX-NEXT: slli a0, a0, 32
; RV64IZDINXZHINX-NEXT: srli a0, a0, 32
Expand Down Expand Up @@ -8290,7 +8290,7 @@ define zeroext i32 @fcvt_wu_h_sat_zext(half %a) nounwind {
; RV64ID-LP64-NEXT: fcvt.wu.s a0, fa5, rtz
; RV64ID-LP64-NEXT: feq.s a1, fa5, fa5
; RV64ID-LP64-NEXT: seqz a1, a1
; RV64ID-LP64-NEXT: addiw a1, a1, -1
; RV64ID-LP64-NEXT: addi a1, a1, -1
; RV64ID-LP64-NEXT: and a0, a0, a1
; RV64ID-LP64-NEXT: slli a0, a0, 32
; RV64ID-LP64-NEXT: srli a0, a0, 32
Expand Down Expand Up @@ -8320,7 +8320,7 @@ define zeroext i32 @fcvt_wu_h_sat_zext(half %a) nounwind {
; RV64ID-NEXT: fcvt.wu.s a0, fa0, rtz
; RV64ID-NEXT: feq.s a1, fa0, fa0
; RV64ID-NEXT: seqz a1, a1
; RV64ID-NEXT: addiw a1, a1, -1
; RV64ID-NEXT: addi a1, a1, -1
; RV64ID-NEXT: and a0, a0, a1
; RV64ID-NEXT: slli a0, a0, 32
; RV64ID-NEXT: srli a0, a0, 32
Expand All @@ -8344,7 +8344,7 @@ define zeroext i32 @fcvt_wu_h_sat_zext(half %a) nounwind {
; CHECK64-IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
; CHECK64-IZFHMIN-NEXT: feq.s a1, fa5, fa5
; CHECK64-IZFHMIN-NEXT: seqz a1, a1
; CHECK64-IZFHMIN-NEXT: addiw a1, a1, -1
; CHECK64-IZFHMIN-NEXT: addi a1, a1, -1
; CHECK64-IZFHMIN-NEXT: and a0, a0, a1
; CHECK64-IZFHMIN-NEXT: slli a0, a0, 32
; CHECK64-IZFHMIN-NEXT: srli a0, a0, 32
Expand All @@ -8366,7 +8366,7 @@ define zeroext i32 @fcvt_wu_h_sat_zext(half %a) nounwind {
; CHECK64-IZHINXMIN-NEXT: fcvt.wu.s a1, a0, rtz
; CHECK64-IZHINXMIN-NEXT: feq.s a0, a0, a0
; CHECK64-IZHINXMIN-NEXT: seqz a0, a0
; CHECK64-IZHINXMIN-NEXT: addiw a0, a0, -1
; CHECK64-IZHINXMIN-NEXT: addi a0, a0, -1
; CHECK64-IZHINXMIN-NEXT: and a0, a1, a0
; CHECK64-IZHINXMIN-NEXT: slli a0, a0, 32
; CHECK64-IZHINXMIN-NEXT: srli a0, a0, 32
Expand All @@ -8388,7 +8388,7 @@ define zeroext i32 @fcvt_wu_h_sat_zext(half %a) nounwind {
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.wu.s a1, a0, rtz
; CHECK64-IZDINXZHINXMIN-NEXT: feq.s a0, a0, a0
; CHECK64-IZDINXZHINXMIN-NEXT: seqz a0, a0
; CHECK64-IZDINXZHINXMIN-NEXT: addiw a0, a0, -1
; CHECK64-IZDINXZHINXMIN-NEXT: addi a0, a0, -1
; CHECK64-IZDINXZHINXMIN-NEXT: and a0, a1, a0
; CHECK64-IZDINXZHINXMIN-NEXT: slli a0, a0, 32
; CHECK64-IZDINXZHINXMIN-NEXT: srli a0, a0, 32
Expand Down Expand Up @@ -8518,13 +8518,13 @@ define signext i32 @fcvt_w_h_sat_sext(half %a) nounwind {
; RV64I-NEXT: call __gtsf2@plt
; RV64I-NEXT: blez a0, .LBB40_4
; RV64I-NEXT: # %bb.3: # %start
; RV64I-NEXT: addiw s1, s3, -1
; RV64I-NEXT: addi s1, s3, -1
; RV64I-NEXT: .LBB40_4: # %start
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __unordsf2@plt
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: addiw a0, a0, -1
; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: and a0, a0, s1
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
Expand Down
44 changes: 14 additions & 30 deletions llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -259,21 +259,13 @@ define ptr @offset_sh3add() {
}

define dso_local void @read_modify_write() local_unnamed_addr nounwind {
; RV32-LABEL: read_modify_write:
; RV32: # %bb.0: # %entry
; RV32-NEXT: lui a0, %hi(s+160)
; RV32-NEXT: lw a1, %lo(s+160)(a0)
; RV32-NEXT: addi a1, a1, 10
; RV32-NEXT: sw a1, %lo(s+160)(a0)
; RV32-NEXT: ret
;
; RV64-LABEL: read_modify_write:
; RV64: # %bb.0: # %entry
; RV64-NEXT: lui a0, %hi(s+160)
; RV64-NEXT: lw a1, %lo(s+160)(a0)
; RV64-NEXT: addiw a1, a1, 10
; RV64-NEXT: sw a1, %lo(s+160)(a0)
; RV64-NEXT: ret
; CHECK-LABEL: read_modify_write:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lui a0, %hi(s+160)
; CHECK-NEXT: lw a1, %lo(s+160)(a0)
; CHECK-NEXT: addi a1, a1, 10
; CHECK-NEXT: sw a1, %lo(s+160)(a0)
; CHECK-NEXT: ret
entry:
%x = load i32, ptr getelementptr inbounds (%struct.S, ptr @s, i32 0, i32 1), align 4
%y = add i32 %x, 10
Expand Down Expand Up @@ -375,21 +367,13 @@ define void @store_sh3add() {
}

define dso_local void @rmw_addi_addi() nounwind {
; RV32-LABEL: rmw_addi_addi:
; RV32: # %bb.0: # %entry
; RV32-NEXT: lui a0, %hi(bar+3211)
; RV32-NEXT: lbu a1, %lo(bar+3211)(a0)
; RV32-NEXT: addi a1, a1, 10
; RV32-NEXT: sb a1, %lo(bar+3211)(a0)
; RV32-NEXT: ret
;
; RV64-LABEL: rmw_addi_addi:
; RV64: # %bb.0: # %entry
; RV64-NEXT: lui a0, %hi(bar+3211)
; RV64-NEXT: lbu a1, %lo(bar+3211)(a0)
; RV64-NEXT: addiw a1, a1, 10
; RV64-NEXT: sb a1, %lo(bar+3211)(a0)
; RV64-NEXT: ret
; CHECK-LABEL: rmw_addi_addi:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lui a0, %hi(bar+3211)
; CHECK-NEXT: lbu a1, %lo(bar+3211)(a0)
; CHECK-NEXT: addi a1, a1, 10
; CHECK-NEXT: sb a1, %lo(bar+3211)(a0)
; CHECK-NEXT: ret
entry:
%0 = load i8, ptr getelementptr inbounds ([0 x i8], ptr @bar, i32 0, i64 3211)
%1 = add i8 %0, 10
Expand Down
20 changes: 10 additions & 10 deletions llvm/test/CodeGen/RISCV/imm.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -588,35 +588,35 @@ define i64 @imm64_6() nounwind {
; RV64I-LABEL: imm64_6:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a0, 9321
; RV64I-NEXT: addiw a0, a0, -1329
; RV64I-NEXT: addi a0, a0, -1329
; RV64I-NEXT: slli a0, a0, 35
; RV64I-NEXT: ret
;
; RV64IZBA-LABEL: imm64_6:
; RV64IZBA: # %bb.0:
; RV64IZBA-NEXT: lui a0, 9321
; RV64IZBA-NEXT: addiw a0, a0, -1329
; RV64IZBA-NEXT: addi a0, a0, -1329
; RV64IZBA-NEXT: slli a0, a0, 35
; RV64IZBA-NEXT: ret
;
; RV64IZBB-LABEL: imm64_6:
; RV64IZBB: # %bb.0:
; RV64IZBB-NEXT: lui a0, 9321
; RV64IZBB-NEXT: addiw a0, a0, -1329
; RV64IZBB-NEXT: addi a0, a0, -1329
; RV64IZBB-NEXT: slli a0, a0, 35
; RV64IZBB-NEXT: ret
;
; RV64IZBS-LABEL: imm64_6:
; RV64IZBS: # %bb.0:
; RV64IZBS-NEXT: lui a0, 9321
; RV64IZBS-NEXT: addiw a0, a0, -1329
; RV64IZBS-NEXT: addi a0, a0, -1329
; RV64IZBS-NEXT: slli a0, a0, 35
; RV64IZBS-NEXT: ret
;
; RV64IXTHEADBB-LABEL: imm64_6:
; RV64IXTHEADBB: # %bb.0:
; RV64IXTHEADBB-NEXT: lui a0, 9321
; RV64IXTHEADBB-NEXT: addiw a0, a0, -1329
; RV64IXTHEADBB-NEXT: addi a0, a0, -1329
; RV64IXTHEADBB-NEXT: slli a0, a0, 35
; RV64IXTHEADBB-NEXT: ret
ret i64 1311768464867721216 ; 0x1234_5678_0000_0000
Expand Down Expand Up @@ -709,7 +709,7 @@ define i64 @imm64_8() nounwind {
; RV64IZBA-LABEL: imm64_8:
; RV64IZBA: # %bb.0:
; RV64IZBA-NEXT: lui a0, 596523
; RV64IZBA-NEXT: addiw a0, a0, 965
; RV64IZBA-NEXT: addi a0, a0, 965
; RV64IZBA-NEXT: slli.uw a0, a0, 13
; RV64IZBA-NEXT: addi a0, a0, -1347
; RV64IZBA-NEXT: slli a0, a0, 12
Expand Down Expand Up @@ -2298,7 +2298,7 @@ define i64 @imm_12900936431479() {
; RV64IZBA-LABEL: imm_12900936431479:
; RV64IZBA: # %bb.0:
; RV64IZBA-NEXT: lui a0, 768956
; RV64IZBA-NEXT: addiw a0, a0, -1093
; RV64IZBA-NEXT: addi a0, a0, -1093
; RV64IZBA-NEXT: slli.uw a0, a0, 12
; RV64IZBA-NEXT: addi a0, a0, 1911
; RV64IZBA-NEXT: ret
Expand Down Expand Up @@ -2353,7 +2353,7 @@ define i64 @imm_12900918536874() {
; RV64IZBA-LABEL: imm_12900918536874:
; RV64IZBA: # %bb.0:
; RV64IZBA-NEXT: lui a0, 768955
; RV64IZBA-NEXT: addiw a0, a0, -1365
; RV64IZBA-NEXT: addi a0, a0, -1365
; RV64IZBA-NEXT: slli.uw a0, a0, 12
; RV64IZBA-NEXT: addi a0, a0, -1366
; RV64IZBA-NEXT: ret
Expand Down Expand Up @@ -2408,7 +2408,7 @@ define i64 @imm_12900925247761() {
; RV64IZBA-LABEL: imm_12900925247761:
; RV64IZBA: # %bb.0:
; RV64IZBA-NEXT: lui a0, 768955
; RV64IZBA-NEXT: addiw a0, a0, 273
; RV64IZBA-NEXT: addi a0, a0, 273
; RV64IZBA-NEXT: slli.uw a0, a0, 12
; RV64IZBA-NEXT: addi a0, a0, 273
; RV64IZBA-NEXT: ret
Expand Down Expand Up @@ -3030,7 +3030,7 @@ define i64 @imm64_same_lo_hi_negative() nounwind {
; RV64IZBA-LABEL: imm64_same_lo_hi_negative:
; RV64IZBA: # %bb.0:
; RV64IZBA-NEXT: lui a0, 526344
; RV64IZBA-NEXT: addiw a0, a0, 128
; RV64IZBA-NEXT: addi a0, a0, 128
; RV64IZBA-NEXT: slli a1, a0, 32
; RV64IZBA-NEXT: add.uw a0, a0, a1
; RV64IZBA-NEXT: ret
Expand Down
36 changes: 18 additions & 18 deletions llvm/test/CodeGen/RISCV/lack-of-signed-truncation-check.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -264,7 +264,7 @@ define i1 @add_ultcmp_i16_i8(i16 %x) nounwind {
;
; RV64-LABEL: add_ultcmp_i16_i8:
; RV64: # %bb.0:
; RV64-NEXT: addiw a0, a0, -128
; RV64-NEXT: addi a0, a0, -128
; RV64-NEXT: slli a0, a0, 48
; RV64-NEXT: srli a0, a0, 56
; RV64-NEXT: sltiu a0, a0, 255
Expand Down Expand Up @@ -431,7 +431,7 @@ define i1 @add_ulecmp_i16_i8(i16 %x) nounwind {
;
; RV64-LABEL: add_ulecmp_i16_i8:
; RV64: # %bb.0:
; RV64-NEXT: addiw a0, a0, -128
; RV64-NEXT: addi a0, a0, -128
; RV64-NEXT: slli a0, a0, 48
; RV64-NEXT: srli a0, a0, 56
; RV64-NEXT: sltiu a0, a0, 255
Expand All @@ -457,7 +457,7 @@ define i1 @add_ugecmp_i16_i8(i16 %x) nounwind {
;
; RV64I-LABEL: add_ugecmp_i16_i8:
; RV64I: # %bb.0:
; RV64I-NEXT: addiw a0, a0, 128
; RV64I-NEXT: addi a0, a0, 128
; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srli a0, a0, 48
; RV64I-NEXT: sltiu a0, a0, 256
Expand All @@ -474,7 +474,7 @@ define i1 @add_ugecmp_i16_i8(i16 %x) nounwind {
;
; RV64ZBB-LABEL: add_ugecmp_i16_i8:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: addiw a0, a0, 128
; RV64ZBB-NEXT: addi a0, a0, 128
; RV64ZBB-NEXT: zext.h a0, a0
; RV64ZBB-NEXT: sltiu a0, a0, 256
; RV64ZBB-NEXT: xori a0, a0, 1
Expand Down Expand Up @@ -645,7 +645,7 @@ define i1 @add_ugtcmp_i16_i8(i16 %x) nounwind {
;
; RV64I-LABEL: add_ugtcmp_i16_i8:
; RV64I: # %bb.0:
; RV64I-NEXT: addiw a0, a0, 128
; RV64I-NEXT: addi a0, a0, 128
; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srli a0, a0, 48
; RV64I-NEXT: sltiu a0, a0, 256
Expand All @@ -662,7 +662,7 @@ define i1 @add_ugtcmp_i16_i8(i16 %x) nounwind {
;
; RV64ZBB-LABEL: add_ugtcmp_i16_i8:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: addiw a0, a0, 128
; RV64ZBB-NEXT: addi a0, a0, 128
; RV64ZBB-NEXT: zext.h a0, a0
; RV64ZBB-NEXT: sltiu a0, a0, 256
; RV64ZBB-NEXT: xori a0, a0, 1
Expand Down Expand Up @@ -751,7 +751,7 @@ define i1 @add_ugecmp_bad_i16_i8_cmp(i16 %x, i16 %y) nounwind {
; RV64ZBB-LABEL: add_ugecmp_bad_i16_i8_cmp:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: zext.h a1, a1
; RV64ZBB-NEXT: addiw a0, a0, 128
; RV64ZBB-NEXT: addi a0, a0, 128
; RV64ZBB-NEXT: zext.h a0, a0
; RV64ZBB-NEXT: sltu a0, a0, a1
; RV64ZBB-NEXT: xori a0, a0, 1
Expand All @@ -774,7 +774,7 @@ define i1 @add_ugecmp_bad_i8_i16(i16 %x) nounwind {
;
; RV64I-LABEL: add_ugecmp_bad_i8_i16:
; RV64I: # %bb.0:
; RV64I-NEXT: addiw a0, a0, 128
; RV64I-NEXT: addi a0, a0, 128
; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srli a0, a0, 48
; RV64I-NEXT: sltiu a0, a0, 128
Expand All @@ -791,7 +791,7 @@ define i1 @add_ugecmp_bad_i8_i16(i16 %x) nounwind {
;
; RV64ZBB-LABEL: add_ugecmp_bad_i8_i16:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: addiw a0, a0, 128
; RV64ZBB-NEXT: addi a0, a0, 128
; RV64ZBB-NEXT: zext.h a0, a0
; RV64ZBB-NEXT: sltiu a0, a0, 128
; RV64ZBB-NEXT: xori a0, a0, 1
Expand All @@ -814,7 +814,7 @@ define i1 @add_ugecmp_bad_i16_i8_c0notpoweroftwo(i16 %x) nounwind {
;
; RV64I-LABEL: add_ugecmp_bad_i16_i8_c0notpoweroftwo:
; RV64I: # %bb.0:
; RV64I-NEXT: addiw a0, a0, 192
; RV64I-NEXT: addi a0, a0, 192
; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srli a0, a0, 48
; RV64I-NEXT: sltiu a0, a0, 256
Expand All @@ -831,7 +831,7 @@ define i1 @add_ugecmp_bad_i16_i8_c0notpoweroftwo(i16 %x) nounwind {
;
; RV64ZBB-LABEL: add_ugecmp_bad_i16_i8_c0notpoweroftwo:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: addiw a0, a0, 192
; RV64ZBB-NEXT: addi a0, a0, 192
; RV64ZBB-NEXT: zext.h a0, a0
; RV64ZBB-NEXT: sltiu a0, a0, 256
; RV64ZBB-NEXT: xori a0, a0, 1
Expand All @@ -854,7 +854,7 @@ define i1 @add_ugecmp_bad_i16_i8_c1notpoweroftwo(i16 %x) nounwind {
;
; RV64I-LABEL: add_ugecmp_bad_i16_i8_c1notpoweroftwo:
; RV64I: # %bb.0:
; RV64I-NEXT: addiw a0, a0, 128
; RV64I-NEXT: addi a0, a0, 128
; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srli a0, a0, 48
; RV64I-NEXT: sltiu a0, a0, 768
Expand All @@ -871,7 +871,7 @@ define i1 @add_ugecmp_bad_i16_i8_c1notpoweroftwo(i16 %x) nounwind {
;
; RV64ZBB-LABEL: add_ugecmp_bad_i16_i8_c1notpoweroftwo:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: addiw a0, a0, 128
; RV64ZBB-NEXT: addi a0, a0, 128
; RV64ZBB-NEXT: zext.h a0, a0
; RV64ZBB-NEXT: sltiu a0, a0, 768
; RV64ZBB-NEXT: xori a0, a0, 1
Expand All @@ -894,7 +894,7 @@ define i1 @add_ugecmp_bad_i16_i8_magic(i16 %x) nounwind {
;
; RV64I-LABEL: add_ugecmp_bad_i16_i8_magic:
; RV64I: # %bb.0:
; RV64I-NEXT: addiw a0, a0, 64
; RV64I-NEXT: addi a0, a0, 64
; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srli a0, a0, 48
; RV64I-NEXT: sltiu a0, a0, 256
Expand All @@ -911,7 +911,7 @@ define i1 @add_ugecmp_bad_i16_i8_magic(i16 %x) nounwind {
;
; RV64ZBB-LABEL: add_ugecmp_bad_i16_i8_magic:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: addiw a0, a0, 64
; RV64ZBB-NEXT: addi a0, a0, 64
; RV64ZBB-NEXT: zext.h a0, a0
; RV64ZBB-NEXT: sltiu a0, a0, 256
; RV64ZBB-NEXT: xori a0, a0, 1
Expand All @@ -934,7 +934,7 @@ define i1 @add_ugecmp_bad_i16_i4(i16 %x) nounwind {
;
; RV64I-LABEL: add_ugecmp_bad_i16_i4:
; RV64I: # %bb.0:
; RV64I-NEXT: addiw a0, a0, 8
; RV64I-NEXT: addi a0, a0, 8
; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srli a0, a0, 48
; RV64I-NEXT: sltiu a0, a0, 16
Expand All @@ -951,7 +951,7 @@ define i1 @add_ugecmp_bad_i16_i4(i16 %x) nounwind {
;
; RV64ZBB-LABEL: add_ugecmp_bad_i16_i4:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: addiw a0, a0, 8
; RV64ZBB-NEXT: addi a0, a0, 8
; RV64ZBB-NEXT: zext.h a0, a0
; RV64ZBB-NEXT: sltiu a0, a0, 16
; RV64ZBB-NEXT: xori a0, a0, 1
Expand All @@ -974,7 +974,7 @@ define i1 @add_ugecmp_bad_i24_i8(i24 %x) nounwind {
;
; RV64-LABEL: add_ugecmp_bad_i24_i8:
; RV64: # %bb.0:
; RV64-NEXT: addiw a0, a0, 128
; RV64-NEXT: addi a0, a0, 128
; RV64-NEXT: slli a0, a0, 40
; RV64-NEXT: srli a0, a0, 40
; RV64-NEXT: sltiu a0, a0, 256
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/machine-outliner-throw.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@ define i32 @func1(i32 %x) #0 {
; CHECK-NEXT: .cfi_offset ra, -8
; CHECK-NEXT: .cfi_offset s0, -16
; CHECK-NEXT: mul a0, a0, a0
; CHECK-NEXT: addiw s0, a0, 1
; CHECK-NEXT: addi s0, a0, 1
; CHECK-NEXT: li a0, 4
; CHECK-NEXT: call __cxa_allocate_exception@plt
; CHECK-NEXT: sw s0, 0(a0)
Expand All @@ -40,7 +40,7 @@ define i32 @func2(i32 %x) #0 {
; CHECK-NEXT: .cfi_offset ra, -8
; CHECK-NEXT: .cfi_offset s0, -16
; CHECK-NEXT: mul a0, a0, a0
; CHECK-NEXT: addiw s0, a0, 1
; CHECK-NEXT: addi s0, a0, 1
; CHECK-NEXT: li a0, 4
; CHECK-NEXT: call __cxa_allocate_exception@plt
; CHECK-NEXT: sw s0, 0(a0)
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/RISCV/memcpy.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -167,7 +167,7 @@ define void @t2(ptr nocapture %C) nounwind {
; RV64-FAST-NEXT: ld a2, %lo(.L.str2)(a1)
; RV64-FAST-NEXT: sd a2, 0(a0)
; RV64-FAST-NEXT: lui a2, 1156
; RV64-FAST-NEXT: addiw a2, a2, 332
; RV64-FAST-NEXT: addi a2, a2, 332
; RV64-FAST-NEXT: addi a1, a1, %lo(.L.str2)
; RV64-FAST-NEXT: ld a3, 24(a1)
; RV64-FAST-NEXT: ld a4, 16(a1)
Expand Down Expand Up @@ -332,10 +332,10 @@ define void @t5(ptr nocapture %C) nounwind {
; RV64-FAST-LABEL: t5:
; RV64-FAST: # %bb.0: # %entry
; RV64-FAST-NEXT: lui a1, 1349
; RV64-FAST-NEXT: addiw a1, a1, 857
; RV64-FAST-NEXT: addi a1, a1, 857
; RV64-FAST-NEXT: sw a1, 3(a0)
; RV64-FAST-NEXT: lui a1, 365861
; RV64-FAST-NEXT: addiw a1, a1, -1980
; RV64-FAST-NEXT: addi a1, a1, -1980
; RV64-FAST-NEXT: sw a1, 0(a0)
; RV64-FAST-NEXT: ret
entry:
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/RISCV/overflow-intrinsics.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -551,7 +551,7 @@ define i1 @uaddo_i8_increment_noncanonical_1(i8 %x, ptr %p) {
;
; RV64-LABEL: uaddo_i8_increment_noncanonical_1:
; RV64: # %bb.0:
; RV64-NEXT: addiw a2, a0, 1
; RV64-NEXT: addi a2, a0, 1
; RV64-NEXT: andi a0, a2, 255
; RV64-NEXT: seqz a0, a0
; RV64-NEXT: sb a2, 0(a1)
Expand Down Expand Up @@ -594,7 +594,7 @@ define i1 @uaddo_i16_increment_noncanonical_3(i16 %x, ptr %p) {
;
; RV64-LABEL: uaddo_i16_increment_noncanonical_3:
; RV64: # %bb.0:
; RV64-NEXT: addiw a2, a0, 1
; RV64-NEXT: addi a2, a0, 1
; RV64-NEXT: slli a0, a2, 48
; RV64-NEXT: srli a0, a0, 48
; RV64-NEXT: seqz a0, a0
Expand Down Expand Up @@ -672,7 +672,7 @@ define i1 @uaddo_i32_decrement_alt(i32 signext %x, ptr %p) {
; RV64-LABEL: uaddo_i32_decrement_alt:
; RV64: # %bb.0:
; RV64-NEXT: snez a2, a0
; RV64-NEXT: addiw a0, a0, -1
; RV64-NEXT: addi a0, a0, -1
; RV64-NEXT: sw a0, 0(a1)
; RV64-NEXT: mv a0, a2
; RV64-NEXT: ret
Expand Down Expand Up @@ -915,7 +915,7 @@ define i1 @usubo_ult_constant_op1_i16(i16 %x, ptr %p) {
; RV64: # %bb.0:
; RV64-NEXT: slli a2, a0, 48
; RV64-NEXT: srli a2, a2, 48
; RV64-NEXT: addiw a3, a0, -44
; RV64-NEXT: addi a3, a0, -44
; RV64-NEXT: sltiu a0, a2, 44
; RV64-NEXT: sh a3, 0(a1)
; RV64-NEXT: ret
Expand All @@ -939,7 +939,7 @@ define i1 @usubo_ugt_constant_op1_i8(i8 %x, ptr %p) {
; RV64: # %bb.0:
; RV64-NEXT: andi a2, a0, 255
; RV64-NEXT: sltiu a2, a2, 45
; RV64-NEXT: addiw a0, a0, -45
; RV64-NEXT: addi a0, a0, -45
; RV64-NEXT: sb a0, 0(a1)
; RV64-NEXT: mv a0, a2
; RV64-NEXT: ret
Expand All @@ -962,7 +962,7 @@ define i1 @usubo_eq_constant1_op1_i32(i32 %x, ptr %p) {
; RV64-LABEL: usubo_eq_constant1_op1_i32:
; RV64: # %bb.0:
; RV64-NEXT: sext.w a2, a0
; RV64-NEXT: addiw a3, a0, -1
; RV64-NEXT: addi a3, a0, -1
; RV64-NEXT: seqz a0, a2
; RV64-NEXT: sw a3, 0(a1)
; RV64-NEXT: ret
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/rem.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -578,7 +578,7 @@ define i16 @urem16(i16 %a, i16 %b) nounwind {
; RV64IM-LABEL: urem16:
; RV64IM: # %bb.0:
; RV64IM-NEXT: lui a2, 16
; RV64IM-NEXT: addiw a2, a2, -1
; RV64IM-NEXT: addi a2, a2, -1
; RV64IM-NEXT: and a1, a1, a2
; RV64IM-NEXT: and a0, a0, a2
; RV64IM-NEXT: remuw a0, a0, a1
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/riscv-codegenprepare-asm.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@ define void @test1(ptr nocapture noundef %a, i32 noundef signext %n) {
; CHECK-NEXT: .LBB0_1: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lw a2, 0(a0)
; CHECK-NEXT: addiw a2, a2, 4
; CHECK-NEXT: addi a2, a2, 4
; CHECK-NEXT: sw a2, 0(a0)
; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: addi a0, a0, 4
Expand Down Expand Up @@ -62,9 +62,9 @@ define void @test2(ptr nocapture noundef %a, i32 noundef signext %n) {
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lw a5, -4(a4)
; CHECK-NEXT: lw a6, 0(a4)
; CHECK-NEXT: addiw a5, a5, 4
; CHECK-NEXT: addi a5, a5, 4
; CHECK-NEXT: sw a5, -4(a4)
; CHECK-NEXT: addiw a6, a6, 4
; CHECK-NEXT: addi a6, a6, 4
; CHECK-NEXT: sw a6, 0(a4)
; CHECK-NEXT: addi a3, a3, 2
; CHECK-NEXT: addi a4, a4, 8
Expand All @@ -75,7 +75,7 @@ define void @test2(ptr nocapture noundef %a, i32 noundef signext %n) {
; CHECK-NEXT: slli a3, a3, 2
; CHECK-NEXT: add a0, a0, a3
; CHECK-NEXT: lw a1, 0(a0)
; CHECK-NEXT: addiw a1, a1, 4
; CHECK-NEXT: addi a1, a1, 4
; CHECK-NEXT: sw a1, 0(a0)
; CHECK-NEXT: .LBB1_7: # %for.cond.cleanup
; CHECK-NEXT: ret
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9,10 +9,10 @@ define i32 @foo(i32 %x, i32 %y, i32 %z) {
; CHECK-LABEL: foo:
; CHECK: # %bb.0:
; CHECK-NEXT: mul a0, a0, a0
; CHECK-NEXT: addiw a0, a0, 1
; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: mul a0, a0, a0
; CHECK-NEXT: add a0, a0, a2
; CHECK-NEXT: addiw a0, a0, 1
; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: sllw a0, a0, a1
; CHECK-NEXT: ret
%b = mul i32 %x, %x
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1659,14 +1659,14 @@ define signext i32 @sext_addiw_zext(i32 zeroext %a) nounwind {
define zeroext i32 @zext_addiw_aext(i32 %a) nounwind {
; RV64I-LABEL: zext_addiw_aext:
; RV64I: # %bb.0:
; RV64I-NEXT: addiw a0, a0, 7
; RV64I-NEXT: addi a0, a0, 7
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
;
; RV64ZBA-LABEL: zext_addiw_aext:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: addiw a0, a0, 7
; RV64ZBA-NEXT: addi a0, a0, 7
; RV64ZBA-NEXT: zext.w a0, a0
; RV64ZBA-NEXT: ret
%1 = add i32 %a, 7
Expand All @@ -1676,14 +1676,14 @@ define zeroext i32 @zext_addiw_aext(i32 %a) nounwind {
define zeroext i32 @zext_addiw_sext(i32 signext %a) nounwind {
; RV64I-LABEL: zext_addiw_sext:
; RV64I: # %bb.0:
; RV64I-NEXT: addiw a0, a0, 8
; RV64I-NEXT: addi a0, a0, 8
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
;
; RV64ZBA-LABEL: zext_addiw_sext:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: addiw a0, a0, 8
; RV64ZBA-NEXT: addi a0, a0, 8
; RV64ZBA-NEXT: zext.w a0, a0
; RV64ZBA-NEXT: ret
%1 = add i32 %a, 8
Expand All @@ -1693,14 +1693,14 @@ define zeroext i32 @zext_addiw_sext(i32 signext %a) nounwind {
define zeroext i32 @zext_addiw_zext(i32 zeroext %a) nounwind {
; RV64I-LABEL: zext_addiw_zext:
; RV64I: # %bb.0:
; RV64I-NEXT: addiw a0, a0, 9
; RV64I-NEXT: addi a0, a0, 9
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
;
; RV64ZBA-LABEL: zext_addiw_zext:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: addiw a0, a0, 9
; RV64ZBA-NEXT: addi a0, a0, 9
; RV64ZBA-NEXT: zext.w a0, a0
; RV64ZBA-NEXT: ret
%1 = add i32 %a, 9
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/rv64i-shift-sext.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -113,7 +113,7 @@ define signext i32 @test9(ptr %0, i64 %1) {
; RV64I-LABEL: test9:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a2, 1
; RV64I-NEXT: addiw a2, a2, 1
; RV64I-NEXT: addi a2, a2, 1
; RV64I-NEXT: addw a1, a1, a2
; RV64I-NEXT: slli a1, a1, 2
; RV64I-NEXT: add a0, a0, a1
Expand All @@ -133,7 +133,7 @@ define signext i32 @test10(ptr %0, i64 %1) {
; RV64I-LABEL: test10:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a2, 30141
; RV64I-NEXT: addiw a2, a2, -747
; RV64I-NEXT: addi a2, a2, -747
; RV64I-NEXT: subw a2, a2, a1
; RV64I-NEXT: slli a2, a2, 2
; RV64I-NEXT: add a0, a0, a2
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/RISCV/rv64i-w-insts-legalization.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,10 +8,10 @@ define signext i32 @addw(i32 signext %s, i32 signext %n, i32 signext %k) nounwin
; CHECK-NEXT: # %bb.1: # %for.body.preheader
; CHECK-NEXT: not a2, a0
; CHECK-NEXT: add a2, a2, a1
; CHECK-NEXT: addiw a3, a0, 1
; CHECK-NEXT: addi a3, a0, 1
; CHECK-NEXT: mul a3, a2, a3
; CHECK-NEXT: subw a1, a1, a0
; CHECK-NEXT: addiw a1, a1, -2
; CHECK-NEXT: addi a1, a1, -2
; CHECK-NEXT: slli a1, a1, 32
; CHECK-NEXT: slli a2, a2, 32
; CHECK-NEXT: mulhu a1, a2, a1
Expand Down Expand Up @@ -56,7 +56,7 @@ define signext i32 @subw(i32 signext %s, i32 signext %n, i32 signext %k) nounwin
; CHECK-NEXT: add a3, a2, a1
; CHECK-NEXT: mul a2, a3, a2
; CHECK-NEXT: subw a1, a1, a0
; CHECK-NEXT: addiw a1, a1, -2
; CHECK-NEXT: addi a1, a1, -2
; CHECK-NEXT: slli a1, a1, 32
; CHECK-NEXT: slli a3, a3, 32
; CHECK-NEXT: mulhu a1, a3, a1
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -173,7 +173,7 @@ define signext i32 @log2_ceil_i32(i32 signext %a) nounwind {
;
; RV64XTHEADBB-LABEL: log2_ceil_i32:
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: addiw a0, a0, -1
; RV64XTHEADBB-NEXT: addi a0, a0, -1
; RV64XTHEADBB-NEXT: not a0, a0
; RV64XTHEADBB-NEXT: slli a0, a0, 32
; RV64XTHEADBB-NEXT: th.ff0 a0, a0
Expand Down Expand Up @@ -774,7 +774,7 @@ define void @bswap_i32_nosext(i32 signext %a, ptr %x) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: srli a2, a0, 8
; RV64I-NEXT: lui a3, 16
; RV64I-NEXT: addiw a3, a3, -256
; RV64I-NEXT: addi a3, a3, -256
; RV64I-NEXT: and a2, a2, a3
; RV64I-NEXT: srliw a4, a0, 24
; RV64I-NEXT: or a2, a2, a4
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@ define signext i32 @orcb32_knownbits(i32 signext %a) nounwind {
; RV64ZBB-NEXT: lui a1, 1044480
; RV64ZBB-NEXT: and a0, a0, a1
; RV64ZBB-NEXT: lui a1, 2048
; RV64ZBB-NEXT: addiw a1, a1, 1
; RV64ZBB-NEXT: addi a1, a1, 1
; RV64ZBB-NEXT: or a0, a0, a1
; RV64ZBB-NEXT: orc.b a0, a0
; RV64ZBB-NEXT: sext.w a0, a0
Expand Down
20 changes: 10 additions & 10 deletions llvm/test/CodeGen/RISCV/rv64zbb.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -169,7 +169,7 @@ define signext i32 @log2_ceil_i32(i32 signext %a) nounwind {
;
; RV64ZBB-LABEL: log2_ceil_i32:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: addiw a0, a0, -1
; RV64ZBB-NEXT: addi a0, a0, -1
; RV64ZBB-NEXT: clzw a0, a0
; RV64ZBB-NEXT: li a1, 32
; RV64ZBB-NEXT: sub a0, a1, a0
Expand Down Expand Up @@ -768,11 +768,11 @@ define <2 x i32> @ctpop_v2i32(<2 x i32> %a) nounwind {
define <2 x i1> @ctpop_v2i32_ult_two(<2 x i32> %a) nounwind {
; RV64I-LABEL: ctpop_v2i32_ult_two:
; RV64I: # %bb.0:
; RV64I-NEXT: addiw a2, a0, -1
; RV64I-NEXT: addi a2, a0, -1
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: addiw a2, a1, -1
; RV64I-NEXT: addi a2, a1, -1
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: sext.w a1, a1
; RV64I-NEXT: seqz a1, a1
Expand All @@ -793,11 +793,11 @@ define <2 x i1> @ctpop_v2i32_ult_two(<2 x i32> %a) nounwind {
define <2 x i1> @ctpop_v2i32_ugt_one(<2 x i32> %a) nounwind {
; RV64I-LABEL: ctpop_v2i32_ugt_one:
; RV64I: # %bb.0:
; RV64I-NEXT: addiw a2, a0, -1
; RV64I-NEXT: addi a2, a0, -1
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: addiw a2, a1, -1
; RV64I-NEXT: addi a2, a1, -1
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: sext.w a1, a1
; RV64I-NEXT: snez a1, a1
Expand All @@ -822,13 +822,13 @@ define <2 x i1> @ctpop_v2i32_eq_one(<2 x i32> %a) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: sext.w a2, a1
; RV64I-NEXT: sext.w a3, a0
; RV64I-NEXT: addiw a4, a0, -1
; RV64I-NEXT: addi a4, a0, -1
; RV64I-NEXT: and a0, a0, a4
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: snez a3, a3
; RV64I-NEXT: and a0, a3, a0
; RV64I-NEXT: addiw a3, a1, -1
; RV64I-NEXT: addi a3, a1, -1
; RV64I-NEXT: and a1, a1, a3
; RV64I-NEXT: sext.w a1, a1
; RV64I-NEXT: seqz a1, a1
Expand All @@ -855,13 +855,13 @@ define <2 x i1> @ctpop_v2i32_ne_one(<2 x i32> %a) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: sext.w a2, a1
; RV64I-NEXT: sext.w a3, a0
; RV64I-NEXT: addiw a4, a0, -1
; RV64I-NEXT: addi a4, a0, -1
; RV64I-NEXT: and a0, a0, a4
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: seqz a3, a3
; RV64I-NEXT: or a0, a3, a0
; RV64I-NEXT: addiw a3, a1, -1
; RV64I-NEXT: addi a3, a1, -1
; RV64I-NEXT: and a1, a1, a3
; RV64I-NEXT: sext.w a1, a1
; RV64I-NEXT: snez a1, a1
Expand Down Expand Up @@ -1518,7 +1518,7 @@ define void @bswap_i32_nosext(i32 signext %a, ptr %x) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: srli a2, a0, 8
; RV64I-NEXT: lui a3, 16
; RV64I-NEXT: addiw a3, a3, -256
; RV64I-NEXT: addi a3, a3, -256
; RV64I-NEXT: and a2, a2, a3
; RV64I-NEXT: srliw a4, a0, 24
; RV64I-NEXT: or a2, a2, a4
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/rv64zbkb.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -303,7 +303,7 @@ define i64 @pack_i64_imm() {
; RV64ZBKB-LABEL: pack_i64_imm:
; RV64ZBKB: # %bb.0:
; RV64ZBKB-NEXT: lui a0, 65793
; RV64ZBKB-NEXT: addiw a0, a0, 16
; RV64ZBKB-NEXT: addi a0, a0, 16
; RV64ZBKB-NEXT: pack a0, a0, a0
; RV64ZBKB-NEXT: ret
ret i64 1157442765409226768 ; 0x0101010101010101
Expand Down
1,055 changes: 348 additions & 707 deletions llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
View file

Large diffs are not rendered by default.

2,655 changes: 881 additions & 1,774 deletions llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
View file

Large diffs are not rendered by default.

230 changes: 75 additions & 155 deletions llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -119,37 +119,21 @@ define <vscale x 32 x i16> @bswap_nxv32i16(<vscale x 32 x i16> %va) {
declare <vscale x 32 x i16> @llvm.bswap.nxv32i16(<vscale x 32 x i16>)

define <vscale x 1 x i32> @bswap_nxv1i32(<vscale x 1 x i32> %va) {
; RV32-LABEL: bswap_nxv1i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; RV32-NEXT: vsrl.vi v9, v8, 8
; RV32-NEXT: lui a0, 16
; RV32-NEXT: addi a0, a0, -256
; RV32-NEXT: vand.vx v9, v9, a0
; RV32-NEXT: vsrl.vi v10, v8, 24
; RV32-NEXT: vor.vv v9, v9, v10
; RV32-NEXT: vand.vx v10, v8, a0
; RV32-NEXT: vsll.vi v10, v10, 8
; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: vor.vv v8, v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: bswap_nxv1i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; RV64-NEXT: vsrl.vi v9, v8, 8
; RV64-NEXT: lui a0, 16
; RV64-NEXT: addiw a0, a0, -256
; RV64-NEXT: vand.vx v9, v9, a0
; RV64-NEXT: vsrl.vi v10, v8, 24
; RV64-NEXT: vor.vv v9, v9, v10
; RV64-NEXT: vand.vx v10, v8, a0
; RV64-NEXT: vsll.vi v10, v10, 8
; RV64-NEXT: vsll.vi v8, v8, 24
; RV64-NEXT: vor.vv v8, v8, v10
; RV64-NEXT: vor.vv v8, v8, v9
; RV64-NEXT: ret
; CHECK-LABEL: bswap_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 8
; CHECK-NEXT: lui a0, 16
; CHECK-NEXT: addi a0, a0, -256
; CHECK-NEXT: vand.vx v9, v9, a0
; CHECK-NEXT: vsrl.vi v10, v8, 24
; CHECK-NEXT: vor.vv v9, v9, v10
; CHECK-NEXT: vand.vx v10, v8, a0
; CHECK-NEXT: vsll.vi v10, v10, 8
; CHECK-NEXT: vsll.vi v8, v8, 24
; CHECK-NEXT: vor.vv v8, v8, v10
; CHECK-NEXT: vor.vv v8, v8, v9
; CHECK-NEXT: ret
;
; CHECK-ZVKB-LABEL: bswap_nxv1i32:
; CHECK-ZVKB: # %bb.0:
Expand All @@ -162,37 +146,21 @@ define <vscale x 1 x i32> @bswap_nxv1i32(<vscale x 1 x i32> %va) {
declare <vscale x 1 x i32> @llvm.bswap.nxv1i32(<vscale x 1 x i32>)

define <vscale x 2 x i32> @bswap_nxv2i32(<vscale x 2 x i32> %va) {
; RV32-LABEL: bswap_nxv2i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; RV32-NEXT: vsrl.vi v9, v8, 8
; RV32-NEXT: lui a0, 16
; RV32-NEXT: addi a0, a0, -256
; RV32-NEXT: vand.vx v9, v9, a0
; RV32-NEXT: vsrl.vi v10, v8, 24
; RV32-NEXT: vor.vv v9, v9, v10
; RV32-NEXT: vand.vx v10, v8, a0
; RV32-NEXT: vsll.vi v10, v10, 8
; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: vor.vv v8, v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: bswap_nxv2i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; RV64-NEXT: vsrl.vi v9, v8, 8
; RV64-NEXT: lui a0, 16
; RV64-NEXT: addiw a0, a0, -256
; RV64-NEXT: vand.vx v9, v9, a0
; RV64-NEXT: vsrl.vi v10, v8, 24
; RV64-NEXT: vor.vv v9, v9, v10
; RV64-NEXT: vand.vx v10, v8, a0
; RV64-NEXT: vsll.vi v10, v10, 8
; RV64-NEXT: vsll.vi v8, v8, 24
; RV64-NEXT: vor.vv v8, v8, v10
; RV64-NEXT: vor.vv v8, v8, v9
; RV64-NEXT: ret
; CHECK-LABEL: bswap_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 8
; CHECK-NEXT: lui a0, 16
; CHECK-NEXT: addi a0, a0, -256
; CHECK-NEXT: vand.vx v9, v9, a0
; CHECK-NEXT: vsrl.vi v10, v8, 24
; CHECK-NEXT: vor.vv v9, v9, v10
; CHECK-NEXT: vand.vx v10, v8, a0
; CHECK-NEXT: vsll.vi v10, v10, 8
; CHECK-NEXT: vsll.vi v8, v8, 24
; CHECK-NEXT: vor.vv v8, v8, v10
; CHECK-NEXT: vor.vv v8, v8, v9
; CHECK-NEXT: ret
;
; CHECK-ZVKB-LABEL: bswap_nxv2i32:
; CHECK-ZVKB: # %bb.0:
Expand All @@ -205,37 +173,21 @@ define <vscale x 2 x i32> @bswap_nxv2i32(<vscale x 2 x i32> %va) {
declare <vscale x 2 x i32> @llvm.bswap.nxv2i32(<vscale x 2 x i32>)

define <vscale x 4 x i32> @bswap_nxv4i32(<vscale x 4 x i32> %va) {
; RV32-LABEL: bswap_nxv4i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; RV32-NEXT: vsrl.vi v10, v8, 8
; RV32-NEXT: lui a0, 16
; RV32-NEXT: addi a0, a0, -256
; RV32-NEXT: vand.vx v10, v10, a0
; RV32-NEXT: vsrl.vi v12, v8, 24
; RV32-NEXT: vor.vv v10, v10, v12
; RV32-NEXT: vand.vx v12, v8, a0
; RV32-NEXT: vsll.vi v12, v12, 8
; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vor.vv v8, v8, v12
; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: bswap_nxv4i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; RV64-NEXT: vsrl.vi v10, v8, 8
; RV64-NEXT: lui a0, 16
; RV64-NEXT: addiw a0, a0, -256
; RV64-NEXT: vand.vx v10, v10, a0
; RV64-NEXT: vsrl.vi v12, v8, 24
; RV64-NEXT: vor.vv v10, v10, v12
; RV64-NEXT: vand.vx v12, v8, a0
; RV64-NEXT: vsll.vi v12, v12, 8
; RV64-NEXT: vsll.vi v8, v8, 24
; RV64-NEXT: vor.vv v8, v8, v12
; RV64-NEXT: vor.vv v8, v8, v10
; RV64-NEXT: ret
; CHECK-LABEL: bswap_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT: vsrl.vi v10, v8, 8
; CHECK-NEXT: lui a0, 16
; CHECK-NEXT: addi a0, a0, -256
; CHECK-NEXT: vand.vx v10, v10, a0
; CHECK-NEXT: vsrl.vi v12, v8, 24
; CHECK-NEXT: vor.vv v10, v10, v12
; CHECK-NEXT: vand.vx v12, v8, a0
; CHECK-NEXT: vsll.vi v12, v12, 8
; CHECK-NEXT: vsll.vi v8, v8, 24
; CHECK-NEXT: vor.vv v8, v8, v12
; CHECK-NEXT: vor.vv v8, v8, v10
; CHECK-NEXT: ret
;
; CHECK-ZVKB-LABEL: bswap_nxv4i32:
; CHECK-ZVKB: # %bb.0:
Expand All @@ -248,37 +200,21 @@ define <vscale x 4 x i32> @bswap_nxv4i32(<vscale x 4 x i32> %va) {
declare <vscale x 4 x i32> @llvm.bswap.nxv4i32(<vscale x 4 x i32>)

define <vscale x 8 x i32> @bswap_nxv8i32(<vscale x 8 x i32> %va) {
; RV32-LABEL: bswap_nxv8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; RV32-NEXT: vsrl.vi v12, v8, 8
; RV32-NEXT: lui a0, 16
; RV32-NEXT: addi a0, a0, -256
; RV32-NEXT: vand.vx v12, v12, a0
; RV32-NEXT: vsrl.vi v16, v8, 24
; RV32-NEXT: vor.vv v12, v12, v16
; RV32-NEXT: vand.vx v16, v8, a0
; RV32-NEXT: vsll.vi v16, v16, 8
; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: vor.vv v8, v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: bswap_nxv8i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; RV64-NEXT: vsrl.vi v12, v8, 8
; RV64-NEXT: lui a0, 16
; RV64-NEXT: addiw a0, a0, -256
; RV64-NEXT: vand.vx v12, v12, a0
; RV64-NEXT: vsrl.vi v16, v8, 24
; RV64-NEXT: vor.vv v12, v12, v16
; RV64-NEXT: vand.vx v16, v8, a0
; RV64-NEXT: vsll.vi v16, v16, 8
; RV64-NEXT: vsll.vi v8, v8, 24
; RV64-NEXT: vor.vv v8, v8, v16
; RV64-NEXT: vor.vv v8, v8, v12
; RV64-NEXT: ret
; CHECK-LABEL: bswap_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vsrl.vi v12, v8, 8
; CHECK-NEXT: lui a0, 16
; CHECK-NEXT: addi a0, a0, -256
; CHECK-NEXT: vand.vx v12, v12, a0
; CHECK-NEXT: vsrl.vi v16, v8, 24
; CHECK-NEXT: vor.vv v12, v12, v16
; CHECK-NEXT: vand.vx v16, v8, a0
; CHECK-NEXT: vsll.vi v16, v16, 8
; CHECK-NEXT: vsll.vi v8, v8, 24
; CHECK-NEXT: vor.vv v8, v8, v16
; CHECK-NEXT: vor.vv v8, v8, v12
; CHECK-NEXT: ret
;
; CHECK-ZVKB-LABEL: bswap_nxv8i32:
; CHECK-ZVKB: # %bb.0:
Expand All @@ -291,37 +227,21 @@ define <vscale x 8 x i32> @bswap_nxv8i32(<vscale x 8 x i32> %va) {
declare <vscale x 8 x i32> @llvm.bswap.nxv8i32(<vscale x 8 x i32>)

define <vscale x 16 x i32> @bswap_nxv16i32(<vscale x 16 x i32> %va) {
; RV32-LABEL: bswap_nxv16i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; RV32-NEXT: vsrl.vi v16, v8, 8
; RV32-NEXT: lui a0, 16
; RV32-NEXT: addi a0, a0, -256
; RV32-NEXT: vand.vx v16, v16, a0
; RV32-NEXT: vsrl.vi v24, v8, 24
; RV32-NEXT: vor.vv v16, v16, v24
; RV32-NEXT: vand.vx v24, v8, a0
; RV32-NEXT: vsll.vi v24, v24, 8
; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vor.vv v8, v8, v24
; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: ret
;
; RV64-LABEL: bswap_nxv16i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; RV64-NEXT: vsrl.vi v16, v8, 8
; RV64-NEXT: lui a0, 16
; RV64-NEXT: addiw a0, a0, -256
; RV64-NEXT: vand.vx v16, v16, a0
; RV64-NEXT: vsrl.vi v24, v8, 24
; RV64-NEXT: vor.vv v16, v16, v24
; RV64-NEXT: vand.vx v24, v8, a0
; RV64-NEXT: vsll.vi v24, v24, 8
; RV64-NEXT: vsll.vi v8, v8, 24
; RV64-NEXT: vor.vv v8, v8, v24
; RV64-NEXT: vor.vv v8, v8, v16
; RV64-NEXT: ret
; CHECK-LABEL: bswap_nxv16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-NEXT: vsrl.vi v16, v8, 8
; CHECK-NEXT: lui a0, 16
; CHECK-NEXT: addi a0, a0, -256
; CHECK-NEXT: vand.vx v16, v16, a0
; CHECK-NEXT: vsrl.vi v24, v8, 24
; CHECK-NEXT: vor.vv v16, v16, v24
; CHECK-NEXT: vand.vx v24, v8, a0
; CHECK-NEXT: vsll.vi v24, v24, 8
; CHECK-NEXT: vsll.vi v8, v8, 24
; CHECK-NEXT: vor.vv v8, v8, v24
; CHECK-NEXT: vor.vv v8, v8, v16
; CHECK-NEXT: ret
;
; CHECK-ZVKB-LABEL: bswap_nxv16i32:
; CHECK-ZVKB: # %bb.0:
Expand Down
460 changes: 150 additions & 310 deletions llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
View file

Large diffs are not rendered by default.

47 changes: 17 additions & 30 deletions llvm/test/CodeGen/RISCV/rvv/combine-sats.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -173,43 +173,27 @@ define <vscale x 2 x i64> @vselect_add_const_nxv2i64(<vscale x 2 x i64> %a0) {
}

define <2 x i16> @vselect_add_const_signbit_v2i16(<2 x i16> %a0) {
; RV32-LABEL: vselect_add_const_signbit_v2i16:
; RV32: # %bb.0:
; RV32-NEXT: lui a0, 8
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; RV32-NEXT: vssubu.vx v8, v8, a0
; RV32-NEXT: ret
;
; RV64-LABEL: vselect_add_const_signbit_v2i16:
; RV64: # %bb.0:
; RV64-NEXT: lui a0, 8
; RV64-NEXT: addiw a0, a0, -1
; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; RV64-NEXT: vssubu.vx v8, v8, a0
; RV64-NEXT: ret
; CHECK-LABEL: vselect_add_const_signbit_v2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, 8
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%cmp = icmp ugt <2 x i16> %a0, <i16 32766, i16 32766>
%v1 = add <2 x i16> %a0, <i16 -32767, i16 -32767>
%v2 = select <2 x i1> %cmp, <2 x i16> %v1, <2 x i16> zeroinitializer
ret <2 x i16> %v2
}

define <vscale x 2 x i16> @vselect_add_const_signbit_nxv2i16(<vscale x 2 x i16> %a0) {
; RV32-LABEL: vselect_add_const_signbit_nxv2i16:
; RV32: # %bb.0:
; RV32-NEXT: lui a0, 8
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
; RV32-NEXT: vssubu.vx v8, v8, a0
; RV32-NEXT: ret
;
; RV64-LABEL: vselect_add_const_signbit_nxv2i16:
; RV64: # %bb.0:
; RV64-NEXT: lui a0, 8
; RV64-NEXT: addiw a0, a0, -1
; RV64-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
; RV64-NEXT: vssubu.vx v8, v8, a0
; RV64-NEXT: ret
; CHECK-LABEL: vselect_add_const_signbit_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, 8
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
; CHECK-NEXT: vssubu.vx v8, v8, a0
; CHECK-NEXT: ret
%cm1 = insertelement <vscale x 2 x i16> poison, i16 32766, i32 0
%splatcm1 = shufflevector <vscale x 2 x i16> %cm1, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
%nc = insertelement <vscale x 2 x i16> poison, i16 -32767, i32 0
Expand Down Expand Up @@ -318,3 +302,6 @@ declare <2 x i64> @llvm.umin.v2i64(<2 x i64>, <2 x i64>)
declare <2 x i64> @llvm.umax.v2i64(<2 x i64>, <2 x i64>)
declare <vscale x 2 x i64> @llvm.umin.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
declare <vscale x 2 x i64> @llvm.umax.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; RV32: {{.*}}
; RV64: {{.*}}
2,237 changes: 742 additions & 1,495 deletions llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
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391 changes: 131 additions & 260 deletions llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
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785 changes: 258 additions & 527 deletions llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll
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1,649 changes: 542 additions & 1,107 deletions llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
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1,919 changes: 648 additions & 1,271 deletions llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
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2,086 changes: 687 additions & 1,399 deletions llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -769,7 +769,7 @@ define i32 @extractelt_sdiv_nxv4i32_splat(<vscale x 4 x i32> %x) {
; RV64NOM-LABEL: extractelt_sdiv_nxv4i32_splat:
; RV64NOM: # %bb.0:
; RV64NOM-NEXT: lui a0, 349525
; RV64NOM-NEXT: addiw a0, a0, 1366
; RV64NOM-NEXT: addi a0, a0, 1366
; RV64NOM-NEXT: vsetvli a1, zero, e32, m2, ta, ma
; RV64NOM-NEXT: vmulh.vx v8, v8, a0
; RV64NOM-NEXT: vsrl.vi v10, v8, 31
Expand Down Expand Up @@ -799,7 +799,7 @@ define i32 @extractelt_udiv_nxv4i32_splat(<vscale x 4 x i32> %x) {
; RV64NOM-LABEL: extractelt_udiv_nxv4i32_splat:
; RV64NOM: # %bb.0:
; RV64NOM-NEXT: lui a0, 349525
; RV64NOM-NEXT: addiw a0, a0, 1366
; RV64NOM-NEXT: addi a0, a0, 1366
; RV64NOM-NEXT: vsetvli a1, zero, e32, m2, ta, ma
; RV64NOM-NEXT: vmulh.vx v8, v8, a0
; RV64NOM-NEXT: vsrl.vi v10, v8, 31
Expand Down
2,005 changes: 667 additions & 1,338 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
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42 changes: 21 additions & 21 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -47,21 +47,21 @@ define void @bitreverse_v8i16(ptr %x, ptr %y) {
; RV64-NEXT: vor.vv v8, v8, v9
; RV64-NEXT: vsrl.vi v9, v8, 4
; RV64-NEXT: lui a1, 1
; RV64-NEXT: addiw a1, a1, -241
; RV64-NEXT: addi a1, a1, -241
; RV64-NEXT: vand.vx v9, v9, a1
; RV64-NEXT: vand.vx v8, v8, a1
; RV64-NEXT: vsll.vi v8, v8, 4
; RV64-NEXT: vor.vv v8, v9, v8
; RV64-NEXT: vsrl.vi v9, v8, 2
; RV64-NEXT: lui a1, 3
; RV64-NEXT: addiw a1, a1, 819
; RV64-NEXT: addi a1, a1, 819
; RV64-NEXT: vand.vx v9, v9, a1
; RV64-NEXT: vand.vx v8, v8, a1
; RV64-NEXT: vsll.vi v8, v8, 2
; RV64-NEXT: vor.vv v8, v9, v8
; RV64-NEXT: vsrl.vi v9, v8, 1
; RV64-NEXT: lui a1, 5
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: vand.vx v9, v9, a1
; RV64-NEXT: vand.vx v8, v8, a1
; RV64-NEXT: vadd.vv v8, v8, v8
Expand Down Expand Up @@ -130,7 +130,7 @@ define void @bitreverse_v4i32(ptr %x, ptr %y) {
; RV64-NEXT: vle32.v v8, (a0)
; RV64-NEXT: vsrl.vi v9, v8, 8
; RV64-NEXT: lui a1, 16
; RV64-NEXT: addiw a1, a1, -256
; RV64-NEXT: addi a1, a1, -256
; RV64-NEXT: vand.vx v9, v9, a1
; RV64-NEXT: vsrl.vi v10, v8, 24
; RV64-NEXT: vor.vv v9, v9, v10
Expand All @@ -141,21 +141,21 @@ define void @bitreverse_v4i32(ptr %x, ptr %y) {
; RV64-NEXT: vor.vv v8, v8, v9
; RV64-NEXT: vsrl.vi v9, v8, 4
; RV64-NEXT: lui a1, 61681
; RV64-NEXT: addiw a1, a1, -241
; RV64-NEXT: addi a1, a1, -241
; RV64-NEXT: vand.vx v9, v9, a1
; RV64-NEXT: vand.vx v8, v8, a1
; RV64-NEXT: vsll.vi v8, v8, 4
; RV64-NEXT: vor.vv v8, v9, v8
; RV64-NEXT: vsrl.vi v9, v8, 2
; RV64-NEXT: lui a1, 209715
; RV64-NEXT: addiw a1, a1, 819
; RV64-NEXT: addi a1, a1, 819
; RV64-NEXT: vand.vx v9, v9, a1
; RV64-NEXT: vand.vx v8, v8, a1
; RV64-NEXT: vsll.vi v8, v8, 2
; RV64-NEXT: vor.vv v8, v9, v8
; RV64-NEXT: vsrl.vi v9, v8, 1
; RV64-NEXT: lui a1, 349525
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: vand.vx v9, v9, a1
; RV64-NEXT: vand.vx v8, v8, a1
; RV64-NEXT: vadd.vv v8, v8, v8
Expand Down Expand Up @@ -368,21 +368,21 @@ define void @bitreverse_v16i16(ptr %x, ptr %y) {
; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v10
; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 4
; LMULMAX2-RV64-NEXT: lui a1, 1
; LMULMAX2-RV64-NEXT: addiw a1, a1, -241
; LMULMAX2-RV64-NEXT: addi a1, a1, -241
; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1
; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1
; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 4
; LMULMAX2-RV64-NEXT: vor.vv v8, v10, v8
; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 2
; LMULMAX2-RV64-NEXT: lui a1, 3
; LMULMAX2-RV64-NEXT: addiw a1, a1, 819
; LMULMAX2-RV64-NEXT: addi a1, a1, 819
; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1
; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1
; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 2
; LMULMAX2-RV64-NEXT: vor.vv v8, v10, v8
; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 1
; LMULMAX2-RV64-NEXT: lui a1, 5
; LMULMAX2-RV64-NEXT: addiw a1, a1, 1365
; LMULMAX2-RV64-NEXT: addi a1, a1, 1365
; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1
; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1
; LMULMAX2-RV64-NEXT: vadd.vv v8, v8, v8
Expand Down Expand Up @@ -453,21 +453,21 @@ define void @bitreverse_v16i16(ptr %x, ptr %y) {
; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 4
; LMULMAX1-RV64-NEXT: lui a2, 1
; LMULMAX1-RV64-NEXT: addiw a2, a2, -241
; LMULMAX1-RV64-NEXT: addi a2, a2, -241
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a2
; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 4
; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 2
; LMULMAX1-RV64-NEXT: lui a3, 3
; LMULMAX1-RV64-NEXT: addiw a3, a3, 819
; LMULMAX1-RV64-NEXT: addi a3, a3, 819
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a3
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a3
; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 2
; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 1
; LMULMAX1-RV64-NEXT: lui a4, 5
; LMULMAX1-RV64-NEXT: addiw a4, a4, 1365
; LMULMAX1-RV64-NEXT: addi a4, a4, 1365
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a4
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a4
; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v8
Expand Down Expand Up @@ -555,7 +555,7 @@ define void @bitreverse_v8i32(ptr %x, ptr %y) {
; LMULMAX2-RV64-NEXT: vle32.v v8, (a0)
; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 8
; LMULMAX2-RV64-NEXT: lui a1, 16
; LMULMAX2-RV64-NEXT: addiw a1, a1, -256
; LMULMAX2-RV64-NEXT: addi a1, a1, -256
; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1
; LMULMAX2-RV64-NEXT: vsrl.vi v12, v8, 24
; LMULMAX2-RV64-NEXT: vor.vv v10, v10, v12
Expand All @@ -566,21 +566,21 @@ define void @bitreverse_v8i32(ptr %x, ptr %y) {
; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v10
; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 4
; LMULMAX2-RV64-NEXT: lui a1, 61681
; LMULMAX2-RV64-NEXT: addiw a1, a1, -241
; LMULMAX2-RV64-NEXT: addi a1, a1, -241
; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1
; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1
; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 4
; LMULMAX2-RV64-NEXT: vor.vv v8, v10, v8
; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 2
; LMULMAX2-RV64-NEXT: lui a1, 209715
; LMULMAX2-RV64-NEXT: addiw a1, a1, 819
; LMULMAX2-RV64-NEXT: addi a1, a1, 819
; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1
; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1
; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 2
; LMULMAX2-RV64-NEXT: vor.vv v8, v10, v8
; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 1
; LMULMAX2-RV64-NEXT: lui a1, 349525
; LMULMAX2-RV64-NEXT: addiw a1, a1, 1365
; LMULMAX2-RV64-NEXT: addi a1, a1, 1365
; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1
; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1
; LMULMAX2-RV64-NEXT: vadd.vv v8, v8, v8
Expand Down Expand Up @@ -662,7 +662,7 @@ define void @bitreverse_v8i32(ptr %x, ptr %y) {
; LMULMAX1-RV64-NEXT: vle32.v v9, (a0)
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 8
; LMULMAX1-RV64-NEXT: lui a2, 16
; LMULMAX1-RV64-NEXT: addiw a2, a2, -256
; LMULMAX1-RV64-NEXT: addi a2, a2, -256
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2
; LMULMAX1-RV64-NEXT: vsrl.vi v11, v8, 24
; LMULMAX1-RV64-NEXT: vor.vv v10, v10, v11
Expand All @@ -673,21 +673,21 @@ define void @bitreverse_v8i32(ptr %x, ptr %y) {
; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 4
; LMULMAX1-RV64-NEXT: lui a3, 61681
; LMULMAX1-RV64-NEXT: addiw a3, a3, -241
; LMULMAX1-RV64-NEXT: addi a3, a3, -241
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a3
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a3
; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 4
; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 2
; LMULMAX1-RV64-NEXT: lui a4, 209715
; LMULMAX1-RV64-NEXT: addiw a4, a4, 819
; LMULMAX1-RV64-NEXT: addi a4, a4, 819
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a4
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a4
; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 2
; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 1
; LMULMAX1-RV64-NEXT: lui a5, 349525
; LMULMAX1-RV64-NEXT: addiw a5, a5, 1365
; LMULMAX1-RV64-NEXT: addi a5, a5, 1365
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a5
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a5
; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v8
Expand Down
368 changes: 120 additions & 248 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
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56 changes: 19 additions & 37 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -33,41 +33,23 @@ define void @bswap_v8i16(ptr %x, ptr %y) {
declare <8 x i16> @llvm.bswap.v8i16(<8 x i16>)

define void @bswap_v4i32(ptr %x, ptr %y) {
; RV32-LABEL: bswap_v4i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vle32.v v8, (a0)
; RV32-NEXT: vsrl.vi v9, v8, 8
; RV32-NEXT: lui a1, 16
; RV32-NEXT: addi a1, a1, -256
; RV32-NEXT: vand.vx v9, v9, a1
; RV32-NEXT: vsrl.vi v10, v8, 24
; RV32-NEXT: vor.vv v9, v9, v10
; RV32-NEXT: vand.vx v10, v8, a1
; RV32-NEXT: vsll.vi v10, v10, 8
; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: vor.vv v8, v8, v9
; RV32-NEXT: vse32.v v8, (a0)
; RV32-NEXT: ret
;
; RV64-LABEL: bswap_v4i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64-NEXT: vle32.v v8, (a0)
; RV64-NEXT: vsrl.vi v9, v8, 8
; RV64-NEXT: lui a1, 16
; RV64-NEXT: addiw a1, a1, -256
; RV64-NEXT: vand.vx v9, v9, a1
; RV64-NEXT: vsrl.vi v10, v8, 24
; RV64-NEXT: vor.vv v9, v9, v10
; RV64-NEXT: vand.vx v10, v8, a1
; RV64-NEXT: vsll.vi v10, v10, 8
; RV64-NEXT: vsll.vi v8, v8, 24
; RV64-NEXT: vor.vv v8, v8, v10
; RV64-NEXT: vor.vv v8, v8, v9
; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: ret
; CHECK-LABEL: bswap_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsrl.vi v9, v8, 8
; CHECK-NEXT: lui a1, 16
; CHECK-NEXT: addi a1, a1, -256
; CHECK-NEXT: vand.vx v9, v9, a1
; CHECK-NEXT: vsrl.vi v10, v8, 24
; CHECK-NEXT: vor.vv v9, v9, v10
; CHECK-NEXT: vand.vx v10, v8, a1
; CHECK-NEXT: vsll.vi v10, v10, 8
; CHECK-NEXT: vsll.vi v8, v8, 24
; CHECK-NEXT: vor.vv v8, v8, v10
; CHECK-NEXT: vor.vv v8, v8, v9
; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
;
; ZVKB-LABEL: bswap_v4i32:
; ZVKB: # %bb.0:
Expand Down Expand Up @@ -269,7 +251,7 @@ define void @bswap_v8i32(ptr %x, ptr %y) {
; LMULMAX2-RV64-NEXT: vle32.v v8, (a0)
; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 8
; LMULMAX2-RV64-NEXT: lui a1, 16
; LMULMAX2-RV64-NEXT: addiw a1, a1, -256
; LMULMAX2-RV64-NEXT: addi a1, a1, -256
; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1
; LMULMAX2-RV64-NEXT: vsrl.vi v12, v8, 24
; LMULMAX2-RV64-NEXT: vor.vv v10, v10, v12
Expand Down Expand Up @@ -319,7 +301,7 @@ define void @bswap_v8i32(ptr %x, ptr %y) {
; LMULMAX1-RV64-NEXT: vle32.v v9, (a0)
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 8
; LMULMAX1-RV64-NEXT: lui a2, 16
; LMULMAX1-RV64-NEXT: addiw a2, a2, -256
; LMULMAX1-RV64-NEXT: addi a2, a2, -256
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2
; LMULMAX1-RV64-NEXT: vsrl.vi v11, v8, 24
; LMULMAX1-RV64-NEXT: vor.vv v10, v10, v11
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-buildvec-of-binop.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -236,7 +236,7 @@ define <4 x i32> @add_constant_rhs_with_identity(i32 %a, i32 %b, i32 %c, i32 %d)
; RV64: # %bb.0:
; RV64-NEXT: addiw a1, a1, 25
; RV64-NEXT: addiw a2, a2, 1
; RV64-NEXT: addiw a3, a3, 2047
; RV64-NEXT: addi a3, a3, 2047
; RV64-NEXT: addiw a3, a3, 308
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64-NEXT: vslide1down.vx v8, v8, a0
Expand Down Expand Up @@ -273,7 +273,7 @@ define <4 x i32> @add_constant_rhs_identity(i32 %a, i32 %b, i32 %c, i32 %d) {
; RV64: # %bb.0:
; RV64-NEXT: addiw a1, a1, 25
; RV64-NEXT: addiw a2, a2, 1
; RV64-NEXT: addiw a3, a3, 2047
; RV64-NEXT: addi a3, a3, 2047
; RV64-NEXT: addiw a3, a3, 308
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64-NEXT: vslide1down.vx v8, v8, a0
Expand Down
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