11 changes: 11 additions & 0 deletions llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -76,6 +76,8 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
RegisterTargetMachine<RISCVTargetMachine> Y(getTheRISCV64Target());
auto *PR = PassRegistry::getPassRegistry();
initializeGlobalISel(*PR);
initializeRISCVO0PreLegalizerCombinerPass(*PR);
initializeRISCVPreLegalizerCombinerPass(*PR);
initializeKCFIPass(*PR);
initializeRISCVMakeCompressibleOptPass(*PR);
initializeRISCVGatherScatterLoweringPass(*PR);
Expand Down Expand Up @@ -263,6 +265,7 @@ class RISCVPassConfig : public TargetPassConfig {
bool addPreISel() override;
bool addInstSelector() override;
bool addIRTranslator() override;
void addPreLegalizeMachineIR() override;
bool addLegalizeMachineIR() override;
bool addRegBankSelect() override;
bool addGlobalInstructionSelect() override;
Expand Down Expand Up @@ -321,6 +324,14 @@ bool RISCVPassConfig::addIRTranslator() {
return false;
}

void RISCVPassConfig::addPreLegalizeMachineIR() {
if (getOptLevel() == CodeGenOptLevel::None) {
addPass(createRISCVO0PreLegalizerCombiner());
} else {
addPass(createRISCVPreLegalizerCombiner());
}
}

bool RISCVPassConfig::addLegalizeMachineIR() {
addPass(new Legalizer());
return false;
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51 changes: 51 additions & 0 deletions llvm/test/CodeGen/RISCV/GlobalISel/combine.ll
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@@ -0,0 +1,51 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -global-isel -verify-machineinstrs -O0 < %s \
; RUN: | FileCheck %s --check-prefixes=RV32,RV32-O0
; RUN: llc -mtriple=riscv64 -global-isel -verify-machineinstrs -O0 < %s \
; RUN: | FileCheck %s --check-prefixes=RV64,RV64-O0
; RUN: llc -mtriple=riscv32 -global-isel -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=RV32,RV32-OPT
; RUN: llc -mtriple=riscv64 -global-isel -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=RV64,RV64-OPT

define i32 @constant_to_rhs(i32 %x) {
; RV32-O0-LABEL: constant_to_rhs:
; RV32-O0: # %bb.0:
; RV32-O0-NEXT: mv a1, a0
; RV32-O0-NEXT: li a0, 1
; RV32-O0-NEXT: add a0, a0, a1
; RV32-O0-NEXT: ret
;
; RV64-O0-LABEL: constant_to_rhs:
; RV64-O0: # %bb.0:
; RV64-O0-NEXT: mv a1, a0
; RV64-O0-NEXT: li a0, 1
; RV64-O0-NEXT: addw a0, a0, a1
; RV64-O0-NEXT: ret
;
; RV32-OPT-LABEL: constant_to_rhs:
; RV32-OPT: # %bb.0:
; RV32-OPT-NEXT: addi a0, a0, 1
; RV32-OPT-NEXT: ret
;
; RV64-OPT-LABEL: constant_to_rhs:
; RV64-OPT: # %bb.0:
; RV64-OPT-NEXT: addiw a0, a0, 1
; RV64-OPT-NEXT: ret
%a = add i32 1, %x
ret i32 %a
}

define i32 @mul_to_shift(i32 %x) {
; RV32-LABEL: mul_to_shift:
; RV32: # %bb.0:
; RV32-NEXT: slli a0, a0, 2
; RV32-NEXT: ret
;
; RV64-LABEL: mul_to_shift:
; RV64: # %bb.0:
; RV64-NEXT: slliw a0, a0, 2
; RV64-NEXT: ret
%a = mul i32 %x, 4
ret i32 %a
}
13 changes: 8 additions & 5 deletions llvm/test/CodeGen/RISCV/GlobalISel/gisel-commandline-option.ll
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@@ -1,22 +1,25 @@
; RUN: llc -mtriple=riscv64-- -debug-pass=Structure %s -o /dev/null 2>&1 \
; RUN: -verify-machineinstrs=0 -O0 -global-isel \
; RUN: | FileCheck %s --check-prefix ENABLED --check-prefix NOFALLBACK
; RUN: | FileCheck %s --check-prefixes=ENABLED,NOFALLBACK,ENABLED-O0

; RUN: llc -mtriple=riscv64-- -debug-pass=Structure %s -o /dev/null 2>&1 \
; RUN: -verify-machineinstrs=0 -global-isel \
; RUN: | FileCheck %s --check-prefix ENABLED --check-prefix NOFALLBACK --check-prefix ENABLED-O1
; RUN: | FileCheck %s --check-prefixes=ENABLED,NOFALLBACK,ENABLED-O1

; RUN: llc -mtriple=riscv64-- -debug-pass=Structure %s -o /dev/null 2>&1 \
; RUN: -verify-machineinstrs=0 -global-isel -global-isel-abort=2 \
; RUN: | FileCheck %s --check-prefix ENABLED --check-prefix FALLBACK --check-prefix ENABLED-O1
; RUN: | FileCheck %s --check-prefixes=ENABLED,FALLBACK,ENABLED-O1

; RUN: llc -mtriple=riscv64-- -debug-pass=Structure %s -o /dev/null 2>&1 \
; RUN: -verify-machineinstrs=0 \
; RUN: | FileCheck %s --check-prefix DISABLED
; RUN: | FileCheck %s --check-prefixes=DISABLED

; ENABLED: IRTranslator
; ENABLED-NEXT: Analysis containing CSE Info
; ENABLED-NEXT: Analysis for ComputingKnownBits
; ENABLED-O0-NEXT: RISCVO0PreLegalizerCombiner
; ENABLED-O1-NEXT: MachineDominator Tree Construction
; ENABLED-NEXT: Analysis containing CSE Info
; ENABLED-O1-NEXT: RISCVPreLegalizerCombiner
; ENABLED-NEXT: Legalizer
; ENABLED-NEXT: RegBankSelect
; ENABLED-NEXT: Analysis for ComputingKnownBits
Expand Down