diff --git a/llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll b/llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
diff --git a/llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll b/llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
@@ -1213,13 +1213,13 @@ define amdgpu_kernel void @dynamic_insertelement_v16i8(<16 x i8> addrspace(1)* %
 ; SI-NEXT:    s_lshr_b32 s4, s11, 24
 ; SI-NEXT:    s_cmp_lg_u32 s6, 15
 ; SI-NEXT:    s_cselect_b32 s4, s4, 5
-; SI-NEXT:    s_lshl_b32 s4, s4, 8
+; SI-NEXT:    s_lshl_b32 s4, s4, 24
 ; SI-NEXT:    s_lshr_b32 s5, s11, 16
 ; SI-NEXT:    s_cmp_lg_u32 s6, 14
 ; SI-NEXT:    s_cselect_b32 s5, s5, 5
 ; SI-NEXT:    s_and_b32 s5, s5, 0xff
-; SI-NEXT:    s_or_b32 s4, s5, s4
-; SI-NEXT:    s_lshl_b32 s4, s4, 16
+; SI-NEXT:    s_lshl_b32 s5, s5, 16
+; SI-NEXT:    s_or_b32 s4, s4, s5
 ; SI-NEXT:    s_lshr_b32 s5, s11, 8
 ; SI-NEXT:    s_cmp_lg_u32 s6, 13
 ; SI-NEXT:    s_cselect_b32 s5, s5, 5
@@ -1233,13 +1233,13 @@ define amdgpu_kernel void @dynamic_insertelement_v16i8(<16 x i8> addrspace(1)* %
 ; SI-NEXT:    s_lshr_b32 s5, s10, 24
 ; SI-NEXT:    s_cmp_lg_u32 s6, 11
 ; SI-NEXT:    s_cselect_b32 s5, s5, 5
-; SI-NEXT:    s_lshl_b32 s5, s5, 8
+; SI-NEXT:    s_lshl_b32 s5, s5, 24
 ; SI-NEXT:    s_lshr_b32 s7, s10, 16
 ; SI-NEXT:    s_cmp_lg_u32 s6, 10
 ; SI-NEXT:    s_cselect_b32 s7, s7, 5
 ; SI-NEXT:    s_and_b32 s7, s7, 0xff
-; SI-NEXT:    s_or_b32 s5, s7, s5
-; SI-NEXT:    s_lshl_b32 s5, s5, 16
+; SI-NEXT:    s_lshl_b32 s7, s7, 16
+; SI-NEXT:    s_or_b32 s5, s5, s7
 ; SI-NEXT:    s_lshr_b32 s7, s10, 8
 ; SI-NEXT:    s_cmp_lg_u32 s6, 9
 ; SI-NEXT:    s_cselect_b32 s7, s7, 5
@@ -1253,13 +1253,13 @@ define amdgpu_kernel void @dynamic_insertelement_v16i8(<16 x i8> addrspace(1)* %
 ; SI-NEXT:    s_lshr_b32 s7, s9, 24
 ; SI-NEXT:    s_cmp_lg_u32 s6, 7
 ; SI-NEXT:    s_cselect_b32 s7, s7, 5
-; SI-NEXT:    s_lshl_b32 s7, s7, 8
+; SI-NEXT:    s_lshl_b32 s7, s7, 24
 ; SI-NEXT:    s_lshr_b32 s10, s9, 16
 ; SI-NEXT:    s_cmp_lg_u32 s6, 6
 ; SI-NEXT:    s_cselect_b32 s10, s10, 5
 ; SI-NEXT:    s_and_b32 s10, s10, 0xff
-; SI-NEXT:    s_or_b32 s7, s10, s7
-; SI-NEXT:    s_lshl_b32 s7, s7, 16
+; SI-NEXT:    s_lshl_b32 s10, s10, 16
+; SI-NEXT:    s_or_b32 s7, s7, s10
 ; SI-NEXT:    s_lshr_b32 s10, s9, 8
 ; SI-NEXT:    s_cmp_lg_u32 s6, 5
 ; SI-NEXT:    s_cselect_b32 s10, s10, 5
@@ -1273,13 +1273,13 @@ define amdgpu_kernel void @dynamic_insertelement_v16i8(<16 x i8> addrspace(1)* %
 ; SI-NEXT:    s_lshr_b32 s9, s8, 24
 ; SI-NEXT:    s_cmp_lg_u32 s6, 3
 ; SI-NEXT:    s_cselect_b32 s9, s9, 5
-; SI-NEXT:    s_lshl_b32 s9, s9, 8
+; SI-NEXT:    s_lshl_b32 s9, s9, 24
 ; SI-NEXT:    s_lshr_b32 s10, s8, 16
 ; SI-NEXT:    s_cmp_lg_u32 s6, 2
 ; SI-NEXT:    s_cselect_b32 s10, s10, 5
 ; SI-NEXT:    s_and_b32 s10, s10, 0xff
-; SI-NEXT:    s_or_b32 s9, s10, s9
-; SI-NEXT:    s_lshl_b32 s9, s9, 16
+; SI-NEXT:    s_lshl_b32 s10, s10, 16
+; SI-NEXT:    s_or_b32 s9, s9, s10
 ; SI-NEXT:    s_lshr_b32 s10, s8, 8
 ; SI-NEXT:    s_cmp_lg_u32 s6, 1
 ; SI-NEXT:    s_cselect_b32 s10, s10, 5

diff --git a/llvm/test/CodeGen/BPF/pr57872.ll b/llvm/test/CodeGen/BPF/pr57872.ll
@@ -1,9 +1,184 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=bpf-- | FileCheck %s
-; XFAIL: *
 
 %struct.event = type { i8, [84 x i8] }
 
 define void @foo(ptr %g) {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    r1 = *(u64 *)(r1 + 0)
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 83)
+; CHECK-NEXT:    *(u8 *)(r10 - 4) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 82)
+; CHECK-NEXT:    *(u8 *)(r10 - 5) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 81)
+; CHECK-NEXT:    *(u8 *)(r10 - 6) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 80)
+; CHECK-NEXT:    *(u8 *)(r10 - 7) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 79)
+; CHECK-NEXT:    *(u8 *)(r10 - 8) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 78)
+; CHECK-NEXT:    *(u8 *)(r10 - 9) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 77)
+; CHECK-NEXT:    *(u8 *)(r10 - 10) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 76)
+; CHECK-NEXT:    *(u8 *)(r10 - 11) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 75)
+; CHECK-NEXT:    *(u8 *)(r10 - 12) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 74)
+; CHECK-NEXT:    *(u8 *)(r10 - 13) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 73)
+; CHECK-NEXT:    *(u8 *)(r10 - 14) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 72)
+; CHECK-NEXT:    *(u8 *)(r10 - 15) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 71)
+; CHECK-NEXT:    *(u8 *)(r10 - 16) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 70)
+; CHECK-NEXT:    *(u8 *)(r10 - 17) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 69)
+; CHECK-NEXT:    *(u8 *)(r10 - 18) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 68)
+; CHECK-NEXT:    *(u8 *)(r10 - 19) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 67)
+; CHECK-NEXT:    *(u8 *)(r10 - 20) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 66)
+; CHECK-NEXT:    *(u8 *)(r10 - 21) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 65)
+; CHECK-NEXT:    *(u8 *)(r10 - 22) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 64)
+; CHECK-NEXT:    *(u8 *)(r10 - 23) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 63)
+; CHECK-NEXT:    *(u8 *)(r10 - 24) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 62)
+; CHECK-NEXT:    *(u8 *)(r10 - 25) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 61)
+; CHECK-NEXT:    *(u8 *)(r10 - 26) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 60)
+; CHECK-NEXT:    *(u8 *)(r10 - 27) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 59)
+; CHECK-NEXT:    *(u8 *)(r10 - 28) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 58)
+; CHECK-NEXT:    *(u8 *)(r10 - 29) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 57)
+; CHECK-NEXT:    *(u8 *)(r10 - 30) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 56)
+; CHECK-NEXT:    *(u8 *)(r10 - 31) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 55)
+; CHECK-NEXT:    *(u8 *)(r10 - 32) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 54)
+; CHECK-NEXT:    *(u8 *)(r10 - 33) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 53)
+; CHECK-NEXT:    *(u8 *)(r10 - 34) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 52)
+; CHECK-NEXT:    *(u8 *)(r10 - 35) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 51)
+; CHECK-NEXT:    *(u8 *)(r10 - 36) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 50)
+; CHECK-NEXT:    *(u8 *)(r10 - 37) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 49)
+; CHECK-NEXT:    *(u8 *)(r10 - 38) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 48)
+; CHECK-NEXT:    *(u8 *)(r10 - 39) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 47)
+; CHECK-NEXT:    *(u8 *)(r10 - 40) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 46)
+; CHECK-NEXT:    *(u8 *)(r10 - 41) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 45)
+; CHECK-NEXT:    *(u8 *)(r10 - 42) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 44)
+; CHECK-NEXT:    *(u8 *)(r10 - 43) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 43)
+; CHECK-NEXT:    *(u8 *)(r10 - 44) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 42)
+; CHECK-NEXT:    *(u8 *)(r10 - 45) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 41)
+; CHECK-NEXT:    *(u8 *)(r10 - 46) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 40)
+; CHECK-NEXT:    *(u8 *)(r10 - 47) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 39)
+; CHECK-NEXT:    *(u8 *)(r10 - 48) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 38)
+; CHECK-NEXT:    *(u8 *)(r10 - 49) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 37)
+; CHECK-NEXT:    *(u8 *)(r10 - 50) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 36)
+; CHECK-NEXT:    *(u8 *)(r10 - 51) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 35)
+; CHECK-NEXT:    *(u8 *)(r10 - 52) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 34)
+; CHECK-NEXT:    *(u8 *)(r10 - 53) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 33)
+; CHECK-NEXT:    *(u8 *)(r10 - 54) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 32)
+; CHECK-NEXT:    *(u8 *)(r10 - 55) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 31)
+; CHECK-NEXT:    *(u8 *)(r10 - 56) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 30)
+; CHECK-NEXT:    *(u8 *)(r10 - 57) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 29)
+; CHECK-NEXT:    *(u8 *)(r10 - 58) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 28)
+; CHECK-NEXT:    *(u8 *)(r10 - 59) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 27)
+; CHECK-NEXT:    *(u8 *)(r10 - 60) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 26)
+; CHECK-NEXT:    *(u8 *)(r10 - 61) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 25)
+; CHECK-NEXT:    *(u8 *)(r10 - 62) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 24)
+; CHECK-NEXT:    *(u8 *)(r10 - 63) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 23)
+; CHECK-NEXT:    *(u8 *)(r10 - 64) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 22)
+; CHECK-NEXT:    *(u8 *)(r10 - 65) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 21)
+; CHECK-NEXT:    *(u8 *)(r10 - 66) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 20)
+; CHECK-NEXT:    *(u8 *)(r10 - 67) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 19)
+; CHECK-NEXT:    *(u8 *)(r10 - 68) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 18)
+; CHECK-NEXT:    *(u8 *)(r10 - 69) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 17)
+; CHECK-NEXT:    *(u8 *)(r10 - 70) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 16)
+; CHECK-NEXT:    *(u8 *)(r10 - 71) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 15)
+; CHECK-NEXT:    *(u8 *)(r10 - 72) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 14)
+; CHECK-NEXT:    *(u8 *)(r10 - 73) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 13)
+; CHECK-NEXT:    *(u8 *)(r10 - 74) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 12)
+; CHECK-NEXT:    *(u8 *)(r10 - 75) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 11)
+; CHECK-NEXT:    *(u8 *)(r10 - 76) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 10)
+; CHECK-NEXT:    *(u8 *)(r10 - 77) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 9)
+; CHECK-NEXT:    *(u8 *)(r10 - 78) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 8)
+; CHECK-NEXT:    *(u8 *)(r10 - 79) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 7)
+; CHECK-NEXT:    *(u8 *)(r10 - 80) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 6)
+; CHECK-NEXT:    *(u8 *)(r10 - 81) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 5)
+; CHECK-NEXT:    *(u8 *)(r10 - 82) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 4)
+; CHECK-NEXT:    *(u8 *)(r10 - 83) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 3)
+; CHECK-NEXT:    *(u8 *)(r10 - 84) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 2)
+; CHECK-NEXT:    *(u8 *)(r10 - 85) = r2
+; CHECK-NEXT:    r2 = *(u8 *)(r1 + 1)
+; CHECK-NEXT:    *(u8 *)(r10 - 86) = r2
+; CHECK-NEXT:    r1 = *(u8 *)(r1 + 0)
+; CHECK-NEXT:    *(u8 *)(r10 - 87) = r1
+; CHECK-NEXT:    r1 = r10
+; CHECK-NEXT:    r1 += -88
+; CHECK-NEXT:    call bar
+; CHECK-NEXT:    exit
 entry:
   %event = alloca %struct.event, align 1
   %hostname = getelementptr inbounds %struct.event, ptr %event, i64 0, i32 1

diff --git a/llvm/test/CodeGen/Mips/cconv/return-struct.ll b/llvm/test/CodeGen/Mips/cconv/return-struct.ll
@@ -175,12 +175,12 @@ define inreg {i48} @ret_struct_3xi16() nounwind {
 ; N32-BE:       # %bb.0: # %entry
 ; N32-BE-NEXT:    lui $1, %hi(struct_3xi16)
 ; N32-BE-NEXT:    lw $2, %lo(struct_3xi16)($1)
-; N32-BE-NEXT:    dsll $2, $2, 16
+; N32-BE-NEXT:    dsll $2, $2, 32
 ; N32-BE-NEXT:    addiu $1, $1, %lo(struct_3xi16)
 ; N32-BE-NEXT:    lhu $1, 4($1)
-; N32-BE-NEXT:    or $1, $1, $2
+; N32-BE-NEXT:    dsll $1, $1, 16
 ; N32-BE-NEXT:    jr $ra
-; N32-BE-NEXT:    dsll $2, $1, 16
+; N32-BE-NEXT:    or $2, $2, $1
 ;
 ; N32-LE-LABEL: ret_struct_3xi16:
 ; N32-LE:       # %bb.0: # %entry
@@ -200,12 +200,12 @@ define inreg {i48} @ret_struct_3xi16() nounwind {
 ; N64-BE-NEXT:    daddiu $1, $1, %hi(struct_3xi16)
 ; N64-BE-NEXT:    dsll $1, $1, 16
 ; N64-BE-NEXT:    lw $2, %lo(struct_3xi16)($1)
-; N64-BE-NEXT:    dsll $2, $2, 16
+; N64-BE-NEXT:    dsll $2, $2, 32
 ; N64-BE-NEXT:    daddiu $1, $1, %lo(struct_3xi16)
 ; N64-BE-NEXT:    lhu $1, 4($1)
-; N64-BE-NEXT:    or $1, $1, $2
+; N64-BE-NEXT:    dsll $1, $1, 16
 ; N64-BE-NEXT:    jr $ra
-; N64-BE-NEXT:    dsll $2, $1, 16
+; N64-BE-NEXT:    or $2, $2, $1
 ;
 ; N64-LE-LABEL: ret_struct_3xi16:
 ; N64-LE:       # %bb.0: # %entry

diff --git a/llvm/test/CodeGen/Mips/cconv/vector.ll b/llvm/test/CodeGen/Mips/cconv/vector.ll
diff --git a/llvm/test/CodeGen/Mips/load-store-left-right.ll b/llvm/test/CodeGen/Mips/load-store-left-right.ll
@@ -977,12 +977,12 @@ define void @pass_array_byval() nounwind {
 ; MIPS32-EB-NEXT:    addu $gp, $2, $25
 ; MIPS32-EB-NEXT:    lw $1, %got(arr)($gp)
 ; MIPS32-EB-NEXT:    lwl $4, 0($1)
-; MIPS32-EB-NEXT:    lwr $4, 3($1)
 ; MIPS32-EB-NEXT:    lbu $2, 5($1)
+; MIPS32-EB-NEXT:    lwr $4, 3($1)
+; MIPS32-EB-NEXT:    sll $2, $2, 16
 ; MIPS32-EB-NEXT:    lbu $3, 4($1)
-; MIPS32-EB-NEXT:    sll $3, $3, 8
+; MIPS32-EB-NEXT:    sll $3, $3, 24
 ; MIPS32-EB-NEXT:    or $2, $3, $2
-; MIPS32-EB-NEXT:    sll $2, $2, 16
 ; MIPS32-EB-NEXT:    lbu $1, 6($1)
 ; MIPS32-EB-NEXT:    sll $1, $1, 8
 ; MIPS32-EB-NEXT:    lw $25, %call16(extern_func)($gp)
@@ -1046,18 +1046,18 @@ define void @pass_array_byval() nounwind {
 ; MIPS64-EL-NEXT:    daddu $1, $1, $25
 ; MIPS64-EL-NEXT:    daddiu $gp, $1, %lo(%neg(%gp_rel(pass_array_byval)))
 ; MIPS64-EL-NEXT:    ld $1, %got_disp(arr)($gp)
-; MIPS64-EL-NEXT:    lwl $2, 3($1)
-; MIPS64-EL-NEXT:    lwr $2, 0($1)
-; MIPS64-EL-NEXT:    daddiu $3, $zero, 1
-; MIPS64-EL-NEXT:    dsll $3, $3, 32
-; MIPS64-EL-NEXT:    daddiu $3, $3, -1
-; MIPS64-EL-NEXT:    and $2, $2, $3
-; MIPS64-EL-NEXT:    lbu $3, 4($1)
-; MIPS64-EL-NEXT:    lbu $4, 5($1)
-; MIPS64-EL-NEXT:    dsll $4, $4, 8
-; MIPS64-EL-NEXT:    or $3, $4, $3
-; MIPS64-EL-NEXT:    dsll $3, $3, 32
-; MIPS64-EL-NEXT:    or $2, $2, $3
+; MIPS64-EL-NEXT:    lbu $2, 4($1)
+; MIPS64-EL-NEXT:    dsll $2, $2, 32
+; MIPS64-EL-NEXT:    lbu $3, 5($1)
+; MIPS64-EL-NEXT:    dsll $3, $3, 40
+; MIPS64-EL-NEXT:    or $2, $3, $2
+; MIPS64-EL-NEXT:    lwl $3, 3($1)
+; MIPS64-EL-NEXT:    lwr $3, 0($1)
+; MIPS64-EL-NEXT:    daddiu $4, $zero, 1
+; MIPS64-EL-NEXT:    dsll $4, $4, 32
+; MIPS64-EL-NEXT:    daddiu $4, $4, -1
+; MIPS64-EL-NEXT:    and $3, $3, $4
+; MIPS64-EL-NEXT:    or $2, $3, $2
 ; MIPS64-EL-NEXT:    lbu $1, 6($1)
 ; MIPS64-EL-NEXT:    dsll $1, $1, 48
 ; MIPS64-EL-NEXT:    ld $25, %call16(extern_func)($gp)
@@ -1079,15 +1079,15 @@ define void @pass_array_byval() nounwind {
 ; MIPS64-EB-NEXT:    daddu $1, $1, $25
 ; MIPS64-EB-NEXT:    daddiu $gp, $1, %lo(%neg(%gp_rel(pass_array_byval)))
 ; MIPS64-EB-NEXT:    ld $1, %got_disp(arr)($gp)
-; MIPS64-EB-NEXT:    lwl $2, 0($1)
-; MIPS64-EB-NEXT:    lwr $2, 3($1)
-; MIPS64-EB-NEXT:    dsll $2, $2, 32
-; MIPS64-EB-NEXT:    lbu $3, 5($1)
-; MIPS64-EB-NEXT:    lbu $4, 4($1)
-; MIPS64-EB-NEXT:    dsll $4, $4, 8
-; MIPS64-EB-NEXT:    or $3, $4, $3
-; MIPS64-EB-NEXT:    dsll $3, $3, 16
-; MIPS64-EB-NEXT:    or $2, $2, $3
+; MIPS64-EB-NEXT:    lbu $2, 5($1)
+; MIPS64-EB-NEXT:    dsll $2, $2, 16
+; MIPS64-EB-NEXT:    lbu $3, 4($1)
+; MIPS64-EB-NEXT:    dsll $3, $3, 24
+; MIPS64-EB-NEXT:    or $2, $3, $2
+; MIPS64-EB-NEXT:    lwl $3, 0($1)
+; MIPS64-EB-NEXT:    lwr $3, 3($1)
+; MIPS64-EB-NEXT:    dsll $3, $3, 32
+; MIPS64-EB-NEXT:    or $2, $3, $2
 ; MIPS64-EB-NEXT:    lbu $1, 6($1)
 ; MIPS64-EB-NEXT:    dsll $1, $1, 8
 ; MIPS64-EB-NEXT:    ld $25, %call16(extern_func)($gp)
@@ -1109,15 +1109,15 @@ define void @pass_array_byval() nounwind {
 ; MIPS64R2-EL-NEXT:    daddu $1, $1, $25
 ; MIPS64R2-EL-NEXT:    daddiu $gp, $1, %lo(%neg(%gp_rel(pass_array_byval)))
 ; MIPS64R2-EL-NEXT:    ld $1, %got_disp(arr)($gp)
-; MIPS64R2-EL-NEXT:    lwl $2, 3($1)
-; MIPS64R2-EL-NEXT:    lwr $2, 0($1)
-; MIPS64R2-EL-NEXT:    dext $2, $2, 0, 32
-; MIPS64R2-EL-NEXT:    lbu $3, 4($1)
-; MIPS64R2-EL-NEXT:    lbu $4, 5($1)
-; MIPS64R2-EL-NEXT:    dsll $4, $4, 8
-; MIPS64R2-EL-NEXT:    or $3, $4, $3
-; MIPS64R2-EL-NEXT:    dsll $3, $3, 32
-; MIPS64R2-EL-NEXT:    or $2, $2, $3
+; MIPS64R2-EL-NEXT:    lbu $2, 4($1)
+; MIPS64R2-EL-NEXT:    dsll $2, $2, 32
+; MIPS64R2-EL-NEXT:    lbu $3, 5($1)
+; MIPS64R2-EL-NEXT:    dsll $3, $3, 40
+; MIPS64R2-EL-NEXT:    or $2, $3, $2
+; MIPS64R2-EL-NEXT:    lwl $3, 3($1)
+; MIPS64R2-EL-NEXT:    lwr $3, 0($1)
+; MIPS64R2-EL-NEXT:    dext $3, $3, 0, 32
+; MIPS64R2-EL-NEXT:    or $2, $3, $2
 ; MIPS64R2-EL-NEXT:    lbu $1, 6($1)
 ; MIPS64R2-EL-NEXT:    dsll $1, $1, 48
 ; MIPS64R2-EL-NEXT:    ld $25, %call16(extern_func)($gp)
@@ -1140,10 +1140,10 @@ define void @pass_array_byval() nounwind {
 ; MIPS64R2-EB-NEXT:    daddiu $gp, $1, %lo(%neg(%gp_rel(pass_array_byval)))
 ; MIPS64R2-EB-NEXT:    ld $1, %got_disp(arr)($gp)
 ; MIPS64R2-EB-NEXT:    lbu $2, 5($1)
+; MIPS64R2-EB-NEXT:    dsll $2, $2, 16
 ; MIPS64R2-EB-NEXT:    lbu $3, 4($1)
-; MIPS64R2-EB-NEXT:    dsll $3, $3, 8
+; MIPS64R2-EB-NEXT:    dsll $3, $3, 24
 ; MIPS64R2-EB-NEXT:    or $2, $3, $2
-; MIPS64R2-EB-NEXT:    dsll $2, $2, 16
 ; MIPS64R2-EB-NEXT:    lwl $3, 0($1)
 ; MIPS64R2-EB-NEXT:    lwr $3, 3($1)
 ; MIPS64R2-EB-NEXT:    dext $3, $3, 0, 32

diff --git a/llvm/test/CodeGen/Mips/unalignedload.ll b/llvm/test/CodeGen/Mips/unalignedload.ll
@@ -43,14 +43,14 @@ define void @bar1() nounwind {
 ; MIPS32-EB-NEXT:    addu $gp, $2, $25
 ; MIPS32-EB-NEXT:    lw $1, %got(s2)($gp)
 ; MIPS32-EB-NEXT:    lbu $2, 3($1)
+; MIPS32-EB-NEXT:    sll $2, $2, 16
 ; MIPS32-EB-NEXT:    lbu $1, 2($1)
-; MIPS32-EB-NEXT:    sll $1, $1, 8
-; MIPS32-EB-NEXT:    or $1, $1, $2
+; MIPS32-EB-NEXT:    sll $1, $1, 24
 ; MIPS32-EB-NEXT:    lw $25, %call16(foo2)($gp)
 ; MIPS32-EB-NEXT:    .reloc ($tmp0), R_MIPS_JALR, foo2
 ; MIPS32-EB-NEXT:  $tmp0:
 ; MIPS32-EB-NEXT:    jalr $25
-; MIPS32-EB-NEXT:    sll $4, $1, 16
+; MIPS32-EB-NEXT:    or $4, $1, $2
 ; MIPS32-EB-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
 ; MIPS32-EB-NEXT:    jr $ra
 ; MIPS32-EB-NEXT:    addiu $sp, $sp, 24
@@ -130,12 +130,12 @@ define void @bar2() nounwind {
 ; MIPS32-EB-NEXT:    addu $gp, $2, $25
 ; MIPS32-EB-NEXT:    lw $1, %got(s4)($gp)
 ; MIPS32-EB-NEXT:    lwl $4, 0($1)
-; MIPS32-EB-NEXT:    lwr $4, 3($1)
 ; MIPS32-EB-NEXT:    lbu $2, 5($1)
+; MIPS32-EB-NEXT:    lwr $4, 3($1)
+; MIPS32-EB-NEXT:    sll $2, $2, 16
 ; MIPS32-EB-NEXT:    lbu $3, 4($1)
-; MIPS32-EB-NEXT:    sll $3, $3, 8
+; MIPS32-EB-NEXT:    sll $3, $3, 24
 ; MIPS32-EB-NEXT:    or $2, $3, $2
-; MIPS32-EB-NEXT:    sll $2, $2, 16
 ; MIPS32-EB-NEXT:    lbu $1, 6($1)
 ; MIPS32-EB-NEXT:    sll $1, $1, 8
 ; MIPS32-EB-NEXT:    lw $25, %call16(foo4)($gp)

diff --git a/llvm/test/CodeGen/RISCV/bswap-bitreverse.ll b/llvm/test/CodeGen/RISCV/bswap-bitreverse.ll
@@ -1499,19 +1499,17 @@ define i64 @test_bitreverse_bswap_i64(i64 %a) nounwind {
 define i32 @pr55484(i32 %0) {
 ; RV32I-LABEL: pr55484:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    srli a1, a0, 8
-; RV32I-NEXT:    slli a0, a0, 8
-; RV32I-NEXT:    or a0, a1, a0
-; RV32I-NEXT:    slli a0, a0, 16
+; RV32I-NEXT:    slli a1, a0, 8
+; RV32I-NEXT:    slli a0, a0, 24
+; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    srai a0, a0, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: pr55484:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    srli a1, a0, 8
-; RV64I-NEXT:    slli a0, a0, 8
-; RV64I-NEXT:    or a0, a1, a0
-; RV64I-NEXT:    slli a0, a0, 48
+; RV64I-NEXT:    slli a1, a0, 40
+; RV64I-NEXT:    slli a0, a0, 56
+; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    srai a0, a0, 48
 ; RV64I-NEXT:    ret
 ;
@@ -1533,19 +1531,17 @@ define i32 @pr55484(i32 %0) {
 ;
 ; RV32ZBKB-LABEL: pr55484:
 ; RV32ZBKB:       # %bb.0:
-; RV32ZBKB-NEXT:    srli a1, a0, 8
-; RV32ZBKB-NEXT:    slli a0, a0, 8
-; RV32ZBKB-NEXT:    or a0, a1, a0
-; RV32ZBKB-NEXT:    slli a0, a0, 16
+; RV32ZBKB-NEXT:    slli a1, a0, 8
+; RV32ZBKB-NEXT:    slli a0, a0, 24
+; RV32ZBKB-NEXT:    or a0, a0, a1
 ; RV32ZBKB-NEXT:    srai a0, a0, 16
 ; RV32ZBKB-NEXT:    ret
 ;
 ; RV64ZBKB-LABEL: pr55484:
 ; RV64ZBKB:       # %bb.0:
-; RV64ZBKB-NEXT:    srli a1, a0, 8
-; RV64ZBKB-NEXT:    slli a0, a0, 8
-; RV64ZBKB-NEXT:    or a0, a1, a0
-; RV64ZBKB-NEXT:    slli a0, a0, 48
+; RV64ZBKB-NEXT:    slli a1, a0, 40
+; RV64ZBKB-NEXT:    slli a0, a0, 56
+; RV64ZBKB-NEXT:    or a0, a0, a1
 ; RV64ZBKB-NEXT:    srai a0, a0, 48
 ; RV64ZBKB-NEXT:    ret
   %2 = lshr i32 %0, 8

diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
@@ -419,13 +419,13 @@ define void @masked_load_v2i32_align1(<2 x i32>* %a, <2 x i32> %m, <2 x i32>* %r
 ; RV32-NEXT:  # %bb.1: # %cond.load
 ; RV32-NEXT:    lbu a3, 1(a0)
 ; RV32-NEXT:    lbu a4, 0(a0)
-; RV32-NEXT:    lbu a5, 3(a0)
-; RV32-NEXT:    lbu a6, 2(a0)
+; RV32-NEXT:    lbu a5, 2(a0)
+; RV32-NEXT:    lbu a6, 3(a0)
 ; RV32-NEXT:    slli a3, a3, 8
 ; RV32-NEXT:    or a3, a3, a4
-; RV32-NEXT:    slli a4, a5, 8
-; RV32-NEXT:    or a4, a4, a6
-; RV32-NEXT:    slli a4, a4, 16
+; RV32-NEXT:    slli a4, a5, 16
+; RV32-NEXT:    slli a5, a6, 24
+; RV32-NEXT:    or a4, a5, a4
 ; RV32-NEXT:    or a3, a4, a3
 ; RV32-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
 ; RV32-NEXT:    vmv.v.x v8, a3
@@ -440,13 +440,13 @@ define void @masked_load_v2i32_align1(<2 x i32>* %a, <2 x i32> %m, <2 x i32>* %r
 ; RV32-NEXT:  .LBB8_3: # %cond.load1
 ; RV32-NEXT:    lbu a2, 5(a0)
 ; RV32-NEXT:    lbu a3, 4(a0)
-; RV32-NEXT:    lbu a4, 7(a0)
-; RV32-NEXT:    lbu a0, 6(a0)
+; RV32-NEXT:    lbu a4, 6(a0)
+; RV32-NEXT:    lbu a0, 7(a0)
 ; RV32-NEXT:    slli a2, a2, 8
 ; RV32-NEXT:    or a2, a2, a3
-; RV32-NEXT:    slli a3, a4, 8
-; RV32-NEXT:    or a0, a3, a0
-; RV32-NEXT:    slli a0, a0, 16
+; RV32-NEXT:    slli a3, a4, 16
+; RV32-NEXT:    slli a0, a0, 24
+; RV32-NEXT:    or a0, a0, a3
 ; RV32-NEXT:    or a0, a0, a2
 ; RV32-NEXT:    vmv.s.x v9, a0
 ; RV32-NEXT:    vsetvli zero, zero, e32, mf2, tu, ma
@@ -467,13 +467,13 @@ define void @masked_load_v2i32_align1(<2 x i32>* %a, <2 x i32> %m, <2 x i32>* %r
 ; RV64-NEXT:  # %bb.1: # %cond.load
 ; RV64-NEXT:    lbu a3, 1(a0)
 ; RV64-NEXT:    lbu a4, 0(a0)
-; RV64-NEXT:    lb a5, 3(a0)
-; RV64-NEXT:    lbu a6, 2(a0)
+; RV64-NEXT:    lbu a5, 2(a0)
+; RV64-NEXT:    lb a6, 3(a0)
 ; RV64-NEXT:    slli a3, a3, 8
 ; RV64-NEXT:    or a3, a3, a4
-; RV64-NEXT:    slli a4, a5, 8
-; RV64-NEXT:    or a4, a4, a6
-; RV64-NEXT:    slli a4, a4, 16
+; RV64-NEXT:    slli a4, a5, 16
+; RV64-NEXT:    slli a5, a6, 24
+; RV64-NEXT:    or a4, a5, a4
 ; RV64-NEXT:    or a3, a4, a3
 ; RV64-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
 ; RV64-NEXT:    vmv.v.x v8, a3
@@ -488,13 +488,13 @@ define void @masked_load_v2i32_align1(<2 x i32>* %a, <2 x i32> %m, <2 x i32>* %r
 ; RV64-NEXT:  .LBB8_3: # %cond.load1
 ; RV64-NEXT:    lbu a2, 5(a0)
 ; RV64-NEXT:    lbu a3, 4(a0)
-; RV64-NEXT:    lb a4, 7(a0)
-; RV64-NEXT:    lbu a0, 6(a0)
+; RV64-NEXT:    lbu a4, 6(a0)
+; RV64-NEXT:    lb a0, 7(a0)
 ; RV64-NEXT:    slli a2, a2, 8
 ; RV64-NEXT:    or a2, a2, a3
-; RV64-NEXT:    slli a3, a4, 8
-; RV64-NEXT:    or a0, a3, a0
-; RV64-NEXT:    slli a0, a0, 16
+; RV64-NEXT:    slli a3, a4, 16
+; RV64-NEXT:    slli a0, a0, 24
+; RV64-NEXT:    or a0, a0, a3
 ; RV64-NEXT:    or a0, a0, a2
 ; RV64-NEXT:    vmv.s.x v9, a0
 ; RV64-NEXT:    vsetvli zero, zero, e32, mf2, tu, ma

diff --git a/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll b/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
@@ -392,14 +392,13 @@ define void @test_srem_vec(<3 x i33>* %X) nounwind {
 ; RV64-NEXT:    lb a0, 12(a0)
 ; RV64-NEXT:    lwu a1, 8(s0)
 ; RV64-NEXT:    slli a0, a0, 32
-; RV64-NEXT:    or a0, a1, a0
 ; RV64-NEXT:    ld a2, 0(s0)
+; RV64-NEXT:    or a0, a1, a0
 ; RV64-NEXT:    slli a0, a0, 29
 ; RV64-NEXT:    srai s1, a0, 31
-; RV64-NEXT:    slli a0, a1, 31
-; RV64-NEXT:    srli a1, a2, 33
+; RV64-NEXT:    srli a0, a2, 2
+; RV64-NEXT:    slli a1, a1, 62
 ; RV64-NEXT:    or a0, a1, a0
-; RV64-NEXT:    slli a0, a0, 31
 ; RV64-NEXT:    srai a0, a0, 31
 ; RV64-NEXT:    slli a1, a2, 31
 ; RV64-NEXT:    srai s2, a1, 31
@@ -428,14 +427,14 @@ define void @test_srem_vec(<3 x i33>* %X) nounwind {
 ; RV64-NEXT:    neg a0, a0
 ; RV64-NEXT:    addi a2, a2, -1
 ; RV64-NEXT:    addi a1, a1, -1
-; RV64-NEXT:    slli a3, a1, 29
-; RV64-NEXT:    srli a3, a3, 61
-; RV64-NEXT:    sb a3, 12(s0)
-; RV64-NEXT:    slli a1, a1, 2
-; RV64-NEXT:    slli a3, a2, 31
-; RV64-NEXT:    srli a3, a3, 62
-; RV64-NEXT:    or a1, a3, a1
-; RV64-NEXT:    sw a1, 8(s0)
+; RV64-NEXT:    slli a3, a1, 2
+; RV64-NEXT:    slli a4, a2, 31
+; RV64-NEXT:    srli a4, a4, 62
+; RV64-NEXT:    or a3, a4, a3
+; RV64-NEXT:    sw a3, 8(s0)
+; RV64-NEXT:    slli a1, a1, 29
+; RV64-NEXT:    srli a1, a1, 61
+; RV64-NEXT:    sb a1, 12(s0)
 ; RV64-NEXT:    slli a0, a0, 31
 ; RV64-NEXT:    srli a0, a0, 31
 ; RV64-NEXT:    slli a1, a2, 33
@@ -533,68 +532,67 @@ define void @test_srem_vec(<3 x i33>* %X) nounwind {
 ;
 ; RV64M-LABEL: test_srem_vec:
 ; RV64M:       # %bb.0:
-; RV64M-NEXT:    lb a1, 12(a0)
+; RV64M-NEXT:    ld a1, 0(a0)
 ; RV64M-NEXT:    lwu a2, 8(a0)
-; RV64M-NEXT:    slli a1, a1, 32
-; RV64M-NEXT:    or a1, a2, a1
-; RV64M-NEXT:    ld a3, 0(a0)
-; RV64M-NEXT:    slli a1, a1, 29
-; RV64M-NEXT:    srai a1, a1, 31
-; RV64M-NEXT:    slli a2, a2, 31
-; RV64M-NEXT:    srli a4, a3, 33
+; RV64M-NEXT:    srli a3, a1, 2
+; RV64M-NEXT:    lb a4, 12(a0)
+; RV64M-NEXT:    slli a5, a2, 62
+; RV64M-NEXT:    or a3, a5, a3
+; RV64M-NEXT:    srai a3, a3, 31
+; RV64M-NEXT:    slli a4, a4, 32
 ; RV64M-NEXT:    lui a5, %hi(.LCPI3_0)
 ; RV64M-NEXT:    ld a5, %lo(.LCPI3_0)(a5)
-; RV64M-NEXT:    or a2, a4, a2
-; RV64M-NEXT:    slli a2, a2, 31
+; RV64M-NEXT:    or a2, a2, a4
+; RV64M-NEXT:    slli a2, a2, 29
 ; RV64M-NEXT:    srai a2, a2, 31
 ; RV64M-NEXT:    mulh a4, a2, a5
 ; RV64M-NEXT:    srli a5, a4, 63
 ; RV64M-NEXT:    srai a4, a4, 1
 ; RV64M-NEXT:    add a4, a4, a5
-; RV64M-NEXT:    slli a5, a4, 3
-; RV64M-NEXT:    sub a4, a4, a5
+; RV64M-NEXT:    slli a5, a4, 2
+; RV64M-NEXT:    add a4, a5, a4
 ; RV64M-NEXT:    lui a5, %hi(.LCPI3_1)
 ; RV64M-NEXT:    ld a5, %lo(.LCPI3_1)(a5)
-; RV64M-NEXT:    slli a3, a3, 31
-; RV64M-NEXT:    srai a3, a3, 31
+; RV64M-NEXT:    slli a1, a1, 31
+; RV64M-NEXT:    srai a1, a1, 31
 ; RV64M-NEXT:    add a2, a2, a4
-; RV64M-NEXT:    mulh a4, a1, a5
+; RV64M-NEXT:    mulh a4, a3, a5
 ; RV64M-NEXT:    srli a5, a4, 63
 ; RV64M-NEXT:    srai a4, a4, 1
 ; RV64M-NEXT:    add a4, a4, a5
-; RV64M-NEXT:    slli a5, a4, 2
-; RV64M-NEXT:    add a4, a5, a4
-; RV64M-NEXT:    add a1, a1, a4
-; RV64M-NEXT:    addi a1, a1, -2
-; RV64M-NEXT:    seqz a1, a1
+; RV64M-NEXT:    slli a5, a4, 3
+; RV64M-NEXT:    sub a4, a4, a5
+; RV64M-NEXT:    add a3, a3, a4
+; RV64M-NEXT:    addi a3, a3, -1
+; RV64M-NEXT:    seqz a3, a3
 ; RV64M-NEXT:    lui a4, %hi(.LCPI3_2)
 ; RV64M-NEXT:    ld a4, %lo(.LCPI3_2)(a4)
 ; RV64M-NEXT:    lui a5, %hi(.LCPI3_3)
 ; RV64M-NEXT:    ld a5, %lo(.LCPI3_3)(a5)
-; RV64M-NEXT:    addi a2, a2, -1
+; RV64M-NEXT:    addi a2, a2, -2
 ; RV64M-NEXT:    seqz a2, a2
-; RV64M-NEXT:    mul a3, a3, a4
-; RV64M-NEXT:    add a3, a3, a5
-; RV64M-NEXT:    slli a4, a3, 63
-; RV64M-NEXT:    srli a3, a3, 1
-; RV64M-NEXT:    or a3, a3, a4
-; RV64M-NEXT:    sltu a3, a5, a3
+; RV64M-NEXT:    mul a1, a1, a4
+; RV64M-NEXT:    add a1, a1, a5
+; RV64M-NEXT:    slli a4, a1, 63
+; RV64M-NEXT:    srli a1, a1, 1
+; RV64M-NEXT:    or a1, a1, a4
+; RV64M-NEXT:    sltu a1, a5, a1
 ; RV64M-NEXT:    addi a2, a2, -1
-; RV64M-NEXT:    addi a1, a1, -1
-; RV64M-NEXT:    neg a3, a3
-; RV64M-NEXT:    slli a4, a1, 29
-; RV64M-NEXT:    srli a4, a4, 61
-; RV64M-NEXT:    sb a4, 12(a0)
-; RV64M-NEXT:    slli a4, a2, 33
+; RV64M-NEXT:    addi a3, a3, -1
+; RV64M-NEXT:    neg a1, a1
+; RV64M-NEXT:    slli a4, a3, 33
+; RV64M-NEXT:    slli a1, a1, 31
+; RV64M-NEXT:    srli a1, a1, 31
+; RV64M-NEXT:    or a1, a1, a4
+; RV64M-NEXT:    sd a1, 0(a0)
+; RV64M-NEXT:    slli a1, a2, 2
 ; RV64M-NEXT:    slli a3, a3, 31
-; RV64M-NEXT:    srli a3, a3, 31
-; RV64M-NEXT:    or a3, a3, a4
-; RV64M-NEXT:    sd a3, 0(a0)
-; RV64M-NEXT:    slli a1, a1, 2
-; RV64M-NEXT:    slli a2, a2, 31
-; RV64M-NEXT:    srli a2, a2, 62
-; RV64M-NEXT:    or a1, a2, a1
+; RV64M-NEXT:    srli a3, a3, 62
+; RV64M-NEXT:    or a1, a3, a1
 ; RV64M-NEXT:    sw a1, 8(a0)
+; RV64M-NEXT:    slli a1, a2, 29
+; RV64M-NEXT:    srli a1, a1, 61
+; RV64M-NEXT:    sb a1, 12(a0)
 ; RV64M-NEXT:    ret
 ;
 ; RV32MV-LABEL: test_srem_vec:
@@ -714,49 +712,48 @@ define void @test_srem_vec(<3 x i33>* %X) nounwind {
 ; RV64MV-NEXT:    sd s0, 48(sp) # 8-byte Folded Spill
 ; RV64MV-NEXT:    addi s0, sp, 64
 ; RV64MV-NEXT:    andi sp, sp, -32
-; RV64MV-NEXT:    lwu a1, 8(a0)
-; RV64MV-NEXT:    ld a2, 0(a0)
-; RV64MV-NEXT:    slli a3, a1, 31
-; RV64MV-NEXT:    srli a4, a2, 33
-; RV64MV-NEXT:    lb a5, 12(a0)
-; RV64MV-NEXT:    or a3, a4, a3
+; RV64MV-NEXT:    lb a1, 12(a0)
+; RV64MV-NEXT:    lwu a2, 8(a0)
+; RV64MV-NEXT:    slli a1, a1, 32
+; RV64MV-NEXT:    ld a3, 0(a0)
+; RV64MV-NEXT:    or a1, a2, a1
+; RV64MV-NEXT:    slli a1, a1, 29
+; RV64MV-NEXT:    srai a1, a1, 31
+; RV64MV-NEXT:    srli a4, a3, 2
+; RV64MV-NEXT:    slli a2, a2, 62
+; RV64MV-NEXT:    lui a5, %hi(.LCPI3_0)
+; RV64MV-NEXT:    ld a5, %lo(.LCPI3_0)(a5)
+; RV64MV-NEXT:    or a2, a2, a4
 ; RV64MV-NEXT:    slli a3, a3, 31
 ; RV64MV-NEXT:    srai a3, a3, 31
-; RV64MV-NEXT:    slli a4, a5, 32
-; RV64MV-NEXT:    or a1, a1, a4
-; RV64MV-NEXT:    lui a4, %hi(.LCPI3_0)
-; RV64MV-NEXT:    ld a4, %lo(.LCPI3_0)(a4)
-; RV64MV-NEXT:    slli a1, a1, 29
-; RV64MV-NEXT:    slli a2, a2, 31
-; RV64MV-NEXT:    srai a2, a2, 31
-; RV64MV-NEXT:    mulh a4, a2, a4
+; RV64MV-NEXT:    mulh a4, a3, a5
 ; RV64MV-NEXT:    srli a5, a4, 63
 ; RV64MV-NEXT:    add a4, a4, a5
 ; RV64MV-NEXT:    li a5, 6
 ; RV64MV-NEXT:    mul a4, a4, a5
 ; RV64MV-NEXT:    lui a5, %hi(.LCPI3_1)
 ; RV64MV-NEXT:    ld a5, %lo(.LCPI3_1)(a5)
-; RV64MV-NEXT:    srai a1, a1, 31
-; RV64MV-NEXT:    sub a2, a2, a4
-; RV64MV-NEXT:    sd a2, 0(sp)
-; RV64MV-NEXT:    mulh a2, a1, a5
-; RV64MV-NEXT:    srli a4, a2, 63
-; RV64MV-NEXT:    srai a2, a2, 1
-; RV64MV-NEXT:    add a2, a2, a4
-; RV64MV-NEXT:    slli a4, a2, 2
+; RV64MV-NEXT:    srai a2, a2, 31
+; RV64MV-NEXT:    sub a3, a3, a4
+; RV64MV-NEXT:    sd a3, 0(sp)
+; RV64MV-NEXT:    mulh a3, a2, a5
+; RV64MV-NEXT:    srli a4, a3, 63
+; RV64MV-NEXT:    srai a3, a3, 1
+; RV64MV-NEXT:    add a3, a3, a4
+; RV64MV-NEXT:    slli a4, a3, 3
 ; RV64MV-NEXT:    lui a5, %hi(.LCPI3_2)
 ; RV64MV-NEXT:    ld a5, %lo(.LCPI3_2)(a5)
-; RV64MV-NEXT:    add a2, a4, a2
+; RV64MV-NEXT:    sub a3, a3, a4
+; RV64MV-NEXT:    add a2, a2, a3
+; RV64MV-NEXT:    sd a2, 8(sp)
+; RV64MV-NEXT:    mulh a2, a1, a5
+; RV64MV-NEXT:    srli a3, a2, 63
+; RV64MV-NEXT:    srai a2, a2, 1
+; RV64MV-NEXT:    add a2, a2, a3
+; RV64MV-NEXT:    slli a3, a2, 2
+; RV64MV-NEXT:    add a2, a3, a2
 ; RV64MV-NEXT:    add a1, a1, a2
 ; RV64MV-NEXT:    sd a1, 16(sp)
-; RV64MV-NEXT:    mulh a1, a3, a5
-; RV64MV-NEXT:    srli a2, a1, 63
-; RV64MV-NEXT:    srai a1, a1, 1
-; RV64MV-NEXT:    add a1, a1, a2
-; RV64MV-NEXT:    slli a2, a1, 3
-; RV64MV-NEXT:    sub a1, a1, a2
-; RV64MV-NEXT:    add a1, a3, a1
-; RV64MV-NEXT:    sd a1, 8(sp)
 ; RV64MV-NEXT:    mv a1, sp
 ; RV64MV-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
 ; RV64MV-NEXT:    vle64.v v8, (a1)

diff --git a/llvm/test/CodeGen/RISCV/unaligned-load-store.ll b/llvm/test/CodeGen/RISCV/unaligned-load-store.ll
@@ -64,27 +64,27 @@ define i32 @load_i32(i32* %p) {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lbu a1, 1(a0)
 ; RV32I-NEXT:    lbu a2, 0(a0)
-; RV32I-NEXT:    lbu a3, 3(a0)
-; RV32I-NEXT:    lbu a0, 2(a0)
+; RV32I-NEXT:    lbu a3, 2(a0)
+; RV32I-NEXT:    lbu a0, 3(a0)
 ; RV32I-NEXT:    slli a1, a1, 8
 ; RV32I-NEXT:    or a1, a1, a2
-; RV32I-NEXT:    slli a2, a3, 8
-; RV32I-NEXT:    or a0, a2, a0
-; RV32I-NEXT:    slli a0, a0, 16
+; RV32I-NEXT:    slli a2, a3, 16
+; RV32I-NEXT:    slli a0, a0, 24
+; RV32I-NEXT:    or a0, a0, a2
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: load_i32:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lbu a1, 1(a0)
 ; RV64I-NEXT:    lbu a2, 0(a0)
-; RV64I-NEXT:    lb a3, 3(a0)
-; RV64I-NEXT:    lbu a0, 2(a0)
+; RV64I-NEXT:    lbu a3, 2(a0)
+; RV64I-NEXT:    lb a0, 3(a0)
 ; RV64I-NEXT:    slli a1, a1, 8
 ; RV64I-NEXT:    or a1, a1, a2
-; RV64I-NEXT:    slli a2, a3, 8
-; RV64I-NEXT:    or a0, a2, a0
-; RV64I-NEXT:    slli a0, a0, 16
+; RV64I-NEXT:    slli a2, a3, 16
+; RV64I-NEXT:    slli a0, a0, 24
+; RV64I-NEXT:    or a0, a0, a2
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
@@ -101,23 +101,23 @@ define i64 @load_i64(i64* %p) {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lbu a1, 1(a0)
 ; RV32I-NEXT:    lbu a2, 0(a0)
-; RV32I-NEXT:    lbu a3, 3(a0)
-; RV32I-NEXT:    lbu a4, 2(a0)
+; RV32I-NEXT:    lbu a3, 2(a0)
+; RV32I-NEXT:    lbu a4, 3(a0)
 ; RV32I-NEXT:    slli a1, a1, 8
 ; RV32I-NEXT:    or a1, a1, a2
-; RV32I-NEXT:    slli a2, a3, 8
-; RV32I-NEXT:    or a2, a2, a4
-; RV32I-NEXT:    slli a2, a2, 16
+; RV32I-NEXT:    slli a2, a3, 16
+; RV32I-NEXT:    slli a3, a4, 24
+; RV32I-NEXT:    or a2, a3, a2
 ; RV32I-NEXT:    or a2, a2, a1
 ; RV32I-NEXT:    lbu a1, 5(a0)
 ; RV32I-NEXT:    lbu a3, 4(a0)
-; RV32I-NEXT:    lbu a4, 7(a0)
-; RV32I-NEXT:    lbu a0, 6(a0)
+; RV32I-NEXT:    lbu a4, 6(a0)
+; RV32I-NEXT:    lbu a0, 7(a0)
 ; RV32I-NEXT:    slli a1, a1, 8
 ; RV32I-NEXT:    or a1, a1, a3
-; RV32I-NEXT:    slli a3, a4, 8
-; RV32I-NEXT:    or a0, a3, a0
-; RV32I-NEXT:    slli a0, a0, 16
+; RV32I-NEXT:    slli a3, a4, 16
+; RV32I-NEXT:    slli a0, a0, 24
+; RV32I-NEXT:    or a0, a0, a3
 ; RV32I-NEXT:    or a1, a0, a1
 ; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:    ret
@@ -126,23 +126,23 @@ define i64 @load_i64(i64* %p) {
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lbu a1, 1(a0)
 ; RV64I-NEXT:    lbu a2, 0(a0)
-; RV64I-NEXT:    lbu a3, 3(a0)
-; RV64I-NEXT:    lbu a4, 2(a0)
+; RV64I-NEXT:    lbu a3, 2(a0)
+; RV64I-NEXT:    lbu a4, 3(a0)
 ; RV64I-NEXT:    slli a1, a1, 8
 ; RV64I-NEXT:    or a1, a1, a2
-; RV64I-NEXT:    slli a2, a3, 8
-; RV64I-NEXT:    or a2, a2, a4
-; RV64I-NEXT:    slli a2, a2, 16
+; RV64I-NEXT:    slli a2, a3, 16
+; RV64I-NEXT:    slli a3, a4, 24
+; RV64I-NEXT:    or a2, a3, a2
 ; RV64I-NEXT:    or a1, a2, a1
 ; RV64I-NEXT:    lbu a2, 5(a0)
 ; RV64I-NEXT:    lbu a3, 4(a0)
-; RV64I-NEXT:    lbu a4, 7(a0)
-; RV64I-NEXT:    lbu a0, 6(a0)
+; RV64I-NEXT:    lbu a4, 6(a0)
+; RV64I-NEXT:    lbu a0, 7(a0)
 ; RV64I-NEXT:    slli a2, a2, 8
 ; RV64I-NEXT:    or a2, a2, a3
-; RV64I-NEXT:    slli a3, a4, 8
-; RV64I-NEXT:    or a0, a3, a0
-; RV64I-NEXT:    slli a0, a0, 16
+; RV64I-NEXT:    slli a3, a4, 16
+; RV64I-NEXT:    slli a0, a0, 24
+; RV64I-NEXT:    or a0, a0, a3
 ; RV64I-NEXT:    or a0, a0, a2
 ; RV64I-NEXT:    slli a0, a0, 32
 ; RV64I-NEXT:    or a0, a0, a1

diff --git a/llvm/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll b/llvm/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll
@@ -73,46 +73,41 @@ define i16 @fun1(<16 x i1> %src)
 define void @fun2(<8 x i32> %src, ptr %p)
 ; CHECK-LABEL: fun2:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    stmg %r14, %r15, 112(%r15)
-; CHECK-NEXT:    .cfi_offset %r14, -48
-; CHECK-NEXT:    .cfi_offset %r15, -40
 ; CHECK-NEXT:    vlgvf %r1, %v26, 3
-; CHECK-NEXT:    vlgvf %r0, %v26, 2
+; CHECK-NEXT:    vlgvf %r5, %v24, 0
+; CHECK-NEXT:    vlgvf %r3, %v24, 1
+; CHECK-NEXT:    srlk %r0, %r1, 8
+; CHECK-NEXT:    sllg %r5, %r5, 33
+; CHECK-NEXT:    sth %r0, 28(%r2)
+; CHECK-NEXT:    rosbg %r5, %r3, 31, 55, 2
+; CHECK-NEXT:    vlgvf %r0, %v24, 2
+; CHECK-NEXT:    sllg %r4, %r3, 58
+; CHECK-NEXT:    vlgvf %r3, %v26, 2
 ; CHECK-NEXT:    stc %r1, 30(%r2)
-; CHECK-NEXT:    srlk %r3, %r1, 8
+; CHECK-NEXT:    rosbg %r4, %r0, 6, 36, 27
 ; CHECK-NEXT:    risbgn %r1, %r1, 33, 167, 0
-; CHECK-NEXT:    vlgvf %r5, %v24, 2
-; CHECK-NEXT:    rosbg %r1, %r0, 2, 32, 31
-; CHECK-NEXT:    sth %r3, 28(%r2)
+; CHECK-NEXT:    rosbg %r1, %r3, 2, 32, 31
 ; CHECK-NEXT:    srlg %r1, %r1, 24
-; CHECK-NEXT:    vlgvf %r3, %v24, 3
+; CHECK-NEXT:    rosbg %r5, %r4, 56, 63, 8
+; CHECK-NEXT:    vlgvf %r4, %v24, 3
 ; CHECK-NEXT:    st %r1, 24(%r2)
 ; CHECK-NEXT:    vlgvf %r1, %v26, 0
-; CHECK-NEXT:    risbgn %r14, %r5, 6, 164, 27
-; CHECK-NEXT:    sllg %r4, %r3, 60
-; CHECK-NEXT:    rosbg %r14, %r3, 37, 63, 60
-; CHECK-NEXT:    sllg %r3, %r14, 8
-; CHECK-NEXT:    rosbg %r4, %r1, 4, 34, 29
-; CHECK-NEXT:    rosbg %r3, %r4, 56, 63, 8
-; CHECK-NEXT:    stg %r3, 8(%r2)
-; CHECK-NEXT:    vlgvf %r3, %v24, 1
-; CHECK-NEXT:    sllg %r4, %r3, 58
-; CHECK-NEXT:    rosbg %r4, %r5, 6, 36, 27
-; CHECK-NEXT:    vlgvf %r5, %v24, 0
-; CHECK-NEXT:    sllg %r5, %r5, 25
-; CHECK-NEXT:    rosbg %r5, %r3, 39, 63, 58
-; CHECK-NEXT:    sllg %r3, %r5, 8
-; CHECK-NEXT:    rosbg %r3, %r4, 56, 63, 8
-; CHECK-NEXT:    stg %r3, 0(%r2)
-; CHECK-NEXT:    vlgvf %r3, %v26, 1
-; CHECK-NEXT:    sllg %r4, %r3, 62
-; CHECK-NEXT:    rosbg %r4, %r0, 2, 32, 31
-; CHECK-NEXT:    risbgn %r0, %r1, 4, 162, 29
-; CHECK-NEXT:    rosbg %r0, %r3, 35, 63, 62
+; CHECK-NEXT:    risbgn %r0, %r0, 6, 164, 27
+; CHECK-NEXT:    rosbg %r0, %r4, 37, 63, 60
+; CHECK-NEXT:    stg %r5, 0(%r2)
+; CHECK-NEXT:    sllg %r5, %r4, 60
 ; CHECK-NEXT:    sllg %r0, %r0, 8
+; CHECK-NEXT:    rosbg %r5, %r1, 4, 34, 29
+; CHECK-NEXT:    risbgn %r1, %r1, 4, 162, 29
+; CHECK-NEXT:    rosbg %r0, %r5, 56, 63, 8
+; CHECK-NEXT:    stg %r0, 8(%r2)
+; CHECK-NEXT:    vlgvf %r0, %v26, 1
+; CHECK-NEXT:    sllg %r4, %r0, 62
+; CHECK-NEXT:    rosbg %r1, %r0, 35, 63, 62
+; CHECK-NEXT:    sllg %r0, %r1, 8
+; CHECK-NEXT:    rosbg %r4, %r3, 2, 32, 31
 ; CHECK-NEXT:    rosbg %r0, %r4, 56, 63, 8
 ; CHECK-NEXT:    stg %r0, 16(%r2)
-; CHECK-NEXT:    lmg %r14, %r15, 112(%r15)
 ; CHECK-NEXT:    br %r14
 {
   %tmp = trunc <8 x i32> %src to <8 x i31>

diff --git a/llvm/test/CodeGen/Thumb/urem-seteq-illegal-types.ll b/llvm/test/CodeGen/Thumb/urem-seteq-illegal-types.ll
@@ -31,12 +31,12 @@ define i1 @test_urem_even(i27 %X) nounwind {
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    ldr r1, .LCPI1_0
 ; CHECK-NEXT:    muls r1, r0, r1
-; CHECK-NEXT:    lsls r0, r1, #26
+; CHECK-NEXT:    lsls r0, r1, #31
 ; CHECK-NEXT:    ldr r2, .LCPI1_1
 ; CHECK-NEXT:    ands r2, r1
 ; CHECK-NEXT:    lsrs r1, r2, #1
-; CHECK-NEXT:    adds r0, r1, r0
-; CHECK-NEXT:    lsls r0, r0, #5
+; CHECK-NEXT:    lsls r1, r1, #5
+; CHECK-NEXT:    adds r0, r0, r1
 ; CHECK-NEXT:    ldr r1, .LCPI1_2
 ; CHECK-NEXT:    cmp r0, r1
 ; CHECK-NEXT:    blo .LBB1_2

diff --git a/llvm/test/CodeGen/X86/bool-vector.ll b/llvm/test/CodeGen/X86/bool-vector.ll
@@ -13,10 +13,10 @@ define i32 @PR15215_bad(<4 x i32> %input) {
 ; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %edx
 ; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %ecx
 ; X86-NEXT:    movb {{[0-9]+}}(%esp), %ah
-; X86-NEXT:    addb %ah, %ah
+; X86-NEXT:    shlb $3, %ah
 ; X86-NEXT:    andb $1, %cl
-; X86-NEXT:    orb %ah, %cl
 ; X86-NEXT:    shlb $2, %cl
+; X86-NEXT:    orb %ah, %cl
 ; X86-NEXT:    addb %dl, %dl
 ; X86-NEXT:    andb $1, %al
 ; X86-NEXT:    orb %dl, %al
@@ -28,10 +28,10 @@ define i32 @PR15215_bad(<4 x i32> %input) {
 ;
 ; X64-LABEL: PR15215_bad:
 ; X64:       # %bb.0: # %entry
-; X64-NEXT:    addb %cl, %cl
+; X64-NEXT:    shlb $3, %cl
 ; X64-NEXT:    andb $1, %dl
-; X64-NEXT:    orb %cl, %dl
 ; X64-NEXT:    shlb $2, %dl
+; X64-NEXT:    orb %cl, %dl
 ; X64-NEXT:    addb %sil, %sil
 ; X64-NEXT:    andb $1, %dil
 ; X64-NEXT:    orb %sil, %dil

diff --git a/llvm/test/CodeGen/X86/combine-bitreverse.ll b/llvm/test/CodeGen/X86/combine-bitreverse.ll
@@ -233,13 +233,13 @@ define i32 @test_bitreverse_shli_bitreverse(i32 %a0) nounwind {
 ; X86-NEXT:    andl $858993459, %ecx # imm = 0x33333333
 ; X86-NEXT:    shrl $2, %eax
 ; X86-NEXT:    andl $858993459, %eax # imm = 0x33333333
-; X86-NEXT:    leal (%eax,%ecx,4), %eax
-; X86-NEXT:    movl %eax, %ecx
-; X86-NEXT:    andl $5592405, %ecx # imm = 0x555555
-; X86-NEXT:    shrl %eax
-; X86-NEXT:    andl $22369621, %eax # imm = 0x1555555
-; X86-NEXT:    leal (%eax,%ecx,2), %eax
-; X86-NEXT:    shll $7, %eax
+; X86-NEXT:    leal (%eax,%ecx,4), %ecx
+; X86-NEXT:    movl %ecx, %eax
+; X86-NEXT:    andl $5592405, %eax # imm = 0x555555
+; X86-NEXT:    shll $6, %ecx
+; X86-NEXT:    andl $-1431655808, %ecx # imm = 0xAAAAAA80
+; X86-NEXT:    shll $8, %eax
+; X86-NEXT:    orl %ecx, %eax
 ; X86-NEXT:    bswapl %eax
 ; X86-NEXT:    movl %eax, %ecx
 ; X86-NEXT:    andl $986895, %ecx # imm = 0xF0F0F
@@ -276,22 +276,22 @@ define i32 @test_bitreverse_shli_bitreverse(i32 %a0) nounwind {
 ; X64-NEXT:    leal (%rdi,%rax,4), %eax
 ; X64-NEXT:    movl %eax, %ecx
 ; X64-NEXT:    andl $5592405, %ecx # imm = 0x555555
-; X64-NEXT:    shrl %eax
-; X64-NEXT:    andl $22369621, %eax # imm = 0x1555555
-; X64-NEXT:    leal (%rax,%rcx,2), %eax
-; X64-NEXT:    shll $7, %eax
-; X64-NEXT:    bswapl %eax
-; X64-NEXT:    movl %eax, %ecx
-; X64-NEXT:    andl $986895, %ecx # imm = 0xF0F0F
-; X64-NEXT:    shll $4, %ecx
-; X64-NEXT:    shrl $4, %eax
-; X64-NEXT:    andl $135204623, %eax # imm = 0x80F0F0F
-; X64-NEXT:    orl %ecx, %eax
-; X64-NEXT:    movl %eax, %ecx
-; X64-NEXT:    andl $3355443, %ecx # imm = 0x333333
-; X64-NEXT:    shrl $2, %eax
-; X64-NEXT:    andl $36909875, %eax # imm = 0x2333333
-; X64-NEXT:    leal (%rax,%rcx,4), %eax
+; X64-NEXT:    shll $6, %eax
+; X64-NEXT:    andl $-1431655808, %eax # imm = 0xAAAAAA80
+; X64-NEXT:    shll $8, %ecx
+; X64-NEXT:    orl %eax, %ecx
+; X64-NEXT:    bswapl %ecx
+; X64-NEXT:    movl %ecx, %eax
+; X64-NEXT:    andl $986895, %eax # imm = 0xF0F0F
+; X64-NEXT:    shll $4, %eax
+; X64-NEXT:    shrl $4, %ecx
+; X64-NEXT:    andl $135204623, %ecx # imm = 0x80F0F0F
+; X64-NEXT:    orl %eax, %ecx
+; X64-NEXT:    movl %ecx, %eax
+; X64-NEXT:    andl $3355443, %eax # imm = 0x333333
+; X64-NEXT:    shrl $2, %ecx
+; X64-NEXT:    andl $36909875, %ecx # imm = 0x2333333
+; X64-NEXT:    leal (%rcx,%rax,4), %eax
 ; X64-NEXT:    movl %eax, %ecx
 ; X64-NEXT:    andl $1431655765, %ecx # imm = 0x55555555
 ; X64-NEXT:    shrl %eax
@@ -322,10 +322,8 @@ define i64 @test_bitreverse_shli_bitreverse_i64(i64 %a) nounwind {
 ; X86-NEXT:    leal (%eax,%ecx,4), %eax
 ; X86-NEXT:    movl %eax, %ecx
 ; X86-NEXT:    andl $357913941, %ecx # imm = 0x15555555
-; X86-NEXT:    shrl %eax
-; X86-NEXT:    andl $1431655765, %eax # imm = 0x55555555
-; X86-NEXT:    leal (%eax,%ecx,2), %eax
-; X86-NEXT:    addl %eax, %eax
+; X86-NEXT:    andl $-1431655766, %eax # imm = 0xAAAAAAAA
+; X86-NEXT:    leal (%eax,%ecx,4), %eax
 ; X86-NEXT:    bswapl %eax
 ; X86-NEXT:    movl %eax, %ecx
 ; X86-NEXT:    andl $235867919, %ecx # imm = 0xE0F0F0F

diff --git a/llvm/test/CodeGen/X86/is_fpclass.ll b/llvm/test/CodeGen/X86/is_fpclass.ll
@@ -857,12 +857,13 @@ define <4 x i1> @isnan_v4f(<4 x float> %x) {
 ; CHECK-32-NEXT:    # kill: def $ah killed $ah killed $ax
 ; CHECK-32-NEXT:    sahf
 ; CHECK-32-NEXT:    setp %dh
+; CHECK-32-NEXT:    shlb $2, %dh
 ; CHECK-32-NEXT:    fucomp %st(0)
 ; CHECK-32-NEXT:    fnstsw %ax
 ; CHECK-32-NEXT:    # kill: def $ah killed $ah killed $ax
 ; CHECK-32-NEXT:    sahf
 ; CHECK-32-NEXT:    setp %dl
-; CHECK-32-NEXT:    addb %dl, %dl
+; CHECK-32-NEXT:    shlb $3, %dl
 ; CHECK-32-NEXT:    orb %dh, %dl
 ; CHECK-32-NEXT:    fucomp %st(0)
 ; CHECK-32-NEXT:    fnstsw %ax
@@ -876,7 +877,6 @@ define <4 x i1> @isnan_v4f(<4 x float> %x) {
 ; CHECK-32-NEXT:    setp %al
 ; CHECK-32-NEXT:    addb %al, %al
 ; CHECK-32-NEXT:    orb %dh, %al
-; CHECK-32-NEXT:    shlb $2, %al
 ; CHECK-32-NEXT:    orb %dl, %al
 ; CHECK-32-NEXT:    movb %al, (%ecx)
 ; CHECK-32-NEXT:    movl %ecx, %eax
@@ -903,11 +903,12 @@ define <4 x i1> @isnan_v4f_strictfp(<4 x float> %x) strictfp {
 ; CHECK-32-NEXT:    andl %ecx, %edx
 ; CHECK-32-NEXT:    cmpl $2139095041, %edx # imm = 0x7F800001
 ; CHECK-32-NEXT:    setge %dh
+; CHECK-32-NEXT:    shlb $2, %dh
 ; CHECK-32-NEXT:    movl {{[0-9]+}}(%esp), %esi
 ; CHECK-32-NEXT:    andl %ecx, %esi
 ; CHECK-32-NEXT:    cmpl $2139095041, %esi # imm = 0x7F800001
 ; CHECK-32-NEXT:    setge %dl
-; CHECK-32-NEXT:    addb %dl, %dl
+; CHECK-32-NEXT:    shlb $3, %dl
 ; CHECK-32-NEXT:    orb %dh, %dl
 ; CHECK-32-NEXT:    movl {{[0-9]+}}(%esp), %esi
 ; CHECK-32-NEXT:    andl %ecx, %esi
@@ -918,7 +919,6 @@ define <4 x i1> @isnan_v4f_strictfp(<4 x float> %x) strictfp {
 ; CHECK-32-NEXT:    setge %cl
 ; CHECK-32-NEXT:    addb %cl, %cl
 ; CHECK-32-NEXT:    orb %dh, %cl
-; CHECK-32-NEXT:    shlb $2, %cl
 ; CHECK-32-NEXT:    orb %dl, %cl
 ; CHECK-32-NEXT:    movb %cl, (%eax)
 ; CHECK-32-NEXT:    popl %esi

diff --git a/llvm/test/CodeGen/X86/vector-sext.ll b/llvm/test/CodeGen/X86/vector-sext.ll
@@ -3519,11 +3519,11 @@ define <4 x i32> @sext_4i17_to_4i32(ptr %ptr) {
 ; SSE2-NEXT:    movd %ecx, %xmm1
 ; SSE2-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
 ; SSE2-NEXT:    movl 8(%rdi), %ecx
-; SSE2-NEXT:    shll $13, %ecx
+; SSE2-NEXT:    shll $28, %ecx
 ; SSE2-NEXT:    movq %rax, %rdx
 ; SSE2-NEXT:    shrq $51, %rdx
-; SSE2-NEXT:    orl %ecx, %edx
 ; SSE2-NEXT:    shll $15, %edx
+; SSE2-NEXT:    orl %ecx, %edx
 ; SSE2-NEXT:    sarl $15, %edx
 ; SSE2-NEXT:    movd %edx, %xmm1
 ; SSE2-NEXT:    shrq $34, %rax
@@ -3548,11 +3548,11 @@ define <4 x i32> @sext_4i17_to_4i32(ptr %ptr) {
 ; SSSE3-NEXT:    movd %ecx, %xmm1
 ; SSSE3-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
 ; SSSE3-NEXT:    movl 8(%rdi), %ecx
-; SSSE3-NEXT:    shll $13, %ecx
+; SSSE3-NEXT:    shll $28, %ecx
 ; SSSE3-NEXT:    movq %rax, %rdx
 ; SSSE3-NEXT:    shrq $51, %rdx
-; SSSE3-NEXT:    orl %ecx, %edx
 ; SSSE3-NEXT:    shll $15, %edx
+; SSSE3-NEXT:    orl %ecx, %edx
 ; SSSE3-NEXT:    sarl $15, %edx
 ; SSSE3-NEXT:    movd %edx, %xmm1
 ; SSSE3-NEXT:    shrq $34, %rax
@@ -3581,10 +3581,10 @@ define <4 x i32> @sext_4i17_to_4i32(ptr %ptr) {
 ; SSE41-NEXT:    sarl $15, %ecx
 ; SSE41-NEXT:    pinsrd $2, %ecx, %xmm0
 ; SSE41-NEXT:    movl 8(%rdi), %ecx
-; SSE41-NEXT:    shll $13, %ecx
+; SSE41-NEXT:    shll $28, %ecx
 ; SSE41-NEXT:    shrq $51, %rax
-; SSE41-NEXT:    orl %ecx, %eax
 ; SSE41-NEXT:    shll $15, %eax
+; SSE41-NEXT:    orl %ecx, %eax
 ; SSE41-NEXT:    sarl $15, %eax
 ; SSE41-NEXT:    pinsrd $3, %eax, %xmm0
 ; SSE41-NEXT:    retq
@@ -3607,10 +3607,10 @@ define <4 x i32> @sext_4i17_to_4i32(ptr %ptr) {
 ; AVX-NEXT:    sarl $15, %ecx
 ; AVX-NEXT:    vpinsrd $2, %ecx, %xmm0, %xmm0
 ; AVX-NEXT:    movl 8(%rdi), %ecx
-; AVX-NEXT:    shll $13, %ecx
+; AVX-NEXT:    shll $28, %ecx
 ; AVX-NEXT:    shrq $51, %rax
-; AVX-NEXT:    orl %ecx, %eax
 ; AVX-NEXT:    shll $15, %eax
+; AVX-NEXT:    orl %ecx, %eax
 ; AVX-NEXT:    sarl $15, %eax
 ; AVX-NEXT:    vpinsrd $3, %eax, %xmm0, %xmm0
 ; AVX-NEXT:    retq