214 changes: 82 additions & 132 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-fma.ll
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87 changes: 32 additions & 55 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-mul.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -8,16 +8,15 @@
define amdgpu_vs float @test_f16_f32_add_ext_mul(half inreg %x, half inreg %y, float inreg %z) {
; GFX9-FAST-DENORM-LABEL: test_f16_f32_add_ext_mul:
; GFX9-FAST-DENORM: ; %bb.0: ; %.entry
; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v0, s0
; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v1, s1
; GFX9-FAST-DENORM-NEXT: v_mad_f32 v0, v0, v1, s2
; GFX9-FAST-DENORM-NEXT: v_mov_b32_e32 v0, s1
; GFX9-FAST-DENORM-NEXT: v_mov_b32_e32 v1, s2
; GFX9-FAST-DENORM-NEXT: v_mad_mix_f32 v0, s0, v0, v1 op_sel_hi:[1,1,0]
; GFX9-FAST-DENORM-NEXT: ; return to shader part epilog
;
; GFX10-FAST-DENORM-LABEL: test_f16_f32_add_ext_mul:
; GFX10-FAST-DENORM: ; %bb.0: ; %.entry
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v0, s0
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v1, s1
; GFX10-FAST-DENORM-NEXT: v_fma_f32 v0, v0, v1, s2
; GFX10-FAST-DENORM-NEXT: v_mov_b32_e32 v0, s2
; GFX10-FAST-DENORM-NEXT: v_fma_mix_f32 v0, s0, s1, v0 op_sel_hi:[1,1,0]
; GFX10-FAST-DENORM-NEXT: ; return to shader part epilog
.entry:
%a = fmul fast half %x, %y
Expand All @@ -29,16 +28,15 @@ define amdgpu_vs float @test_f16_f32_add_ext_mul(half inreg %x, half inreg %y, f
define amdgpu_vs float @test_f16_f32_add_ext_mul_rhs(half inreg %x, half inreg %y, float inreg %z) {
; GFX9-FAST-DENORM-LABEL: test_f16_f32_add_ext_mul_rhs:
; GFX9-FAST-DENORM: ; %bb.0: ; %.entry
; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v0, s0
; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v1, s1
; GFX9-FAST-DENORM-NEXT: v_mad_f32 v0, v0, v1, s2
; GFX9-FAST-DENORM-NEXT: v_mov_b32_e32 v0, s1
; GFX9-FAST-DENORM-NEXT: v_mov_b32_e32 v1, s2
; GFX9-FAST-DENORM-NEXT: v_mad_mix_f32 v0, s0, v0, v1 op_sel_hi:[1,1,0]
; GFX9-FAST-DENORM-NEXT: ; return to shader part epilog
;
; GFX10-FAST-DENORM-LABEL: test_f16_f32_add_ext_mul_rhs:
; GFX10-FAST-DENORM: ; %bb.0: ; %.entry
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v0, s0
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v1, s1
; GFX10-FAST-DENORM-NEXT: v_fma_f32 v0, v0, v1, s2
; GFX10-FAST-DENORM-NEXT: v_mov_b32_e32 v0, s2
; GFX10-FAST-DENORM-NEXT: v_fma_mix_f32 v0, s0, s1, v0 op_sel_hi:[1,1,0]
; GFX10-FAST-DENORM-NEXT: ; return to shader part epilog
.entry:
%a = fmul fast half %x, %y
Expand Down Expand Up @@ -70,25 +68,16 @@ define amdgpu_vs <5 x float> @test_5xf16_5xf32_add_ext_mul(<5 x half> inreg %x,
;
; GFX10-FAST-DENORM-LABEL: test_5xf16_5xf32_add_ext_mul:
; GFX10-FAST-DENORM: ; %bb.0: ; %.entry
; GFX10-FAST-DENORM-NEXT: s_lshr_b32 s11, s0, 16
; GFX10-FAST-DENORM-NEXT: s_lshr_b32 s12, s1, 16
; GFX10-FAST-DENORM-NEXT: s_lshr_b32 s13, s3, 16
; GFX10-FAST-DENORM-NEXT: s_lshr_b32 s14, s4, 16
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v0, s0
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v1, s11
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v2, s1
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v3, s12
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v4, s2
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v5, s3
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v6, s13
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v7, s4
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v8, s14
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v9, s5
; GFX10-FAST-DENORM-NEXT: v_fma_f32 v0, v0, v5, s6
; GFX10-FAST-DENORM-NEXT: v_fma_f32 v1, v1, v6, s7
; GFX10-FAST-DENORM-NEXT: v_fma_f32 v2, v2, v7, s8
; GFX10-FAST-DENORM-NEXT: v_fma_f32 v3, v3, v8, s9
; GFX10-FAST-DENORM-NEXT: v_fma_f32 v4, v4, v9, s10
; GFX10-FAST-DENORM-NEXT: v_mov_b32_e32 v0, s6
; GFX10-FAST-DENORM-NEXT: v_mov_b32_e32 v1, s7
; GFX10-FAST-DENORM-NEXT: v_mov_b32_e32 v2, s8
; GFX10-FAST-DENORM-NEXT: v_mov_b32_e32 v3, s9
; GFX10-FAST-DENORM-NEXT: v_mov_b32_e32 v4, s10
; GFX10-FAST-DENORM-NEXT: v_fma_mix_f32 v0, s0, s3, v0 op_sel_hi:[1,1,0]
; GFX10-FAST-DENORM-NEXT: v_fma_mix_f32 v1, s0, s3, v1 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; GFX10-FAST-DENORM-NEXT: v_fma_mix_f32 v2, s1, s4, v2 op_sel_hi:[1,1,0]
; GFX10-FAST-DENORM-NEXT: v_fma_mix_f32 v3, s1, s4, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; GFX10-FAST-DENORM-NEXT: v_fma_mix_f32 v4, s2, s5, v4 op_sel_hi:[1,1,0]
; GFX10-FAST-DENORM-NEXT: ; return to shader part epilog
.entry:
%a = fmul fast <5 x half> %x, %y
Expand Down Expand Up @@ -122,30 +111,18 @@ define amdgpu_vs <6 x float> @test_6xf16_6xf32_add_ext_mul_rhs(<6 x half> inreg
;
; GFX10-FAST-DENORM-LABEL: test_6xf16_6xf32_add_ext_mul_rhs:
; GFX10-FAST-DENORM: ; %bb.0: ; %.entry
; GFX10-FAST-DENORM-NEXT: s_lshr_b32 s12, s0, 16
; GFX10-FAST-DENORM-NEXT: s_lshr_b32 s13, s1, 16
; GFX10-FAST-DENORM-NEXT: s_lshr_b32 s14, s2, 16
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v0, s0
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v2, s1
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v4, s2
; GFX10-FAST-DENORM-NEXT: s_lshr_b32 s0, s3, 16
; GFX10-FAST-DENORM-NEXT: s_lshr_b32 s1, s4, 16
; GFX10-FAST-DENORM-NEXT: s_lshr_b32 s2, s5, 16
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v1, s12
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v3, s13
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v5, s14
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v6, s3
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v7, s0
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v8, s4
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v9, s1
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v10, s5
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v11, s2
; GFX10-FAST-DENORM-NEXT: v_fma_f32 v0, v0, v6, s6
; GFX10-FAST-DENORM-NEXT: v_fma_f32 v1, v1, v7, s7
; GFX10-FAST-DENORM-NEXT: v_fma_f32 v2, v2, v8, s8
; GFX10-FAST-DENORM-NEXT: v_fma_f32 v3, v3, v9, s9
; GFX10-FAST-DENORM-NEXT: v_fma_f32 v4, v4, v10, s10
; GFX10-FAST-DENORM-NEXT: v_fma_f32 v5, v5, v11, s11
; GFX10-FAST-DENORM-NEXT: v_mov_b32_e32 v0, s6
; GFX10-FAST-DENORM-NEXT: v_mov_b32_e32 v1, s7
; GFX10-FAST-DENORM-NEXT: v_mov_b32_e32 v2, s8
; GFX10-FAST-DENORM-NEXT: v_mov_b32_e32 v3, s9
; GFX10-FAST-DENORM-NEXT: v_mov_b32_e32 v4, s10
; GFX10-FAST-DENORM-NEXT: v_mov_b32_e32 v5, s11
; GFX10-FAST-DENORM-NEXT: v_fma_mix_f32 v0, s0, s3, v0 op_sel_hi:[1,1,0]
; GFX10-FAST-DENORM-NEXT: v_fma_mix_f32 v1, s0, s3, v1 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; GFX10-FAST-DENORM-NEXT: v_fma_mix_f32 v2, s1, s4, v2 op_sel_hi:[1,1,0]
; GFX10-FAST-DENORM-NEXT: v_fma_mix_f32 v3, s1, s4, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; GFX10-FAST-DENORM-NEXT: v_fma_mix_f32 v4, s2, s5, v4 op_sel_hi:[1,1,0]
; GFX10-FAST-DENORM-NEXT: v_fma_mix_f32 v5, s2, s5, v5 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; GFX10-FAST-DENORM-NEXT: ; return to shader part epilog
.entry:
%a = fmul fast <6 x half> %x, %y
Expand Down
50 changes: 14 additions & 36 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-mul.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -6,16 +6,12 @@
define amdgpu_vs float @test_f16_to_f32_sub_ext_mul(half %x, half %y, float %z) {
; GFX9-DENORM-LABEL: test_f16_to_f32_sub_ext_mul:
; GFX9-DENORM: ; %bb.0: ; %entry
; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX9-DENORM-NEXT: v_mad_f32 v0, v0, v1, -v2
; GFX9-DENORM-NEXT: v_mad_mix_f32 v0, v0, v1, -v2 op_sel_hi:[1,1,0]
; GFX9-DENORM-NEXT: ; return to shader part epilog
;
; GFX10-DENORM-LABEL: test_f16_to_f32_sub_ext_mul:
; GFX10-DENORM: ; %bb.0: ; %entry
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX10-DENORM-NEXT: v_fma_f32 v0, v0, v1, -v2
; GFX10-DENORM-NEXT: v_fma_mix_f32 v0, v0, v1, -v2 op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: ; return to shader part epilog
entry:
%a = fmul fast half %x, %y
Expand All @@ -28,16 +24,12 @@ entry:
define amdgpu_vs float @test_f16_to_f32_sub_ext_mul_rhs(float %x, half %y, half %z) {
; GFX9-DENORM-LABEL: test_f16_to_f32_sub_ext_mul_rhs:
; GFX9-DENORM: ; %bb.0: ; %.entry
; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v2, v2
; GFX9-DENORM-NEXT: v_mad_f32 v0, -v1, v2, v0
; GFX9-DENORM-NEXT: v_mad_mix_f32 v0, -v1, v2, v0 op_sel_hi:[1,1,0]
; GFX9-DENORM-NEXT: ; return to shader part epilog
;
; GFX10-DENORM-LABEL: test_f16_to_f32_sub_ext_mul_rhs:
; GFX10-DENORM: ; %bb.0: ; %.entry
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v2, v2
; GFX10-DENORM-NEXT: v_fma_f32 v0, -v1, v2, v0
; GFX10-DENORM-NEXT: v_fma_mix_f32 v0, -v1, v2, v0 op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: ; return to shader part epilog
.entry:
%a = fmul fast half %y, %z
Expand All @@ -64,18 +56,12 @@ define amdgpu_vs <4 x float> @test_v4f16_to_v4f32_sub_ext_mul(<4 x half> %x, <4
;
; GFX10-DENORM-LABEL: test_v4f16_to_v4f32_sub_ext_mul:
; GFX10-DENORM: ; %bb.0: ; %entry
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v8, v0
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v10, v1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v11, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v0, v2
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v2, v3
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_fma_f32 v0, v8, v0, -v4
; GFX10-DENORM-NEXT: v_fma_f32 v1, v9, v1, -v5
; GFX10-DENORM-NEXT: v_fma_f32 v2, v10, v2, -v6
; GFX10-DENORM-NEXT: v_fma_f32 v3, v11, v3, -v7
; GFX10-DENORM-NEXT: v_fma_mix_f32 v4, v0, v2, -v4 op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: v_fma_mix_f32 v5, v0, v2, -v5 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: v_fma_mix_f32 v2, v1, v3, -v6 op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: v_fma_mix_f32 v3, v1, v3, -v7 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: v_mov_b32_e32 v0, v4
; GFX10-DENORM-NEXT: v_mov_b32_e32 v1, v5
; GFX10-DENORM-NEXT: ; return to shader part epilog
entry:
%a = fmul fast <4 x half> %x, %y
Expand All @@ -102,18 +88,10 @@ define amdgpu_vs <4 x float> @test_v4f16_to_v4f32_sub_ext_mul_rhs(<4 x float> %x
;
; GFX10-DENORM-LABEL: test_v4f16_to_v4f32_sub_ext_mul_rhs:
; GFX10-DENORM: ; %bb.0: ; %.entry
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v8, v4
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v9, v5
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v10, v6
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v6, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v11, v7
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v7, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_fma_f32 v0, -v8, v10, v0
; GFX10-DENORM-NEXT: v_fma_f32 v1, -v4, v6, v1
; GFX10-DENORM-NEXT: v_fma_f32 v2, -v9, v11, v2
; GFX10-DENORM-NEXT: v_fma_f32 v3, -v5, v7, v3
; GFX10-DENORM-NEXT: v_fma_mix_f32 v0, -v4, v6, v0 op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: v_fma_mix_f32 v1, -v4, v6, v1 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: v_fma_mix_f32 v2, -v5, v7, v2 op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: v_fma_mix_f32 v3, -v5, v7, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: ; return to shader part epilog
.entry:
%a = fmul fast <4 x half> %y, %z
Expand Down
114 changes: 34 additions & 80 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-neg-mul.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,16 +6,12 @@
define amdgpu_vs float @test_f16_to_f32_sub_ext_neg_mul(half %x, half %y, float %z) {
; GFX9-DENORM-LABEL: test_f16_to_f32_sub_ext_neg_mul:
; GFX9-DENORM: ; %bb.0: ; %entry
; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX9-DENORM-NEXT: v_cvt_f32_f16_e64 v1, -v1
; GFX9-DENORM-NEXT: v_mad_f32 v0, v0, v1, -v2
; GFX9-DENORM-NEXT: v_mad_mix_f32 v0, v0, -v1, -v2 op_sel_hi:[1,1,0]
; GFX9-DENORM-NEXT: ; return to shader part epilog
;
; GFX10-DENORM-LABEL: test_f16_to_f32_sub_ext_neg_mul:
; GFX10-DENORM: ; %bb.0: ; %entry
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e64 v1, -v1
; GFX10-DENORM-NEXT: v_fma_f32 v0, v0, v1, -v2
; GFX10-DENORM-NEXT: v_fma_mix_f32 v0, v0, -v1, -v2 op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: ; return to shader part epilog
entry:
%a = fmul fast half %x, %y
Expand All @@ -29,16 +25,12 @@ entry:
define amdgpu_vs float @test_f16_to_f32_sub_neg_ext_mul(half %x, half %y, float %z) {
; GFX9-DENORM-LABEL: test_f16_to_f32_sub_neg_ext_mul:
; GFX9-DENORM: ; %bb.0: ; %entry
; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX9-DENORM-NEXT: v_cvt_f32_f16_e64 v1, -v1
; GFX9-DENORM-NEXT: v_mad_f32 v0, v0, v1, -v2
; GFX9-DENORM-NEXT: v_mad_mix_f32 v0, v0, -v1, -v2 op_sel_hi:[1,1,0]
; GFX9-DENORM-NEXT: ; return to shader part epilog
;
; GFX10-DENORM-LABEL: test_f16_to_f32_sub_neg_ext_mul:
; GFX10-DENORM: ; %bb.0: ; %entry
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e64 v1, -v1
; GFX10-DENORM-NEXT: v_fma_f32 v0, v0, v1, -v2
; GFX10-DENORM-NEXT: v_fma_mix_f32 v0, v0, -v1, -v2 op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: ; return to shader part epilog
entry:
%a = fmul fast half %x, %y
Expand All @@ -53,16 +45,12 @@ entry:
define amdgpu_vs float @test_f16_to_f32_sub_ext_neg_mul2(float %x, half %y, half %z) {
; GFX9-DENORM-LABEL: test_f16_to_f32_sub_ext_neg_mul2:
; GFX9-DENORM: ; %bb.0: ; %entry
; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX9-DENORM-NEXT: v_cvt_f32_f16_e64 v2, -v2
; GFX9-DENORM-NEXT: v_mad_f32 v0, -v1, v2, v0
; GFX9-DENORM-NEXT: v_mad_mix_f32 v0, -v1, -v2, v0 op_sel_hi:[1,1,0]
; GFX9-DENORM-NEXT: ; return to shader part epilog
;
; GFX10-DENORM-LABEL: test_f16_to_f32_sub_ext_neg_mul2:
; GFX10-DENORM: ; %bb.0: ; %entry
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e64 v2, -v2
; GFX10-DENORM-NEXT: v_fma_f32 v0, -v1, v2, v0
; GFX10-DENORM-NEXT: v_fma_mix_f32 v0, -v1, -v2, v0 op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: ; return to shader part epilog
entry:
%a = fmul fast half %y, %z
Expand All @@ -76,16 +64,12 @@ entry:
define amdgpu_vs float @test_f16_to_f32_sub_neg_ext_mul2(float %x, half %y, half %z) {
; GFX9-DENORM-LABEL: test_f16_to_f32_sub_neg_ext_mul2:
; GFX9-DENORM: ; %bb.0: ; %entry
; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX9-DENORM-NEXT: v_cvt_f32_f16_e64 v2, -v2
; GFX9-DENORM-NEXT: v_mad_f32 v0, -v1, v2, v0
; GFX9-DENORM-NEXT: v_mad_mix_f32 v0, -v1, -v2, v0 op_sel_hi:[1,1,0]
; GFX9-DENORM-NEXT: ; return to shader part epilog
;
; GFX10-DENORM-LABEL: test_f16_to_f32_sub_neg_ext_mul2:
; GFX10-DENORM: ; %bb.0: ; %entry
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e64 v2, -v2
; GFX10-DENORM-NEXT: v_fma_f32 v0, -v1, v2, v0
; GFX10-DENORM-NEXT: v_fma_mix_f32 v0, -v1, -v2, v0 op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: ; return to shader part epilog
entry:
%a = fmul fast half %y, %z
Expand Down Expand Up @@ -113,20 +97,13 @@ define amdgpu_vs <4 x float> @test_v4f16_to_v4f32_sub_ext_neg_mul(<4 x half> %x,
;
; GFX10-DENORM-LABEL: test_v4f16_to_v4f32_sub_ext_neg_mul:
; GFX10-DENORM: ; %bb.0: ; %entry
; GFX10-DENORM-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
; GFX10-DENORM-NEXT: v_xor_b32_e32 v3, 0x80008000, v3
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v8, v0
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v10, v1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v11, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v0, v2
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v2, v3
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_fma_f32 v0, v8, v0, -v4
; GFX10-DENORM-NEXT: v_fma_f32 v1, v9, v1, -v5
; GFX10-DENORM-NEXT: v_fma_f32 v2, v10, v2, -v6
; GFX10-DENORM-NEXT: v_fma_f32 v3, v11, v3, -v7
; GFX10-DENORM-NEXT: v_xor_b32_e32 v8, 0x80008000, v2
; GFX10-DENORM-NEXT: v_xor_b32_e32 v9, 0x80008000, v3
; GFX10-DENORM-NEXT: v_fma_mix_f32 v5, v0, -v2, -v5 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: v_fma_mix_f32 v3, v1, -v3, -v7 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: v_fma_mix_f32 v0, v0, v8, -v4 op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: v_fma_mix_f32 v2, v1, v9, -v6 op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: v_mov_b32_e32 v1, v5
; GFX10-DENORM-NEXT: ; return to shader part epilog
entry:
%a = fmul fast <4 x half> %x, %y
Expand Down Expand Up @@ -154,20 +131,13 @@ define amdgpu_vs <4 x float> @test_v4f16_to_v4f32_sub_neg_ext_mul(<4 x half> %x,
;
; GFX10-DENORM-LABEL: test_v4f16_to_v4f32_sub_neg_ext_mul:
; GFX10-DENORM: ; %bb.0: ; %entry
; GFX10-DENORM-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
; GFX10-DENORM-NEXT: v_xor_b32_e32 v3, 0x80008000, v3
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v8, v0
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v10, v1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v11, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v0, v2
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v2, v3
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_fma_f32 v0, v8, v0, -v4
; GFX10-DENORM-NEXT: v_fma_f32 v1, v9, v1, -v5
; GFX10-DENORM-NEXT: v_fma_f32 v2, v10, v2, -v6
; GFX10-DENORM-NEXT: v_fma_f32 v3, v11, v3, -v7
; GFX10-DENORM-NEXT: v_xor_b32_e32 v8, 0x80008000, v2
; GFX10-DENORM-NEXT: v_xor_b32_e32 v9, 0x80008000, v3
; GFX10-DENORM-NEXT: v_fma_mix_f32 v5, v0, -v2, -v5 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: v_fma_mix_f32 v3, v1, -v3, -v7 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: v_fma_mix_f32 v0, v0, v8, -v4 op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: v_fma_mix_f32 v2, v1, v9, -v6 op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: v_mov_b32_e32 v1, v5
; GFX10-DENORM-NEXT: ; return to shader part epilog
entry:
%a = fmul fast <4 x half> %x, %y
Expand Down Expand Up @@ -196,20 +166,12 @@ define amdgpu_vs <4 x float> @test_v4f16_to_v4f32_sub_ext_neg_mul2(<4 x float> %
;
; GFX10-DENORM-LABEL: test_v4f16_to_v4f32_sub_ext_neg_mul2:
; GFX10-DENORM: ; %bb.0: ; %entry
; GFX10-DENORM-NEXT: v_xor_b32_e32 v6, 0x80008000, v6
; GFX10-DENORM-NEXT: v_xor_b32_e32 v7, 0x80008000, v7
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v8, v4
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v9, v5
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v10, v6
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v6, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v11, v7
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v7, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_fma_f32 v0, -v8, v10, v0
; GFX10-DENORM-NEXT: v_fma_f32 v1, -v4, v6, v1
; GFX10-DENORM-NEXT: v_fma_f32 v2, -v9, v11, v2
; GFX10-DENORM-NEXT: v_fma_f32 v3, -v5, v7, v3
; GFX10-DENORM-NEXT: v_xor_b32_e32 v8, 0x80008000, v6
; GFX10-DENORM-NEXT: v_xor_b32_e32 v9, 0x80008000, v7
; GFX10-DENORM-NEXT: v_fma_mix_f32 v1, -v4, -v6, v1 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: v_fma_mix_f32 v3, -v5, -v7, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: v_fma_mix_f32 v0, -v4, v8, v0 op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: v_fma_mix_f32 v2, -v5, v9, v2 op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: ; return to shader part epilog
entry:
%a = fmul fast <4 x half> %y, %z
Expand Down Expand Up @@ -237,20 +199,12 @@ define amdgpu_vs <4 x float> @test_v4f16_to_v4f32_sub_neg_ext_mul2(<4 x float> %
;
; GFX10-DENORM-LABEL: test_v4f16_to_v4f32_sub_neg_ext_mul2:
; GFX10-DENORM: ; %bb.0: ; %entry
; GFX10-DENORM-NEXT: v_xor_b32_e32 v6, 0x80008000, v6
; GFX10-DENORM-NEXT: v_xor_b32_e32 v7, 0x80008000, v7
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v8, v4
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v9, v5
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v10, v6
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v6, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v11, v7
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v7, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_fma_f32 v0, -v8, v10, v0
; GFX10-DENORM-NEXT: v_fma_f32 v1, -v4, v6, v1
; GFX10-DENORM-NEXT: v_fma_f32 v2, -v9, v11, v2
; GFX10-DENORM-NEXT: v_fma_f32 v3, -v5, v7, v3
; GFX10-DENORM-NEXT: v_xor_b32_e32 v8, 0x80008000, v6
; GFX10-DENORM-NEXT: v_xor_b32_e32 v9, 0x80008000, v7
; GFX10-DENORM-NEXT: v_fma_mix_f32 v1, -v4, -v6, v1 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: v_fma_mix_f32 v3, -v5, -v7, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: v_fma_mix_f32 v0, -v4, v8, v0 op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: v_fma_mix_f32 v2, -v5, v9, v2 op_sel_hi:[1,1,0]
; GFX10-DENORM-NEXT: ; return to shader part epilog
entry:
%a = fmul fast <4 x half> %y, %z
Expand Down
169 changes: 169 additions & 0 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-insertvecelt-to-shufflevector.mir
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Original file line number Diff line number Diff line change
@@ -0,0 +1,169 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs -o - %s | FileCheck %s --check-prefixes=CHECK,GFX9PLUS
# RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs -o - %s | FileCheck %s --check-prefixes=CHECK,VI

---
name: test_v2s16_idx0
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0
; GFX9PLUS-LABEL: name: test_v2s16_idx0
; GFX9PLUS: liveins: $vgpr0
; GFX9PLUS-NEXT: {{ $}}
; GFX9PLUS-NEXT: %src:_(<2 x s16>) = COPY $vgpr0
; GFX9PLUS-NEXT: %elt:_(s16) = G_CONSTANT i16 42
; GFX9PLUS-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX9PLUS-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR %elt(s16), [[DEF]](s16)
; GFX9PLUS-NEXT: %ins:_(<2 x s16>) = G_SHUFFLE_VECTOR %src(<2 x s16>), [[BUILD_VECTOR]], shufflemask(2, 1)
; GFX9PLUS-NEXT: $vgpr0 = COPY %ins(<2 x s16>)
; VI-LABEL: name: test_v2s16_idx0
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: %src:_(<2 x s16>) = COPY $vgpr0
; VI-NEXT: %idx:_(s32) = G_CONSTANT i32 0
; VI-NEXT: %elt:_(s16) = G_CONSTANT i16 42
; VI-NEXT: %ins:_(<2 x s16>) = G_INSERT_VECTOR_ELT %src, %elt(s16), %idx(s32)
; VI-NEXT: $vgpr0 = COPY %ins(<2 x s16>)
%src:_(<2 x s16>) = COPY $vgpr0
%idx:_(s32) = G_CONSTANT i32 0
%elt:_(s16) = G_CONSTANT i16 42
%ins:_(<2 x s16>) = G_INSERT_VECTOR_ELT %src, %elt, %idx
$vgpr0 = COPY %ins
...

---
name: test_v2s16_idx1
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0
; GFX9PLUS-LABEL: name: test_v2s16_idx1
; GFX9PLUS: liveins: $vgpr0
; GFX9PLUS-NEXT: {{ $}}
; GFX9PLUS-NEXT: %src:_(<2 x s16>) = COPY $vgpr0
; GFX9PLUS-NEXT: %elt:_(s16) = G_CONSTANT i16 42
; GFX9PLUS-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX9PLUS-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR %elt(s16), [[DEF]](s16)
; GFX9PLUS-NEXT: %ins:_(<2 x s16>) = G_SHUFFLE_VECTOR %src(<2 x s16>), [[BUILD_VECTOR]], shufflemask(0, 2)
; GFX9PLUS-NEXT: $vgpr0 = COPY %ins(<2 x s16>)
; VI-LABEL: name: test_v2s16_idx1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: %src:_(<2 x s16>) = COPY $vgpr0
; VI-NEXT: %idx:_(s32) = G_CONSTANT i32 1
; VI-NEXT: %elt:_(s16) = G_CONSTANT i16 42
; VI-NEXT: %ins:_(<2 x s16>) = G_INSERT_VECTOR_ELT %src, %elt(s16), %idx(s32)
; VI-NEXT: $vgpr0 = COPY %ins(<2 x s16>)
%src:_(<2 x s16>) = COPY $vgpr0
%idx:_(s32) = G_CONSTANT i32 1
%elt:_(s16) = G_CONSTANT i16 42
%ins:_(<2 x s16>) = G_INSERT_VECTOR_ELT %src, %elt, %idx
$vgpr0 = COPY %ins
...

---
name: test_v2s16_idx2_nofold
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_v2s16_idx2_nofold
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ins:_(<2 x s16>) = G_IMPLICIT_DEF
; CHECK-NEXT: $vgpr0 = COPY %ins(<2 x s16>)
%src:_(<2 x s16>) = COPY $vgpr0
%idx:_(s32) = G_CONSTANT i32 2
%elt:_(s16) = G_CONSTANT i16 42
%ins:_(<2 x s16>) = G_INSERT_VECTOR_ELT %src, %elt, %idx
$vgpr0 = COPY %ins
...

---
name: test_v3s16_idx2
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2
; GFX9PLUS-LABEL: name: test_v3s16_idx2
; GFX9PLUS: liveins: $vgpr0_vgpr1_vgpr2
; GFX9PLUS-NEXT: {{ $}}
; GFX9PLUS-NEXT: %src:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; GFX9PLUS-NEXT: %truncsrc:_(<3 x s16>) = G_TRUNC %src(<3 x s32>)
; GFX9PLUS-NEXT: %elt:_(s16) = G_CONSTANT i16 42
; GFX9PLUS-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX9PLUS-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s16>) = G_BUILD_VECTOR %elt(s16), [[DEF]](s16), [[DEF]](s16)
; GFX9PLUS-NEXT: %ins:_(<3 x s16>) = G_SHUFFLE_VECTOR %truncsrc(<3 x s16>), [[BUILD_VECTOR]], shufflemask(0, 1, 3)
; GFX9PLUS-NEXT: %zextins:_(<3 x s32>) = G_ZEXT %ins(<3 x s16>)
; GFX9PLUS-NEXT: $vgpr0_vgpr1_vgpr2 = COPY %zextins(<3 x s32>)
; VI-LABEL: name: test_v3s16_idx2
; VI: liveins: $vgpr0_vgpr1_vgpr2
; VI-NEXT: {{ $}}
; VI-NEXT: %src:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; VI-NEXT: %truncsrc:_(<3 x s16>) = G_TRUNC %src(<3 x s32>)
; VI-NEXT: %idx:_(s32) = G_CONSTANT i32 2
; VI-NEXT: %elt:_(s16) = G_CONSTANT i16 42
; VI-NEXT: %ins:_(<3 x s16>) = G_INSERT_VECTOR_ELT %truncsrc, %elt(s16), %idx(s32)
; VI-NEXT: %zextins:_(<3 x s32>) = G_ZEXT %ins(<3 x s16>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY %zextins(<3 x s32>)
%src:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%truncsrc:_(<3 x s16>) = G_TRUNC %src
%idx:_(s32) = G_CONSTANT i32 2
%elt:_(s16) = G_CONSTANT i16 42
%ins:_(<3 x s16>) = G_INSERT_VECTOR_ELT %truncsrc, %elt, %idx
%zextins:_(<3 x s32>) = G_ZEXT %ins
$vgpr0_vgpr1_vgpr2 = COPY %zextins
...

---
name: test_v2s32_idx1
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_v2s32_idx1
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %src:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK-NEXT: %elt:_(s32) = G_CONSTANT i32 42
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR %elt(s32), [[DEF]](s32)
; CHECK-NEXT: %ins:_(<2 x s32>) = G_SHUFFLE_VECTOR %src(<2 x s32>), [[BUILD_VECTOR]], shufflemask(0, 2)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY %ins(<2 x s32>)
%src:_(<2 x s32>) = COPY $vgpr0_vgpr1
%idx:_(s32) = G_CONSTANT i32 1
%elt:_(s32) = G_CONSTANT i32 42
%ins:_(<2 x s32>) = G_INSERT_VECTOR_ELT %src, %elt, %idx
$vgpr0_vgpr1 = COPY %ins
...

---
name: test_v4s16_idx3
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
; GFX9PLUS-LABEL: name: test_v4s16_idx3
; GFX9PLUS: liveins: $vgpr0_vgpr1
; GFX9PLUS-NEXT: {{ $}}
; GFX9PLUS-NEXT: %src:_(<4 x s16>) = COPY $vgpr0_vgpr1
; GFX9PLUS-NEXT: %elt:_(s16) = G_CONSTANT i16 42
; GFX9PLUS-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX9PLUS-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR %elt(s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16)
; GFX9PLUS-NEXT: %ins:_(<4 x s16>) = G_SHUFFLE_VECTOR %src(<4 x s16>), [[BUILD_VECTOR]], shufflemask(0, 1, 2, 4)
; GFX9PLUS-NEXT: $vgpr0_vgpr1 = COPY %ins(<4 x s16>)
; VI-LABEL: name: test_v4s16_idx3
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: %src:_(<4 x s16>) = COPY $vgpr0_vgpr1
; VI-NEXT: %idx:_(s32) = G_CONSTANT i32 3
; VI-NEXT: %elt:_(s16) = G_CONSTANT i16 42
; VI-NEXT: %ins:_(<4 x s16>) = G_INSERT_VECTOR_ELT %src, %elt(s16), %idx(s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY %ins(<4 x s16>)
%src:_(<4 x s16>) = COPY $vgpr0_vgpr1
%idx:_(s32) = G_CONSTANT i32 3
%elt:_(s16) = G_CONSTANT i16 42
%ins:_(<4 x s16>) = G_INSERT_VECTOR_ELT %src, %elt, %idx
$vgpr0_vgpr1 = COPY %ins
...
577 changes: 409 additions & 168 deletions llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
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2,293 changes: 1,525 additions & 768 deletions llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
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1,496 changes: 1,028 additions & 468 deletions llvm/test/CodeGen/AMDGPU/mad-mix.ll
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