22 changes: 10 additions & 12 deletions llvm/lib/CodeGen/MachineLICM.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -428,7 +428,7 @@ void MachineLICM::ProcessMI(MachineInstr *MI,
if (Def && !RuledOut) {
int FI = INT_MIN;
if ((!HasNonInvariantUse && IsLICMCandidate(*MI)) ||
(TII->isLoadFromStackSlot(MI, FI) && MFI->isSpillSlotObjectIndex(FI)))
(TII->isLoadFromStackSlot(*MI, FI) && MFI->isSpillSlotObjectIndex(FI)))
Candidates.push_back(CandidateInfo(MI, Def, FI));
}
}
Expand Down Expand Up @@ -982,7 +982,7 @@ bool MachineLICM::HasHighOperandLatency(MachineInstr &MI,
if (MOReg != Reg)
continue;

if (TII->hasHighOperandLatency(SchedModel, MRI, &MI, DefIdx, &UseMI, i))
if (TII->hasHighOperandLatency(SchedModel, MRI, MI, DefIdx, UseMI, i))
return true;
}

Expand All @@ -996,7 +996,7 @@ bool MachineLICM::HasHighOperandLatency(MachineInstr &MI,
/// Return true if the instruction is marked "cheap" or the operand latency
/// between its def and a use is one or less.
bool MachineLICM::IsCheapInstruction(MachineInstr &MI) const {
if (TII->isAsCheapAsAMove(&MI) || MI.isCopyLike())
if (TII->isAsCheapAsAMove(MI) || MI.isCopyLike())
return true;

bool isCheap = false;
Expand All @@ -1010,7 +1010,7 @@ bool MachineLICM::IsCheapInstruction(MachineInstr &MI) const {
if (TargetRegisterInfo::isPhysicalRegister(Reg))
continue;

if (!TII->hasLowDefLatency(SchedModel, &MI, i))
if (!TII->hasLowDefLatency(SchedModel, MI, i))
return false;
isCheap = true;
}
Expand Down Expand Up @@ -1086,7 +1086,7 @@ bool MachineLICM::IsProfitableToHoist(MachineInstr &MI) {

// Rematerializable instructions should always be hoisted since the register
// allocator can just pull them down again when needed.
if (TII->isTriviallyReMaterializable(&MI, AA))
if (TII->isTriviallyReMaterializable(MI, AA))
return true;

// FIXME: If there are long latency loop-invariant instructions inside the
Expand Down Expand Up @@ -1139,8 +1139,7 @@ bool MachineLICM::IsProfitableToHoist(MachineInstr &MI) {

// High register pressure situation, only hoist if the instruction is going
// to be remat'ed.
if (!TII->isTriviallyReMaterializable(&MI, AA) &&
!MI.isInvariantLoad(AA)) {
if (!TII->isTriviallyReMaterializable(MI, AA) && !MI.isInvariantLoad(AA)) {
DEBUG(dbgs() << "Can't remat / high reg-pressure: " << MI);
return false;
}
Expand Down Expand Up @@ -1177,10 +1176,9 @@ MachineInstr *MachineLICM::ExtractHoistableLoad(MachineInstr *MI) {
unsigned Reg = MRI->createVirtualRegister(RC);

SmallVector<MachineInstr *, 2> NewMIs;
bool Success =
TII->unfoldMemoryOperand(MF, MI, Reg,
/*UnfoldLoad=*/true, /*UnfoldStore=*/false,
NewMIs);
bool Success = TII->unfoldMemoryOperand(MF, *MI, Reg,
/*UnfoldLoad=*/true,
/*UnfoldStore=*/false, NewMIs);
(void)Success;
assert(Success &&
"unfoldMemoryOperand failed when getOpcodeAfterMemoryUnfold "
Expand Down Expand Up @@ -1221,7 +1219,7 @@ const MachineInstr*
MachineLICM::LookForDuplicate(const MachineInstr *MI,
std::vector<const MachineInstr*> &PrevMIs) {
for (const MachineInstr *PrevMI : PrevMIs)
if (TII->produceSameValue(MI, PrevMI, (PreRegAlloc ? MRI : nullptr)))
if (TII->produceSameValue(*MI, *PrevMI, (PreRegAlloc ? MRI : nullptr)))
return PrevMI;

return nullptr;
Expand Down
11 changes: 6 additions & 5 deletions llvm/lib/CodeGen/MachineScheduler.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -406,7 +406,7 @@ static bool isSchedBoundary(MachineBasicBlock::iterator MI,
MachineBasicBlock *MBB,
MachineFunction *MF,
const TargetInstrInfo *TII) {
return MI->isCall() || TII->isSchedulingBoundary(MI, MBB, *MF);
return MI->isCall() || TII->isSchedulingBoundary(*MI, MBB, *MF);
}

/// Main driver for both MachineScheduler and PostMachineScheduler.
Expand Down Expand Up @@ -1402,7 +1402,7 @@ void BaseMemOpClusterMutation::clusterNeighboringMemOps(
SUnit *SU = MemOps[Idx];
unsigned BaseReg;
int64_t Offset;
if (TII->getMemOpBaseRegImmOfs(SU->getInstr(), BaseReg, Offset, TRI))
if (TII->getMemOpBaseRegImmOfs(*SU->getInstr(), BaseReg, Offset, TRI))
MemOpRecords.push_back(MemOpInfo(SU, BaseReg, Offset));
}
if (MemOpRecords.size() < 2)
Expand All @@ -1418,8 +1418,9 @@ void BaseMemOpClusterMutation::clusterNeighboringMemOps(

SUnit *SUa = MemOpRecords[Idx].SU;
SUnit *SUb = MemOpRecords[Idx+1].SU;
if (TII->shouldClusterMemOps(SUa->getInstr(), SUb->getInstr(), ClusterLength)
&& DAG->addEdge(SUb, SDep(SUa, SDep::Cluster))) {
if (TII->shouldClusterMemOps(*SUa->getInstr(), *SUb->getInstr(),
ClusterLength) &&
DAG->addEdge(SUb, SDep(SUa, SDep::Cluster))) {
DEBUG(dbgs() << "Cluster ld/st SU(" << SUa->NodeNum << ") - SU("
<< SUb->NodeNum << ")\n");
// Copy successor edges from SUa to SUb. Interleaving computation
Expand Down Expand Up @@ -1529,7 +1530,7 @@ void MacroFusion::apply(ScheduleDAGInstrs *DAGInstrs) {
if (!HasDataDep(TRI, *Branch, *Pred))
continue;

if (!TII.shouldScheduleAdjacent(Pred, Branch))
if (!TII.shouldScheduleAdjacent(*Pred, *Branch))
continue;

// Create a single weak edge from SU to ExitSU. The only effect is to cause
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/CodeGen/MachineSink.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -366,7 +366,7 @@ bool MachineSinking::isWorthBreakingCriticalEdge(MachineInstr *MI,
if (!CEBCandidates.insert(std::make_pair(From, To)).second)
return true;

if (!MI->isCopy() && !TII->isAsCheapAsAMove(MI))
if (!MI->isCopy() && !TII->isAsCheapAsAMove(*MI))
return true;

// MI is cheap, we probably don't want to break the critical edge for it.
Expand Down Expand Up @@ -700,7 +700,7 @@ static bool SinkingPreventsImplicitNullCheck(MachineInstr *MI,

unsigned BaseReg;
int64_t Offset;
if (!TII->getMemOpBaseRegImmOfs(MI, BaseReg, Offset, TRI))
if (!TII->getMemOpBaseRegImmOfs(*MI, BaseReg, Offset, TRI))
return false;

if (!(MI->mayLoad() && !MI->isPredicable()))
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/MachineVerifier.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -880,7 +880,7 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
}

StringRef ErrorInfo;
if (!TII->verifyInstruction(MI, ErrorInfo))
if (!TII->verifyInstruction(*MI, ErrorInfo))
report(ErrorInfo.data(), MI);
}

Expand Down
18 changes: 8 additions & 10 deletions llvm/lib/CodeGen/PeepholeOptimizer.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -564,13 +564,13 @@ bool PeepholeOptimizer::optimizeCmpInstr(MachineInstr *MI,
// physical register, we can try to optimize it.
unsigned SrcReg, SrcReg2;
int CmpMask, CmpValue;
if (!TII->analyzeCompare(MI, SrcReg, SrcReg2, CmpMask, CmpValue) ||
if (!TII->analyzeCompare(*MI, SrcReg, SrcReg2, CmpMask, CmpValue) ||
TargetRegisterInfo::isPhysicalRegister(SrcReg) ||
(SrcReg2 != 0 && TargetRegisterInfo::isPhysicalRegister(SrcReg2)))
return false;

// Attempt to optimize the comparison instruction.
if (TII->optimizeCompareInstr(MI, SrcReg, SrcReg2, CmpMask, CmpValue, MRI)) {
if (TII->optimizeCompareInstr(*MI, SrcReg, SrcReg2, CmpMask, CmpValue, MRI)) {
++NumCmps;
return true;
}
Expand All @@ -585,11 +585,11 @@ bool PeepholeOptimizer::optimizeSelect(MachineInstr *MI,
unsigned FalseOp = 0;
bool Optimizable = false;
SmallVector<MachineOperand, 4> Cond;
if (TII->analyzeSelect(MI, Cond, TrueOp, FalseOp, Optimizable))
if (TII->analyzeSelect(*MI, Cond, TrueOp, FalseOp, Optimizable))
return false;
if (!Optimizable)
return false;
if (!TII->optimizeSelect(MI, LocalMIs))
if (!TII->optimizeSelect(*MI, LocalMIs))
return false;
MI->eraseFromParent();
++NumSelects;
Expand All @@ -599,7 +599,7 @@ bool PeepholeOptimizer::optimizeSelect(MachineInstr *MI,
/// \brief Check if a simpler conditional branch can be
// generated
bool PeepholeOptimizer::optimizeCondBranch(MachineInstr *MI) {
return TII->optimizeCondBranch(MI);
return TII->optimizeCondBranch(*MI);
}

/// \brief Try to find the next source that share the same register file
Expand Down Expand Up @@ -1351,7 +1351,7 @@ bool PeepholeOptimizer::foldImmediate(
continue;
DenseMap<unsigned, MachineInstr*>::iterator II = ImmDefMIs.find(Reg);
assert(II != ImmDefMIs.end() && "couldn't find immediate definition");
if (TII->FoldImmediate(MI, II->second, Reg, MRI)) {
if (TII->FoldImmediate(*MI, *II->second, Reg, MRI)) {
++NumImmFold;
return true;
}
Expand Down Expand Up @@ -1636,10 +1636,8 @@ bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) {
// we need it for markUsesInDebugValueAsUndef().
unsigned FoldedReg = FoldAsLoadDefReg;
MachineInstr *DefMI = nullptr;
MachineInstr *FoldMI = TII->optimizeLoadInstr(MI, MRI,
FoldAsLoadDefReg,
DefMI);
if (FoldMI) {
if (MachineInstr *FoldMI =
TII->optimizeLoadInstr(*MI, MRI, FoldAsLoadDefReg, DefMI)) {
// Update LocalMIs since we replaced MI with FoldMI and deleted
// DefMI.
DEBUG(dbgs() << "Replacing: " << *MI);
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/PostRASchedulerList.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -340,7 +340,7 @@ bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
// Calls are not scheduling boundaries before register allocation, but
// post-ra we don't gain anything by scheduling across calls since we
// don't need to worry about register pressure.
if (MI->isCall() || TII->isSchedulingBoundary(MI, &MBB, Fn)) {
if (MI->isCall() || TII->isSchedulingBoundary(*MI, &MBB, Fn)) {
Scheduler.enterRegion(&MBB, I, Current, CurrentCount - Count);
Scheduler.setEndIndex(CurrentCount);
Scheduler.schedule();
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/CodeGen/PrologEpilogInserter.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1056,7 +1056,7 @@ void PEI::replaceFrameIndices(MachineBasicBlock *BB, MachineFunction &Fn,
if (I->getOpcode() == FrameSetupOpcode ||
I->getOpcode() == FrameDestroyOpcode) {
InsideCallSequence = (I->getOpcode() == FrameSetupOpcode);
SPAdj += TII.getSPAdjust(I);
SPAdj += TII.getSPAdjust(*I);

I = TFI->eliminateCallFramePseudoInstr(Fn, *BB, I);
continue;
Expand Down Expand Up @@ -1135,7 +1135,7 @@ void PEI::replaceFrameIndices(MachineBasicBlock *BB, MachineFunction &Fn,
// if I itself referred to a frame index, we shouldn't count its own
// adjustment.
if (MI && InsideCallSequence)
SPAdj += TII.getSPAdjust(MI);
SPAdj += TII.getSPAdjust(*MI);

if (DoIncr && I != BB->end()) ++I;

Expand Down
10 changes: 5 additions & 5 deletions llvm/lib/CodeGen/RegisterCoalescer.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -684,7 +684,7 @@ bool RegisterCoalescer::removeCopyByCommutingDef(const CoalescerPair &CP,
// operands then all possible variants (i.e. op#1<->op#2, op#1<->op#3,
// op#2<->op#3) of commute transformation should be considered/tried here.
unsigned NewDstIdx = TargetInstrInfo::CommuteAnyOperandIndex;
if (!TII->findCommutedOpIndices(DefMI, UseOpIdx, NewDstIdx))
if (!TII->findCommutedOpIndices(*DefMI, UseOpIdx, NewDstIdx))
return false;

MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
Expand Down Expand Up @@ -718,7 +718,7 @@ bool RegisterCoalescer::removeCopyByCommutingDef(const CoalescerPair &CP,
// transformation. Start by commuting the instruction.
MachineBasicBlock *MBB = DefMI->getParent();
MachineInstr *NewMI =
TII->commuteInstruction(DefMI, false, UseOpIdx, NewDstIdx);
TII->commuteInstruction(*DefMI, false, UseOpIdx, NewDstIdx);
if (!NewMI)
return false;
if (TargetRegisterInfo::isVirtualRegister(IntA.reg) &&
Expand Down Expand Up @@ -901,9 +901,9 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
IsDefCopy = true;
return false;
}
if (!TII->isAsCheapAsAMove(DefMI))
if (!TII->isAsCheapAsAMove(*DefMI))
return false;
if (!TII->isTriviallyReMaterializable(DefMI, AA))
if (!TII->isTriviallyReMaterializable(*DefMI, AA))
return false;
if (!definesFullReg(*DefMI, SrcReg))
return false;
Expand Down Expand Up @@ -953,7 +953,7 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
MachineBasicBlock *MBB = CopyMI->getParent();
MachineBasicBlock::iterator MII =
std::next(MachineBasicBlock::iterator(CopyMI));
TII->reMaterialize(*MBB, MII, DstReg, SrcIdx, DefMI, *TRI);
TII->reMaterialize(*MBB, MII, DstReg, SrcIdx, *DefMI, *TRI);
MachineInstr *NewMI = std::prev(MII);
NewMI->setDebugLoc(DL);

Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -569,7 +569,7 @@ static bool MIsNeedChainEdge(AliasAnalysis *AA, const MachineFrameInfo *MFI,
"Dependency checked between two loads");

// Let the target decide if memory accesses cannot possibly overlap.
if (TII->areMemAccessesTriviallyDisjoint(MIa, MIb, AA))
if (TII->areMemAccessesTriviallyDisjoint(*MIa, *MIb, AA))
return false;

// To this point analysis is generic. From here on we do need AA.
Expand Down
9 changes: 5 additions & 4 deletions llvm/lib/CodeGen/StackSlotColoring.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -386,8 +386,7 @@ bool StackSlotColoring::RemoveDeadStores(MachineBasicBlock* MBB) {
break;

int FirstSS, SecondSS;
if (TII->isStackSlotCopy(I, FirstSS, SecondSS) &&
FirstSS == SecondSS &&
if (TII->isStackSlotCopy(*I, FirstSS, SecondSS) && FirstSS == SecondSS &&
FirstSS != -1) {
++NumDead;
changed = true;
Expand All @@ -400,8 +399,10 @@ bool StackSlotColoring::RemoveDeadStores(MachineBasicBlock* MBB) {

unsigned LoadReg = 0;
unsigned StoreReg = 0;
if (!(LoadReg = TII->isLoadFromStackSlot(I, FirstSS))) continue;
if (!(StoreReg = TII->isStoreToStackSlot(NextMI, SecondSS))) continue;
if (!(LoadReg = TII->isLoadFromStackSlot(*I, FirstSS)))
continue;
if (!(StoreReg = TII->isStoreToStackSlot(*NextMI, SecondSS)))
continue;
if (FirstSS != SecondSS || LoadReg != StoreReg || FirstSS == -1) continue;

++NumDead;
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/TailDuplicator.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -341,7 +341,7 @@ void TailDuplicator::duplicateInstruction(
MachineFunction &MF,
DenseMap<unsigned, RegSubRegPair> &LocalVRMap,
const DenseSet<unsigned> &UsedByPhi) {
MachineInstr *NewMI = TII->duplicate(MI, MF);
MachineInstr *NewMI = TII->duplicate(*MI, MF);
if (PreRegAlloc) {
for (unsigned i = 0, e = NewMI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = NewMI->getOperand(i);
Expand Down
313 changes: 145 additions & 168 deletions llvm/lib/CodeGen/TargetInstrInfo.cpp
View file

Large diffs are not rendered by default.

20 changes: 10 additions & 10 deletions llvm/lib/CodeGen/TargetSchedule.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -77,7 +77,7 @@ unsigned TargetSchedModel::getNumMicroOps(const MachineInstr *MI,
const MCSchedClassDesc *SC) const {
if (hasInstrItineraries()) {
int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass());
return (UOps >= 0) ? UOps : TII->getNumMicroOps(&InstrItins, MI);
return (UOps >= 0) ? UOps : TII->getNumMicroOps(&InstrItins, *MI);
}
if (hasInstrSchedModel()) {
if (!SC)
Expand Down Expand Up @@ -156,13 +156,13 @@ unsigned TargetSchedModel::computeOperandLatency(
const MachineInstr *UseMI, unsigned UseOperIdx) const {

if (!hasInstrSchedModel() && !hasInstrItineraries())
return TII->defaultDefLatency(SchedModel, DefMI);
return TII->defaultDefLatency(SchedModel, *DefMI);

if (hasInstrItineraries()) {
int OperLatency = 0;
if (UseMI) {
OperLatency = TII->getOperandLatency(&InstrItins, DefMI, DefOperIdx,
UseMI, UseOperIdx);
OperLatency = TII->getOperandLatency(&InstrItins, *DefMI, DefOperIdx,
*UseMI, UseOperIdx);
}
else {
unsigned DefClass = DefMI->getDesc().getSchedClass();
Expand All @@ -172,15 +172,15 @@ unsigned TargetSchedModel::computeOperandLatency(
return OperLatency;

// No operand latency was found.
unsigned InstrLatency = TII->getInstrLatency(&InstrItins, DefMI);
unsigned InstrLatency = TII->getInstrLatency(&InstrItins, *DefMI);

// Expected latency is the max of the stage latency and itinerary props.
// Rather than directly querying InstrItins stage latency, we call a TII
// hook to allow subtargets to specialize latency. This hook is only
// applicable to the InstrItins model. InstrSchedModel should model all
// special cases without TII hooks.
InstrLatency = std::max(InstrLatency,
TII->defaultDefLatency(SchedModel, DefMI));
InstrLatency =
std::max(InstrLatency, TII->defaultDefLatency(SchedModel, *DefMI));
return InstrLatency;
}
// hasInstrSchedModel()
Expand Down Expand Up @@ -219,7 +219,7 @@ unsigned TargetSchedModel::computeOperandLatency(
// FIXME: Automatically giving all implicit defs defaultDefLatency is
// undesirable. We should only do it for defs that are known to the MC
// desc like flags. Truly implicit defs should get 1 cycle latency.
return DefMI->isTransient() ? 0 : TII->defaultDefLatency(SchedModel, DefMI);
return DefMI->isTransient() ? 0 : TII->defaultDefLatency(SchedModel, *DefMI);
}

unsigned
Expand Down Expand Up @@ -254,14 +254,14 @@ TargetSchedModel::computeInstrLatency(const MachineInstr *MI,
// Allow subtargets to compute Bundle latencies outside the machine model.
if (hasInstrItineraries() || MI->isBundle() ||
(!hasInstrSchedModel() && !UseDefaultDefLatency))
return TII->getInstrLatency(&InstrItins, MI);
return TII->getInstrLatency(&InstrItins, *MI);

if (hasInstrSchedModel()) {
const MCSchedClassDesc *SCDesc = resolveSchedClass(MI);
if (SCDesc->isValid())
return computeInstrLatency(*SCDesc);
}
return TII->defaultDefLatency(SchedModel, MI);
return TII->defaultDefLatency(SchedModel, *MI);
}

unsigned TargetSchedModel::
Expand Down
16 changes: 8 additions & 8 deletions llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -647,7 +647,7 @@ bool TwoAddressInstructionPass::commuteInstruction(MachineInstr *MI,
unsigned Dist) {
unsigned RegC = MI->getOperand(RegCIdx).getReg();
DEBUG(dbgs() << "2addr: COMMUTING : " << *MI);
MachineInstr *NewMI = TII->commuteInstruction(MI, false, RegBIdx, RegCIdx);
MachineInstr *NewMI = TII->commuteInstruction(*MI, false, RegBIdx, RegCIdx);

if (NewMI == nullptr) {
DEBUG(dbgs() << "2addr: COMMUTING FAILED!\n");
Expand Down Expand Up @@ -695,7 +695,7 @@ TwoAddressInstructionPass::convertInstTo3Addr(MachineBasicBlock::iterator &mi,
unsigned Dist) {
// FIXME: Why does convertToThreeAddress() need an iterator reference?
MachineFunction::iterator MFI = MBB->getIterator();
MachineInstr *NewMI = TII->convertToThreeAddress(MFI, mi, LV);
MachineInstr *NewMI = TII->convertToThreeAddress(MFI, *mi, LV);
assert(MBB->getIterator() == MFI &&
"convertToThreeAddress changed iterator reference");
if (!NewMI)
Expand Down Expand Up @@ -861,7 +861,7 @@ rescheduleMIBelowKill(MachineBasicBlock::iterator &mi,
if (!MI->isSafeToMove(AA, SeenStore))
return false;

if (TII->getInstrLatency(InstrItins, MI) > 1)
if (TII->getInstrLatency(InstrItins, *MI) > 1)
// FIXME: Needs more sophisticated heuristics.
return false;

Expand Down Expand Up @@ -993,7 +993,7 @@ bool TwoAddressInstructionPass::isDefTooClose(unsigned Reg, unsigned Dist,
return true; // Below MI
unsigned DefDist = DDI->second;
assert(Dist > DefDist && "Visited def already?");
if (TII->getInstrLatency(InstrItins, &DefMI) > (Dist - DefDist))
if (TII->getInstrLatency(InstrItins, DefMI) > (Dist - DefDist))
return true;
}
return false;
Expand Down Expand Up @@ -1174,7 +1174,7 @@ bool TwoAddressInstructionPass::tryInstructionCommute(MachineInstr *MI,
// other commutable operands and does not change the values of passed
// variables.
if (OtherOpIdx == BaseOpIdx ||
!TII->findCommutedOpIndices(MI, BaseOpIdx, OtherOpIdx))
!TII->findCommutedOpIndices(*MI, BaseOpIdx, OtherOpIdx))
continue;

unsigned OtherOpReg = MI->getOperand(OtherOpIdx).getReg();
Expand Down Expand Up @@ -1307,9 +1307,9 @@ tryInstructionTransform(MachineBasicBlock::iterator &mi,
TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI, *MF));
unsigned Reg = MRI->createVirtualRegister(RC);
SmallVector<MachineInstr *, 2> NewMIs;
if (!TII->unfoldMemoryOperand(*MF, &MI, Reg,
/*UnfoldLoad=*/true,/*UnfoldStore=*/false,
NewMIs)) {
if (!TII->unfoldMemoryOperand(*MF, MI, Reg,
/*UnfoldLoad=*/true,
/*UnfoldStore=*/false, NewMIs)) {
DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
return false;
}
Expand Down
12 changes: 6 additions & 6 deletions llvm/lib/Target/AArch64/AArch64BranchRelaxation.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -177,7 +177,7 @@ void AArch64BranchRelaxation::scanFunction() {
void AArch64BranchRelaxation::computeBlockSize(const MachineBasicBlock &MBB) {
unsigned Size = 0;
for (const MachineInstr &MI : MBB)
Size += TII->GetInstSizeInBytes(&MI);
Size += TII->GetInstSizeInBytes(MI);
BlockInfo[MBB.getNumber()].Size = Size;
}

Expand All @@ -195,7 +195,7 @@ unsigned AArch64BranchRelaxation::getInstrOffset(MachineInstr *MI) const {
// Sum instructions before MI in MBB.
for (MachineBasicBlock::iterator I = MBB->begin(); &*I != MI; ++I) {
assert(I != MBB->end() && "Didn't find MI in its own basic block?");
Offset += TII->GetInstSizeInBytes(I);
Offset += TII->GetInstSizeInBytes(*I);
}
return Offset;
}
Expand Down Expand Up @@ -420,7 +420,7 @@ bool AArch64BranchRelaxation::fixupConditionalBranch(MachineInstr *MI) {
MachineBasicBlock *NewBB = splitBlockBeforeInstr(MI);
// No need for the branch to the next block. We're adding an unconditional
// branch to the destination.
int delta = TII->GetInstSizeInBytes(&MBB->back());
int delta = TII->GetInstSizeInBytes(MBB->back());
BlockInfo[MBB->getNumber()].Size -= delta;
MBB->back().eraseFromParent();
// BlockInfo[SplitBB].Offset is wrong temporarily, fixed below
Expand All @@ -446,12 +446,12 @@ bool AArch64BranchRelaxation::fixupConditionalBranch(MachineInstr *MI) {
if (MI->getOpcode() == AArch64::Bcc)
invertBccCondition(MIB);
MIB.addMBB(NextBB);
BlockInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(&MBB->back());
BlockInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(MBB->back());
BuildMI(MBB, DebugLoc(), TII->get(AArch64::B)).addMBB(DestBB);
BlockInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(&MBB->back());
BlockInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(MBB->back());

// Remove the old conditional branch. It may or may not still be in MBB.
BlockInfo[MI->getParent()->getNumber()].Size -= TII->GetInstSizeInBytes(MI);
BlockInfo[MI->getParent()->getNumber()].Size -= TII->GetInstSizeInBytes(*MI);
MI->eraseFromParent();

// Finally, keep the block offsets up to date.
Expand Down
357 changes: 177 additions & 180 deletions llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
View file

Large diffs are not rendered by default.

64 changes: 32 additions & 32 deletions llvm/lib/Target/AArch64/AArch64InstrInfo.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -45,77 +45,77 @@ class AArch64InstrInfo : public AArch64GenInstrInfo {
/// always be able to get register info as well (through this method).
const AArch64RegisterInfo &getRegisterInfo() const { return RI; }

unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
unsigned GetInstSizeInBytes(const MachineInstr &MI) const;

bool isAsCheapAsAMove(const MachineInstr *MI) const override;
bool isAsCheapAsAMove(const MachineInstr &MI) const override;

bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
unsigned &DstReg, unsigned &SubIdx) const override;

bool
areMemAccessesTriviallyDisjoint(MachineInstr *MIa, MachineInstr *MIb,
areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
AliasAnalysis *AA = nullptr) const override;

unsigned isLoadFromStackSlot(const MachineInstr *MI,
unsigned isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex) const override;
unsigned isStoreToStackSlot(const MachineInstr *MI,
unsigned isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex) const override;

/// Returns true if there is a shiftable register and that the shift value
/// is non-zero.
bool hasShiftedReg(const MachineInstr *MI) const;
bool hasShiftedReg(const MachineInstr &MI) const;

/// Returns true if there is an extendable register and that the extending
/// value is non-zero.
bool hasExtendedReg(const MachineInstr *MI) const;
bool hasExtendedReg(const MachineInstr &MI) const;

/// \brief Does this instruction set its full destination register to zero?
bool isGPRZero(const MachineInstr *MI) const;
bool isGPRZero(const MachineInstr &MI) const;

/// \brief Does this instruction rename a GPR without modifying bits?
bool isGPRCopy(const MachineInstr *MI) const;
bool isGPRCopy(const MachineInstr &MI) const;

/// \brief Does this instruction rename an FPR without modifying bits?
bool isFPRCopy(const MachineInstr *MI) const;
bool isFPRCopy(const MachineInstr &MI) const;

/// Return true if this is load/store scales or extends its register offset.
/// This refers to scaling a dynamic index as opposed to scaled immediates.
/// MI should be a memory op that allows scaled addressing.
bool isScaledAddr(const MachineInstr *MI) const;
bool isScaledAddr(const MachineInstr &MI) const;

/// Return true if pairing the given load or store is hinted to be
/// unprofitable.
bool isLdStPairSuppressed(const MachineInstr *MI) const;
bool isLdStPairSuppressed(const MachineInstr &MI) const;

/// Return true if this is an unscaled load/store.
bool isUnscaledLdSt(unsigned Opc) const;

/// Return true if this is an unscaled load/store.
bool isUnscaledLdSt(MachineInstr *MI) const;
bool isUnscaledLdSt(MachineInstr &MI) const;

/// Return true if this is a load/store that can be potentially paired/merged.
bool isCandidateToMergeOrPair(MachineInstr *MI) const;
bool isCandidateToMergeOrPair(MachineInstr &MI) const;

/// Hint that pairing the given load or store is unprofitable.
void suppressLdStPair(MachineInstr *MI) const;
void suppressLdStPair(MachineInstr &MI) const;

bool getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg,
int64_t &Offset,
const TargetRegisterInfo *TRI) const override;

bool getMemOpBaseRegImmOfsWidth(MachineInstr *LdSt, unsigned &BaseReg,
bool getMemOpBaseRegImmOfsWidth(MachineInstr &LdSt, unsigned &BaseReg,
int64_t &Offset, unsigned &Width,
const TargetRegisterInfo *TRI) const;

bool enableClusterLoads() const override { return true; }

bool enableClusterStores() const override { return true; }

bool shouldClusterMemOps(MachineInstr *FirstLdSt, MachineInstr *SecondLdSt,
unsigned NumLoads) const override;
bool shouldClusterMemOps(MachineInstr &FirstLdSt, MachineInstr &SecondLdSt,
unsigned NumLoads) const override;

bool shouldScheduleAdjacent(MachineInstr *First,
MachineInstr *Second) const override;
bool shouldScheduleAdjacent(MachineInstr &First,
MachineInstr &Second) const override;

MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx,
uint64_t Offset, const MDNode *Var,
Expand All @@ -141,11 +141,11 @@ class AArch64InstrInfo : public AArch64GenInstrInfo {
const TargetRegisterInfo *TRI) const override;

using TargetInstrInfo::foldMemoryOperandImpl;
MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
ArrayRef<unsigned> Ops,
MachineBasicBlock::iterator InsertPt,
int FrameIndex,
LiveIntervals *LIS = nullptr) const override;
MachineInstr *
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
ArrayRef<unsigned> Ops,
MachineBasicBlock::iterator InsertPt, int FrameIndex,
LiveIntervals *LIS = nullptr) const override;

bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB,
Expand All @@ -168,15 +168,15 @@ class AArch64InstrInfo : public AArch64GenInstrInfo {
/// analyzeCompare - For a comparison instruction, return the source registers
/// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
/// Return true if the comparison instruction can be analyzed.
bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
unsigned &SrcReg2, int &CmpMask,
int &CmpValue) const override;
/// optimizeCompareInstr - Convert the instruction supplying the argument to
/// the comparison into one that sets the zero bit in the flags register.
bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
unsigned SrcReg2, int CmpMask, int CmpValue,
const MachineRegisterInfo *MRI) const override;
bool optimizeCondBranch(MachineInstr *MI) const override;
bool optimizeCondBranch(MachineInstr &MI) const override;

/// Return true when a code sequence can improve throughput. It
/// should be called only for instructions in loops.
Expand All @@ -201,7 +201,7 @@ class AArch64InstrInfo : public AArch64GenInstrInfo {
/// AArch64 supports MachineCombiner.
bool useMachineCombiner() const override;

bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
bool expandPostRAPseudo(MachineInstr &MI) const override;

std::pair<unsigned, unsigned>
decomposeMachineOperandsTargetFlags(unsigned TF) const override;
Expand All @@ -214,8 +214,8 @@ class AArch64InstrInfo : public AArch64GenInstrInfo {
void instantiateCondBranch(MachineBasicBlock &MBB, const DebugLoc &DL,
MachineBasicBlock *TBB,
ArrayRef<MachineOperand> Cond) const;
bool substituteCmpToZero(MachineInstr *CmpInstr,
unsigned SrcReg, const MachineRegisterInfo *MRI) const;
bool substituteCmpToZero(MachineInstr &CmpInstr, unsigned SrcReg,
const MachineRegisterInfo *MRI) const;
};

/// emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg
Expand Down
42 changes: 21 additions & 21 deletions llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -604,10 +604,10 @@ static bool isLdOffsetInRangeOfSt(MachineInstr *LoadInst,
assert(isMatchingStore(LoadInst, StoreInst) && "Expect only matched ld/st.");
int LoadSize = getMemScale(LoadInst);
int StoreSize = getMemScale(StoreInst);
int UnscaledStOffset = TII->isUnscaledLdSt(StoreInst)
int UnscaledStOffset = TII->isUnscaledLdSt(*StoreInst)
? getLdStOffsetOp(StoreInst).getImm()
: getLdStOffsetOp(StoreInst).getImm() * StoreSize;
int UnscaledLdOffset = TII->isUnscaledLdSt(LoadInst)
int UnscaledLdOffset = TII->isUnscaledLdSt(*LoadInst)
? getLdStOffsetOp(LoadInst).getImm()
: getLdStOffsetOp(LoadInst).getImm() * LoadSize;
return (UnscaledStOffset <= UnscaledLdOffset) &&
Expand Down Expand Up @@ -963,8 +963,8 @@ AArch64LoadStoreOpt::promoteLoadFromStore(MachineBasicBlock::iterator LoadI,
// performance and correctness are verified only in little-endian.
if (!Subtarget->isLittleEndian())
return NextI;
bool IsUnscaled = TII->isUnscaledLdSt(LoadI);
assert(IsUnscaled == TII->isUnscaledLdSt(StoreI) &&
bool IsUnscaled = TII->isUnscaledLdSt(*LoadI);
assert(IsUnscaled == TII->isUnscaledLdSt(*StoreI) &&
"Unsupported ld/st match");
assert(LoadSize <= StoreSize && "Invalid load size");
int UnscaledLdOffset = IsUnscaled
Expand Down Expand Up @@ -1072,24 +1072,24 @@ static int alignTo(int Num, int PowOf2) {
return (Num + PowOf2 - 1) & ~(PowOf2 - 1);
}

static bool mayAlias(MachineInstr *MIa, MachineInstr *MIb,
static bool mayAlias(MachineInstr &MIa, MachineInstr &MIb,
const AArch64InstrInfo *TII) {
// One of the instructions must modify memory.
if (!MIa->mayStore() && !MIb->mayStore())
if (!MIa.mayStore() && !MIb.mayStore())
return false;

// Both instructions must be memory operations.
if (!MIa->mayLoadOrStore() && !MIb->mayLoadOrStore())
if (!MIa.mayLoadOrStore() && !MIb.mayLoadOrStore())
return false;

return !TII->areMemAccessesTriviallyDisjoint(MIa, MIb);
}

static bool mayAlias(MachineInstr *MIa,
static bool mayAlias(MachineInstr &MIa,
SmallVectorImpl<MachineInstr *> &MemInsns,
const AArch64InstrInfo *TII) {
for (auto &MIb : MemInsns)
if (mayAlias(MIa, MIb, TII))
for (MachineInstr *MIb : MemInsns)
if (mayAlias(MIa, *MIb, TII))
return true;

return false;
Expand Down Expand Up @@ -1146,7 +1146,7 @@ bool AArch64LoadStoreOpt::findMatchingStore(
return false;

// If we encounter a store aliased with the load, return early.
if (MI->mayStore() && mayAlias(LoadMI, MI, TII))
if (MI->mayStore() && mayAlias(*LoadMI, *MI, TII))
return false;
} while (MBBI != B && Count < Limit);
return false;
Expand All @@ -1158,12 +1158,12 @@ static bool areCandidatesToMergeOrPair(MachineInstr *FirstMI, MachineInstr *MI,
LdStPairFlags &Flags,
const AArch64InstrInfo *TII) {
// If this is volatile or if pairing is suppressed, not a candidate.
if (MI->hasOrderedMemoryRef() || TII->isLdStPairSuppressed(MI))
if (MI->hasOrderedMemoryRef() || TII->isLdStPairSuppressed(*MI))
return false;

// We should have already checked FirstMI for pair suppression and volatility.
assert(!FirstMI->hasOrderedMemoryRef() &&
!TII->isLdStPairSuppressed(FirstMI) &&
!TII->isLdStPairSuppressed(*FirstMI) &&
"FirstMI shouldn't get here if either of these checks are true.");

unsigned OpcA = FirstMI->getOpcode();
Expand Down Expand Up @@ -1212,7 +1212,7 @@ AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
++MBBI;

bool MayLoad = FirstMI->mayLoad();
bool IsUnscaled = TII->isUnscaledLdSt(FirstMI);
bool IsUnscaled = TII->isUnscaledLdSt(*FirstMI);
unsigned Reg = getLdStRegOp(FirstMI).getReg();
unsigned BaseReg = getLdStBaseOp(FirstMI).getReg();
int Offset = getLdStOffsetOp(FirstMI).getImm();
Expand Down Expand Up @@ -1249,7 +1249,7 @@ AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
// a relocation.
unsigned MIBaseReg = getLdStBaseOp(MI).getReg();
int MIOffset = getLdStOffsetOp(MI).getImm();
bool MIIsUnscaled = TII->isUnscaledLdSt(MI);
bool MIIsUnscaled = TII->isUnscaledLdSt(*MI);
if (IsUnscaled != MIIsUnscaled) {
// We're trying to pair instructions that differ in how they are scaled.
// If FirstMI is scaled then scale the offset of MI accordingly.
Expand Down Expand Up @@ -1314,7 +1314,7 @@ AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
// first.
if (!ModifiedRegs[getLdStRegOp(MI).getReg()] &&
!(MI->mayLoad() && UsedRegs[getLdStRegOp(MI).getReg()]) &&
!mayAlias(MI, MemInsns, TII)) {
!mayAlias(*MI, MemInsns, TII)) {
Flags.setMergeForward(false);
return MBBI;
}
Expand All @@ -1325,7 +1325,7 @@ AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
// into the second.
if (!ModifiedRegs[getLdStRegOp(FirstMI).getReg()] &&
!(MayLoad && UsedRegs[getLdStRegOp(FirstMI).getReg()]) &&
!mayAlias(FirstMI, MemInsns, TII)) {
!mayAlias(*FirstMI, MemInsns, TII)) {
Flags.setMergeForward(true);
return MBBI;
}
Expand Down Expand Up @@ -1610,7 +1610,7 @@ bool AArch64LoadStoreOpt::tryToMergeLdStInst(
MachineInstr *MI = MBBI;
MachineBasicBlock::iterator E = MI->getParent()->end();

if (!TII->isCandidateToMergeOrPair(MI))
if (!TII->isCandidateToMergeOrPair(*MI))
return false;

// For promotable zero stores, the stored value should be WZR.
Expand Down Expand Up @@ -1642,13 +1642,13 @@ bool AArch64LoadStoreOpt::tryToPairLdStInst(MachineBasicBlock::iterator &MBBI) {
MachineInstr *MI = MBBI;
MachineBasicBlock::iterator E = MI->getParent()->end();

if (!TII->isCandidateToMergeOrPair(MI))
if (!TII->isCandidateToMergeOrPair(*MI))
return false;

// Early exit if the offset is not possible to match. (6 bits of positive
// range, plus allow an extra one in case we find a later insn that matches
// with Offset-1)
bool IsUnscaled = TII->isUnscaledLdSt(MI);
bool IsUnscaled = TII->isUnscaledLdSt(*MI);
int Offset = getLdStOffsetOp(MI).getImm();
int OffsetStride = IsUnscaled ? getMemScale(MI) : 1;
if (!inBoundsForPair(IsUnscaled, Offset, OffsetStride))
Expand All @@ -1660,7 +1660,7 @@ bool AArch64LoadStoreOpt::tryToPairLdStInst(MachineBasicBlock::iterator &MBBI) {
findMatchingInsn(MBBI, Flags, LdStLimit, /* FindNarrowMerge = */ false);
if (Paired != E) {
++NumPairCreated;
if (TII->isUnscaledLdSt(MI))
if (TII->isUnscaledLdSt(*MI))
++NumUnscaledPairCreated;
// Keeping the iterator straight is a pain, so we let the merge routine tell
// us what the next instruction is after it's done mucking about.
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/AArch64/AArch64SchedCyclone.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -108,7 +108,7 @@ def WriteX : SchedWriteRes<[]> { let Latency = 0; }
// The move is replaced by a single nop micro-op.
// MOVZ Rd, #0
// AND Rd, Rzr, #imm
def WriteZPred : SchedPredicate<[{TII->isGPRZero(MI)}]>;
def WriteZPred : SchedPredicate<[{TII->isGPRZero(*MI)}]>;
def WriteImmZ : SchedWriteVariant<[
SchedVar<WriteZPred, [WriteX]>,
SchedVar<NoSchedPred, [WriteImm]>]>;
Expand All @@ -117,8 +117,8 @@ def : InstRW<[WriteImmZ], (instrs MOVZWi,MOVZXi,ANDWri,ANDXri)>;
// Move GPR is a register rename and single nop micro-op.
// ORR Xd, XZR, Xm
// ADD Xd, Xn, #0
def WriteIMovPred : SchedPredicate<[{TII->isGPRCopy(MI)}]>;
def WriteVMovPred : SchedPredicate<[{TII->isFPRCopy(MI)}]>;
def WriteIMovPred : SchedPredicate<[{TII->isGPRCopy(*MI)}]>;
def WriteVMovPred : SchedPredicate<[{TII->isFPRCopy(*MI)}]>;
def WriteMov : SchedWriteVariant<[
SchedVar<WriteIMovPred, [WriteX]>,
SchedVar<WriteVMovPred, [WriteX]>,
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/AArch64/AArch64Schedule.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -51,15 +51,15 @@ def WriteSTIdx : SchedWrite; // Store to a register index (maybe scaled).
def ReadAdrBase : SchedRead; // Read the base resister of a reg-offset LD/ST.

// Predicate for determining when a shiftable register is shifted.
def RegShiftedPred : SchedPredicate<[{TII->hasShiftedReg(MI)}]>;
def RegShiftedPred : SchedPredicate<[{TII->hasShiftedReg(*MI)}]>;

// Predicate for determining when a extendedable register is extended.
def RegExtendedPred : SchedPredicate<[{TII->hasExtendedReg(MI)}]>;
def RegExtendedPred : SchedPredicate<[{TII->hasExtendedReg(*MI)}]>;

// ScaledIdxPred is true if a WriteLDIdx operand will be
// scaled. Subtargets can use this to dynamically select resources and
// latency for WriteLDIdx and ReadAdrBase.
def ScaledIdxPred : SchedPredicate<[{TII->isScaledAddr(MI)}]>;
def ScaledIdxPred : SchedPredicate<[{TII->isScaledAddr(*MI)}]>;

// Serialized two-level address load.
// EXAMPLE: LOADGot
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/AArch64/AArch64StorePairSuppress.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -145,15 +145,15 @@ bool AArch64StorePairSuppress::runOnMachineFunction(MachineFunction &MF) {
continue;
unsigned BaseReg;
int64_t Offset;
if (TII->getMemOpBaseRegImmOfs(&MI, BaseReg, Offset, TRI)) {
if (TII->getMemOpBaseRegImmOfs(MI, BaseReg, Offset, TRI)) {
if (PrevBaseReg == BaseReg) {
// If this block can take STPs, skip ahead to the next block.
if (!SuppressSTP && shouldAddSTPToBlock(MI.getParent()))
break;
// Otherwise, continue unpairing the stores in this block.
DEBUG(dbgs() << "Unpairing store " << MI << "\n");
SuppressSTP = true;
TII->suppressLdStPair(&MI);
TII->suppressLdStPair(MI);
}
PrevBaseReg = BaseReg;
} else
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -92,7 +92,7 @@ void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) {
AMDGPUMCInstLower MCInstLowering(OutContext, STI);

StringRef Err;
if (!STI.getInstrInfo()->verifyInstruction(MI, Err)) {
if (!STI.getInstrInfo()->verifyInstruction(*MI, Err)) {
LLVMContext &C = MI->getParent()->getParent()->getFunction()->getContext();
C.emitError("Illegal instruction detected: " + Err);
MI->dump();
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/R600ClauseMergePass.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -181,7 +181,7 @@ bool R600ClauseMergePass::runOnMachineFunction(MachineFunction &MF) {
MachineBasicBlock::iterator LatestCFAlu = E;
while (I != E) {
MachineInstr *MI = I++;
if ((!TII->canBeConsideredALU(MI) && !isCFAlu(MI)) ||
if ((!TII->canBeConsideredALU(*MI) && !isCFAlu(MI)) ||
TII->mustBeLastInClause(MI->getOpcode()))
LatestCFAlu = E;
if (!isCFAlu(MI))
Expand Down
12 changes: 6 additions & 6 deletions llvm/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -318,15 +318,15 @@ class R600ControlFlowFinalizer : public MachineFunctionPass {
MachineBasicBlock::iterator ClauseHead = I;
std::vector<MachineInstr *> ClauseContent;
unsigned AluInstCount = 0;
bool IsTex = TII->usesTextureCache(ClauseHead);
bool IsTex = TII->usesTextureCache(*ClauseHead);
std::set<unsigned> DstRegs;
for (MachineBasicBlock::iterator E = MBB.end(); I != E; ++I) {
if (IsTrivialInst(I))
continue;
if (AluInstCount >= MaxFetchInst)
break;
if ((IsTex && !TII->usesTextureCache(I)) ||
(!IsTex && !TII->usesVertexCache(I)))
if ((IsTex && !TII->usesTextureCache(*I)) ||
(!IsTex && !TII->usesVertexCache(*I)))
break;
if (!isCompatibleWithClause(I, DstRegs))
break;
Expand All @@ -347,8 +347,8 @@ class R600ControlFlowFinalizer : public MachineFunctionPass {
AMDGPU::ALU_LITERAL_Z,
AMDGPU::ALU_LITERAL_W
};
const SmallVector<std::pair<MachineOperand *, int64_t>, 3 > Srcs =
TII->getSrcs(MI);
const SmallVector<std::pair<MachineOperand *, int64_t>, 3> Srcs =
TII->getSrcs(*MI);
for (const auto &Src:Srcs) {
if (Src.first->getReg() != AMDGPU::ALU_LITERAL_X)
continue;
Expand Down Expand Up @@ -516,7 +516,7 @@ class R600ControlFlowFinalizer : public MachineFunctionPass {

for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
I != E;) {
if (TII->usesTextureCache(I) || TII->usesVertexCache(I)) {
if (TII->usesTextureCache(*I) || TII->usesVertexCache(*I)) {
DEBUG(dbgs() << CfCount << ":"; I->dump(););
FetchClauses.push_back(MakeFetchClause(MBB, I));
CfCount++;
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/AMDGPU/R600EmitClauseMarkers.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -122,8 +122,8 @@ class R600EmitClauseMarkers : public MachineFunctionPass {
if (!TII->isALUInstr(MI->getOpcode()) && MI->getOpcode() != AMDGPU::DOT_4)
return true;

const SmallVectorImpl<std::pair<MachineOperand *, int64_t> > &Consts =
TII->getSrcs(MI);
const SmallVectorImpl<std::pair<MachineOperand *, int64_t>> &Consts =
TII->getSrcs(*MI);
assert((TII->isALUInstr(MI->getOpcode()) ||
MI->getOpcode() == AMDGPU::DOT_4) && "Can't assign Const");
for (unsigned i = 0, n = Consts.size(); i < n; ++i) {
Expand Down Expand Up @@ -245,7 +245,7 @@ class R600EmitClauseMarkers : public MachineFunctionPass {
// clause as predicated alus).
if (AluInstCount > 0)
break;
if (TII->getFlagOp(I).getImm() & MO_FLAG_PUSH)
if (TII->getFlagOp(*I).getImm() & MO_FLAG_PUSH)
PushBeforeModifier = true;
AluInstCount ++;
continue;
Expand Down
26 changes: 13 additions & 13 deletions llvm/lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -60,7 +60,7 @@ void R600ExpandSpecialInstrsPass::SetFlagInNewMI(MachineInstr *NewMI,
int OpIdx = TII->getOperandIdx(*OldMI, Op);
if (OpIdx > -1) {
uint64_t Val = OldMI->getOperand(OpIdx).getImm();
TII->setImmOperand(NewMI, Op, Val);
TII->setImmOperand(*NewMI, Op, Val);
}
}

Expand Down Expand Up @@ -107,11 +107,11 @@ bool R600ExpandSpecialInstrsPass::runOnMachineFunction(MachineFunction &MF) {
MI.getOperand(0).getReg(), // dst
MI.getOperand(1).getReg(), // src0
AMDGPU::ZERO); // src1
TII->addFlag(PredSet, 0, MO_FLAG_MASK);
TII->addFlag(*PredSet, 0, MO_FLAG_MASK);
if (Flags & MO_FLAG_PUSH) {
TII->setImmOperand(PredSet, AMDGPU::OpName::update_exec_mask, 1);
TII->setImmOperand(*PredSet, AMDGPU::OpName::update_exec_mask, 1);
} else {
TII->setImmOperand(PredSet, AMDGPU::OpName::update_pred, 1);
TII->setImmOperand(*PredSet, AMDGPU::OpName::update_pred, 1);
}
MI.eraseFromParent();
continue;
Expand All @@ -137,9 +137,9 @@ bool R600ExpandSpecialInstrsPass::runOnMachineFunction(MachineFunction &MF) {
BMI->bundleWithPred();
}
if (Chan >= 2)
TII->addFlag(BMI, 0, MO_FLAG_MASK);
TII->addFlag(*BMI, 0, MO_FLAG_MASK);
if (Chan != 3)
TII->addFlag(BMI, 0, MO_FLAG_NOT_LAST);
TII->addFlag(*BMI, 0, MO_FLAG_NOT_LAST);
}

MI.eraseFromParent();
Expand All @@ -166,9 +166,9 @@ bool R600ExpandSpecialInstrsPass::runOnMachineFunction(MachineFunction &MF) {
BMI->bundleWithPred();
}
if (Chan < 2)
TII->addFlag(BMI, 0, MO_FLAG_MASK);
TII->addFlag(*BMI, 0, MO_FLAG_MASK);
if (Chan != 3)
TII->addFlag(BMI, 0, MO_FLAG_NOT_LAST);
TII->addFlag(*BMI, 0, MO_FLAG_NOT_LAST);
}

MI.eraseFromParent();
Expand All @@ -189,7 +189,7 @@ bool R600ExpandSpecialInstrsPass::runOnMachineFunction(MachineFunction &MF) {
BMI->bundleWithPred();
}
if (Chan != 3)
TII->addFlag(BMI, 0, MO_FLAG_NOT_LAST);
TII->addFlag(*BMI, 0, MO_FLAG_NOT_LAST);
}

MI.eraseFromParent();
Expand All @@ -212,10 +212,10 @@ bool R600ExpandSpecialInstrsPass::runOnMachineFunction(MachineFunction &MF) {
BMI->bundleWithPred();
}
if (Mask) {
TII->addFlag(BMI, 0, MO_FLAG_MASK);
TII->addFlag(*BMI, 0, MO_FLAG_MASK);
}
if (Chan != 3)
TII->addFlag(BMI, 0, MO_FLAG_NOT_LAST);
TII->addFlag(*BMI, 0, MO_FLAG_NOT_LAST);
unsigned Opcode = BMI->getOpcode();
// While not strictly necessary from hw point of view, we force
// all src operands of a dot4 inst to belong to the same slot.
Expand Down Expand Up @@ -330,10 +330,10 @@ bool R600ExpandSpecialInstrsPass::runOnMachineFunction(MachineFunction &MF) {
if (Chan != 0)
NewMI->bundleWithPred();
if (Mask) {
TII->addFlag(NewMI, 0, MO_FLAG_MASK);
TII->addFlag(*NewMI, 0, MO_FLAG_MASK);
}
if (NotLast) {
TII->addFlag(NewMI, 0, MO_FLAG_NOT_LAST);
TII->addFlag(*NewMI, 0, MO_FLAG_NOT_LAST);
}
SetFlagInNewMI(NewMI, &MI, AMDGPU::OpName::clamp);
SetFlagInNewMI(NewMI, &MI, AMDGPU::OpName::literal);
Expand Down
16 changes: 8 additions & 8 deletions llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -242,7 +242,7 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
AMDGPU::MOV,
MI->getOperand(0).getReg(),
MI->getOperand(1).getReg());
TII->addFlag(NewMI, 0, MO_FLAG_CLAMP);
TII->addFlag(*NewMI, 0, MO_FLAG_CLAMP);
break;
}

Expand All @@ -251,7 +251,7 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
AMDGPU::MOV,
MI->getOperand(0).getReg(),
MI->getOperand(1).getReg());
TII->addFlag(NewMI, 0, MO_FLAG_ABS);
TII->addFlag(*NewMI, 0, MO_FLAG_ABS);
break;
}

Expand All @@ -260,15 +260,15 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
AMDGPU::MOV,
MI->getOperand(0).getReg(),
MI->getOperand(1).getReg());
TII->addFlag(NewMI, 0, MO_FLAG_NEG);
TII->addFlag(*NewMI, 0, MO_FLAG_NEG);
break;
}

case AMDGPU::MASK_WRITE: {
unsigned maskedRegister = MI->getOperand(0).getReg();
assert(TargetRegisterInfo::isVirtualRegister(maskedRegister));
MachineInstr * defInstr = MRI.getVRegDef(maskedRegister);
TII->addFlag(defInstr, 0, MO_FLAG_MASK);
TII->addFlag(*defInstr, 0, MO_FLAG_MASK);
break;
}

Expand All @@ -294,8 +294,8 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
case AMDGPU::CONST_COPY: {
MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, MI, AMDGPU::MOV,
MI->getOperand(0).getReg(), AMDGPU::ALU_CONST);
TII->setImmOperand(NewMI, AMDGPU::OpName::src0_sel,
MI->getOperand(1).getImm());
TII->setImmOperand(*NewMI, AMDGPU::OpName::src0_sel,
MI->getOperand(1).getImm());
break;
}

Expand Down Expand Up @@ -532,7 +532,7 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
.addOperand(MI->getOperand(1))
.addImm(OPCODE_IS_NOT_ZERO)
.addImm(0); // Flags
TII->addFlag(NewMI, 0, MO_FLAG_PUSH);
TII->addFlag(*NewMI, 0, MO_FLAG_PUSH);
BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))
.addOperand(MI->getOperand(0))
.addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
Expand All @@ -546,7 +546,7 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
.addOperand(MI->getOperand(1))
.addImm(OPCODE_IS_NOT_ZERO_INT)
.addImm(0); // Flags
TII->addFlag(NewMI, 0, MO_FLAG_PUSH);
TII->addFlag(*NewMI, 0, MO_FLAG_PUSH);
BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))
.addOperand(MI->getOperand(0))
.addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
Expand Down
222 changes: 116 additions & 106 deletions llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
View file

Large diffs are not rendered by default.

33 changes: 16 additions & 17 deletions llvm/lib/Target/AMDGPU/R600InstrInfo.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -32,8 +32,7 @@ class R600InstrInfo final : public AMDGPUInstrInfo {
const R600Subtarget &ST;

std::vector<std::pair<int, unsigned>>
ExtractSrcs(MachineInstr *MI,
const DenseMap<unsigned, unsigned> &PV,
ExtractSrcs(MachineInstr &MI, const DenseMap<unsigned, unsigned> &PV,
unsigned &ConstCount) const;

MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
Expand Down Expand Up @@ -83,23 +82,23 @@ class R600InstrInfo final : public AMDGPUInstrInfo {

/// \returns true if this \p Opcode represents an ALU instruction or an
/// instruction that will be lowered in ExpandSpecialInstrs Pass.
bool canBeConsideredALU(const MachineInstr *MI) const;
bool canBeConsideredALU(const MachineInstr &MI) const;

bool isTransOnly(unsigned Opcode) const;
bool isTransOnly(const MachineInstr *MI) const;
bool isTransOnly(const MachineInstr &MI) const;
bool isVectorOnly(unsigned Opcode) const;
bool isVectorOnly(const MachineInstr *MI) const;
bool isVectorOnly(const MachineInstr &MI) const;
bool isExport(unsigned Opcode) const;

bool usesVertexCache(unsigned Opcode) const;
bool usesVertexCache(const MachineInstr *MI) const;
bool usesVertexCache(const MachineInstr &MI) const;
bool usesTextureCache(unsigned Opcode) const;
bool usesTextureCache(const MachineInstr *MI) const;
bool usesTextureCache(const MachineInstr &MI) const;

bool mustBeLastInClause(unsigned Opcode) const;
bool usesAddressRegister(MachineInstr *MI) const;
bool definesAddressRegister(MachineInstr *MI) const;
bool readsLDSSrcReg(const MachineInstr *MI) const;
bool usesAddressRegister(MachineInstr &MI) const;
bool definesAddressRegister(MachineInstr &MI) const;
bool readsLDSSrcReg(const MachineInstr &MI) const;

/// \returns The operand index for the given source number. Legal values
/// for SrcNum are 0, 1, and 2.
Expand All @@ -114,7 +113,7 @@ class R600InstrInfo final : public AMDGPUInstrInfo {
/// If register is ALU_LITERAL, second member is IMM.
/// Otherwise, second member value is undefined.
SmallVector<std::pair<MachineOperand *, int64_t>, 3>
getSrcs(MachineInstr *MI) const;
getSrcs(MachineInstr &MI) const;

unsigned isLegalUpTo(
const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
Expand Down Expand Up @@ -205,13 +204,13 @@ class R600InstrInfo final : public AMDGPUInstrInfo {
unsigned int getPredicationCost(const MachineInstr &) const override;

unsigned int getInstrLatency(const InstrItineraryData *ItinData,
const MachineInstr *MI,
const MachineInstr &MI,
unsigned *PredCost = nullptr) const override;

int getInstrLatency(const InstrItineraryData *ItinData,
SDNode *Node) const override { return 1;}

bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
bool expandPostRAPseudo(MachineInstr &MI) const override;

/// \brief Reserve the registers that may be accesed using indirect addressing.
void reserveIndirectRegisters(BitVector &Reserved,
Expand Down Expand Up @@ -286,13 +285,13 @@ class R600InstrInfo final : public AMDGPUInstrInfo {
int getOperandIdx(unsigned Opcode, unsigned Op) const;

/// \brief Helper function for setting instruction flag values.
void setImmOperand(MachineInstr *MI, unsigned Op, int64_t Imm) const;
void setImmOperand(MachineInstr &MI, unsigned Op, int64_t Imm) const;

/// \returns true if this instruction has an operand for storing target flags.
bool hasFlagOperand(const MachineInstr &MI) const;

///\brief Add one of the MO_FLAG* flags to the specified \p Operand.
void addFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
void addFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) const;

///\brief Determine if the specified \p Flag is set on this \p Operand.
bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const;
Expand All @@ -301,11 +300,11 @@ class R600InstrInfo final : public AMDGPUInstrInfo {
/// \param Flag The flag being set.
///
/// \returns the operand containing the flags for this instruction.
MachineOperand &getFlagOp(MachineInstr *MI, unsigned SrcIdx = 0,
MachineOperand &getFlagOp(MachineInstr &MI, unsigned SrcIdx = 0,
unsigned Flag = 0) const;

/// \brief Clear the specified flag on the instruction.
void clearFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
void clearFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) const;

// Helper functions that check the opcode for status information
bool isRegisterStore(const MachineInstr &MI) const;
Expand Down
9 changes: 4 additions & 5 deletions llvm/lib/Target/AMDGPU/R600MachineScheduler.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -222,7 +222,7 @@ bool R600SchedStrategy::regBelongsToClass(unsigned Reg,
R600SchedStrategy::AluKind R600SchedStrategy::getAluKind(SUnit *SU) const {
MachineInstr *MI = SU->getInstr();

if (TII->isTransOnly(MI))
if (TII->isTransOnly(*MI))
return AluTrans;

switch (MI->getOpcode()) {
Expand Down Expand Up @@ -286,7 +286,7 @@ R600SchedStrategy::AluKind R600SchedStrategy::getAluKind(SUnit *SU) const {
return AluT_XYZW;

// LDS src registers cannot be used in the Trans slot.
if (TII->readsLDSSrcReg(MI))
if (TII->readsLDSSrcReg(*MI))
return AluT_XYZW;

return AluAny;
Expand Down Expand Up @@ -323,9 +323,8 @@ SUnit *R600SchedStrategy::PopInst(std::vector<SUnit *> &Q, bool AnyALU) {
It != E; ++It) {
SUnit *SU = *It;
InstructionsGroupCandidate.push_back(SU->getInstr());
if (TII->fitsConstReadLimitations(InstructionsGroupCandidate)
&& (!AnyALU || !TII->isVectorOnly(SU->getInstr()))
) {
if (TII->fitsConstReadLimitations(InstructionsGroupCandidate) &&
(!AnyALU || !TII->isVectorOnly(*SU->getInstr()))) {
InstructionsGroupCandidate.pop_back();
Q.erase((It + 1).base());
return SU;
Expand Down
20 changes: 10 additions & 10 deletions llvm/lib/Target/AMDGPU/R600Packetizer.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -94,7 +94,7 @@ class R600PacketizerList : public VLIWPacketizerList {
continue;
}
unsigned Dst = BI->getOperand(DstIdx).getReg();
if (isTrans || TII->isTransOnly(&*BI)) {
if (isTrans || TII->isTransOnly(*BI)) {
Result[Dst] = AMDGPU::PS;
continue;
}
Expand Down Expand Up @@ -207,10 +207,10 @@ class R600PacketizerList : public VLIWPacketizerList {
}
}

bool ARDef = TII->definesAddressRegister(MII) ||
TII->definesAddressRegister(MIJ);
bool ARUse = TII->usesAddressRegister(MII) ||
TII->usesAddressRegister(MIJ);
bool ARDef =
TII->definesAddressRegister(*MII) || TII->definesAddressRegister(*MIJ);
bool ARUse =
TII->usesAddressRegister(*MII) || TII->usesAddressRegister(*MIJ);

return !ARDef || !ARUse;
}
Expand All @@ -230,14 +230,14 @@ class R600PacketizerList : public VLIWPacketizerList {
const DenseMap<unsigned, unsigned> &PV,
std::vector<R600InstrInfo::BankSwizzle> &BS,
bool &isTransSlot) {
isTransSlot = TII->isTransOnly(&MI);
isTransSlot = TII->isTransOnly(MI);
assert (!isTransSlot || VLIW5);

// Is the dst reg sequence legal ?
if (!isTransSlot && !CurrentPacketMIs.empty()) {
if (getSlot(MI) <= getSlot(*CurrentPacketMIs.back())) {
if (ConsideredInstUsesAlreadyWrittenVectorElement &&
!TII->isVectorOnly(&MI) && VLIW5) {
!TII->isVectorOnly(MI) && VLIW5) {
isTransSlot = true;
DEBUG({
dbgs() << "Considering as Trans Inst :";
Expand Down Expand Up @@ -284,7 +284,7 @@ class R600PacketizerList : public VLIWPacketizerList {
}

// We cannot read LDS source registrs from the Trans slot.
if (isTransSlot && TII->readsLDSSrcReg(&MI))
if (isTransSlot && TII->readsLDSSrcReg(MI))
return false;

CurrentPacketMIs.pop_back();
Expand Down Expand Up @@ -319,7 +319,7 @@ class R600PacketizerList : public VLIWPacketizerList {
return It;
}
endPacket(MI.getParent(), MI);
if (TII->isTransOnly(&MI))
if (TII->isTransOnly(MI))
return MI;
return VLIWPacketizerList::addToPacket(MI);
}
Expand Down Expand Up @@ -378,7 +378,7 @@ bool R600Packetizer::runOnMachineFunction(MachineFunction &Fn) {
// instruction stream until we find the nearest boundary.
MachineBasicBlock::iterator I = RegionEnd;
for(;I != MBB->begin(); --I, --RemainingCount) {
if (TII->isSchedulingBoundary(&*std::prev(I), &*MBB, Fn))
if (TII->isSchedulingBoundary(*std::prev(I), &*MBB, Fn))
break;
}
I = MBB->begin();
Expand Down
8 changes: 4 additions & 4 deletions llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -132,7 +132,7 @@ static bool tryAddToFoldList(std::vector<FoldCandidate> &FoldList,
MachineInstr *MI, unsigned OpNo,
MachineOperand *OpToFold,
const SIInstrInfo *TII) {
if (!TII->isOperandLegal(MI, OpNo, OpToFold)) {
if (!TII->isOperandLegal(*MI, OpNo, OpToFold)) {

// Special case for v_mac_f32_e64 if we are trying to fold into src2
unsigned Opc = MI->getOpcode();
Expand All @@ -159,7 +159,7 @@ static bool tryAddToFoldList(std::vector<FoldCandidate> &FoldList,
// see if this makes it possible to fold.
unsigned CommuteIdx0 = TargetInstrInfo::CommuteAnyOperandIndex;
unsigned CommuteIdx1 = TargetInstrInfo::CommuteAnyOperandIndex;
bool CanCommute = TII->findCommutedOpIndices(MI, CommuteIdx0, CommuteIdx1);
bool CanCommute = TII->findCommutedOpIndices(*MI, CommuteIdx0, CommuteIdx1);

if (CanCommute) {
if (CommuteIdx0 == OpNo)
Expand All @@ -177,10 +177,10 @@ static bool tryAddToFoldList(std::vector<FoldCandidate> &FoldList,
return false;

if (!CanCommute ||
!TII->commuteInstruction(MI, false, CommuteIdx0, CommuteIdx1))
!TII->commuteInstruction(*MI, false, CommuteIdx0, CommuteIdx1))
return false;

if (!TII->isOperandLegal(MI, OpNo, OpToFold))
if (!TII->isOperandLegal(*MI, OpNo, OpToFold))
return false;
}

Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/SIISelLowering.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3223,7 +3223,7 @@ void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,

if (TII->isVOP3(MI->getOpcode())) {
// Make sure constant bus requirements are respected.
TII->legalizeOperandsVOP3(MRI, MI);
TII->legalizeOperandsVOP3(MRI, *MI);
return;
}

Expand Down
850 changes: 420 additions & 430 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
View file

Large diffs are not rendered by default.

93 changes: 43 additions & 50 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -54,40 +54,39 @@ class SIInstrInfo final : public AMDGPUInstrInfo {
unsigned SubIdx,
const TargetRegisterClass *SubRC) const;

void swapOperands(MachineBasicBlock::iterator Inst) const;
void swapOperands(MachineInstr &Inst) const;

void lowerScalarAbs(SmallVectorImpl<MachineInstr *> &Worklist,
MachineInstr *Inst) const;
MachineInstr &Inst) const;

void splitScalar64BitUnaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
MachineInstr *Inst, unsigned Opcode) const;
MachineInstr &Inst, unsigned Opcode) const;

void splitScalar64BitBinaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
MachineInstr *Inst, unsigned Opcode) const;
MachineInstr &Inst, unsigned Opcode) const;

void splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
MachineInstr *Inst) const;
MachineInstr &Inst) const;
void splitScalar64BitBFE(SmallVectorImpl<MachineInstr *> &Worklist,
MachineInstr *Inst) const;
MachineInstr &Inst) const;

void addUsersToMoveToVALUWorklist(
unsigned Reg, MachineRegisterInfo &MRI,
SmallVectorImpl<MachineInstr *> &Worklist) const;

void addSCCDefUsersToVALUWorklist(
MachineInstr *SCCDefInst, SmallVectorImpl<MachineInstr *> &Worklist) const;
void
addSCCDefUsersToVALUWorklist(MachineInstr &SCCDefInst,
SmallVectorImpl<MachineInstr *> &Worklist) const;

const TargetRegisterClass *
getDestEquivalentVGPRClass(const MachineInstr &Inst) const;

bool checkInstOffsetsDoNotOverlap(MachineInstr *MIa,
MachineInstr *MIb) const;
bool checkInstOffsetsDoNotOverlap(MachineInstr &MIa, MachineInstr &MIb) const;

unsigned findUsedSGPR(const MachineInstr *MI, int OpIndices[3]) const;
unsigned findUsedSGPR(const MachineInstr &MI, int OpIndices[3]) const;

protected:
MachineInstr *commuteInstructionImpl(MachineInstr *MI,
bool NewMI,
MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
unsigned OpIdx0,
unsigned OpIdx1) const override;

Expand All @@ -98,45 +97,40 @@ class SIInstrInfo final : public AMDGPUInstrInfo {
return RI;
}

bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
AliasAnalysis *AA) const override;

bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
int64_t &Offset1,
int64_t &Offset2) const override;

bool getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg,
int64_t &Offset,
const TargetRegisterInfo *TRI) const final;

bool shouldClusterMemOps(MachineInstr *FirstLdSt,
MachineInstr *SecondLdSt,
bool shouldClusterMemOps(MachineInstr &FirstLdSt, MachineInstr &SecondLdSt,
unsigned NumLoads) const final;

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
bool KillSrc) const override;

unsigned calculateLDSSpillAddress(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
RegScavenger *RS,
unsigned TmpReg,
unsigned Offset,
unsigned Size) const;
unsigned calculateLDSSpillAddress(MachineBasicBlock &MBB, MachineInstr &MI,
RegScavenger *RS, unsigned TmpReg,
unsigned Offset, unsigned Size) const;

void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned SrcReg, bool isKill, int FrameIndex,
MachineBasicBlock::iterator MI, unsigned SrcReg,
bool isKill, int FrameIndex,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const override;

void loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, int FrameIndex,
const TargetRegisterClass *RC,
MachineBasicBlock::iterator MI, unsigned DestReg,
int FrameIndex, const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const override;

bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
bool expandPostRAPseudo(MachineInstr &MI) const override;

// \brief Returns an opcode that can be used to move a value to a \p DstRC
// register. If there is no hardware instruction that can store to \p
Expand All @@ -146,8 +140,7 @@ class SIInstrInfo final : public AMDGPUInstrInfo {
LLVM_READONLY
int commuteOpcode(const MachineInstr &MI) const;

bool findCommutedOpIndices(MachineInstr *MI,
unsigned &SrcOpIdx1,
bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
unsigned &SrcOpIdx2) const override;

bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
Expand All @@ -164,20 +157,20 @@ class SIInstrInfo final : public AMDGPUInstrInfo {
bool ReverseBranchCondition(
SmallVectorImpl<MachineOperand> &Cond) const override;

bool areMemAccessesTriviallyDisjoint(
MachineInstr *MIa, MachineInstr *MIb,
AliasAnalysis *AA = nullptr) const override;
bool
areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
AliasAnalysis *AA = nullptr) const override;

bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
unsigned Reg, MachineRegisterInfo *MRI) const final;
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg,
MachineRegisterInfo *MRI) const final;

unsigned getMachineCSELookAheadLimit() const override { return 500; }

MachineInstr *convertToThreeAddress(MachineFunction::iterator &MBB,
MachineBasicBlock::iterator &MI,
MachineInstr &MI,
LiveVariables *LV) const override;

bool isSchedulingBoundary(const MachineInstr *MI,
bool isSchedulingBoundary(const MachineInstr &MI,
const MachineBasicBlock *MBB,
const MachineFunction &MF) const override;

Expand Down Expand Up @@ -361,7 +354,7 @@ class SIInstrInfo final : public AMDGPUInstrInfo {
bool isInlineConstant(const MachineOperand &MO, unsigned OpSize) const;
bool isLiteralConstant(const MachineOperand &MO, unsigned OpSize) const;

bool isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,
bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo,
const MachineOperand &MO) const;

/// \brief Return true if this 64-bit VALU instruction has a 32-bit encoding.
Expand All @@ -380,7 +373,7 @@ class SIInstrInfo final : public AMDGPUInstrInfo {
bool hasModifiersSet(const MachineInstr &MI,
unsigned OpName) const;

bool verifyInstruction(const MachineInstr *MI,
bool verifyInstruction(const MachineInstr &MI,
StringRef &ErrInfo) const override;

static unsigned getVALUOp(const MachineInstr &MI);
Expand Down Expand Up @@ -428,11 +421,11 @@ class SIInstrInfo final : public AMDGPUInstrInfo {
///
/// If the operand being legalized is a register, then a COPY will be used
/// instead of MOV.
void legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const;
void legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const;

/// \brief Check if \p MO is a legal operand if it was the \p OpIdx Operand
/// for \p MI.
bool isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
bool isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
const MachineOperand *MO = nullptr) const;

/// \brief Check if \p MO would be a valid operand for the given operand
Expand All @@ -450,23 +443,23 @@ class SIInstrInfo final : public AMDGPUInstrInfo {

/// \brief Legalize operands in \p MI by either commuting it or inserting a
/// copy of src1.
void legalizeOperandsVOP2(MachineRegisterInfo &MRI, MachineInstr *MI) const;
void legalizeOperandsVOP2(MachineRegisterInfo &MRI, MachineInstr &MI) const;

/// \brief Fix operands in \p MI to satisfy constant bus requirements.
void legalizeOperandsVOP3(MachineRegisterInfo &MRI, MachineInstr *MI) const;
void legalizeOperandsVOP3(MachineRegisterInfo &MRI, MachineInstr &MI) const;

/// Copy a value from a VGPR (\p SrcReg) to SGPR. This function can only
/// be used when it is know that the value in SrcReg is same across all
/// threads in the wave.
/// \returns The SGPR register that \p SrcReg was copied to.
unsigned readlaneVGPRToSGPR(unsigned SrcReg, MachineInstr *UseMI,
MachineRegisterInfo &MRI) const;
unsigned readlaneVGPRToSGPR(unsigned SrcReg, MachineInstr &UseMI,
MachineRegisterInfo &MRI) const;

void legalizeOperandsSMRD(MachineRegisterInfo &MRI, MachineInstr *MI) const;
void legalizeOperandsSMRD(MachineRegisterInfo &MRI, MachineInstr &MI) const;

/// \brief Legalize all operands in this instruction. This function may
/// create new instruction and insert them before \p MI.
void legalizeOperands(MachineInstr *MI) const;
void legalizeOperands(MachineInstr &MI) const;

/// \brief Replace this instruction's opcode with the equivalent VALU
/// opcode. This function will also move the users of \p MI to the
Expand Down Expand Up @@ -505,8 +498,8 @@ class SIInstrInfo final : public AMDGPUInstrInfo {
uint64_t getDefaultRsrcDataFormat() const;
uint64_t getScratchRsrcWords23() const;

bool isLowLatencyInstruction(const MachineInstr *MI) const;
bool isHighLatencyInstruction(const MachineInstr *MI) const;
bool isLowLatencyInstruction(const MachineInstr &MI) const;
bool isHighLatencyInstruction(const MachineInstr &MI) const;

/// \brief Return the descriptor of the target-specific machine instruction
/// that corresponds to the specified pseudo or native opcode.
Expand Down
14 changes: 7 additions & 7 deletions llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1694,7 +1694,7 @@ void SIScheduleDAGMI::moveLowLatencies() {

for (SDep& PredDep : SU->Preds) {
SUnit *Pred = PredDep.getSUnit();
if (SITII->isLowLatencyInstruction(Pred->getInstr())) {
if (SITII->isLowLatencyInstruction(*Pred->getInstr())) {
IsLowLatencyUser = true;
}
if (Pred->NodeNum >= DAGSize)
Expand All @@ -1704,7 +1704,7 @@ void SIScheduleDAGMI::moveLowLatencies() {
MinPos = PredPos + 1;
}

if (SITII->isLowLatencyInstruction(SU->getInstr())) {
if (SITII->isLowLatencyInstruction(*SU->getInstr())) {
unsigned BestPos = LastLowLatencyUser + 1;
if ((int)BestPos <= LastLowLatencyPos)
BestPos = LastLowLatencyPos + 1;
Expand All @@ -1729,7 +1729,7 @@ void SIScheduleDAGMI::moveLowLatencies() {
bool CopyForLowLat = false;
for (SDep& SuccDep : SU->Succs) {
SUnit *Succ = SuccDep.getSUnit();
if (SITII->isLowLatencyInstruction(Succ->getInstr())) {
if (SITII->isLowLatencyInstruction(*Succ->getInstr())) {
CopyForLowLat = true;
}
}
Expand Down Expand Up @@ -1814,12 +1814,12 @@ void SIScheduleDAGMI::schedule()
SUnit *SU = &SUnits[i];
unsigned BaseLatReg;
int64_t OffLatReg;
if (SITII->isLowLatencyInstruction(SU->getInstr())) {
if (SITII->isLowLatencyInstruction(*SU->getInstr())) {
IsLowLatencySU[i] = 1;
if (SITII->getMemOpBaseRegImmOfs(SU->getInstr(), BaseLatReg,
OffLatReg, TRI))
if (SITII->getMemOpBaseRegImmOfs(*SU->getInstr(), BaseLatReg, OffLatReg,
TRI))
LowLatencyOffset[i] = OffLatReg;
} else if (SITII->isHighLatencyInstruction(SU->getInstr()))
} else if (SITII->isHighLatencyInstruction(*SU->getInstr()))
IsHighLatencySU[i] = 1;
}

Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -651,7 +651,7 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
default: {
int64_t Offset = FrameInfo->getObjectOffset(Index);
FIOp.ChangeToImmediate(Offset);
if (!TII->isImmOperandLegal(MI, FIOperandNum, FIOp)) {
if (!TII->isImmOperandLegal(*MI, FIOperandNum, FIOp)) {
unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
BuildMI(*MBB, MI, MI->getDebugLoc(),
TII->get(AMDGPU::V_MOV_B32_e32), TmpReg)
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -172,7 +172,7 @@ static void foldImmediates(MachineInstr &MI, const SIInstrInfo *TII,
}

// We have failed to fold src0, so commute the instruction and try again.
if (TryToCommute && MI.isCommutable() && TII->commuteInstruction(&MI))
if (TryToCommute && MI.isCommutable() && TII->commuteInstruction(MI))
foldImmediates(MI, TII, MRI, false);

}
Expand Down Expand Up @@ -312,7 +312,7 @@ bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) {
if (!canShrink(MI, TII, TRI, MRI)) {
// Try commuting the instruction and see if that enables us to shrink
// it.
if (!MI.isCommutable() || !TII->commuteInstruction(&MI) ||
if (!MI.isCommutable() || !TII->commuteInstruction(MI) ||
!canShrink(MI, TII, TRI, MRI))
continue;
}
Expand Down
985 changes: 501 additions & 484 deletions llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
View file

Large diffs are not rendered by default.

80 changes: 43 additions & 37 deletions llvm/lib/Target/ARM/ARMBaseInstrInfo.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -92,8 +92,7 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
/// non-commutable pair of operand indices OpIdx1 and OpIdx2.
/// Even though the instruction is commutable, the method may still
/// fail to commute the operands, null pointer is returned in such cases.
MachineInstr *commuteInstructionImpl(MachineInstr *MI,
bool NewMI,
MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
unsigned OpIdx1,
unsigned OpIdx2) const override;

Expand All @@ -106,7 +105,7 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;

MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
MachineBasicBlock::iterator &MBBI,
MachineInstr &MI,
LiveVariables *LV) const override;

virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0;
Expand Down Expand Up @@ -155,15 +154,15 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {

/// GetInstSize - Returns the size of the specified MachineInstr.
///
virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
virtual unsigned GetInstSizeInBytes(const MachineInstr &MI) const;

unsigned isLoadFromStackSlot(const MachineInstr *MI,
unsigned isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex) const override;
unsigned isStoreToStackSlot(const MachineInstr *MI,
unsigned isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex) const override;
unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
int &FrameIndex) const override;
unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
int &FrameIndex) const override;

void copyToCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
Expand All @@ -189,21 +188,21 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const override;

bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
bool expandPostRAPseudo(MachineInstr &MI) const override;

void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SubIdx,
const MachineInstr *Orig,
const MachineInstr &Orig,
const TargetRegisterInfo &TRI) const override;

MachineInstr *duplicate(MachineInstr *Orig,
MachineInstr *duplicate(MachineInstr &Orig,
MachineFunction &MF) const override;

const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
unsigned SubIdx, unsigned State,
const TargetRegisterInfo *TRI) const;

bool produceSameValue(const MachineInstr *MI0, const MachineInstr *MI1,
bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1,
const MachineRegisterInfo *MRI) const override;

/// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
Expand All @@ -226,7 +225,7 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
int64_t Offset1, int64_t Offset2,
unsigned NumLoads) const override;

bool isSchedulingBoundary(const MachineInstr *MI,
bool isSchedulingBoundary(const MachineInstr &MI,
const MachineBasicBlock *MBB,
const MachineFunction &MF) const override;

Expand All @@ -251,58 +250,58 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
/// in SrcReg and SrcReg2 if having two register operands, and the value it
/// compares against in CmpValue. Return true if the comparison instruction
/// can be analyzed.
bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
unsigned &SrcReg2, int &CmpMask,
int &CmpValue) const override;

/// optimizeCompareInstr - Convert the instruction to set the zero flag so
/// that we can remove a "comparison with zero"; Remove a redundant CMP
/// instruction if the flags can be updated in the same way by an earlier
/// instruction such as SUB.
bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
unsigned SrcReg2, int CmpMask, int CmpValue,
const MachineRegisterInfo *MRI) const override;

bool analyzeSelect(const MachineInstr *MI,
SmallVectorImpl<MachineOperand> &Cond,
unsigned &TrueOp, unsigned &FalseOp,
bool &Optimizable) const override;
bool analyzeSelect(const MachineInstr &MI,
SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp,
unsigned &FalseOp, bool &Optimizable) const override;

MachineInstr *optimizeSelect(MachineInstr *MI,
MachineInstr *optimizeSelect(MachineInstr &MI,
SmallPtrSetImpl<MachineInstr *> &SeenMIs,
bool) const override;

/// FoldImmediate - 'Reg' is known to be defined by a move immediate
/// instruction, try to fold the immediate into the use instruction.
bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
unsigned Reg, MachineRegisterInfo *MRI) const override;
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg,
MachineRegisterInfo *MRI) const override;

unsigned getNumMicroOps(const InstrItineraryData *ItinData,
const MachineInstr *MI) const override;
const MachineInstr &MI) const override;

int getOperandLatency(const InstrItineraryData *ItinData,
const MachineInstr *DefMI, unsigned DefIdx,
const MachineInstr *UseMI,
const MachineInstr &DefMI, unsigned DefIdx,
const MachineInstr &UseMI,
unsigned UseIdx) const override;
int getOperandLatency(const InstrItineraryData *ItinData,
SDNode *DefNode, unsigned DefIdx,
SDNode *UseNode, unsigned UseIdx) const override;

/// VFP/NEON execution domains.
std::pair<uint16_t, uint16_t>
getExecutionDomain(const MachineInstr *MI) const override;
void setExecutionDomain(MachineInstr *MI, unsigned Domain) const override;
getExecutionDomain(const MachineInstr &MI) const override;
void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override;

unsigned getPartialRegUpdateClearance(const MachineInstr*, unsigned,
const TargetRegisterInfo*) const override;
void breakPartialRegDependency(MachineBasicBlock::iterator, unsigned,
unsigned
getPartialRegUpdateClearance(const MachineInstr &, unsigned,
const TargetRegisterInfo *) const override;
void breakPartialRegDependency(MachineInstr &, unsigned,
const TargetRegisterInfo *TRI) const override;

/// Get the number of addresses by LDM or VLDM or zero for unknown.
unsigned getNumLDMAddresses(const MachineInstr *MI) const;
unsigned getNumLDMAddresses(const MachineInstr &MI) const;

private:
unsigned getInstBundleLength(const MachineInstr *MI) const;
unsigned getInstBundleLength(const MachineInstr &MI) const;

int getVLDMDefCycle(const InstrItineraryData *ItinData,
const MCInstrDesc &DefMCID,
Expand All @@ -326,26 +325,33 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
const MCInstrDesc &UseMCID,
unsigned UseIdx, unsigned UseAlign) const;

int getOperandLatencyImpl(const InstrItineraryData *ItinData,
const MachineInstr &DefMI, unsigned DefIdx,
const MCInstrDesc &DefMCID, unsigned DefAdj,
const MachineOperand &DefMO, unsigned Reg,
const MachineInstr &UseMI, unsigned UseIdx,
const MCInstrDesc &UseMCID, unsigned UseAdj) const;

unsigned getPredicationCost(const MachineInstr &MI) const override;

unsigned getInstrLatency(const InstrItineraryData *ItinData,
const MachineInstr *MI,
const MachineInstr &MI,
unsigned *PredCost = nullptr) const override;

int getInstrLatency(const InstrItineraryData *ItinData,
SDNode *Node) const override;

bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
const MachineRegisterInfo *MRI,
const MachineInstr *DefMI, unsigned DefIdx,
const MachineInstr *UseMI,
const MachineInstr &DefMI, unsigned DefIdx,
const MachineInstr &UseMI,
unsigned UseIdx) const override;
bool hasLowDefLatency(const TargetSchedModel &SchedModel,
const MachineInstr *DefMI,
const MachineInstr &DefMI,
unsigned DefIdx) const override;

/// verifyInstruction - Perform target specific instruction verification.
bool verifyInstruction(const MachineInstr *MI,
bool verifyInstruction(const MachineInstr &MI,
StringRef &ErrInfo) const override;

virtual void expandLoadStackGuard(MachineBasicBlock::iterator MI) const = 0;
Expand Down
22 changes: 11 additions & 11 deletions llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -919,7 +919,7 @@ void ARMConstantIslands::computeBlockSize(MachineBasicBlock *MBB) {

for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E;
++I) {
BBI.Size += TII->GetInstSizeInBytes(I);
BBI.Size += TII->GetInstSizeInBytes(*I);
// For inline asm, GetInstSizeInBytes returns a conservative estimate.
// The actual size may be smaller, but still a multiple of the instr size.
if (I->isInlineAsm())
Expand Down Expand Up @@ -950,7 +950,7 @@ unsigned ARMConstantIslands::getOffsetOf(MachineInstr *MI) const {
// Sum instructions before MI in MBB.
for (MachineBasicBlock::iterator I = MBB->begin(); &*I != MI; ++I) {
assert(I != MBB->end() && "Didn't find MI in its own basic block?");
Offset += TII->GetInstSizeInBytes(I);
Offset += TII->GetInstSizeInBytes(*I);
}
return Offset;
}
Expand Down Expand Up @@ -1458,7 +1458,7 @@ void ARMConstantIslands::createNewWater(unsigned CPUserIndex,
// iterates at least once.
BaseInsertOffset =
std::max(UserBBI.postOffset() - UPad - 8,
UserOffset + TII->GetInstSizeInBytes(UserMI) + 1);
UserOffset + TII->GetInstSizeInBytes(*UserMI) + 1);
DEBUG(dbgs() << format("Move inside block: %#x\n", BaseInsertOffset));
}
unsigned EndInsertOffset = BaseInsertOffset + 4 + UPad +
Expand All @@ -1468,9 +1468,9 @@ void ARMConstantIslands::createNewWater(unsigned CPUserIndex,
unsigned CPUIndex = CPUserIndex+1;
unsigned NumCPUsers = CPUsers.size();
MachineInstr *LastIT = nullptr;
for (unsigned Offset = UserOffset+TII->GetInstSizeInBytes(UserMI);
for (unsigned Offset = UserOffset + TII->GetInstSizeInBytes(*UserMI);
Offset < BaseInsertOffset;
Offset += TII->GetInstSizeInBytes(MI), MI = std::next(MI)) {
Offset += TII->GetInstSizeInBytes(*MI), MI = std::next(MI)) {
assert(MI != UserMBB->end() && "Fell off end of block");
if (CPUIndex < NumCPUsers && CPUsers[CPUIndex].MI == MI) {
CPUser &U = CPUsers[CPUIndex];
Expand Down Expand Up @@ -1771,7 +1771,7 @@ ARMConstantIslands::fixupConditionalBr(ImmBranch &Br) {
splitBlockBeforeInstr(MI);
// No need for the branch to the next block. We're adding an unconditional
// branch to the destination.
int delta = TII->GetInstSizeInBytes(&MBB->back());
int delta = TII->GetInstSizeInBytes(MBB->back());
BBInfo[MBB->getNumber()].Size -= delta;
MBB->back().eraseFromParent();
// BBInfo[SplitBB].Offset is wrong temporarily, fixed below
Expand All @@ -1787,18 +1787,18 @@ ARMConstantIslands::fixupConditionalBr(ImmBranch &Br) {
BuildMI(MBB, DebugLoc(), TII->get(MI->getOpcode()))
.addMBB(NextBB).addImm(CC).addReg(CCReg);
Br.MI = &MBB->back();
BBInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(&MBB->back());
BBInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(MBB->back());
if (isThumb)
BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB)
.addImm(ARMCC::AL).addReg(0);
else
BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB);
BBInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(&MBB->back());
BBInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(MBB->back());
unsigned MaxDisp = getUnconditionalBrDisp(Br.UncondBr);
ImmBranches.push_back(ImmBranch(&MBB->back(), MaxDisp, false, Br.UncondBr));

// Remove the old conditional branch. It may or may not still be in MBB.
BBInfo[MI->getParent()->getNumber()].Size -= TII->GetInstSizeInBytes(MI);
BBInfo[MI->getParent()->getNumber()].Size -= TII->GetInstSizeInBytes(*MI);
MI->eraseFromParent();
adjustBBOffsetsAfter(MBB);
return true;
Expand Down Expand Up @@ -2211,8 +2211,8 @@ bool ARMConstantIslands::optimizeThumb2JumpTables() {
}
}

unsigned NewSize = TII->GetInstSizeInBytes(NewJTMI);
unsigned OrigSize = TII->GetInstSizeInBytes(MI);
unsigned NewSize = TII->GetInstSizeInBytes(*NewJTMI);
unsigned OrigSize = TII->GetInstSizeInBytes(*MI);
MI->eraseFromParent();

int Delta = OrigSize - NewSize + DeadSize;
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/ARM/ARMFrameLowering.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1360,7 +1360,7 @@ static unsigned GetFunctionSizeInBytes(const MachineFunction &MF,
unsigned FnSize = 0;
for (auto &MBB : MF) {
for (auto &MI : MBB)
FnSize += TII.GetInstSizeInBytes(&MI);
FnSize += TII.GetInstSizeInBytes(MI);
}
return FnSize;
}
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/ARM/ARMISelLowering.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2053,7 +2053,7 @@ bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
if (!Def)
return false;
if (!Flags.isByVal()) {
if (!TII->isLoadFromStackSlot(Def, FI))
if (!TII->isLoadFromStackSlot(*Def, FI))
return false;
} else {
return false;
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/ARM/ARMScheduleA9.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2025,12 +2025,12 @@ def A9WriteAdr#NumAddr : WriteSequence<[A9WriteAdr], NumAddr>;

// Define a predicate to select the LDM based on number of memory addresses.
def A9LMAdr#NumAddr#Pred :
SchedPredicate<"(TII->getNumLDMAddresses(MI)+1)/2 == "#NumAddr>;
SchedPredicate<"(TII->getNumLDMAddresses(*MI)+1)/2 == "#NumAddr>;

} // foreach NumAddr

// Fall-back for unknown LDMs.
def A9LMUnknownPred : SchedPredicate<"TII->getNumLDMAddresses(MI) == 0">;
def A9LMUnknownPred : SchedPredicate<"TII->getNumLDMAddresses(*MI) == 0">;

// LDM/VLDM/VLDn address generation latency & resources.
// Dynamically select the A9WriteAdrN sequence using a predicate.
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/ARM/ARMScheduleSwift.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -374,7 +374,7 @@ let SchedModel = SwiftModel in {
}
// Predicate.
foreach NumAddr = 1-16 in {
def SwiftLMAddr#NumAddr#Pred : SchedPredicate<"TII->getNumLDMAddresses(MI) == "#NumAddr>;
def SwiftLMAddr#NumAddr#Pred : SchedPredicate<"TII->getNumLDMAddresses(*MI) == "#NumAddr>;
}
def SwiftWriteLDMAddrNoWB : SchedWriteRes<[SwiftUnitP01]> { let Latency = 0; }
def SwiftWriteLDMAddrWB : SchedWriteRes<[SwiftUnitP01, SwiftUnitP01]>;
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -718,19 +718,19 @@ Thumb2SizeReduce::ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
if (Reg1 != Reg0)
return false;
// Try to commute the operands to make it a 2-address instruction.
MachineInstr *CommutedMI = TII->commuteInstruction(MI);
MachineInstr *CommutedMI = TII->commuteInstruction(*MI);
if (!CommutedMI)
return false;
}
} else if (Reg0 != Reg1) {
// Try to commute the operands to make it a 2-address instruction.
unsigned CommOpIdx1 = 1;
unsigned CommOpIdx2 = TargetInstrInfo::CommuteAnyOperandIndex;
if (!TII->findCommutedOpIndices(MI, CommOpIdx1, CommOpIdx2) ||
if (!TII->findCommutedOpIndices(*MI, CommOpIdx1, CommOpIdx2) ||
MI->getOperand(CommOpIdx2).getReg() != Reg0)
return false;
MachineInstr *CommutedMI =
TII->commuteInstruction(MI, false, CommOpIdx1, CommOpIdx2);
TII->commuteInstruction(*MI, false, CommOpIdx1, CommOpIdx2);
if (!CommutedMI)
return false;
}
Expand Down
24 changes: 12 additions & 12 deletions llvm/lib/Target/AVR/AVRInstrInfo.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -60,15 +60,15 @@ void AVRInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
.addReg(SrcReg, getKillRegState(KillSrc));
}

unsigned AVRInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
unsigned AVRInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex) const {
switch (MI->getOpcode()) {
switch (MI.getOpcode()) {
case AVR::LDDRdPtrQ:
case AVR::LDDWRdYQ: { //:FIXME: remove this once PR13375 gets fixed
if ((MI->getOperand(1).isFI()) && (MI->getOperand(2).isImm()) &&
(MI->getOperand(2).getImm() == 0)) {
FrameIndex = MI->getOperand(1).getIndex();
return MI->getOperand(0).getReg();
if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
MI.getOperand(2).getImm() == 0) {
FrameIndex = MI.getOperand(1).getIndex();
return MI.getOperand(0).getReg();
}
break;
}
Expand All @@ -79,15 +79,15 @@ unsigned AVRInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
return 0;
}

unsigned AVRInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
unsigned AVRInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex) const {
switch (MI->getOpcode()) {
switch (MI.getOpcode()) {
case AVR::STDPtrQRr:
case AVR::STDWPtrQRr: {
if ((MI->getOperand(0).isFI()) && (MI->getOperand(1).isImm()) &&
(MI->getOperand(1).getImm() == 0)) {
FrameIndex = MI->getOperand(0).getIndex();
return MI->getOperand(2).getReg();
if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
MI.getOperand(1).getImm() == 0) {
FrameIndex = MI.getOperand(0).getIndex();
return MI.getOperand(2).getReg();
}
break;
}
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/AVR/AVRInstrInfo.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -84,9 +84,9 @@ class AVRInstrInfo : public AVRGenInstrInfo {
MachineBasicBlock::iterator MI, unsigned DestReg,
int FrameIndex, const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const override;
unsigned isLoadFromStackSlot(const MachineInstr *MI,
unsigned isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex) const override;
unsigned isStoreToStackSlot(const MachineInstr *MI,
unsigned isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex) const override;

// Branch analysis.
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -823,7 +823,7 @@ bool HexagonExpandCondsets::canMoveMemTo(MachineInstr *TheI, MachineInstr *ToI,
bool IsLoad = TheI->mayLoad(), IsStore = TheI->mayStore();
if (!IsLoad && !IsStore)
return true;
if (HII->areMemAccessesTriviallyDisjoint(TheI, ToI))
if (HII->areMemAccessesTriviallyDisjoint(*TheI, *ToI))
return true;
if (TheI->hasUnmodeledSideEffects())
return false;
Expand Down
10 changes: 5 additions & 5 deletions llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1926,8 +1926,8 @@ void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF,

for (auto &In : B) {
int LFI, SFI;
bool Load = HII.isLoadFromStackSlot(&In, LFI) && !HII.isPredicated(In);
bool Store = HII.isStoreToStackSlot(&In, SFI) && !HII.isPredicated(In);
bool Load = HII.isLoadFromStackSlot(In, LFI) && !HII.isPredicated(In);
bool Store = HII.isStoreToStackSlot(In, SFI) && !HII.isPredicated(In);
if (Load && Store) {
// If it's both a load and a store, then we won't handle it.
BadFIs.insert(LFI);
Expand Down Expand Up @@ -2146,7 +2146,7 @@ void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF,
MachineInstr *MI = &*It;
NextIt = std::next(It);
int TFI;
if (!HII.isLoadFromStackSlot(MI, TFI) || TFI != FI)
if (!HII.isLoadFromStackSlot(*MI, TFI) || TFI != FI)
continue;
unsigned DstR = MI->getOperand(0).getReg();
assert(MI->getOperand(0).getSubReg() == 0);
Expand All @@ -2156,9 +2156,9 @@ void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF,
unsigned MemSize = (1U << (HII.getMemAccessSize(MI) - 1));
assert(HII.getAddrMode(MI) == HexagonII::BaseImmOffset);
unsigned CopyOpc = TargetOpcode::COPY;
if (HII.isSignExtendingLoad(MI))
if (HII.isSignExtendingLoad(*MI))
CopyOpc = (MemSize == 1) ? Hexagon::A2_sxtb : Hexagon::A2_sxth;
else if (HII.isZeroExtendingLoad(MI))
else if (HII.isZeroExtendingLoad(*MI))
CopyOpc = (MemSize == 1) ? Hexagon::A2_zxtb : Hexagon::A2_zxth;
CopyOut = BuildMI(B, It, DL, HII.get(CopyOpc), DstR)
.addReg(FoundR, getKillRegState(MI == EI));
Expand Down
10 changes: 5 additions & 5 deletions llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -450,8 +450,8 @@ bool HexagonHardwareLoops::findInductionRegister(MachineLoop *L,

unsigned CmpReg1 = 0, CmpReg2 = 0;
int CmpImm = 0, CmpMask = 0;
bool CmpAnalyzed = TII->analyzeCompare(PredI, CmpReg1, CmpReg2,
CmpMask, CmpImm);
bool CmpAnalyzed =
TII->analyzeCompare(*PredI, CmpReg1, CmpReg2, CmpMask, CmpImm);
// Fail if the compare was not analyzed, or it's not comparing a register
// with an immediate value. Not checking the mask here, since we handle
// the individual compare opcodes (including A4_cmpb*) later on.
Expand Down Expand Up @@ -620,8 +620,8 @@ CountValue *HexagonHardwareLoops::getLoopTripCount(MachineLoop *L,

unsigned CmpReg1 = 0, CmpReg2 = 0;
int Mask = 0, ImmValue = 0;
bool AnalyzedCmp = TII->analyzeCompare(CondI, CmpReg1, CmpReg2,
Mask, ImmValue);
bool AnalyzedCmp =
TII->analyzeCompare(*CondI, CmpReg1, CmpReg2, Mask, ImmValue);
if (!AnalyzedCmp)
return nullptr;

Expand Down Expand Up @@ -1420,7 +1420,7 @@ bool HexagonHardwareLoops::loopCountMayWrapOrUnderFlow(
unsigned CmpReg1 = 0, CmpReg2 = 0;
int CmpMask = 0, CmpValue = 0;

if (!TII->analyzeCompare(MI, CmpReg1, CmpReg2, CmpMask, CmpValue))
if (!TII->analyzeCompare(*MI, CmpReg1, CmpReg2, CmpMask, CmpValue))
continue;

MachineBasicBlock *TBB = 0, *FBB = 0;
Expand Down
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