24 changes: 9 additions & 15 deletions llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h
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Expand Up @@ -72,16 +72,6 @@ class HexagonCVIResource : public HexagonResource {
using UnitsAndLanes = std::pair<unsigned, unsigned>;

private:
// Available HVX slots.
enum {
CVI_NONE = 0,
CVI_XLANE = 1 << 0,
CVI_SHIFT = 1 << 1,
CVI_MPY0 = 1 << 2,
CVI_MPY1 = 1 << 3,
CVI_ZW = 1 << 4
};

// Count of adjacent slots that the insn requires to be executed.
unsigned Lanes;
// Flag whether the insn is a load or a store.
Expand Down Expand Up @@ -177,21 +167,23 @@ class HexagonShuffler {
bool ReportErrors;
bool CheckFailure;
std::vector<std::pair<SMLoc, std::string>> AppliedRestrictions;
bool applySlotRestrictions(HexagonPacketSummary const &Summary);

bool applySlotRestrictions(HexagonPacketSummary const &Summary,
const bool DoShuffle);
void restrictSlot1AOK(HexagonPacketSummary const &Summary);
void restrictNoSlot1Store(HexagonPacketSummary const &Summary);
void restrictNoSlot1();
bool restrictStoreLoadOrder(HexagonPacketSummary const &Summary);
void restrictBranchOrder(HexagonPacketSummary const &Summary);
void restrictPreferSlot3(HexagonPacketSummary const &Summary);
void restrictPreferSlot3(HexagonPacketSummary const &Summary,
const bool DoShuffle);
void permitNonSlot();

Optional<HexagonPacket> tryAuction(HexagonPacketSummary const &Summary) const;
Optional<HexagonPacket> tryAuction(HexagonPacketSummary const &Summary);

HexagonPacketSummary GetPacketSummary();
bool ValidPacketMemoryOps(HexagonPacketSummary const &Summary) const;
bool ValidResourceUsage(HexagonPacketSummary const &Summary);
bool validPacketInsts() const;

public:
using iterator = HexagonPacket::iterator;
Expand All @@ -205,7 +197,7 @@ class HexagonShuffler {
// Reset to initial state.
void reset();
// Check if the bundle may be validly shuffled.
bool check();
bool check(const bool RequireShuffle = true);
// Reorder the insn handles in the bundle.
bool shuffle();

Expand Down Expand Up @@ -242,6 +234,8 @@ class HexagonShuffler {

// Return the error code for the last check or shuffling of the bundle.
void reportError(Twine const &Msg);
void reportResourceError(HexagonPacketSummary const &Summary, StringRef Err);
void reportResourceUsage(HexagonPacketSummary const &Summary);
};

} // end namespace llvm
Expand Down
4 changes: 4 additions & 0 deletions llvm/test/MC/Hexagon/PacketRules/bundle_option.s
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@@ -0,0 +1,4 @@
# RUN: not llvm-mc -arch=hexagon -filetype=asm %s 2>%t; FileCheck %s <%t

{ nop }:junk
# CHECK: 3:9: error: 'junk' is not a valid bundle option
10 changes: 10 additions & 0 deletions llvm/test/MC/Hexagon/PacketRules/cof_max1.s
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@@ -0,0 +1,10 @@
# RUN: not llvm-mc -triple=hexagon -filetype=asm %s 2>&1 | FileCheck %s

{ jumpr r0
jumpr r0 }
# CHECK: 3:3: error: Instruction may not be in a packet with other branches

{ jump unknown
if (p0) jump unknown }
# CHECK: 7:3: error: Instruction may not be the first branch in packet

46 changes: 46 additions & 0 deletions llvm/test/MC/Hexagon/PacketRules/newvalue_producers.s
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@@ -0,0 +1,46 @@
# RUN: not llvm-mc -arch=hexagon -mhvx -filetype=asm %s 2>%t; FileCheck %s <%t

{ r0=memw(r1=##0)
memw(r0)=r1.new }
# CHECK: 3:3: note: Absolute-set registers cannot be a new-value producer
# CHECK: 4:3: error: Instruction does not have a valid new register producer

{ r1:0=r1:0
memw(r0)=r0.new }
# CHECK: 8:3: note: Double registers cannot be new-value producers
# CHECK: 9:3: error: Instruction does not have a valid new register producer

{ r1=memw(r0++m0)
memw(r0)=r0.new }
# CHECK: 13:3: note: Auto-increment registers cannot be a new-value producer
# CHECK: 14:3: error: Instruction does not have a valid new register producer

{ r0=sfadd(r0,r0)
if (cmp.eq(r0.new,r0)) jump:t 0x0 }
# CHECK: 18:3: note: FPU instructions cannot be new-value producers for jumps
# CHECK: 19:3: error: Instruction does not have a valid new register producer

{ v0=vmem(r0++m0)
memw(r0)=r0.new }
# CHECK: 23:3: note: Auto-increment registers cannot be a new-value producer
# CHECK: 24:3: error: Instruction does not have a valid new register producer

{ if (p0) r0=r0
if (!p0) memw(r0)=r0.new }
# CHECK: 28:3: note: Register producer has the opposite predicate sense as consumer
# CHECK: 29:3: error: Instruction does not have a valid new register producer

{ if (p0) r0=r0
memw(r0)=r0.new }
# CHECK: 33:3: note: Register producer is predicated and consumer is unconditional
# CHECK: 34:3: error: Instruction does not have a valid new register producer

{ if (p0) r0=r0
if (cmp.eq(r0.new,r0)) jump:t 0x0 }
# CHECK: 38:3: note: Register producer is predicated and consumer is unconditional
# CHECK: 39:3: error: Instruction does not have a valid new register producer

{ r0=memw(r1=##0)
if (p0) memw(r0)=r1.new }
# CHECK: 43:3: note: Absolute-set registers cannot be a new-value producer
# CHECK: 44:3: error: Instruction does not have a valid new register producer
41 changes: 41 additions & 0 deletions llvm/test/MC/Hexagon/PacketRules/newvalue_producers_pass.s
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# RUN: llvm-mc -arch=hexagon -mhvx -mcpu=hexagonv65 -filetype=obj %s | llvm-objdump --mattr=+hvxv65 -d - | FileCheck %s

{ r0=r0
memw(r0)=r0.new }
# CHECK: { r0 = r0
# CHECK: memw(r0+#0) = r0.new }

{ v0=v0
vmem(r0)=v0.new }
# CHECK: { v0 = v0
# CHECK: vmem(r0+#0) = v0.new }

{ v1:0=v1:0
vmem(r0)=v0.new }
# CHECK: { v1:0 = vcombine(v1,v0)
# CHECK: vmem(r0+#0) = v0.new }

{ r0=r0
if (cmp.eq(r0.new,r0)) jump:t 0x0 }
# CHECK: { r0 = r0
# CHECK: if (cmp.eq(r0.new,r0)) jump:t 0x18

{ vtmp.h=vgather(r0,m0,v0.h).h
vmem(r0)=vtmp.new }
# CHECK: { vtmp.h = vgather(r0,m0,v0.h).h
# CHECK: vmem(r0+#0) = vtmp.new }

{ if (p0) r0=r0
if (p0) memw(r0)=r0.new }
# CHECK: { if (p0) r0 = add(r0,#0)
# CHECK: if (p0) memw(r0+#0) = r0.new }

{ r0=r0
if (p0) memw(r0)=r0.new }
# CHECK: { r0 = r0
# CHECK: if (p0) memw(r0+#0) = r0.new }

{ r0=r0
if (!p0) memw(r0)=r0.new }
# CHECK: { r0 = r0
# CHECK: if (!p0) memw(r0+#0) = r0.new }
7 changes: 4 additions & 3 deletions llvm/test/MC/Hexagon/PacketRules/restrict_ax.s
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@@ -1,4 +1,5 @@
# RUN: not llvm-mc -arch=hexagon -filetype=asm %s 2>%t; FileCheck %s <%t

{ r0=memw_locked(r0)
r1=-mpyi(r0,#0) }
# RUN: not llvm-mc -arch=hexagon -filetype=asm %s 2>%t; FileCheck %s --check-prefix=CHECK00 <%t
# CHECK00: 1:3: error: Instruction can only be in a packet with ALU or non-FPU XTYPE instructions
r1=sfadd(r0,r0) }
# CHECK: 3:3: error: Instruction can only be in a packet with ALU or non-FPU XTYPE instructions
15 changes: 15 additions & 0 deletions llvm/test/MC/Hexagon/PacketRules/restrict_no_slot1_store.s
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@@ -0,0 +1,15 @@
# RUN: not llvm-mc -triple=hexagon -filetype=asm %s 2>&1 | FileCheck %s

{ r0=sub(#1,r0)
r1=sub(#1, r0)
memw(r0)=r0
if (p3) dealloc_return }


# CHECK: note: Instruction can utilize slots: 0, 1, 2, 3
# CHECK: note: Instruction can utilize slots: 0, 1, 2, 3
# CHECK: note: Instruction can utilize slots: <None>
# CHECK: note: Instruction can utilize slots: 0
# CHECK: note: Instruction was restricted from being in slot 1
# CHECK: note: Instruction does not allow a store in slot 1
# CHECK: error: invalid instruction packet: slot error
11 changes: 11 additions & 0 deletions llvm/test/MC/Hexagon/PacketRules/restrict_no_slot1_store_pass.s
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@@ -0,0 +1,11 @@
# RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump -d - | FileCheck %s

{ r0=sub(#1,r0)
r1=sub(#1, r0)
r2=sub(#1, r0)
if (p3) dealloc_return }

# CHECK: { r0 = sub(#1,r0)
# CHECK: r1 = sub(#1,r0)
# CHECK: r2 = sub(#1,r0)
# CHECK: if (p3) dealloc_return }
11 changes: 11 additions & 0 deletions llvm/test/MC/Hexagon/PacketRules/restrict_slot1_aok_pass.s
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@@ -0,0 +1,11 @@
# RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump -d - | FileCheck %s

{ r0=sub(#1,r0)
r1=sub(#1, r0)
r2=sub(#1, r0)
dczeroa(r0) }

# CHECK: { r0 = sub(#1,r0)
# CHECK: r1 = sub(#1,r0)
# CHECK: r2 = sub(#1,r0)
# CHECK: dczeroa(r0) }