66 changes: 13 additions & 53 deletions llvm/test/CodeGen/AArch64/fastcc.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
; Without tailcallopt fastcc still means the caller cleans up the
; stack, so try to make sure this is respected.

define fastcc void @func_stack0() uwtable {
define fastcc void @func_stack0() {
; CHECK-LABEL: func_stack0:
; CHECK: sub sp, sp, #48
; CHECK: add x29, sp, #32
Expand Down Expand Up @@ -49,21 +49,15 @@ define fastcc void @func_stack0() uwtable {
ret void
; CHECK: ldp x29, x30, [sp, #32]
; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w30
; CHECK-NEXT: .cfi_restore w29
; CHECK-NEXT: ret


; CHECK-TAIL: ldp x29, x30, [sp, #32]
; CHECK-TAIL-NEXT: add sp, sp, #48
; CHECK-TAIL-NEXT: .cfi_def_cfa_offset 0
; CHECK-TAIL-NEXT: .cfi_restore w30
; CHECK-TAIL-NEXT: .cfi_restore w29
; CHECK-TAIL-NEXT: ret
}

define fastcc void @func_stack8([8 x i64], i32 %stacked) uwtable {
define fastcc void @func_stack8([8 x i64], i32 %stacked) {
; CHECK-LABEL: func_stack8:
; CHECK: sub sp, sp, #48
; CHECK: stp x29, x30, [sp, #32]
Expand Down Expand Up @@ -106,24 +100,17 @@ define fastcc void @func_stack8([8 x i64], i32 %stacked) uwtable {
; CHECK-TAIL-NOT: sub sp, sp

ret void
; CHECK-NEXT: .cfi_def_cfa wsp, 48
; CHECK-NEXT: ldp x29, x30, [sp, #32]
; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w30
; CHECK-NEXT: .cfi_restore w29
; CHECK: add sp, sp, #48
; CHECK-NEXT: ret


; CHECK-TAIL: ldp x29, x30, [sp, #32]
; CHECK-TAIL-NEXT: add sp, sp, #64
; CHECK-TAIL-NEXT: .cfi_def_cfa_offset -16
; CHECK-TAIL-NEXT: .cfi_restore w30
; CHECK-TAIL-NEXT: .cfi_restore w29
; CHECK-TAIL-NEXT: ret
}

define fastcc void @func_stack32([8 x i64], i128 %stacked0, i128 %stacked1) uwtable {
define fastcc void @func_stack32([8 x i64], i128 %stacked0, i128 %stacked1) {
; CHECK-LABEL: func_stack32:
; CHECK: add x29, sp, #32

Expand Down Expand Up @@ -159,42 +146,30 @@ define fastcc void @func_stack32([8 x i64], i128 %stacked0, i128 %stacked1) uwta
; CHECK-TAIL-NOT: sub sp, sp

ret void
; CHECK: .cfi_def_cfa wsp, 48
; CHECK-NEXT: ldp x29, x30, [sp, #32]
; CHECK: ldp x29, x30, [sp, #32]
; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w30
; CHECK-NEXT: .cfi_restore w29
; CHECK-NEXT: ret

; CHECK-TAIL: ldp x29, x30, [sp, #32]
; CHECK-TAIL-NEXT: add sp, sp, #80
; CHECK-TAIL-NEXT: .cfi_def_cfa_offset -32
; CHECK-TAIL-NEXT: .cfi_restore w30
; CHECK-TAIL-NEXT: .cfi_restore w29
; CHECK-TAIL-NEXT: ret
}

; Check that arg stack pop is done after callee-save restore when no frame pointer is used.
define fastcc void @func_stack32_leaf([8 x i64], i128 %stacked0, i128 %stacked1) uwtable {
define fastcc void @func_stack32_leaf([8 x i64], i128 %stacked0, i128 %stacked1) {
; CHECK-LABEL: func_stack32_leaf:
; CHECK: str x20, [sp, #-16]!
; CHECK: nop
; CHECK-NEXT: //NO_APP
; CHECK-NEXT: ldr x20, [sp], #16
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w20
; CHECK-NEXT: ret

; CHECK-TAIL-LABEL: func_stack32_leaf:
; CHECK-TAIL: str x20, [sp, #-16]!
; CHECK-TAIL: nop
; CHECK-TAIL-NEXT: //NO_APP
; CHECK-TAIL-NEXT: ldr x20, [sp], #16
; CHECK-TAIL-NEXT: .cfi_def_cfa_offset 0
; CHECK-TAIL-NEXT: add sp, sp, #32
; CHECK-TAIL-NEXT: .cfi_def_cfa_offset -32
; CHECK-TAIL-NEXT: .cfi_restore w20
; CHECK-TAIL-NEXT: add sp, sp, #32
; CHECK-TAIL-NEXT: ret

; CHECK-TAIL-RZ-LABEL: func_stack32_leaf:
Expand All @@ -203,10 +178,7 @@ define fastcc void @func_stack32_leaf([8 x i64], i128 %stacked0, i128 %stacked1)
; CHECK-TAIL-RZ: nop
; CHECK-TAIL-RZ-NEXT: //NO_APP
; CHECK-TAIL-RZ-NEXT: ldr x20, [sp], #16
; CHECK-TAIL-RZ-NEXT: .cfi_def_cfa_offset 0
; CHECK-TAIL-RZ-NEXT: add sp, sp, #32
; CHECK-TAIL-RZ-NEXT: .cfi_def_cfa_offset -32
; CHECK-TAIL-RZ-NEXT: .cfi_restore w20
; CHECK-TAIL-RZ-NEXT: add sp, sp, #32
; CHECK-TAIL-RZ-NEXT: ret

; Make sure there is a callee-save register to save/restore.
Expand All @@ -215,7 +187,7 @@ define fastcc void @func_stack32_leaf([8 x i64], i128 %stacked0, i128 %stacked1)
}

; Check that arg stack pop is done after callee-save restore when no frame pointer is used.
define fastcc void @func_stack32_leaf_local([8 x i64], i128 %stacked0, i128 %stacked1) uwtable {
define fastcc void @func_stack32_leaf_local([8 x i64], i128 %stacked0, i128 %stacked1) {
; CHECK-LABEL: func_stack32_leaf_local:
; CHECK: sub sp, sp, #32
; CHECK-NEXT: .cfi_def_cfa_offset 32
Expand All @@ -224,8 +196,6 @@ define fastcc void @func_stack32_leaf_local([8 x i64], i128 %stacked0, i128 %sta
; CHECK-NEXT: //NO_APP
; CHECK-NEXT: ldr x20, [sp, #16]
; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w20
; CHECK-NEXT: ret

; CHECK-TAIL-LABEL: func_stack32_leaf_local:
Expand All @@ -236,8 +206,6 @@ define fastcc void @func_stack32_leaf_local([8 x i64], i128 %stacked0, i128 %sta
; CHECK-TAIL-NEXT: //NO_APP
; CHECK-TAIL-NEXT: ldr x20, [sp, #16]
; CHECK-TAIL-NEXT: add sp, sp, #64
; CHECK-TAIL-NEXT: .cfi_def_cfa_offset -32
; CHECK-TAIL-NEXT: .cfi_restore w20
; CHECK-TAIL-NEXT: ret

; CHECK-TAIL-RZ-LABEL: func_stack32_leaf_local:
Expand All @@ -246,10 +214,7 @@ define fastcc void @func_stack32_leaf_local([8 x i64], i128 %stacked0, i128 %sta
; CHECK-TAIL-RZ: nop
; CHECK-TAIL-RZ-NEXT: //NO_APP
; CHECK-TAIL-RZ-NEXT: ldr x20, [sp], #16
; CHECK-TAIL-RZ-NEXT: .cfi_def_cfa_offset 0
; CHECK-TAIL-RZ-NEXT: add sp, sp, #32
; CHECK-TAIL-RZ-NEXT: .cfi_def_cfa_offset -32
; CHECK-TAIL-RZ-NEXT: .cfi_restore w20
; CHECK-TAIL-RZ-NEXT: add sp, sp, #32
; CHECK-TAIL-RZ-NEXT: ret

%val0 = alloca [2 x i64], align 8
Expand All @@ -260,24 +225,19 @@ define fastcc void @func_stack32_leaf_local([8 x i64], i128 %stacked0, i128 %sta
}

; Check that arg stack pop is done after callee-save restore when no frame pointer is used.
define fastcc void @func_stack32_leaf_local_nocs([8 x i64], i128 %stacked0, i128 %stacked1) uwtable {
define fastcc void @func_stack32_leaf_local_nocs([8 x i64], i128 %stacked0, i128 %stacked1) {
; CHECK-LABEL: func_stack32_leaf_local_nocs:
; CHECK: sub sp, sp, #16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: add sp, sp, #16
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK: add sp, sp, #16
; CHECK-NEXT: ret

; CHECK-TAIL-LABEL: func_stack32_leaf_local_nocs:
; CHECK-TAIL: sub sp, sp, #16
; CHECK-TAIL-NEXT: .cfi_def_cfa_offset 16
; CHECK-TAIL-NEXT: add sp, sp, #48
; CHECK-TAIL-NEXT: .cfi_def_cfa_offset -32
; CHECK-TAIL: add sp, sp, #48
; CHECK-TAIL-NEXT: ret

; CHECK-TAIL-RZ-LABEL: func_stack32_leaf_local_nocs:
; CHECK-TAIL-RZ: add sp, sp, #32
; CHECK-TAIL-RZ-NEXT: .cfi_def_cfa_offset -32
; CHECK-TAIL-RZ-NEXT: ret

%val0 = alloca [2 x i64], align 8
Expand Down
7 changes: 1 addition & 6 deletions llvm/test/CodeGen/AArch64/framelayout-sve-calleesaves-fix.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@
# RUN: llc -mattr=+sve -mtriple=aarch64-none-linux-gnu -start-before=prologepilog %s -o - | FileCheck %s

--- |
define aarch64_sve_vector_pcs void @fix_restorepoint_p4() uwtable { entry: unreachable }
define aarch64_sve_vector_pcs void @fix_restorepoint_p4() { entry: unreachable }
; CHECK-LABEL: fix_restorepoint_p4:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
Expand All @@ -18,15 +18,10 @@
; CHECK-NEXT: // implicit-def: $z8
; CHECK-NEXT: // implicit-def: $p4
; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG
; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr z8, [sp, #1, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: .cfi_def_cfa wsp, 16
; CHECK-NEXT: .cfi_restore z8
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w29
; CHECK-NEXT: ret
...
name: fix_restorepoint_p4
Expand Down
293 changes: 15 additions & 278 deletions llvm/test/CodeGen/AArch64/framelayout-sve.mir
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Large diffs are not rendered by default.

8 changes: 1 addition & 7 deletions llvm/test/CodeGen/AArch64/framelayout-unaligned-fp.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@ target triple = "aarch64-unknown-linux-gnu"
@a = global i64 0, align 4


define i64 @b() uwtable {
define i64 @b() {
entry:
%call = tail call i64 @d()
%0 = alloca i8, i64 ptrtoint (i64 ()* @d to i64), align 16
Expand All @@ -33,15 +33,9 @@ entry:
; CHECK-NEXT: add x29, sp, #8

; CHECK: sub sp, x29, #8
; CHECK-NEXT: .cfi_def_cfa wsp, 32
; CHECK-NEXT: ldp x29, x30, [sp, #8]
; CHECK-NEXT: ldr x19, [sp, #24]
; CHECK-NEXT: ldr d8, [sp], #32
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w19
; CHECK-NEXT: .cfi_restore w30
; CHECK-NEXT: .cfi_restore w29
; CHECK-NEXT: .cfi_restore b8
; CHECK-NEXT: ret

declare i64 @d()
Expand Down
7 changes: 1 addition & 6 deletions llvm/test/CodeGen/AArch64/large-stack.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,7 @@ entry:

declare dso_local i32 @printf(i8*, ...)

attributes #0 = { noinline optnone "frame-pointer"="all" uwtable }
attributes #0 = { noinline optnone "frame-pointer"="all" }

; CHECK: stp x[[SPILL_REG1:[0-9]+]], x[[SPILL_REG2:[0-9]+]], [sp, #-[[SPILL_OFFSET1:[0-9]+]]]
; CHECK-NEXT: .cfi_def_cfa_offset [[SPILL_OFFSET1]]
Expand All @@ -48,10 +48,5 @@ attributes #0 = { noinline optnone "frame-pointer"="all" uwtable }
; CHECK-COUNT-128: add sp, sp, #[[STACK1]], lsl #12
; CHECK-NEXT: add sp, sp, #[[STACK2]], lsl #12
; CHECK-NEXT: add sp, sp, #[[STACK3]]
; CHECK-NEXT: .cfi_def_cfa wsp, [[SPILL_OFFSET1]]
; CHECK-NEXT: ldr x[[SPILL_REG3]], [sp, #[[SPILL_OFFSET2]]]
; CHECK-NEXT: ldp x[[SPILL_REG1]], x[[SPILL_REG2]], [sp], #[[SPILL_OFFSET1]]
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w[[SPILL_REG3]]
; CHECK-NEXT: .cfi_restore w[[SPILL_REG2]]
; CHECK-NEXT: .cfi_restore w[[SPILL_REG1]]
10 changes: 2 additions & 8 deletions llvm/test/CodeGen/AArch64/local_vars.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -23,7 +23,7 @@ define void @trivial_func() nounwind {
ret void
}

define void @trivial_fp_func() uwtable {
define void @trivial_fp_func() {
; CHECK-LABEL: trivial_fp_func:
; CHECK: str x30, [sp, #-16]!
; CHECK-NOT: mov x29, sp
Expand All @@ -43,15 +43,9 @@ define void @trivial_fp_func() uwtable {
ret void

; CHECK: ldr x30, [sp], #16
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w30
; CHECK-NEXT: ret

; CHECK-WITHFP-ARM64: .cfi_def_cfa wsp, 16
; CHECK-WITHFP-ARM64-NEXT: ldp x29, x30, [sp], #16
; CHECK-WITHFP-ARM64-NEXT: .cfi_def_cfa_offset 0
; CHECK-WITHFP-ARM64-NEXT: .cfi_restore w30
; CHECK-WITHFP-ARM64-NEXT: .cfi_restore w29
; CHECK-WITHFP-ARM64: ldp x29, x30, [sp], #16
; CHECK-WITHFP-ARM64-NEXT: ret
}

Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AArch64/machine-outliner-remarks.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -102,7 +102,7 @@ define void @bar() #0 !dbg !27 {
ret void
}

attributes #0 = { noredzone nounwind ssp uwtable minsize "frame-pointer"="none" "target-cpu"="cyclone" }
attributes #0 = { noredzone nounwind ssp uwtable "frame-pointer"="none" "target-cpu"="cyclone" }

!llvm.dbg.cu = !{!0}
!llvm.module.flags = !{!3, !4, !5, !6}
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-thunk.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -65,7 +65,7 @@ entry:
ret i32 %add
}

attributes #0 = { "sign-return-address"="non-leaf" minsize }
attributes #0 = { "sign-return-address"="non-leaf" }

; CHECK-NOT: OUTLINED_FUNCTION_{{.*}}
; CHECK-NOT: .cfi_b_key_frame
Expand Down
5 changes: 1 addition & 4 deletions llvm/test/CodeGen/AArch64/merge-store-dependency.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@
@gv0 = internal unnamed_addr global i32 0, align 4
@gv1 = internal unnamed_addr global %struct1** null, align 8

define void @test(%struct1* %fde, i32 %fd, void (i32, i32, i8*)* %func, i8* %arg) uwtable {
define void @test(%struct1* %fde, i32 %fd, void (i32, i32, i8*)* %func, i8* %arg) {
;CHECK-LABEL: test
; A53-LABEL: test:
; A53: // %bb.0: // %entry
Expand Down Expand Up @@ -45,9 +45,6 @@ define void @test(%struct1* %fde, i32 %fd, void (i32, i32, i8*)* %func, i8* %arg
; A53-NEXT: adrp x8, gv1
; A53-NEXT: str x0, [x8, :lo12:gv1]
; A53-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
; A53-NEXT: .cfi_def_cfa_offset 0
; A53-NEXT: .cfi_restore w19
; A53-NEXT: .cfi_restore w30
; A53-NEXT: ret
; A53-NEXT: .LBB0_4: // %while.body.i.split
; A53-NEXT: // =>This Inner Loop Header: Depth=1
Expand Down
6 changes: 1 addition & 5 deletions llvm/test/CodeGen/AArch64/optimize-cond-branch.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@ target triple = "arm64--"
; formed in SelectionDAG, optimizeCondBranch() only triggers if the and
; instruction is in a different block than the conditional jump.

define void @func() uwtable {
define void @func() {
; CHECK-LABEL: func:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #1
Expand All @@ -24,16 +24,12 @@ define void @func() uwtable {
; CHECK-NEXT: ldr w8, [x8]
; CHECK-NEXT: and w0, w8, #0x100
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w30
; CHECK-NEXT: cbz w0, .LBB0_5
; CHECK-NEXT: .LBB0_3: // %common.ret.sink.split
; CHECK-NEXT: b extfunc
; CHECK-NEXT: .LBB0_4: // %b2
; CHECK-NEXT: bl extfunc
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w30
; CHECK-NEXT: cbnz w0, .LBB0_3
; CHECK-NEXT: .LBB0_5: // %common.ret
; CHECK-NEXT: ret
Expand Down
11 changes: 1 addition & 10 deletions llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
@B = external dso_local local_unnamed_addr global [8 x [8 x i64]], align 8
@C = external dso_local local_unnamed_addr global [8 x [8 x i64]], align 8

define dso_local void @run_test() local_unnamed_addr uwtable {
define dso_local void @run_test() local_unnamed_addr #0 {
; CHECK-LABEL: run_test:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: sub sp, sp, #96
Expand Down Expand Up @@ -175,15 +175,6 @@ define dso_local void @run_test() local_unnamed_addr uwtable {
; CHECK-NEXT: stp q4, q3, [x8, #432]
; CHECK-NEXT: str q0, [x8, #496]
; CHECK-NEXT: add sp, sp, #96
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore b8
; CHECK-NEXT: .cfi_restore b9
; CHECK-NEXT: .cfi_restore b10
; CHECK-NEXT: .cfi_restore b11
; CHECK-NEXT: .cfi_restore b12
; CHECK-NEXT: .cfi_restore b13
; CHECK-NEXT: .cfi_restore b14
; CHECK-NEXT: .cfi_restore b15
; CHECK-NEXT: ret
; CH`ECK-NEXT: .cfi_offset b9, -16
entry:
Expand Down
11 changes: 3 additions & 8 deletions llvm/test/CodeGen/AArch64/settag.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -116,37 +116,35 @@ entry:
ret void
}

define void @stg_alloca1() uwtable {
define void @stg_alloca1() {
; CHECK-LABEL: stg_alloca1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: sub sp, sp, #16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: stg sp, [sp], #16
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: ret
entry:
%a = alloca i8, i32 16, align 16
call void @llvm.aarch64.settag(i8* %a, i64 16)
ret void
}

define void @stg_alloca5() uwtable {
define void @stg_alloca5() {
; CHECK-LABEL: stg_alloca5:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: sub sp, sp, #80
; CHECK-NEXT: .cfi_def_cfa_offset 80
; CHECK-NEXT: st2g sp, [sp, #32]
; CHECK-NEXT: stg sp, [sp, #64]
; CHECK-NEXT: st2g sp, [sp], #80
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: ret
entry:
%a = alloca i8, i32 80, align 16
call void @llvm.aarch64.settag(i8* %a, i64 80)
ret void
}

define void @stg_alloca17() uwtable {
define void @stg_alloca17() {
; CHECK-LABEL: stg_alloca17:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: sub sp, sp, #288
Expand All @@ -161,10 +159,7 @@ define void @stg_alloca17() uwtable {
; CHECK-NEXT: cbnz x8, .LBB11_1
; CHECK-NEXT: // %bb.2: // %entry
; CHECK-NEXT: stg sp, [sp], #16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w29
; CHECK-NEXT: ret
entry:
%a = alloca i8, i32 272, align 16
Expand Down
11 changes: 1 addition & 10 deletions llvm/test/CodeGen/AArch64/shrink-wrapping-vla.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,7 @@
;
; RUN: llc -mtriple aarch64-linux %s -o - | FileCheck %s

define dso_local void @f(i32 %n, i32* nocapture %x) uwtable {
define dso_local void @f(i32 %n, i32* nocapture %x) {
entry:
%cmp = icmp slt i32 %n, 0
br i1 %cmp, label %return, label %if.end
Expand Down Expand Up @@ -80,10 +80,6 @@ declare void @llvm.stackrestore(i8*)
; CHECK: stp x29, x30, [sp, #-16]!
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: mov x29, sp
; CHECK-NEXT: .cfi_def_cfa w29, 16
; CHECK-NEXT: .cfi_offset w30, -8
; CHECK-NEXT: .cfi_offset w29, -16


; VLA allocation
; CHECK: mov [[X2:x[0-9]+]], sp
Expand All @@ -97,9 +93,4 @@ declare void @llvm.stackrestore(i8*)
; CHECK: mov sp, [[SAVE]]
; Epilogue
; CHECK-NEXT: mov sp, x29
; CHECK-NEXT: .cfi_def_cfa wsp, 16
; CHECK-NEXT: ldp x29, x30, [sp], #16
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w30
; CHECK-NEXT: .cfi_restore w29
; CHECK-NEXT: ret
3 changes: 1 addition & 2 deletions llvm/test/CodeGen/AArch64/speculation-hardening-loads.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -138,7 +138,7 @@ entry:
ret <2 x double> %vld1_lane
}

define i32 @deadload() speculative_load_hardening uwtable {
define i32 @deadload() speculative_load_hardening {
entry:
; CHECK-LABEL: deadload
; CHECK: cmp sp, #0
Expand All @@ -147,7 +147,6 @@ entry:
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: ldr w8, [sp, #12]
; CHECK-NEXT: add sp, sp, #16
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: mov [[TMPREG:x[0-9]+]], sp
; CHECK-NEXT: and [[TMPREG]], [[TMPREG]], x16
; CHECK-NEXT: mov sp, [[TMPREG]]
Expand Down
8 changes: 1 addition & 7 deletions llvm/test/CodeGen/AArch64/split-vector-insert.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@
; REQUIRES: asserts

target triple = "aarch64-unknown-linux-gnu"
attributes #0 = {"target-features"="+sve" uwtable}
attributes #0 = {"target-features"="+sve"}

declare <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64>, <8 x i64>, i64)
declare <vscale x 2 x double> @llvm.experimental.vector.insert.nxv2f64.v8f64(<vscale x 2 x double>, <8 x double>, i64)
Expand Down Expand Up @@ -52,10 +52,7 @@ define <vscale x 2 x i64> @test_nxv2i64_v8i64(<vscale x 2 x i64> %a, <8 x i64> %
; CHECK-NEXT: str q4, [x9, x8]
; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp, #2, mul vl]
; CHECK-NEXT: addvl sp, sp, #3
; CHECK-NEXT: .cfi_def_cfa wsp, 16
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w29
; CHECK-NEXT: ret


Expand Down Expand Up @@ -109,10 +106,7 @@ define <vscale x 2 x double> @test_nxv2f64_v8f64(<vscale x 2 x double> %a, <8 x
; CHECK-NEXT: str q4, [x9, x8]
; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp, #2, mul vl]
; CHECK-NEXT: addvl sp, sp, #3
; CHECK-NEXT: .cfi_def_cfa wsp, 16
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w29
; CHECK-NEXT: ret


Expand Down
6 changes: 1 addition & 5 deletions llvm/test/CodeGen/AArch64/stack-guard-sysreg.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -81,11 +81,7 @@ define dso_local void @foo(i64 %t) local_unnamed_addr #0 {
; CHECK-NEXT: b.ne .LBB0_2
; CHECK-NEXT: // %bb.1: // %entry
; CHECK-NEXT: mov sp, x29
; CHECK-NEXT: .cfi_def_cfa wsp, 16
; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w30
; CHECK-NEXT: .cfi_restore w29
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB0_2: // %entry
; CHECK-NEXT: bl __stack_chk_fail
Expand All @@ -100,7 +96,7 @@ declare void @baz(i32*)

; CHECK-BAD-OFFSET: LLVM ERROR: Unable to encode Stack Protector Guard Offset

attributes #0 = { sspstrong uwtable }
attributes #0 = { sspstrong }
!llvm.module.flags = !{!1, !2, !3}

!1 = !{i32 2, !"stack-protector-guard", !"sysreg"}
Expand Down
10 changes: 3 additions & 7 deletions llvm/test/CodeGen/AArch64/storepairsuppress_minsize.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@
declare %T_IN_BLOCK @return_in_block()
@in_block_store = dso_local global %T_IN_BLOCK zeroinitializer, align 8

define void @test_default() uwtable {
define void @test_default() {
; CHECK-LABEL: test_default:
; CHECK: // %bb.0:
; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
Expand All @@ -23,15 +23,13 @@ define void @test_default() uwtable {
; CHECK-NEXT: str d4, [x8, #32]
; CHECK-NEXT: str d5, [x8, #40]
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w30
; CHECK-NEXT: ret
%1 = call %T_IN_BLOCK @return_in_block()
store %T_IN_BLOCK %1, %T_IN_BLOCK* @in_block_store
ret void
}

define void @test_minsize() minsize uwtable {
define void @test_minsize() minsize {
; CHECK-LABEL: test_minsize:
; CHECK: // %bb.0:
; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
Expand All @@ -50,7 +48,7 @@ define void @test_minsize() minsize uwtable {
ret void
}

define void @test_optsize() optsize uwtable {
define void @test_optsize() optsize {
; CHECK-LABEL: test_optsize:
; CHECK: // %bb.0:
; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
Expand All @@ -63,8 +61,6 @@ define void @test_optsize() optsize uwtable {
; CHECK-NEXT: stp d2, d3, [x8, #16]
; CHECK-NEXT: stp d4, d5, [x8, #32]
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w30
; CHECK-NEXT: ret
%1 = call %T_IN_BLOCK @return_in_block()
store %T_IN_BLOCK %1, %T_IN_BLOCK* @in_block_store
Expand Down
5 changes: 1 addition & 4 deletions llvm/test/CodeGen/AArch64/sve-extract-scalable-vector.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -56,7 +56,7 @@ define <vscale x 14 x i1> @extract_nxv14i1_nxv28i1_0(<vscale x 28 x i1> %in) {
ret <vscale x 14 x i1> %res
}

define <vscale x 14 x i1> @extract_nxv14i1_nxv28i1_14(<vscale x 28 x i1> %in) uwtable {
define <vscale x 14 x i1> @extract_nxv14i1_nxv28i1_14(<vscale x 28 x i1> %in) {
; CHECK-LABEL: extract_nxv14i1_nxv28i1_14:
; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
Expand Down Expand Up @@ -90,10 +90,7 @@ define <vscale x 14 x i1> @extract_nxv14i1_nxv28i1_14(<vscale x 28 x i1> %in) uw
; CHECK-NEXT: uzp1 p0.h, p0.h, p3.h
; CHECK-NEXT: uzp1 p0.b, p0.b, p1.b
; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: .cfi_def_cfa wsp, 16
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w29
; CHECK-NEXT: ret
%res = call <vscale x 14 x i1> @llvm.experimental.vector.extract.nxv14i1.nxv28i1(<vscale x 28 x i1> %in, i64 14)
ret <vscale x 14 x i1> %res
Expand Down
517 changes: 0 additions & 517 deletions llvm/test/CodeGen/AArch64/sve-fixed-length-fp-select.ll
View file

Large diffs are not rendered by default.

2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AArch64/sve-fixed-length-fp-vselect.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -312,4 +312,4 @@ define void @select_v32f64(<32 x double>* %a, <32 x double>* %b) #0 {
ret void
}

attributes #0 = { "target-features"="+sve" uwtable }
attributes #0 = { "target-features"="+sve" }
66 changes: 1 addition & 65 deletions llvm/test/CodeGen/AArch64/sve-fixed-length-int-vselect.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -130,11 +130,7 @@ define void @select_v32i8(<32 x i8>* %a, <32 x i8>* %b, <32 x i1>* %c) #0 {
; CHECK-NEXT: sel z0.b, p1, z1.b, z2.b
; CHECK-NEXT: st1b { z0.b }, p0, [x0]
; CHECK-NEXT: mov sp, x29
; CHECK-NEXT: .cfi_def_cfa wsp, 16
; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w30
; CHECK-NEXT: .cfi_restore w29
; CHECK-NEXT: ret
%mask = load <32 x i1>, <32 x i1>* %c
%op1 = load <32 x i8>, <32 x i8>* %a
Expand Down Expand Up @@ -294,11 +290,7 @@ define void @select_v64i8(<64 x i8>* %a, <64 x i8>* %b, <64 x i1>* %c) #0 {
; VBITS_GE_512-NEXT: sel z0.b, p1, z1.b, z2.b
; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x0]
; VBITS_GE_512-NEXT: mov sp, x29
; VBITS_GE_512-NEXT: .cfi_def_cfa wsp, 16
; VBITS_GE_512-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; VBITS_GE_512-NEXT: .cfi_def_cfa_offset 0
; VBITS_GE_512-NEXT: .cfi_restore w30
; VBITS_GE_512-NEXT: .cfi_restore w29
; VBITS_GE_512-NEXT: ret
%mask = load <64 x i1>, <64 x i1>* %c
%op1 = load <64 x i8>, <64 x i8>* %a
Expand Down Expand Up @@ -587,11 +579,7 @@ define void @select_v128i8(<128 x i8>* %a, <128 x i8>* %b, <128 x i1>* %c) #0 {
; VBITS_GE_1024-NEXT: sel z0.b, p1, z1.b, z2.b
; VBITS_GE_1024-NEXT: st1b { z0.b }, p0, [x0]
; VBITS_GE_1024-NEXT: mov sp, x29
; VBITS_GE_1024-NEXT: .cfi_def_cfa wsp, 16
; VBITS_GE_1024-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; VBITS_GE_1024-NEXT: .cfi_def_cfa_offset 0
; VBITS_GE_1024-NEXT: .cfi_restore w30
; VBITS_GE_1024-NEXT: .cfi_restore w29
; VBITS_GE_1024-NEXT: ret
%mask = load <128 x i1>, <128 x i1>* %c
%op1 = load <128 x i8>, <128 x i8>* %a
Expand Down Expand Up @@ -1138,11 +1126,7 @@ define void @select_v256i8(<256 x i8>* %a, <256 x i8>* %b, <256 x i1>* %c) #0 {
; VBITS_GE_2048-NEXT: sel z0.b, p1, z1.b, z2.b
; VBITS_GE_2048-NEXT: st1b { z0.b }, p0, [x0]
; VBITS_GE_2048-NEXT: mov sp, x29
; VBITS_GE_2048-NEXT: .cfi_def_cfa wsp, 16
; VBITS_GE_2048-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; VBITS_GE_2048-NEXT: .cfi_def_cfa_offset 0
; VBITS_GE_2048-NEXT: .cfi_restore w30
; VBITS_GE_2048-NEXT: .cfi_restore w29
; VBITS_GE_2048-NEXT: ret
%mask = load <256 x i1>, <256 x i1>* %c
%op1 = load <256 x i8>, <256 x i8>* %a
Expand Down Expand Up @@ -1231,11 +1215,7 @@ define void @select_v16i16(<16 x i16>* %a, <16 x i16>* %b, <16 x i1>* %c) #0 {
; CHECK-NEXT: sel z0.h, p1, z1.h, z2.h
; CHECK-NEXT: st1h { z0.h }, p0, [x0]
; CHECK-NEXT: mov sp, x29
; CHECK-NEXT: .cfi_def_cfa wsp, 16
; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w30
; CHECK-NEXT: .cfi_restore w29
; CHECK-NEXT: ret
%mask = load <16 x i1>, <16 x i1>* %c
%op1 = load <16 x i16>, <16 x i16>* %a
Expand Down Expand Up @@ -1331,11 +1311,7 @@ define void @select_v32i16(<32 x i16>* %a, <32 x i16>* %b, <32 x i1>* %c) #0 {
; VBITS_GE_512-NEXT: sel z0.h, p1, z1.h, z2.h
; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0]
; VBITS_GE_512-NEXT: mov sp, x29
; VBITS_GE_512-NEXT: .cfi_def_cfa wsp, 16
; VBITS_GE_512-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; VBITS_GE_512-NEXT: .cfi_def_cfa_offset 0
; VBITS_GE_512-NEXT: .cfi_restore w30
; VBITS_GE_512-NEXT: .cfi_restore w29
; VBITS_GE_512-NEXT: ret
%mask = load <32 x i1>, <32 x i1>* %c
%op1 = load <32 x i16>, <32 x i16>* %a
Expand Down Expand Up @@ -1495,11 +1471,7 @@ define void @select_v64i16(<64 x i16>* %a, <64 x i16>* %b, <64 x i1>* %c) #0 {
; VBITS_GE_1024-NEXT: sel z0.h, p1, z1.h, z2.h
; VBITS_GE_1024-NEXT: st1h { z0.h }, p0, [x0]
; VBITS_GE_1024-NEXT: mov sp, x29
; VBITS_GE_1024-NEXT: .cfi_def_cfa wsp, 16
; VBITS_GE_1024-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; VBITS_GE_1024-NEXT: .cfi_def_cfa_offset 0
; VBITS_GE_1024-NEXT: .cfi_restore w30
; VBITS_GE_1024-NEXT: .cfi_restore w29
; VBITS_GE_1024-NEXT: ret
%mask = load <64 x i1>, <64 x i1>* %c
%op1 = load <64 x i16>, <64 x i16>* %a
Expand Down Expand Up @@ -1788,11 +1760,7 @@ define void @select_v128i16(<128 x i16>* %a, <128 x i16>* %b, <128 x i1>* %c) #0
; VBITS_GE_2048-NEXT: sel z0.h, p1, z1.h, z2.h
; VBITS_GE_2048-NEXT: st1h { z0.h }, p0, [x0]
; VBITS_GE_2048-NEXT: mov sp, x29
; VBITS_GE_2048-NEXT: .cfi_def_cfa wsp, 16
; VBITS_GE_2048-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; VBITS_GE_2048-NEXT: .cfi_def_cfa_offset 0
; VBITS_GE_2048-NEXT: .cfi_restore w30
; VBITS_GE_2048-NEXT: .cfi_restore w29
; VBITS_GE_2048-NEXT: ret
%mask = load <128 x i1>, <128 x i1>* %c
%op1 = load <128 x i16>, <128 x i16>* %a
Expand Down Expand Up @@ -1861,11 +1829,7 @@ define void @select_v8i32(<8 x i32>* %a, <8 x i32>* %b, <8 x i1>* %c) #0 {
; CHECK-NEXT: sel z0.s, p1, z1.s, z2.s
; CHECK-NEXT: st1w { z0.s }, p0, [x0]
; CHECK-NEXT: mov sp, x29
; CHECK-NEXT: .cfi_def_cfa wsp, 16
; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w30
; CHECK-NEXT: .cfi_restore w29
; CHECK-NEXT: ret
%mask = load <8 x i1>, <8 x i1>* %c
%op1 = load <8 x i32>, <8 x i32>* %a
Expand Down Expand Up @@ -1921,11 +1885,7 @@ define void @select_v16i32(<16 x i32>* %a, <16 x i32>* %b, <16 x i1>* %c) #0 {
; VBITS_GE_512-NEXT: sel z0.s, p1, z1.s, z2.s
; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0]
; VBITS_GE_512-NEXT: mov sp, x29
; VBITS_GE_512-NEXT: .cfi_def_cfa wsp, 16
; VBITS_GE_512-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; VBITS_GE_512-NEXT: .cfi_def_cfa_offset 0
; VBITS_GE_512-NEXT: .cfi_restore w30
; VBITS_GE_512-NEXT: .cfi_restore w29
; VBITS_GE_512-NEXT: ret
%mask = load <16 x i1>, <16 x i1>* %c
%op1 = load <16 x i32>, <16 x i32>* %a
Expand Down Expand Up @@ -2005,11 +1965,7 @@ define void @select_v32i32(<32 x i32>* %a, <32 x i32>* %b, <32 x i1>* %c) #0 {
; VBITS_GE_1024-NEXT: sel z0.s, p1, z1.s, z2.s
; VBITS_GE_1024-NEXT: st1w { z0.s }, p0, [x0]
; VBITS_GE_1024-NEXT: mov sp, x29
; VBITS_GE_1024-NEXT: .cfi_def_cfa wsp, 16
; VBITS_GE_1024-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; VBITS_GE_1024-NEXT: .cfi_def_cfa_offset 0
; VBITS_GE_1024-NEXT: .cfi_restore w30
; VBITS_GE_1024-NEXT: .cfi_restore w29
; VBITS_GE_1024-NEXT: ret
%mask = load <32 x i1>, <32 x i1>* %c
%op1 = load <32 x i32>, <32 x i32>* %a
Expand Down Expand Up @@ -2137,11 +2093,7 @@ define void @select_v64i32(<64 x i32>* %a, <64 x i32>* %b, <64 x i1>* %c) #0 {
; VBITS_GE_2048-NEXT: sel z0.s, p1, z1.s, z2.s
; VBITS_GE_2048-NEXT: st1w { z0.s }, p0, [x0]
; VBITS_GE_2048-NEXT: mov sp, x29
; VBITS_GE_2048-NEXT: .cfi_def_cfa wsp, 16
; VBITS_GE_2048-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; VBITS_GE_2048-NEXT: .cfi_def_cfa_offset 0
; VBITS_GE_2048-NEXT: .cfi_restore w30
; VBITS_GE_2048-NEXT: .cfi_restore w29
; VBITS_GE_2048-NEXT: ret
%mask = load <64 x i1>, <64 x i1>* %c
%op1 = load <64 x i32>, <64 x i32>* %a
Expand Down Expand Up @@ -2208,11 +2160,7 @@ define void @select_v4i64(<4 x i64>* %a, <4 x i64>* %b, <4 x i1>* %c) #0 {
; CHECK-NEXT: sel z0.d, p1, z1.d, z2.d
; CHECK-NEXT: st1d { z0.d }, p0, [x0]
; CHECK-NEXT: mov sp, x29
; CHECK-NEXT: .cfi_def_cfa wsp, 16
; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w30
; CHECK-NEXT: .cfi_restore w29
; CHECK-NEXT: ret
%mask = load <4 x i1>, <4 x i1>* %c
%op1 = load <4 x i64>, <4 x i64>* %a
Expand Down Expand Up @@ -2263,11 +2211,7 @@ define void @select_v8i64(<8 x i64>* %a, <8 x i64>* %b, <8 x i1>* %c) #0 {
; VBITS_GE_512-NEXT: sel z0.d, p1, z1.d, z2.d
; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0]
; VBITS_GE_512-NEXT: mov sp, x29
; VBITS_GE_512-NEXT: .cfi_def_cfa wsp, 16
; VBITS_GE_512-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; VBITS_GE_512-NEXT: .cfi_def_cfa_offset 0
; VBITS_GE_512-NEXT: .cfi_restore w30
; VBITS_GE_512-NEXT: .cfi_restore w29
; VBITS_GE_512-NEXT: ret
%mask = load <8 x i1>, <8 x i1>* %c
%op1 = load <8 x i64>, <8 x i64>* %a
Expand Down Expand Up @@ -2338,11 +2282,7 @@ define void @select_v16i64(<16 x i64>* %a, <16 x i64>* %b, <16 x i1>* %c) #0 {
; VBITS_GE_1024-NEXT: sel z0.d, p1, z1.d, z2.d
; VBITS_GE_1024-NEXT: st1d { z0.d }, p0, [x0]
; VBITS_GE_1024-NEXT: mov sp, x29
; VBITS_GE_1024-NEXT: .cfi_def_cfa wsp, 16
; VBITS_GE_1024-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; VBITS_GE_1024-NEXT: .cfi_def_cfa_offset 0
; VBITS_GE_1024-NEXT: .cfi_restore w30
; VBITS_GE_1024-NEXT: .cfi_restore w29
; VBITS_GE_1024-NEXT: ret
%mask = load <16 x i1>, <16 x i1>* %c
%op1 = load <16 x i64>, <16 x i64>* %a
Expand Down Expand Up @@ -2484,11 +2424,7 @@ define void @select_v32i64(<32 x i64>* %a, <32 x i64>* %b, <32 x i1>* %c) #0 {
; VBITS_GE_2048-NEXT: sel z0.d, p1, z1.d, z2.d
; VBITS_GE_2048-NEXT: st1d { z0.d }, p0, [x0]
; VBITS_GE_2048-NEXT: mov sp, x29
; VBITS_GE_2048-NEXT: .cfi_def_cfa wsp, 16
; VBITS_GE_2048-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; VBITS_GE_2048-NEXT: .cfi_def_cfa_offset 0
; VBITS_GE_2048-NEXT: .cfi_restore w30
; VBITS_GE_2048-NEXT: .cfi_restore w29
; VBITS_GE_2048-NEXT: ret
%mask = load <32 x i1>, <32 x i1>* %c
%op1 = load <32 x i64>, <32 x i64>* %a
Expand All @@ -2498,4 +2434,4 @@ define void @select_v32i64(<32 x i64>* %a, <32 x i64>* %b, <32 x i1>* %c) #0 {
ret void
}

attributes #0 = { "target-features"="+sve" uwtable }
attributes #0 = { "target-features"="+sve" }
6 changes: 1 addition & 5 deletions llvm/test/CodeGen/AArch64/sve-fixed-length-vector-shuffle.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -950,11 +950,7 @@ define void @shuffle_ext_invalid(<4 x double>* %a, <4 x double>* %b) #0 {
; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp]
; CHECK-NEXT: st1d { z0.d }, p0, [x0]
; CHECK-NEXT: mov sp, x29
; CHECK-NEXT: .cfi_def_cfa wsp, 16
; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w30
; CHECK-NEXT: .cfi_restore w29
; CHECK-NEXT: ret
%op1 = load <4 x double>, <4 x double>* %a
%op2 = load <4 x double>, <4 x double>* %b
Expand All @@ -963,4 +959,4 @@ define void @shuffle_ext_invalid(<4 x double>* %a, <4 x double>* %b) #0 {
ret void
}

attributes #0 = { "target-features"="+sve" uwtable }
attributes #0 = { "target-features"="+sve" }
5 changes: 1 addition & 4 deletions llvm/test/CodeGen/AArch64/sve-insert-element.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -496,7 +496,7 @@ define <vscale x 16 x i1> @test_predicate_insert_16xi1(<vscale x 16 x i1> %val,
ret <vscale x 16 x i1> %res
}

define <vscale x 32 x i1> @test_predicate_insert_32xi1(<vscale x 32 x i1> %val, i1 %elt, i32 %idx) uwtable {
define <vscale x 32 x i1> @test_predicate_insert_32xi1(<vscale x 32 x i1> %val, i1 %elt, i32 %idx) {
; CHECK-LABEL: test_predicate_insert_32xi1:
; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
Expand Down Expand Up @@ -524,10 +524,7 @@ define <vscale x 32 x i1> @test_predicate_insert_32xi1(<vscale x 32 x i1> %val,
; CHECK-NEXT: cmpne p0.b, p1/z, z0.b, #0
; CHECK-NEXT: cmpne p1.b, p1/z, z1.b, #0
; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: .cfi_def_cfa wsp, 16
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w29
; CHECK-NEXT: ret
%res = insertelement <vscale x 32 x i1> %val, i1 %elt, i32 %idx
ret <vscale x 32 x i1> %res
Expand Down
10 changes: 2 additions & 8 deletions llvm/test/CodeGen/AArch64/sve-insert-vector.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -186,7 +186,7 @@ define void @insert_nxv8i64_nxv16i64_hi(<vscale x 8 x i64> %sv0, <vscale x 16 x
ret void
}

define void @insert_v2i64_nxv16i64(<2 x i64> %sv0, <2 x i64> %sv1, <vscale x 16 x i64>* %out) uwtable {
define void @insert_v2i64_nxv16i64(<2 x i64> %sv0, <2 x i64> %sv1, <vscale x 16 x i64>* %out) {
; CHECK-LABEL: insert_v2i64_nxv16i64:
; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
Expand All @@ -207,10 +207,7 @@ define void @insert_v2i64_nxv16i64(<2 x i64> %sv0, <2 x i64> %sv1, <vscale x 16
; CHECK-NEXT: st1d { z1.d }, p0, [x0, #1, mul vl]
; CHECK-NEXT: st1d { z0.d }, p0, [x0]
; CHECK-NEXT: addvl sp, sp, #4
; CHECK-NEXT: .cfi_def_cfa wsp, 16
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w29
; CHECK-NEXT: ret
%v0 = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv0, i64 0)
%v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> %v0, <2 x i64> %sv1, i64 4)
Expand All @@ -231,7 +228,7 @@ define void @insert_v2i64_nxv16i64_lo0(<2 x i64>* %psv, <vscale x 16 x i64>* %ou
ret void
}

define void @insert_v2i64_nxv16i64_lo2(<2 x i64>* %psv, <vscale x 16 x i64>* %out) uwtable {
define void @insert_v2i64_nxv16i64_lo2(<2 x i64>* %psv, <vscale x 16 x i64>* %out) {
; CHECK-LABEL: insert_v2i64_nxv16i64_lo2:
; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
Expand All @@ -247,10 +244,7 @@ define void @insert_v2i64_nxv16i64_lo2(<2 x i64>* %psv, <vscale x 16 x i64>* %ou
; CHECK-NEXT: st1d { z1.d }, p0, [x1, #1, mul vl]
; CHECK-NEXT: st1d { z0.d }, p0, [x1]
; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: .cfi_def_cfa wsp, 16
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w29
; CHECK-NEXT: ret
%sv = load <2 x i64>, <2 x i64>* %psv
%v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv, i64 2)
Expand Down
20 changes: 4 additions & 16 deletions llvm/test/CodeGen/AArch64/sve-ldnf1.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,26 +4,26 @@
# Test that prologepilog works for each of the LDNF1 instructions for stack-based objects.
#
--- |
define void @testcase_positive_offset() uwtable {
define void @testcase_positive_offset() {
%dummy = alloca <vscale x 2 x i64>, align 8
%object = alloca <vscale x 2 x i64>, align 8
; Reads from %object at offset 63 * readsize
ret void
}
define void @testcase_negative_offset() uwtable {
define void @testcase_negative_offset() {
%dummy = alloca <vscale x 2 x i64>, align 8
%object = alloca <vscale x 2 x i64>, align 8
; Reads from %object at offset 63 * readsize
ret void
}

define void @testcase_positive_offset_out_of_range() uwtable {
define void @testcase_positive_offset_out_of_range() {
%dummy = alloca <vscale x 2 x i64>, align 8
%object = alloca <vscale x 2 x i64>, align 8
; Reads from %object at offset 64 * readsize
ret void
}
define void @testcase_negative_offset_out_of_range() uwtable {
define void @testcase_negative_offset_out_of_range() {
%dummy = alloca <vscale x 2 x i64>, align 8
%object = alloca <vscale x 2 x i64>, align 8
; Reads from %object at offset -1 * readsize
Expand Down Expand Up @@ -65,10 +65,7 @@ body: |
; CHECK-NEXT: renamable $z0 = LDNF1SW_D_IMM renamable $p0, $sp, 7 :: (load (s32) from %ir.object, align 8)
; CHECK-NEXT: renamable $z0 = LDNF1D_IMM renamable $p0, $sp, 7 :: (load (s64) from %ir.object)
; CHECK-NEXT: $sp = frame-destroy ADDVL_XXI $sp, 4
; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa $wsp, 16
; CHECK-NEXT: early-clobber $sp, $fp = frame-destroy LDRXpost $sp, 16 :: (load (s64) from %stack.2)
; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 0
; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $w29
; CHECK-NEXT: RET_ReallyLR implicit $z0
renamable $z0 = LDNF1B_IMM renamable $p0, %stack.1.object, 7 :: (load 1 from %ir.object, align 2)
renamable $z0 = LDNF1B_H_IMM renamable $p0, %stack.1.object, 7 :: (load 1 from %ir.object, align 2)
Expand Down Expand Up @@ -124,10 +121,7 @@ body: |
; CHECK-NEXT: renamable $z0 = LDNF1SW_D_IMM renamable $p0, $sp, -8 :: (load (s32) from %ir.object, align 8)
; CHECK-NEXT: renamable $z0 = LDNF1D_IMM renamable $p0, $sp, -8 :: (load (s64) from %ir.object)
; CHECK-NEXT: $sp = frame-destroy ADDVL_XXI $sp, 4
; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa $wsp, 16
; CHECK-NEXT: early-clobber $sp, $fp = frame-destroy LDRXpost $sp, 16 :: (load (s64) from %stack.2)
; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 0
; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $w29
; CHECK-NEXT: RET_ReallyLR implicit $z0
renamable $z0 = LDNF1B_IMM renamable $p0, %stack.1.object, -8 :: (load 1 from %ir.object, align 2)
renamable $z0 = LDNF1B_H_IMM renamable $p0, %stack.1.object, -8 :: (load 1 from %ir.object, align 2)
Expand Down Expand Up @@ -197,10 +191,7 @@ body: |
; CHECK-NEXT: $x8 = ADDPL_XXI $sp, 4
; CHECK-NEXT: renamable $z0 = LDNF1SW_D_IMM renamable $p0, killed $x8, 7 :: (load (s32) from %ir.object, align 8)
; CHECK-NEXT: $sp = frame-destroy ADDVL_XXI $sp, 4
; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa $wsp, 16
; CHECK-NEXT: early-clobber $sp, $fp = frame-destroy LDRXpost $sp, 16 :: (load (s64) from %stack.2)
; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 0
; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $w29
; CHECK-NEXT: RET_ReallyLR implicit $z0
renamable $z0 = LDNF1B_IMM renamable $p0, %stack.1.object, 8 :: (load 1 from %ir.object, align 2)
renamable $z0 = LDNF1B_H_IMM renamable $p0, %stack.1.object, 8 :: (load 1 from %ir.object, align 2)
Expand Down Expand Up @@ -269,10 +260,7 @@ body: |
; CHECK-NEXT: $x8 = ADDPL_XXI $sp, -4
; CHECK-NEXT: renamable $z0 = LDNF1SW_D_IMM renamable $p0, killed $x8, -8 :: (load (s32) from %ir.object, align 8)
; CHECK-NEXT: $sp = frame-destroy ADDVL_XXI $sp, 4
; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa $wsp, 16
; CHECK-NEXT: early-clobber $sp, $fp = frame-destroy LDRXpost $sp, 16 :: (load (s64) from %stack.2)
; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 0
; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $w29
; CHECK-NEXT: RET_ReallyLR implicit $z0
renamable $z0 = LDNF1B_IMM renamable $p0, %stack.1.object, -9 :: (load 1 from %ir.object, align 2)
renamable $z0 = LDNF1B_H_IMM renamable $p0, %stack.1.object, -9 :: (load 1 from %ir.object, align 2)
Expand Down
20 changes: 4 additions & 16 deletions llvm/test/CodeGen/AArch64/sve-ldstnt1.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,26 +4,26 @@
# Test that prologepilog works for each of the LDNT1/STNT1 instructions for stack-based objects.
#
--- |
define void @testcase_positive_offset() uwtable {
define void @testcase_positive_offset() {
%dummy = alloca <vscale x 2 x i64>, align 8
%object = alloca <vscale x 2 x i64>, align 8
; Reads from %object at offset 7 * readsize
ret void
}
define void @testcase_negative_offset() uwtable {
define void @testcase_negative_offset() {
%dummy = alloca <vscale x 2 x i64>, align 8
%object = alloca <vscale x 2 x i64>, align 8
; Reads from %object at offset -8 * readsize
ret void
}

define void @testcase_positive_offset_out_of_range() uwtable {
define void @testcase_positive_offset_out_of_range() {
%dummy = alloca <vscale x 2 x i64>, align 8
%object = alloca <vscale x 2 x i64>, align 8
; Reads from %object at offset 8 * readsize
ret void
}
define void @testcase_negative_offset_out_of_range() uwtable {
define void @testcase_negative_offset_out_of_range() {
%dummy = alloca <vscale x 2 x i64>, align 8
%object = alloca <vscale x 2 x i64>, align 8
; Reads from %object at offset -9 * readsize
Expand Down Expand Up @@ -57,10 +57,7 @@ body: |
; CHECK-NEXT: STNT1W_ZRI renamable $z0, renamable $p0, $sp, 7 :: (store (s32) into %ir.object, align 8)
; CHECK-NEXT: STNT1D_ZRI renamable $z0, renamable $p0, $sp, 7 :: (store (s64) into %ir.object)
; CHECK-NEXT: $sp = frame-destroy ADDVL_XXI $sp, 4
; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa $wsp, 16
; CHECK-NEXT: early-clobber $sp, $fp = frame-destroy LDRXpost $sp, 16 :: (load (s64) from %stack.2)
; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 0
; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $w29
; CHECK-NEXT: RET_ReallyLR implicit $z0
renamable $z0 = LDNT1B_ZRI renamable $p0, %stack.1.object, 7 :: (load 1 from %ir.object, align 2)
renamable $z0 = LDNT1H_ZRI renamable $p0, %stack.1.object, 7 :: (load 2 from %ir.object, align 2)
Expand Down Expand Up @@ -100,10 +97,7 @@ body: |
; CHECK-NEXT: STNT1W_ZRI renamable $z0, renamable $p0, $sp, -8 :: (store (s32) into %ir.object, align 8)
; CHECK-NEXT: STNT1D_ZRI renamable $z0, renamable $p0, $sp, -8 :: (store (s64) into %ir.object)
; CHECK-NEXT: $sp = frame-destroy ADDVL_XXI $sp, 4
; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa $wsp, 16
; CHECK-NEXT: early-clobber $sp, $fp = frame-destroy LDRXpost $sp, 16 :: (load (s64) from %stack.2)
; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 0
; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $w29
; CHECK-NEXT: RET_ReallyLR implicit $z0
renamable $z0 = LDNT1B_ZRI renamable $p0, %stack.1.object, -8 :: (load 1 from %ir.object, align 2)
renamable $z0 = LDNT1H_ZRI renamable $p0, %stack.1.object, -8 :: (load 2 from %ir.object, align 2)
Expand Down Expand Up @@ -151,10 +145,7 @@ body: |
; CHECK-NEXT: $x8 = ADDVL_XXI $sp, 1
; CHECK-NEXT: STNT1D_ZRI renamable $z0, renamable $p0, killed $x8, 7 :: (store (s64) into %ir.object)
; CHECK-NEXT: $sp = frame-destroy ADDVL_XXI $sp, 4
; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa $wsp, 16
; CHECK-NEXT: early-clobber $sp, $fp = frame-destroy LDRXpost $sp, 16 :: (load (s64) from %stack.2)
; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 0
; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $w29
; CHECK-NEXT: RET_ReallyLR implicit $z0
renamable $z0 = LDNT1B_ZRI renamable $p0, %stack.1.object, 8 :: (load 1 from %ir.object, align 2)
renamable $z0 = LDNT1H_ZRI renamable $p0, %stack.1.object, 8 :: (load 2 from %ir.object, align 2)
Expand Down Expand Up @@ -202,10 +193,7 @@ body: |
; CHECK-NEXT: $x8 = ADDVL_XXI $sp, -1
; CHECK-NEXT: STNT1D_ZRI renamable $z0, renamable $p0, killed $x8, -8 :: (store (s64) into %ir.object)
; CHECK-NEXT: $sp = frame-destroy ADDVL_XXI $sp, 4
; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa $wsp, 16
; CHECK-NEXT: early-clobber $sp, $fp = frame-destroy LDRXpost $sp, 16 :: (load (s64) from %stack.2)
; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 0
; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $w29
; CHECK-NEXT: RET_ReallyLR implicit $z0
renamable $z0 = LDNT1B_ZRI renamable $p0, %stack.1.object, -9 :: (load 1 from %ir.object, align 2)
renamable $z0 = LDNT1H_ZRI renamable $p0, %stack.1.object, -9 :: (load 2 from %ir.object, align 2)
Expand Down
10 changes: 2 additions & 8 deletions llvm/test/CodeGen/AArch64/sve-pred-arith.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -46,7 +46,7 @@ define <vscale x 2 x i1> @add_nxv2i1(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b)

; ILLEGAL ADDS

define aarch64_sve_vector_pcs <vscale x 64 x i1> @add_nxv64i1(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b) uwtable {
define aarch64_sve_vector_pcs <vscale x 64 x i1> @add_nxv64i1(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b) {
; CHECK-LABEL: add_nxv64i1:
; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
Expand Down Expand Up @@ -74,10 +74,7 @@ define aarch64_sve_vector_pcs <vscale x 64 x i1> @add_nxv64i1(<vscale x 64 x i1>
; CHECK-NEXT: ldr p5, [sp, #6, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: .cfi_def_cfa wsp, 16
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w29
; CHECK-NEXT: ret
%res = add <vscale x 64 x i1> %a, %b
ret <vscale x 64 x i1> %res;
Expand Down Expand Up @@ -130,7 +127,7 @@ define <vscale x 2 x i1> @sub_xv2i1(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b)
; ILLEGAL SUBGS


define aarch64_sve_vector_pcs <vscale x 64 x i1> @sub_nxv64i1(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b) uwtable {
define aarch64_sve_vector_pcs <vscale x 64 x i1> @sub_nxv64i1(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b) {
; CHECK-LABEL: sub_nxv64i1:
; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
Expand Down Expand Up @@ -158,10 +155,7 @@ define aarch64_sve_vector_pcs <vscale x 64 x i1> @sub_nxv64i1(<vscale x 64 x i1>
; CHECK-NEXT: ldr p5, [sp, #6, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: .cfi_def_cfa wsp, 16
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w29
; CHECK-NEXT: ret
%res = sub <vscale x 64 x i1> %a, %b
ret <vscale x 64 x i1> %res;
Expand Down
4 changes: 1 addition & 3 deletions llvm/test/CodeGen/AArch64/sve-varargs.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@ declare i32 @sve_printf(i8*, <vscale x 4 x i32>, ...)

@.str_1 = internal constant [6 x i8] c"boo!\0A\00"

define void @foo(<vscale x 4 x i32> %x) uwtable {
define void @foo(<vscale x 4 x i32> %x) {
; CHECK-LABEL: foo:
; CHECK: // %bb.0:
; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
Expand All @@ -15,8 +15,6 @@ define void @foo(<vscale x 4 x i32> %x) uwtable {
; CHECK-NEXT: add x0, x0, :lo12:.str_1
; CHECK-NEXT: bl sve_printf
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w30
; CHECK-NEXT: ret
%f = getelementptr [6 x i8], [6 x i8]* @.str_1, i64 0, i64 0
call i32 (i8*, <vscale x 4 x i32>, ...) @sve_printf(i8* %f, <vscale x 4 x i32> %x)
Expand Down
30 changes: 13 additions & 17 deletions llvm/test/CodeGen/AArch64/swifttail-call.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,18 +16,17 @@ define swifttailcc void @caller_to0_from0() nounwind {
; COMMON-NEXT: b callee_stack0
}

define swifttailcc void @caller_to0_from8([8 x i64], i64) #0 {
define swifttailcc void @caller_to0_from8([8 x i64], i64) {
; COMMON-LABEL: caller_to0_from8:

musttail call swifttailcc void @callee_stack0()
ret void

; COMMON: add sp, sp, #16
; COMMON-NEXT: .cfi_def_cfa_offset -16
; COMMON-NEXT: b callee_stack0
}

define swifttailcc void @caller_to8_from0() #0 {
define swifttailcc void @caller_to8_from0() {
; COMMON-LABEL: caller_to8_from0:

; Key point is that the "42" should go #16 below incoming stack
Expand All @@ -39,7 +38,7 @@ define swifttailcc void @caller_to8_from0() #0 {
; COMMON-NEXT: b callee_stack8
}

define swifttailcc void @caller_to8_from8([8 x i64], i64 %a) #0 {
define swifttailcc void @caller_to8_from8([8 x i64], i64 %a) {
; COMMON-LABEL: caller_to8_from8:
; COMMON-NOT: sub sp,

Expand All @@ -51,7 +50,7 @@ define swifttailcc void @caller_to8_from8([8 x i64], i64 %a) #0 {
; COMMON-NEXT: b callee_stack8
}

define swifttailcc void @caller_to16_from8([8 x i64], i64 %a) #0 {
define swifttailcc void @caller_to16_from8([8 x i64], i64 %a) {
; COMMON-LABEL: caller_to16_from8:
; COMMON-NOT: sub sp,

Expand All @@ -66,7 +65,7 @@ define swifttailcc void @caller_to16_from8([8 x i64], i64 %a) #0 {
}


define swifttailcc void @caller_to8_from24([8 x i64], i64 %a, i64 %b, i64 %c) #0 {
define swifttailcc void @caller_to8_from24([8 x i64], i64 %a, i64 %b, i64 %c) {
; COMMON-LABEL: caller_to8_from24:
; COMMON-NOT: sub sp,

Expand All @@ -75,12 +74,11 @@ define swifttailcc void @caller_to8_from24([8 x i64], i64 %a, i64 %b, i64 %c) #0
ret void

; COMMON: str {{x[0-9]+}}, [sp, #16]!
; COMMON-NEXT: .cfi_def_cfa_offset -16
; COMMON-NEXT: b callee_stack8
}


define swifttailcc void @caller_to16_from16([8 x i64], i64 %a, i64 %b) #0 {
define swifttailcc void @caller_to16_from16([8 x i64], i64 %a, i64 %b) {
; COMMON-LABEL: caller_to16_from16:
; COMMON-NOT: sub sp,

Expand All @@ -107,7 +105,7 @@ define swifttailcc void @disable_tail_calls() nounwind "disable-tail-calls"="tru

; Weakly-referenced extern functions cannot be tail-called, as AAELF does
; not define the behaviour of branch instructions to undefined weak symbols.
define swifttailcc void @caller_weak() #0 {
define swifttailcc void @caller_weak() {
; COMMON-LABEL: caller_weak:
; COMMON: bl callee_weak
tail call void @callee_weak()
Expand All @@ -116,7 +114,7 @@ define swifttailcc void @caller_weak() #0 {

declare { [2 x float] } @get_vec2()

define { [3 x float] } @test_add_elem() #0 {
define { [3 x float] } @test_add_elem() {
; SDAG-LABEL: test_add_elem:
; SDAG: bl get_vec2
; SDAG: fmov s2, #1.0
Expand All @@ -140,7 +138,7 @@ define { [3 x float] } @test_add_elem() #0 {
}

declare double @get_double()
define { double, [2 x double] } @test_mismatched_insert() #0 {
define { double, [2 x double] } @test_mismatched_insert() {
; COMMON-LABEL: test_mismatched_insert:
; COMMON: bl get_double
; COMMON: bl get_double
Expand All @@ -158,7 +156,7 @@ define { double, [2 x double] } @test_mismatched_insert() #0 {
ret { double, [2 x double] } %res.012
}

define void @fromC_totail() #0 {
define void @fromC_totail() {
; COMMON-LABEL: fromC_totail:
; COMMON: sub sp, sp, #48

Expand All @@ -176,7 +174,7 @@ define void @fromC_totail() #0 {
ret void
}

define void @fromC_totail_noreservedframe(i32 %len) #0 {
define void @fromC_totail_noreservedframe(i32 %len) {
; COMMON-LABEL: fromC_totail_noreservedframe:
; COMMON: stp x29, x30, [sp, #-48]!

Expand All @@ -200,7 +198,7 @@ define void @fromC_totail_noreservedframe(i32 %len) #0 {

declare void @Ccallee_stack8([8 x i64], i64)

define swifttailcc void @fromtail_toC() #0 {
define swifttailcc void @fromtail_toC() {
; COMMON-LABEL: fromtail_toC:
; COMMON: sub sp, sp, #32

Expand All @@ -222,13 +220,11 @@ define swifttailcc void @fromtail_toC() #0 {
}

declare swifttailcc i8* @SwiftSelf(i8 * swiftasync %context, i8* swiftself %closure)
define swiftcc i8* @CallSwiftSelf(i8* swiftself %closure, i8* %context) #0 {
define swiftcc i8* @CallSwiftSelf(i8* swiftself %closure, i8* %context) {
; CHECK-LABEL: CallSwiftSelf:
; CHECK: stp x20
;call void asm "","~{r13}"() ; We get a push r13 but why not with the call
; below?
%res = call swifttailcc i8* @SwiftSelf(i8 * swiftasync %context, i8* swiftself %closure)
ret i8* %res
}

attributes #0 = { uwtable }
22 changes: 9 additions & 13 deletions llvm/test/CodeGen/AArch64/tail-call.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,18 +16,17 @@ define fastcc void @caller_to0_from0() nounwind {
; COMMON-NEXT: b callee_stack0
}

define fastcc void @caller_to0_from8([8 x i64], i64) #0 {
define fastcc void @caller_to0_from8([8 x i64], i64) {
; COMMON-LABEL: caller_to0_from8:

tail call fastcc void @callee_stack0()
ret void

; COMMON: add sp, sp, #16
; COMMON: .cfi_def_cfa_offset -16
; COMMON-NEXT: b callee_stack0
}

define fastcc void @caller_to8_from0() #0 {
define fastcc void @caller_to8_from0() {
; COMMON-LABEL: caller_to8_from0:

; Key point is that the "42" should go #16 below incoming stack
Expand All @@ -39,7 +38,7 @@ define fastcc void @caller_to8_from0() #0 {
; COMMON-NEXT: b callee_stack8
}

define fastcc void @caller_to8_from8([8 x i64], i64 %a) #0 {
define fastcc void @caller_to8_from8([8 x i64], i64 %a) {
; COMMON-LABEL: caller_to8_from8:
; COMMON-NOT: sub sp,

Expand All @@ -51,7 +50,7 @@ define fastcc void @caller_to8_from8([8 x i64], i64 %a) #0 {
; COMMON-NEXT: b callee_stack8
}

define fastcc void @caller_to16_from8([8 x i64], i64 %a) #0 {
define fastcc void @caller_to16_from8([8 x i64], i64 %a) {
; COMMON-LABEL: caller_to16_from8:
; COMMON-NOT: sub sp,

Expand All @@ -66,7 +65,7 @@ define fastcc void @caller_to16_from8([8 x i64], i64 %a) #0 {
}


define fastcc void @caller_to8_from24([8 x i64], i64 %a, i64 %b, i64 %c) #0 {
define fastcc void @caller_to8_from24([8 x i64], i64 %a, i64 %b, i64 %c) {
; COMMON-LABEL: caller_to8_from24:
; COMMON-NOT: sub sp,

Expand All @@ -75,12 +74,11 @@ define fastcc void @caller_to8_from24([8 x i64], i64 %a, i64 %b, i64 %c) #0 {
ret void

; COMMON: str {{x[0-9]+}}, [sp, #16]!
; COMMON: .cfi_def_cfa_offset -16
; COMMON-NEXT: b callee_stack8
}


define fastcc void @caller_to16_from16([8 x i64], i64 %a, i64 %b) #0 {
define fastcc void @caller_to16_from16([8 x i64], i64 %a, i64 %b) {
; COMMON-LABEL: caller_to16_from16:
; COMMON-NOT: sub sp,

Expand All @@ -107,7 +105,7 @@ define fastcc void @disable_tail_calls() nounwind "disable-tail-calls"="true" {

; Weakly-referenced extern functions cannot be tail-called, as AAELF does
; not define the behaviour of branch instructions to undefined weak symbols.
define fastcc void @caller_weak() #0 {
define fastcc void @caller_weak() {
; COMMON-LABEL: caller_weak:
; COMMON: bl callee_weak
tail call void @callee_weak()
Expand All @@ -116,7 +114,7 @@ define fastcc void @caller_weak() #0 {

declare { [2 x float] } @get_vec2()

define { [3 x float] } @test_add_elem() #0 {
define { [3 x float] } @test_add_elem() {
; SDAG-LABEL: test_add_elem:
; SDAG: bl get_vec2
; SDAG: fmov s2, #1.0
Expand All @@ -140,7 +138,7 @@ define { [3 x float] } @test_add_elem() #0 {
}

declare double @get_double()
define { double, [2 x double] } @test_mismatched_insert() #0 {
define { double, [2 x double] } @test_mismatched_insert() {
; COMMON-LABEL: test_mismatched_insert:
; COMMON: bl get_double
; COMMON: bl get_double
Expand All @@ -157,5 +155,3 @@ define { double, [2 x double] } @test_mismatched_insert() #0 {

ret { double, [2 x double] } %res.012
}

attributes #0 = { uwtable }
31 changes: 12 additions & 19 deletions llvm/test/CodeGen/AArch64/tailcc-tail-call.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,18 +16,17 @@ define tailcc void @caller_to0_from0() nounwind {
; COMMON-NEXT: b callee_stack0
}

define tailcc void @caller_to0_from8([8 x i64], i64) #0 {
define tailcc void @caller_to0_from8([8 x i64], i64) {
; COMMON-LABEL: caller_to0_from8:

tail call tailcc void @callee_stack0()
ret void

; COMMON: add sp, sp, #16
; COMMON: .cfi_def_cfa_offset -16
; COMMON-NEXT: b callee_stack0
}

define tailcc void @caller_to8_from0() "frame-pointer"="all" uwtable {
define tailcc void @caller_to8_from0() "frame-pointer"="all"{
; COMMON-LABEL: caller_to8_from0:

; Key point is that the "42" should go #16 below incoming stack
Expand All @@ -41,13 +40,10 @@ define tailcc void @caller_to8_from0() "frame-pointer"="all" uwtable {
; from an interrupt if the kernel does not honour a red-zone, and a larger
; call could well overflow the red zone even if it is present.
; COMMON-NOT: sub sp,
; COMMON-NEXT: .cfi_def_cfa_offset 16
; COMMON-NEXT: .cfi_restore w30
; COMMON-NEXT: .cfi_restore w29
; COMMON-NEXT: b callee_stack8
}

define tailcc void @caller_to8_from8([8 x i64], i64 %a) #0 {
define tailcc void @caller_to8_from8([8 x i64], i64 %a) {
; COMMON-LABEL: caller_to8_from8:
; COMMON-NOT: sub sp,

Expand All @@ -59,7 +55,7 @@ define tailcc void @caller_to8_from8([8 x i64], i64 %a) #0 {
; COMMON-NEXT: b callee_stack8
}

define tailcc void @caller_to16_from8([8 x i64], i64 %a) #0 {
define tailcc void @caller_to16_from8([8 x i64], i64 %a) {
; COMMON-LABEL: caller_to16_from8:
; COMMON-NOT: sub sp,

Expand All @@ -74,7 +70,7 @@ define tailcc void @caller_to16_from8([8 x i64], i64 %a) #0 {
}


define tailcc void @caller_to8_from24([8 x i64], i64 %a, i64 %b, i64 %c) #0 {
define tailcc void @caller_to8_from24([8 x i64], i64 %a, i64 %b, i64 %c) {
; COMMON-LABEL: caller_to8_from24:
; COMMON-NOT: sub sp,

Expand All @@ -83,12 +79,11 @@ define tailcc void @caller_to8_from24([8 x i64], i64 %a, i64 %b, i64 %c) #0 {
ret void

; COMMON: str {{x[0-9]+}}, [sp, #16]!
; COMMON-NEXT: .cfi_def_cfa_offset -16
; COMMON-NEXT: b callee_stack8
}


define tailcc void @caller_to16_from16([8 x i64], i64 %a, i64 %b) #0 {
define tailcc void @caller_to16_from16([8 x i64], i64 %a, i64 %b) {
; COMMON-LABEL: caller_to16_from16:
; COMMON-NOT: sub sp,

Expand All @@ -115,7 +110,7 @@ define tailcc void @disable_tail_calls() nounwind "disable-tail-calls"="true" {

; Weakly-referenced extern functions cannot be tail-called, as AAELF does
; not define the behaviour of branch instructions to undefined weak symbols.
define tailcc void @caller_weak() #0 {
define tailcc void @caller_weak() {
; COMMON-LABEL: caller_weak:
; COMMON: bl callee_weak
tail call void @callee_weak()
Expand All @@ -124,7 +119,7 @@ define tailcc void @caller_weak() #0 {

declare { [2 x float] } @get_vec2()

define { [3 x float] } @test_add_elem() #0 {
define { [3 x float] } @test_add_elem() {
; SDAG-LABEL: test_add_elem:
; SDAG: bl get_vec2
; SDAG: fmov s2, #1.0
Expand All @@ -148,7 +143,7 @@ define { [3 x float] } @test_add_elem() #0 {
}

declare double @get_double()
define { double, [2 x double] } @test_mismatched_insert() #0 {
define { double, [2 x double] } @test_mismatched_insert() {
; COMMON-LABEL: test_mismatched_insert:
; COMMON: bl get_double
; COMMON: bl get_double
Expand All @@ -166,7 +161,7 @@ define { double, [2 x double] } @test_mismatched_insert() #0 {
ret { double, [2 x double] } %res.012
}

define void @fromC_totail() #0 {
define void @fromC_totail() {
; COMMON-LABEL: fromC_totail:
; COMMON: sub sp, sp, #32

Expand All @@ -184,7 +179,7 @@ define void @fromC_totail() #0 {
ret void
}

define void @fromC_totail_noreservedframe(i32 %len) #0 {
define void @fromC_totail_noreservedframe(i32 %len) {
; COMMON-LABEL: fromC_totail_noreservedframe:
; COMMON: stp x29, x30, [sp, #-32]!

Expand All @@ -208,7 +203,7 @@ define void @fromC_totail_noreservedframe(i32 %len) #0 {

declare void @Ccallee_stack8([8 x i64], i64)

define tailcc void @fromtail_toC() #0 {
define tailcc void @fromtail_toC() {
; COMMON-LABEL: fromtail_toC:
; COMMON: sub sp, sp, #32

Expand All @@ -228,5 +223,3 @@ define tailcc void @fromtail_toC() #0 {
call void @Ccallee_stack8([8 x i64] undef, i64 42)
ret void
}

attributes #0 = { uwtable }
132 changes: 2 additions & 130 deletions llvm/test/CodeGen/AArch64/unwind-preserved.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -O0 -global-isel=1 -global-isel-abort=0 < %s | FileCheck %s --check-prefix=GISEL

; Test that z0 is saved/restored, as the unwinder may only retain the low 64bits (d0).
define <vscale x 4 x i32> @invoke_callee_may_throw_sve(<vscale x 4 x i32> %v) uwtable personality i8 0 {
define <vscale x 4 x i32> @invoke_callee_may_throw_sve(<vscale x 4 x i32> %v) personality i8 0 {
; CHECK-LABEL: invoke_callee_may_throw_sve:
; CHECK: .Lfunc_begin0:
; CHECK-NEXT: .cfi_startproc
Expand Down Expand Up @@ -61,7 +61,6 @@ define <vscale x 4 x i32> @invoke_callee_may_throw_sve(<vscale x 4 x i32> %v) uw
; CHECK-NEXT: .LBB0_1: // %.Lcontinue
; CHECK-NEXT: ldr z0, [sp, #1, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x90, 0x01, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 144 * VG
; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload
Expand Down Expand Up @@ -91,25 +90,12 @@ define <vscale x 4 x i32> @invoke_callee_may_throw_sve(<vscale x 4 x i32> %v) uw
; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #18
; CHECK-NEXT: .cfi_def_cfa wsp, 16
; CHECK-NEXT: .cfi_restore z8
; CHECK-NEXT: .cfi_restore z9
; CHECK-NEXT: .cfi_restore z10
; CHECK-NEXT: .cfi_restore z11
; CHECK-NEXT: .cfi_restore z12
; CHECK-NEXT: .cfi_restore z13
; CHECK-NEXT: .cfi_restore z14
; CHECK-NEXT: .cfi_restore z15
; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w30
; CHECK-NEXT: .cfi_restore w29
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB0_2: // %.Lunwind
; CHECK-NEXT: .Ltmp2:
; CHECK-NEXT: ldr z0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x90, 0x01, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 144 * VG
; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload
Expand Down Expand Up @@ -139,19 +125,7 @@ define <vscale x 4 x i32> @invoke_callee_may_throw_sve(<vscale x 4 x i32> %v) uw
; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #18
; CHECK-NEXT: .cfi_def_cfa wsp, 16
; CHECK-NEXT: .cfi_restore z8
; CHECK-NEXT: .cfi_restore z9
; CHECK-NEXT: .cfi_restore z10
; CHECK-NEXT: .cfi_restore z11
; CHECK-NEXT: .cfi_restore z12
; CHECK-NEXT: .cfi_restore z13
; CHECK-NEXT: .cfi_restore z14
; CHECK-NEXT: .cfi_restore z15
; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w30
; CHECK-NEXT: .cfi_restore w29
; CHECK-NEXT: ret
;
; GISEL-LABEL: invoke_callee_may_throw_sve:
Expand Down Expand Up @@ -211,7 +185,6 @@ define <vscale x 4 x i32> @invoke_callee_may_throw_sve(<vscale x 4 x i32> %v) uw
; GISEL-NEXT: .LBB0_1: // %.Lcontinue
; GISEL-NEXT: ldr z0, [sp, #1, mul vl] // 16-byte Folded Reload
; GISEL-NEXT: addvl sp, sp, #2
; GISEL-NEXT: .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x90, 0x01, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 144 * VG
; GISEL-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload
; GISEL-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload
; GISEL-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload
Expand Down Expand Up @@ -241,25 +214,12 @@ define <vscale x 4 x i32> @invoke_callee_may_throw_sve(<vscale x 4 x i32> %v) uw
; GISEL-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload
; GISEL-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload
; GISEL-NEXT: addvl sp, sp, #18
; GISEL-NEXT: .cfi_def_cfa wsp, 16
; GISEL-NEXT: .cfi_restore z8
; GISEL-NEXT: .cfi_restore z9
; GISEL-NEXT: .cfi_restore z10
; GISEL-NEXT: .cfi_restore z11
; GISEL-NEXT: .cfi_restore z12
; GISEL-NEXT: .cfi_restore z13
; GISEL-NEXT: .cfi_restore z14
; GISEL-NEXT: .cfi_restore z15
; GISEL-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; GISEL-NEXT: .cfi_def_cfa_offset 0
; GISEL-NEXT: .cfi_restore w30
; GISEL-NEXT: .cfi_restore w29
; GISEL-NEXT: ret
; GISEL-NEXT: .LBB0_2: // %.Lunwind
; GISEL-NEXT: .Ltmp2:
; GISEL-NEXT: ldr z0, [sp] // 16-byte Folded Reload
; GISEL-NEXT: addvl sp, sp, #2
; GISEL-NEXT: .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x90, 0x01, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 144 * VG
; GISEL-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload
; GISEL-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload
; GISEL-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload
Expand Down Expand Up @@ -289,19 +249,7 @@ define <vscale x 4 x i32> @invoke_callee_may_throw_sve(<vscale x 4 x i32> %v) uw
; GISEL-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload
; GISEL-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload
; GISEL-NEXT: addvl sp, sp, #18
; GISEL-NEXT: .cfi_def_cfa wsp, 16
; GISEL-NEXT: .cfi_restore z8
; GISEL-NEXT: .cfi_restore z9
; GISEL-NEXT: .cfi_restore z10
; GISEL-NEXT: .cfi_restore z11
; GISEL-NEXT: .cfi_restore z12
; GISEL-NEXT: .cfi_restore z13
; GISEL-NEXT: .cfi_restore z14
; GISEL-NEXT: .cfi_restore z15
; GISEL-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; GISEL-NEXT: .cfi_def_cfa_offset 0
; GISEL-NEXT: .cfi_restore w30
; GISEL-NEXT: .cfi_restore w29
; GISEL-NEXT: ret
%result = invoke <vscale x 4 x i32> @may_throw_sve(<vscale x 4 x i32> %v) to label %.Lcontinue unwind label %.Lunwind
.Lcontinue:
Expand All @@ -315,7 +263,7 @@ declare <vscale x 4 x i32> @may_throw_sve(<vscale x 4 x i32> %v);


; Test that q0 is saved/restored, as the unwinder may only retain the low 64bits (d0).
define aarch64_vector_pcs <4 x i32> @invoke_callee_may_throw_neon(<4 x i32> %v) uwtable personality i8 0 {
define aarch64_vector_pcs <4 x i32> @invoke_callee_may_throw_neon(<4 x i32> %v) personality i8 0 {
; CHECK-LABEL: invoke_callee_may_throw_neon:
; CHECK: .Lfunc_begin1:
; CHECK-NEXT: .cfi_startproc
Expand Down Expand Up @@ -367,25 +315,6 @@ define aarch64_vector_pcs <4 x i32> @invoke_callee_may_throw_neon(<4 x i32> %v)
; CHECK-NEXT: ldp q21, q20, [sp, #64] // 32-byte Folded Reload
; CHECK-NEXT: ldp q23, q22, [sp, #32] // 32-byte Folded Reload
; CHECK-NEXT: add sp, sp, #304
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w30
; CHECK-NEXT: .cfi_restore w29
; CHECK-NEXT: .cfi_restore b8
; CHECK-NEXT: .cfi_restore b9
; CHECK-NEXT: .cfi_restore b10
; CHECK-NEXT: .cfi_restore b11
; CHECK-NEXT: .cfi_restore b12
; CHECK-NEXT: .cfi_restore b13
; CHECK-NEXT: .cfi_restore b14
; CHECK-NEXT: .cfi_restore b15
; CHECK-NEXT: .cfi_restore b16
; CHECK-NEXT: .cfi_restore b17
; CHECK-NEXT: .cfi_restore b18
; CHECK-NEXT: .cfi_restore b19
; CHECK-NEXT: .cfi_restore b20
; CHECK-NEXT: .cfi_restore b21
; CHECK-NEXT: .cfi_restore b22
; CHECK-NEXT: .cfi_restore b23
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB1_2: // %.Lunwind
; CHECK-NEXT: .Ltmp5:
Expand All @@ -400,25 +329,6 @@ define aarch64_vector_pcs <4 x i32> @invoke_callee_may_throw_neon(<4 x i32> %v)
; CHECK-NEXT: ldp q21, q20, [sp, #64] // 32-byte Folded Reload
; CHECK-NEXT: ldp q23, q22, [sp, #32] // 32-byte Folded Reload
; CHECK-NEXT: add sp, sp, #304
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w30
; CHECK-NEXT: .cfi_restore w29
; CHECK-NEXT: .cfi_restore b8
; CHECK-NEXT: .cfi_restore b9
; CHECK-NEXT: .cfi_restore b10
; CHECK-NEXT: .cfi_restore b11
; CHECK-NEXT: .cfi_restore b12
; CHECK-NEXT: .cfi_restore b13
; CHECK-NEXT: .cfi_restore b14
; CHECK-NEXT: .cfi_restore b15
; CHECK-NEXT: .cfi_restore b16
; CHECK-NEXT: .cfi_restore b17
; CHECK-NEXT: .cfi_restore b18
; CHECK-NEXT: .cfi_restore b19
; CHECK-NEXT: .cfi_restore b20
; CHECK-NEXT: .cfi_restore b21
; CHECK-NEXT: .cfi_restore b22
; CHECK-NEXT: .cfi_restore b23
; CHECK-NEXT: ret
;
; GISEL-LABEL: invoke_callee_may_throw_neon:
Expand Down Expand Up @@ -472,25 +382,6 @@ define aarch64_vector_pcs <4 x i32> @invoke_callee_may_throw_neon(<4 x i32> %v)
; GISEL-NEXT: ldp q21, q20, [sp, #64] // 32-byte Folded Reload
; GISEL-NEXT: ldp q23, q22, [sp, #32] // 32-byte Folded Reload
; GISEL-NEXT: add sp, sp, #304
; GISEL-NEXT: .cfi_def_cfa_offset 0
; GISEL-NEXT: .cfi_restore w30
; GISEL-NEXT: .cfi_restore w29
; GISEL-NEXT: .cfi_restore b8
; GISEL-NEXT: .cfi_restore b9
; GISEL-NEXT: .cfi_restore b10
; GISEL-NEXT: .cfi_restore b11
; GISEL-NEXT: .cfi_restore b12
; GISEL-NEXT: .cfi_restore b13
; GISEL-NEXT: .cfi_restore b14
; GISEL-NEXT: .cfi_restore b15
; GISEL-NEXT: .cfi_restore b16
; GISEL-NEXT: .cfi_restore b17
; GISEL-NEXT: .cfi_restore b18
; GISEL-NEXT: .cfi_restore b19
; GISEL-NEXT: .cfi_restore b20
; GISEL-NEXT: .cfi_restore b21
; GISEL-NEXT: .cfi_restore b22
; GISEL-NEXT: .cfi_restore b23
; GISEL-NEXT: ret
; GISEL-NEXT: .LBB1_2: // %.Lunwind
; GISEL-NEXT: .Ltmp5:
Expand All @@ -505,25 +396,6 @@ define aarch64_vector_pcs <4 x i32> @invoke_callee_may_throw_neon(<4 x i32> %v)
; GISEL-NEXT: ldp q21, q20, [sp, #64] // 32-byte Folded Reload
; GISEL-NEXT: ldp q23, q22, [sp, #32] // 32-byte Folded Reload
; GISEL-NEXT: add sp, sp, #304
; GISEL-NEXT: .cfi_def_cfa_offset 0
; GISEL-NEXT: .cfi_restore w30
; GISEL-NEXT: .cfi_restore w29
; GISEL-NEXT: .cfi_restore b8
; GISEL-NEXT: .cfi_restore b9
; GISEL-NEXT: .cfi_restore b10
; GISEL-NEXT: .cfi_restore b11
; GISEL-NEXT: .cfi_restore b12
; GISEL-NEXT: .cfi_restore b13
; GISEL-NEXT: .cfi_restore b14
; GISEL-NEXT: .cfi_restore b15
; GISEL-NEXT: .cfi_restore b16
; GISEL-NEXT: .cfi_restore b17
; GISEL-NEXT: .cfi_restore b18
; GISEL-NEXT: .cfi_restore b19
; GISEL-NEXT: .cfi_restore b20
; GISEL-NEXT: .cfi_restore b21
; GISEL-NEXT: .cfi_restore b22
; GISEL-NEXT: .cfi_restore b23
; GISEL-NEXT: ret
%result = invoke aarch64_vector_pcs <4 x i32> @may_throw_neon(<4 x i32> %v) to label %.Lcontinue unwind label %.Lunwind
.Lcontinue:
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7 changes: 1 addition & 6 deletions llvm/test/Transforms/CodeGenPrepare/AArch64/large-offset-gep.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -134,7 +134,7 @@ while_end:
declare %struct_type* @foo()
declare void @foo2()

define void @test4(i32 %n) uwtable personality i32 (...)* @__FrameHandler {
define void @test4(i32 %n) personality i32 (...)* @__FrameHandler {
; CHECK-LABEL: test4:
; CHECK: .Lfunc_begin0:
; CHECK-NEXT: .cfi_startproc
Expand Down Expand Up @@ -171,11 +171,6 @@ define void @test4(i32 %n) uwtable personality i32 (...)* @__FrameHandler {
; CHECK-NEXT: .LBB3_4: // %while_end
; CHECK-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: ldp x30, x21, [sp], #32 // 16-byte Folded Reload
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w19
; CHECK-NEXT: .cfi_restore w20
; CHECK-NEXT: .cfi_restore w21
; CHECK-NEXT: .cfi_restore w30
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB3_5: // %cleanup
; CHECK-NEXT: .Ltmp2:
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12 changes: 2 additions & 10 deletions ...ateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll.generated.expected
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Original file line number Diff line number Diff line change
Expand Up @@ -90,13 +90,9 @@ attributes #0 = { noredzone nounwind ssp uwtable "frame-pointer"="all" }
; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: bl OUTLINED_FUNCTION_0
; CHECK-NEXT: .LBB0_5:
; CHECK-NEXT: mov w0, wzr
; CHECK-NEXT: .cfi_def_cfa wsp, 48
; CHECK-NEXT: ldp x29, x30, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: mov w0, wzr
; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w30
; CHECK-NEXT: .cfi_restore w29
; CHECK-NEXT: ret
;
; CHECK-LABEL: main:
Expand All @@ -121,13 +117,9 @@ attributes #0 = { noredzone nounwind ssp uwtable "frame-pointer"="all" }
; CHECK-NEXT: //APP
; CHECK-NEXT: //NO_APP
; CHECK-NEXT: stp w10, w8, [x29, #-12]
; CHECK-NEXT: stp w9, w11, [sp, #12]
; CHECK-NEXT: .cfi_def_cfa wsp, 48
; CHECK-NEXT: ldp x29, x30, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: stp w9, w11, [sp, #12]
; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w30
; CHECK-NEXT: .cfi_restore w29
; CHECK-NEXT: ret
;
; CHECK-LABEL: OUTLINED_FUNCTION_0:
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12 changes: 2 additions & 10 deletions ...eTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll.nogenerated.expected
View file
Original file line number Diff line number Diff line change
Expand Up @@ -31,13 +31,9 @@ define dso_local i32 @check_boundaries() #0 {
; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: bl OUTLINED_FUNCTION_0
; CHECK-NEXT: .LBB0_5:
; CHECK-NEXT: mov w0, wzr
; CHECK-NEXT: .cfi_def_cfa wsp, 48
; CHECK-NEXT: ldp x29, x30, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: mov w0, wzr
; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w30
; CHECK-NEXT: .cfi_restore w29
; CHECK-NEXT: ret
%1 = alloca i32, align 4
%2 = alloca i32, align 4
Expand Down Expand Up @@ -98,13 +94,9 @@ define dso_local i32 @main() #0 {
; CHECK-NEXT: //APP
; CHECK-NEXT: //NO_APP
; CHECK-NEXT: stp w10, w8, [x29, #-12]
; CHECK-NEXT: stp w9, w11, [sp, #12]
; CHECK-NEXT: .cfi_def_cfa wsp, 48
; CHECK-NEXT: ldp x29, x30, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: stp w9, w11, [sp, #12]
; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w30
; CHECK-NEXT: .cfi_restore w29
; CHECK-NEXT: ret
%1 = alloca i32, align 4
%2 = alloca i32, align 4
Expand Down