85 changes: 85 additions & 0 deletions llvm/test/CodeGen/RISCV/atomicrmw-cond-sub-clamp.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -51,7 +51,12 @@ define i8 @atomicrmw_usub_cond_i8(ptr %ptr, i8 %val) {
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: .cfi_restore s0
; RV32I-NEXT: .cfi_restore s1
; RV32I-NEXT: .cfi_restore s2
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomicrmw_usub_cond_i8:
Expand Down Expand Up @@ -129,7 +134,12 @@ define i8 @atomicrmw_usub_cond_i8(ptr %ptr, i8 %val) {
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: .cfi_restore s0
; RV64I-NEXT: .cfi_restore s1
; RV64I-NEXT: .cfi_restore s2
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_usub_cond_i8:
Expand Down Expand Up @@ -216,7 +226,13 @@ define i16 @atomicrmw_usub_cond_i16(ptr %ptr, i16 %val) {
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: .cfi_restore s0
; RV32I-NEXT: .cfi_restore s1
; RV32I-NEXT: .cfi_restore s2
; RV32I-NEXT: .cfi_restore s3
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomicrmw_usub_cond_i16:
Expand Down Expand Up @@ -300,7 +316,13 @@ define i16 @atomicrmw_usub_cond_i16(ptr %ptr, i16 %val) {
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: .cfi_restore s0
; RV64I-NEXT: .cfi_restore s1
; RV64I-NEXT: .cfi_restore s2
; RV64I-NEXT: .cfi_restore s3
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_usub_cond_i16:
Expand Down Expand Up @@ -378,7 +400,11 @@ define i32 @atomicrmw_usub_cond_i32(ptr %ptr, i32 %val) {
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: .cfi_restore s0
; RV32I-NEXT: .cfi_restore s1
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomicrmw_usub_cond_i32:
Expand Down Expand Up @@ -442,7 +468,12 @@ define i32 @atomicrmw_usub_cond_i32(ptr %ptr, i32 %val) {
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: .cfi_restore s0
; RV64I-NEXT: .cfi_restore s1
; RV64I-NEXT: .cfi_restore s2
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_usub_cond_i32:
Expand Down Expand Up @@ -529,7 +560,12 @@ define i64 @atomicrmw_usub_cond_i64(ptr %ptr, i64 %val) {
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: .cfi_restore s0
; RV32I-NEXT: .cfi_restore s1
; RV32I-NEXT: .cfi_restore s2
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomicrmw_usub_cond_i64:
Expand Down Expand Up @@ -586,7 +622,12 @@ define i64 @atomicrmw_usub_cond_i64(ptr %ptr, i64 %val) {
; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32IA-NEXT: .cfi_restore ra
; RV32IA-NEXT: .cfi_restore s0
; RV32IA-NEXT: .cfi_restore s1
; RV32IA-NEXT: .cfi_restore s2
; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: .cfi_def_cfa_offset 0
; RV32IA-NEXT: ret
;
; RV64I-LABEL: atomicrmw_usub_cond_i64:
Expand Down Expand Up @@ -621,7 +662,11 @@ define i64 @atomicrmw_usub_cond_i64(ptr %ptr, i64 %val) {
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: .cfi_restore s0
; RV64I-NEXT: .cfi_restore s1
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_usub_cond_i64:
Expand Down Expand Up @@ -686,7 +731,11 @@ define i8 @atomicrmw_usub_sat_i8(ptr %ptr, i8 %val) {
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: .cfi_restore s0
; RV32I-NEXT: .cfi_restore s1
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomicrmw_usub_sat_i8:
Expand Down Expand Up @@ -759,7 +808,11 @@ define i8 @atomicrmw_usub_sat_i8(ptr %ptr, i8 %val) {
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: .cfi_restore s0
; RV64I-NEXT: .cfi_restore s1
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_usub_sat_i8:
Expand Down Expand Up @@ -841,7 +894,12 @@ define i16 @atomicrmw_usub_sat_i16(ptr %ptr, i16 %val) {
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: .cfi_restore s0
; RV32I-NEXT: .cfi_restore s1
; RV32I-NEXT: .cfi_restore s2
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomicrmw_usub_sat_i16:
Expand Down Expand Up @@ -920,7 +978,12 @@ define i16 @atomicrmw_usub_sat_i16(ptr %ptr, i16 %val) {
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: .cfi_restore s0
; RV64I-NEXT: .cfi_restore s1
; RV64I-NEXT: .cfi_restore s2
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_usub_sat_i16:
Expand Down Expand Up @@ -997,7 +1060,11 @@ define i32 @atomicrmw_usub_sat_i32(ptr %ptr, i32 %val) {
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: .cfi_restore s0
; RV32I-NEXT: .cfi_restore s1
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomicrmw_usub_sat_i32:
Expand Down Expand Up @@ -1057,7 +1124,11 @@ define i32 @atomicrmw_usub_sat_i32(ptr %ptr, i32 %val) {
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: .cfi_restore s0
; RV64I-NEXT: .cfi_restore s1
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_usub_sat_i32:
Expand Down Expand Up @@ -1142,7 +1213,12 @@ define i64 @atomicrmw_usub_sat_i64(ptr %ptr, i64 %val) {
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: .cfi_restore s0
; RV32I-NEXT: .cfi_restore s1
; RV32I-NEXT: .cfi_restore s2
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomicrmw_usub_sat_i64:
Expand Down Expand Up @@ -1198,7 +1274,12 @@ define i64 @atomicrmw_usub_sat_i64(ptr %ptr, i64 %val) {
; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32IA-NEXT: .cfi_restore ra
; RV32IA-NEXT: .cfi_restore s0
; RV32IA-NEXT: .cfi_restore s1
; RV32IA-NEXT: .cfi_restore s2
; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: .cfi_def_cfa_offset 0
; RV32IA-NEXT: ret
;
; RV64I-LABEL: atomicrmw_usub_sat_i64:
Expand Down Expand Up @@ -1233,7 +1314,11 @@ define i64 @atomicrmw_usub_sat_i64(ptr %ptr, i64 %val) {
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: .cfi_restore s0
; RV64I-NEXT: .cfi_restore s1
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_usub_sat_i64:
Expand Down
85 changes: 85 additions & 0 deletions llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -47,7 +47,11 @@ define i8 @atomicrmw_uinc_wrap_i8(ptr %ptr, i8 %val) {
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: .cfi_restore s0
; RV32I-NEXT: .cfi_restore s1
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomicrmw_uinc_wrap_i8:
Expand Down Expand Up @@ -121,7 +125,11 @@ define i8 @atomicrmw_uinc_wrap_i8(ptr %ptr, i8 %val) {
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: .cfi_restore s0
; RV64I-NEXT: .cfi_restore s1
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_uinc_wrap_i8:
Expand Down Expand Up @@ -204,7 +212,12 @@ define i16 @atomicrmw_uinc_wrap_i16(ptr %ptr, i16 %val) {
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: .cfi_restore s0
; RV32I-NEXT: .cfi_restore s1
; RV32I-NEXT: .cfi_restore s2
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomicrmw_uinc_wrap_i16:
Expand Down Expand Up @@ -284,7 +297,12 @@ define i16 @atomicrmw_uinc_wrap_i16(ptr %ptr, i16 %val) {
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: .cfi_restore s0
; RV64I-NEXT: .cfi_restore s1
; RV64I-NEXT: .cfi_restore s2
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_uinc_wrap_i16:
Expand Down Expand Up @@ -362,7 +380,11 @@ define i32 @atomicrmw_uinc_wrap_i32(ptr %ptr, i32 %val) {
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: .cfi_restore s0
; RV32I-NEXT: .cfi_restore s1
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomicrmw_uinc_wrap_i32:
Expand Down Expand Up @@ -422,7 +444,11 @@ define i32 @atomicrmw_uinc_wrap_i32(ptr %ptr, i32 %val) {
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: .cfi_restore s0
; RV64I-NEXT: .cfi_restore s1
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_uinc_wrap_i32:
Expand Down Expand Up @@ -507,7 +533,12 @@ define i64 @atomicrmw_uinc_wrap_i64(ptr %ptr, i64 %val) {
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: .cfi_restore s0
; RV32I-NEXT: .cfi_restore s1
; RV32I-NEXT: .cfi_restore s2
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomicrmw_uinc_wrap_i64:
Expand Down Expand Up @@ -562,7 +593,12 @@ define i64 @atomicrmw_uinc_wrap_i64(ptr %ptr, i64 %val) {
; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32IA-NEXT: .cfi_restore ra
; RV32IA-NEXT: .cfi_restore s0
; RV32IA-NEXT: .cfi_restore s1
; RV32IA-NEXT: .cfi_restore s2
; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: .cfi_def_cfa_offset 0
; RV32IA-NEXT: ret
;
; RV64I-LABEL: atomicrmw_uinc_wrap_i64:
Expand Down Expand Up @@ -597,7 +633,11 @@ define i64 @atomicrmw_uinc_wrap_i64(ptr %ptr, i64 %val) {
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: .cfi_restore s0
; RV64I-NEXT: .cfi_restore s1
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_uinc_wrap_i64:
Expand Down Expand Up @@ -674,7 +714,12 @@ define i8 @atomicrmw_udec_wrap_i8(ptr %ptr, i8 %val) {
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: .cfi_restore s0
; RV32I-NEXT: .cfi_restore s1
; RV32I-NEXT: .cfi_restore s2
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomicrmw_udec_wrap_i8:
Expand Down Expand Up @@ -770,7 +815,12 @@ define i8 @atomicrmw_udec_wrap_i8(ptr %ptr, i8 %val) {
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: .cfi_restore s0
; RV64I-NEXT: .cfi_restore s1
; RV64I-NEXT: .cfi_restore s2
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_udec_wrap_i8:
Expand Down Expand Up @@ -875,7 +925,13 @@ define i16 @atomicrmw_udec_wrap_i16(ptr %ptr, i16 %val) {
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: .cfi_restore s0
; RV32I-NEXT: .cfi_restore s1
; RV32I-NEXT: .cfi_restore s2
; RV32I-NEXT: .cfi_restore s3
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomicrmw_udec_wrap_i16:
Expand Down Expand Up @@ -977,7 +1033,13 @@ define i16 @atomicrmw_udec_wrap_i16(ptr %ptr, i16 %val) {
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: .cfi_restore s0
; RV64I-NEXT: .cfi_restore s1
; RV64I-NEXT: .cfi_restore s2
; RV64I-NEXT: .cfi_restore s3
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_udec_wrap_i16:
Expand Down Expand Up @@ -1073,7 +1135,11 @@ define i32 @atomicrmw_udec_wrap_i32(ptr %ptr, i32 %val) {
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: .cfi_restore s0
; RV32I-NEXT: .cfi_restore s1
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomicrmw_udec_wrap_i32:
Expand Down Expand Up @@ -1155,7 +1221,12 @@ define i32 @atomicrmw_udec_wrap_i32(ptr %ptr, i32 %val) {
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: .cfi_restore s0
; RV64I-NEXT: .cfi_restore s1
; RV64I-NEXT: .cfi_restore s2
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_udec_wrap_i32:
Expand Down Expand Up @@ -1258,7 +1329,12 @@ define i64 @atomicrmw_udec_wrap_i64(ptr %ptr, i64 %val) {
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: .cfi_restore s0
; RV32I-NEXT: .cfi_restore s1
; RV32I-NEXT: .cfi_restore s2
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomicrmw_udec_wrap_i64:
Expand Down Expand Up @@ -1321,7 +1397,12 @@ define i64 @atomicrmw_udec_wrap_i64(ptr %ptr, i64 %val) {
; RV32IA-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32IA-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32IA-NEXT: .cfi_restore ra
; RV32IA-NEXT: .cfi_restore s0
; RV32IA-NEXT: .cfi_restore s1
; RV32IA-NEXT: .cfi_restore s2
; RV32IA-NEXT: addi sp, sp, 32
; RV32IA-NEXT: .cfi_def_cfa_offset 0
; RV32IA-NEXT: ret
;
; RV64I-LABEL: atomicrmw_udec_wrap_i64:
Expand Down Expand Up @@ -1364,7 +1445,11 @@ define i64 @atomicrmw_udec_wrap_i64(ptr %ptr, i64 %val) {
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: .cfi_restore s0
; RV64I-NEXT: .cfi_restore s1
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_udec_wrap_i64:
Expand Down
148 changes: 148 additions & 0 deletions llvm/test/CodeGen/RISCV/branch-relaxation.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -306,7 +306,21 @@ define void @relax_jal_spill_32() {
; CHECK-RV32-NEXT: lw s9, 20(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw s10, 16(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw s11, 12(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: .cfi_restore ra
; CHECK-RV32-NEXT: .cfi_restore s0
; CHECK-RV32-NEXT: .cfi_restore s1
; CHECK-RV32-NEXT: .cfi_restore s2
; CHECK-RV32-NEXT: .cfi_restore s3
; CHECK-RV32-NEXT: .cfi_restore s4
; CHECK-RV32-NEXT: .cfi_restore s5
; CHECK-RV32-NEXT: .cfi_restore s6
; CHECK-RV32-NEXT: .cfi_restore s7
; CHECK-RV32-NEXT: .cfi_restore s8
; CHECK-RV32-NEXT: .cfi_restore s9
; CHECK-RV32-NEXT: .cfi_restore s10
; CHECK-RV32-NEXT: .cfi_restore s11
; CHECK-RV32-NEXT: addi sp, sp, 64
; CHECK-RV32-NEXT: .cfi_def_cfa_offset 0
; CHECK-RV32-NEXT: ret
;
; CHECK-RV64-LABEL: relax_jal_spill_32:
Expand Down Expand Up @@ -534,7 +548,21 @@ define void @relax_jal_spill_32() {
; CHECK-RV64-NEXT: ld s9, 40(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld s10, 32(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld s11, 24(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: .cfi_restore ra
; CHECK-RV64-NEXT: .cfi_restore s0
; CHECK-RV64-NEXT: .cfi_restore s1
; CHECK-RV64-NEXT: .cfi_restore s2
; CHECK-RV64-NEXT: .cfi_restore s3
; CHECK-RV64-NEXT: .cfi_restore s4
; CHECK-RV64-NEXT: .cfi_restore s5
; CHECK-RV64-NEXT: .cfi_restore s6
; CHECK-RV64-NEXT: .cfi_restore s7
; CHECK-RV64-NEXT: .cfi_restore s8
; CHECK-RV64-NEXT: .cfi_restore s9
; CHECK-RV64-NEXT: .cfi_restore s10
; CHECK-RV64-NEXT: .cfi_restore s11
; CHECK-RV64-NEXT: addi sp, sp, 128
; CHECK-RV64-NEXT: .cfi_def_cfa_offset 0
; CHECK-RV64-NEXT: ret

%ra = call i32 asm sideeffect "addi ra, x0, 1", "={ra}"()
Expand Down Expand Up @@ -825,6 +853,7 @@ define void @relax_jal_spill_32_adjust_spill_slot() {
; CHECK-RV32-NEXT: # reg use t6
; CHECK-RV32-NEXT: #NO_APP
; CHECK-RV32-NEXT: addi sp, s0, -2032
; CHECK-RV32-NEXT: .cfi_def_cfa sp, 2032
; CHECK-RV32-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw s0, 2024(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw s1, 2020(sp) # 4-byte Folded Reload
Expand All @@ -838,7 +867,21 @@ define void @relax_jal_spill_32_adjust_spill_slot() {
; CHECK-RV32-NEXT: lw s9, 1988(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw s10, 1984(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw s11, 1980(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: .cfi_restore ra
; CHECK-RV32-NEXT: .cfi_restore s0
; CHECK-RV32-NEXT: .cfi_restore s1
; CHECK-RV32-NEXT: .cfi_restore s2
; CHECK-RV32-NEXT: .cfi_restore s3
; CHECK-RV32-NEXT: .cfi_restore s4
; CHECK-RV32-NEXT: .cfi_restore s5
; CHECK-RV32-NEXT: .cfi_restore s6
; CHECK-RV32-NEXT: .cfi_restore s7
; CHECK-RV32-NEXT: .cfi_restore s8
; CHECK-RV32-NEXT: .cfi_restore s9
; CHECK-RV32-NEXT: .cfi_restore s10
; CHECK-RV32-NEXT: .cfi_restore s11
; CHECK-RV32-NEXT: addi sp, sp, 2032
; CHECK-RV32-NEXT: .cfi_def_cfa_offset 0
; CHECK-RV32-NEXT: ret
;
; CHECK-RV64-LABEL: relax_jal_spill_32_adjust_spill_slot:
Expand Down Expand Up @@ -1071,6 +1114,7 @@ define void @relax_jal_spill_32_adjust_spill_slot() {
; CHECK-RV64-NEXT: # reg use t6
; CHECK-RV64-NEXT: #NO_APP
; CHECK-RV64-NEXT: addi sp, s0, -2032
; CHECK-RV64-NEXT: .cfi_def_cfa sp, 2032
; CHECK-RV64-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld s0, 2016(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld s1, 2008(sp) # 8-byte Folded Reload
Expand All @@ -1084,7 +1128,21 @@ define void @relax_jal_spill_32_adjust_spill_slot() {
; CHECK-RV64-NEXT: ld s9, 1944(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld s10, 1936(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld s11, 1928(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: .cfi_restore ra
; CHECK-RV64-NEXT: .cfi_restore s0
; CHECK-RV64-NEXT: .cfi_restore s1
; CHECK-RV64-NEXT: .cfi_restore s2
; CHECK-RV64-NEXT: .cfi_restore s3
; CHECK-RV64-NEXT: .cfi_restore s4
; CHECK-RV64-NEXT: .cfi_restore s5
; CHECK-RV64-NEXT: .cfi_restore s6
; CHECK-RV64-NEXT: .cfi_restore s7
; CHECK-RV64-NEXT: .cfi_restore s8
; CHECK-RV64-NEXT: .cfi_restore s9
; CHECK-RV64-NEXT: .cfi_restore s10
; CHECK-RV64-NEXT: .cfi_restore s11
; CHECK-RV64-NEXT: addi sp, sp, 2032
; CHECK-RV64-NEXT: .cfi_def_cfa_offset 0
; CHECK-RV64-NEXT: ret

; If the stack is large and the offset of BranchRelaxationScratchFrameIndex
Expand Down Expand Up @@ -1489,7 +1547,21 @@ define void @relax_jal_spill_64() {
; CHECK-RV32-NEXT: lw s9, 228(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw s10, 224(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw s11, 220(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: .cfi_restore ra
; CHECK-RV32-NEXT: .cfi_restore s0
; CHECK-RV32-NEXT: .cfi_restore s1
; CHECK-RV32-NEXT: .cfi_restore s2
; CHECK-RV32-NEXT: .cfi_restore s3
; CHECK-RV32-NEXT: .cfi_restore s4
; CHECK-RV32-NEXT: .cfi_restore s5
; CHECK-RV32-NEXT: .cfi_restore s6
; CHECK-RV32-NEXT: .cfi_restore s7
; CHECK-RV32-NEXT: .cfi_restore s8
; CHECK-RV32-NEXT: .cfi_restore s9
; CHECK-RV32-NEXT: .cfi_restore s10
; CHECK-RV32-NEXT: .cfi_restore s11
; CHECK-RV32-NEXT: addi sp, sp, 272
; CHECK-RV32-NEXT: .cfi_def_cfa_offset 0
; CHECK-RV32-NEXT: ret
;
; CHECK-RV64-LABEL: relax_jal_spill_64:
Expand Down Expand Up @@ -1715,7 +1787,21 @@ define void @relax_jal_spill_64() {
; CHECK-RV64-NEXT: ld s9, 24(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld s10, 16(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld s11, 8(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: .cfi_restore ra
; CHECK-RV64-NEXT: .cfi_restore s0
; CHECK-RV64-NEXT: .cfi_restore s1
; CHECK-RV64-NEXT: .cfi_restore s2
; CHECK-RV64-NEXT: .cfi_restore s3
; CHECK-RV64-NEXT: .cfi_restore s4
; CHECK-RV64-NEXT: .cfi_restore s5
; CHECK-RV64-NEXT: .cfi_restore s6
; CHECK-RV64-NEXT: .cfi_restore s7
; CHECK-RV64-NEXT: .cfi_restore s8
; CHECK-RV64-NEXT: .cfi_restore s9
; CHECK-RV64-NEXT: .cfi_restore s10
; CHECK-RV64-NEXT: .cfi_restore s11
; CHECK-RV64-NEXT: addi sp, sp, 112
; CHECK-RV64-NEXT: .cfi_def_cfa_offset 0
; CHECK-RV64-NEXT: ret

%ra = call i64 asm sideeffect "addi ra, x0, 1", "={ra}"()
Expand Down Expand Up @@ -2318,6 +2404,7 @@ define void @relax_jal_spill_64_adjust_spill_slot() {
; CHECK-RV32-NEXT: # reg use t6
; CHECK-RV32-NEXT: #NO_APP
; CHECK-RV32-NEXT: addi sp, s0, -2032
; CHECK-RV32-NEXT: .cfi_def_cfa sp, 2032
; CHECK-RV32-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw s0, 2024(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw s1, 2020(sp) # 4-byte Folded Reload
Expand All @@ -2331,7 +2418,21 @@ define void @relax_jal_spill_64_adjust_spill_slot() {
; CHECK-RV32-NEXT: lw s9, 1988(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw s10, 1984(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw s11, 1980(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: .cfi_restore ra
; CHECK-RV32-NEXT: .cfi_restore s0
; CHECK-RV32-NEXT: .cfi_restore s1
; CHECK-RV32-NEXT: .cfi_restore s2
; CHECK-RV32-NEXT: .cfi_restore s3
; CHECK-RV32-NEXT: .cfi_restore s4
; CHECK-RV32-NEXT: .cfi_restore s5
; CHECK-RV32-NEXT: .cfi_restore s6
; CHECK-RV32-NEXT: .cfi_restore s7
; CHECK-RV32-NEXT: .cfi_restore s8
; CHECK-RV32-NEXT: .cfi_restore s9
; CHECK-RV32-NEXT: .cfi_restore s10
; CHECK-RV32-NEXT: .cfi_restore s11
; CHECK-RV32-NEXT: addi sp, sp, 2032
; CHECK-RV32-NEXT: .cfi_def_cfa_offset 0
; CHECK-RV32-NEXT: ret
;
; CHECK-RV64-LABEL: relax_jal_spill_64_adjust_spill_slot:
Expand Down Expand Up @@ -2552,6 +2653,7 @@ define void @relax_jal_spill_64_adjust_spill_slot() {
; CHECK-RV64-NEXT: # reg use t6
; CHECK-RV64-NEXT: #NO_APP
; CHECK-RV64-NEXT: addi sp, s0, -2032
; CHECK-RV64-NEXT: .cfi_def_cfa sp, 2032
; CHECK-RV64-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld s0, 2016(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld s1, 2008(sp) # 8-byte Folded Reload
Expand All @@ -2565,7 +2667,21 @@ define void @relax_jal_spill_64_adjust_spill_slot() {
; CHECK-RV64-NEXT: ld s9, 1944(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld s10, 1936(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld s11, 1928(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: .cfi_restore ra
; CHECK-RV64-NEXT: .cfi_restore s0
; CHECK-RV64-NEXT: .cfi_restore s1
; CHECK-RV64-NEXT: .cfi_restore s2
; CHECK-RV64-NEXT: .cfi_restore s3
; CHECK-RV64-NEXT: .cfi_restore s4
; CHECK-RV64-NEXT: .cfi_restore s5
; CHECK-RV64-NEXT: .cfi_restore s6
; CHECK-RV64-NEXT: .cfi_restore s7
; CHECK-RV64-NEXT: .cfi_restore s8
; CHECK-RV64-NEXT: .cfi_restore s9
; CHECK-RV64-NEXT: .cfi_restore s10
; CHECK-RV64-NEXT: .cfi_restore s11
; CHECK-RV64-NEXT: addi sp, sp, 2032
; CHECK-RV64-NEXT: .cfi_def_cfa_offset 0
; CHECK-RV64-NEXT: ret

; If the stack is large and the offset of BranchRelaxationScratchFrameIndex
Expand Down Expand Up @@ -2673,6 +2789,7 @@ define void @relax_jal_spill_32_restore_block_correspondence() {
; CHECK-RV32-NEXT: .cfi_offset s9, -44
; CHECK-RV32-NEXT: .cfi_offset s10, -48
; CHECK-RV32-NEXT: .cfi_offset s11, -52
; CHECK-RV32-NEXT: .cfi_remember_state
; CHECK-RV32-NEXT: #APP
; CHECK-RV32-NEXT: li ra, 1
; CHECK-RV32-NEXT: #NO_APP
Expand Down Expand Up @@ -2873,9 +2990,24 @@ define void @relax_jal_spill_32_restore_block_correspondence() {
; CHECK-RV32-NEXT: lw s9, 20(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw s10, 16(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw s11, 12(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: .cfi_restore ra
; CHECK-RV32-NEXT: .cfi_restore s0
; CHECK-RV32-NEXT: .cfi_restore s1
; CHECK-RV32-NEXT: .cfi_restore s2
; CHECK-RV32-NEXT: .cfi_restore s3
; CHECK-RV32-NEXT: .cfi_restore s4
; CHECK-RV32-NEXT: .cfi_restore s5
; CHECK-RV32-NEXT: .cfi_restore s6
; CHECK-RV32-NEXT: .cfi_restore s7
; CHECK-RV32-NEXT: .cfi_restore s8
; CHECK-RV32-NEXT: .cfi_restore s9
; CHECK-RV32-NEXT: .cfi_restore s10
; CHECK-RV32-NEXT: .cfi_restore s11
; CHECK-RV32-NEXT: addi sp, sp, 64
; CHECK-RV32-NEXT: .cfi_def_cfa_offset 0
; CHECK-RV32-NEXT: ret
; CHECK-RV32-NEXT: .LBB6_5: # %cond_3
; CHECK-RV32-NEXT: .cfi_restore_state
; CHECK-RV32-NEXT: beq t1, t2, .LBB6_4
; CHECK-RV32-NEXT: # %bb.6: # %space
; CHECK-RV32-NEXT: #APP
Expand Down Expand Up @@ -2915,6 +3047,7 @@ define void @relax_jal_spill_32_restore_block_correspondence() {
; CHECK-RV64-NEXT: .cfi_offset s9, -88
; CHECK-RV64-NEXT: .cfi_offset s10, -96
; CHECK-RV64-NEXT: .cfi_offset s11, -104
; CHECK-RV64-NEXT: .cfi_remember_state
; CHECK-RV64-NEXT: #APP
; CHECK-RV64-NEXT: li ra, 1
; CHECK-RV64-NEXT: #NO_APP
Expand Down Expand Up @@ -3120,9 +3253,24 @@ define void @relax_jal_spill_32_restore_block_correspondence() {
; CHECK-RV64-NEXT: ld s9, 40(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld s10, 32(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: ld s11, 24(sp) # 8-byte Folded Reload
; CHECK-RV64-NEXT: .cfi_restore ra
; CHECK-RV64-NEXT: .cfi_restore s0
; CHECK-RV64-NEXT: .cfi_restore s1
; CHECK-RV64-NEXT: .cfi_restore s2
; CHECK-RV64-NEXT: .cfi_restore s3
; CHECK-RV64-NEXT: .cfi_restore s4
; CHECK-RV64-NEXT: .cfi_restore s5
; CHECK-RV64-NEXT: .cfi_restore s6
; CHECK-RV64-NEXT: .cfi_restore s7
; CHECK-RV64-NEXT: .cfi_restore s8
; CHECK-RV64-NEXT: .cfi_restore s9
; CHECK-RV64-NEXT: .cfi_restore s10
; CHECK-RV64-NEXT: .cfi_restore s11
; CHECK-RV64-NEXT: addi sp, sp, 128
; CHECK-RV64-NEXT: .cfi_def_cfa_offset 0
; CHECK-RV64-NEXT: ret
; CHECK-RV64-NEXT: .LBB6_5: # %cond_3
; CHECK-RV64-NEXT: .cfi_restore_state
; CHECK-RV64-NEXT: sext.w t5, t2
; CHECK-RV64-NEXT: sext.w t6, t1
; CHECK-RV64-NEXT: beq t6, t5, .LBB6_4
Expand Down
96 changes: 88 additions & 8 deletions llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -432,7 +432,8 @@ define void @callee() nounwind {
; RV32IZCMP-NEXT: sw a0, %lo(var+4)(t0)
; RV32IZCMP-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
; RV32IZCMP-NEXT: sw a0, %lo(var)(t0)
; RV32IZCMP-NEXT: cm.popret {ra, s0-s11}, 96
; RV32IZCMP-NEXT: cm.pop {ra, s0-s11}, 96
; RV32IZCMP-NEXT: ret
;
; RV32IZCMP-WITH-FP-LABEL: callee:
; RV32IZCMP-WITH-FP: # %bb.0:
Expand Down Expand Up @@ -941,7 +942,8 @@ define void @callee() nounwind {
; RV64IZCMP-NEXT: sw a0, %lo(var+4)(t0)
; RV64IZCMP-NEXT: ld a0, 40(sp) # 8-byte Folded Reload
; RV64IZCMP-NEXT: sw a0, %lo(var)(t0)
; RV64IZCMP-NEXT: cm.popret {ra, s0-s11}, 160
; RV64IZCMP-NEXT: cm.pop {ra, s0-s11}, 160
; RV64IZCMP-NEXT: ret
;
; RV64IZCMP-WITH-FP-LABEL: callee:
; RV64IZCMP-WITH-FP: # %bb.0:
Expand Down Expand Up @@ -1611,7 +1613,8 @@ define void @caller() nounwind {
; RV32IZCMP-NEXT: lw a0, 92(sp) # 4-byte Folded Reload
; RV32IZCMP-NEXT: sw a0, %lo(var)(s0)
; RV32IZCMP-NEXT: addi sp, sp, 48
; RV32IZCMP-NEXT: cm.popret {ra, s0-s11}, 112
; RV32IZCMP-NEXT: cm.pop {ra, s0-s11}, 112
; RV32IZCMP-NEXT: ret
;
; RV32IZCMP-WITH-FP-LABEL: caller:
; RV32IZCMP-WITH-FP: # %bb.0:
Expand Down Expand Up @@ -2306,7 +2309,8 @@ define void @caller() nounwind {
; RV64IZCMP-NEXT: ld a0, 168(sp) # 8-byte Folded Reload
; RV64IZCMP-NEXT: sw a0, %lo(var)(s0)
; RV64IZCMP-NEXT: addi sp, sp, 128
; RV64IZCMP-NEXT: cm.popret {ra, s0-s11}, 160
; RV64IZCMP-NEXT: cm.pop {ra, s0-s11}, 160
; RV64IZCMP-NEXT: ret
;
; RV64IZCMP-WITH-FP-LABEL: caller:
; RV64IZCMP-WITH-FP: # %bb.0:
Expand Down Expand Up @@ -2472,7 +2476,9 @@ define void @foo() {
; RV32I-NEXT: li s4, 0
; RV32I-NEXT: #NO_APP
; RV32I-NEXT: lw s4, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: .cfi_restore s4
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret
;
; RV32I-ILP32E-LABEL: foo:
Expand Down Expand Up @@ -2500,7 +2506,11 @@ define void @foo() {
; RV32I-WITH-FP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: lw s4, 4(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: .cfi_restore ra
; RV32I-WITH-FP-NEXT: .cfi_restore s0
; RV32I-WITH-FP-NEXT: .cfi_restore s4
; RV32I-WITH-FP-NEXT: addi sp, sp, 16
; RV32I-WITH-FP-NEXT: .cfi_def_cfa_offset 0
; RV32I-WITH-FP-NEXT: ret
;
; RV32IZCMP-LABEL: foo:
Expand All @@ -2511,7 +2521,10 @@ define void @foo() {
; RV32IZCMP-NEXT: #APP
; RV32IZCMP-NEXT: li s4, 0
; RV32IZCMP-NEXT: #NO_APP
; RV32IZCMP-NEXT: cm.popret {ra, s0-s4}, 32
; RV32IZCMP-NEXT: cm.pop {ra, s0-s4}, 32
; RV32IZCMP-NEXT: .cfi_def_cfa_offset 0
; RV32IZCMP-NEXT: .cfi_restore s4
; RV32IZCMP-NEXT: ret
;
; RV32IZCMP-WITH-FP-LABEL: foo:
; RV32IZCMP-WITH-FP: # %bb.0: # %entry
Expand All @@ -2531,7 +2544,11 @@ define void @foo() {
; RV32IZCMP-WITH-FP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZCMP-WITH-FP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IZCMP-WITH-FP-NEXT: lw s4, 4(sp) # 4-byte Folded Reload
; RV32IZCMP-WITH-FP-NEXT: .cfi_restore ra
; RV32IZCMP-WITH-FP-NEXT: .cfi_restore s0
; RV32IZCMP-WITH-FP-NEXT: .cfi_restore s4
; RV32IZCMP-WITH-FP-NEXT: addi sp, sp, 16
; RV32IZCMP-WITH-FP-NEXT: .cfi_def_cfa_offset 0
; RV32IZCMP-WITH-FP-NEXT: ret
;
; RV64I-LABEL: foo:
Expand All @@ -2544,7 +2561,9 @@ define void @foo() {
; RV64I-NEXT: li s4, 0
; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s4, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: .cfi_restore s4
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret
;
; RV64I-LP64E-LABEL: foo:
Expand Down Expand Up @@ -2572,7 +2591,11 @@ define void @foo() {
; RV64I-WITH-FP-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: ld s4, 8(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: .cfi_restore ra
; RV64I-WITH-FP-NEXT: .cfi_restore s0
; RV64I-WITH-FP-NEXT: .cfi_restore s4
; RV64I-WITH-FP-NEXT: addi sp, sp, 32
; RV64I-WITH-FP-NEXT: .cfi_def_cfa_offset 0
; RV64I-WITH-FP-NEXT: ret
;
; RV64IZCMP-LABEL: foo:
Expand All @@ -2583,7 +2606,10 @@ define void @foo() {
; RV64IZCMP-NEXT: #APP
; RV64IZCMP-NEXT: li s4, 0
; RV64IZCMP-NEXT: #NO_APP
; RV64IZCMP-NEXT: cm.popret {ra, s0-s4}, 48
; RV64IZCMP-NEXT: cm.pop {ra, s0-s4}, 48
; RV64IZCMP-NEXT: .cfi_def_cfa_offset 0
; RV64IZCMP-NEXT: .cfi_restore s4
; RV64IZCMP-NEXT: ret
;
; RV64IZCMP-WITH-FP-LABEL: foo:
; RV64IZCMP-WITH-FP: # %bb.0: # %entry
Expand All @@ -2603,7 +2629,11 @@ define void @foo() {
; RV64IZCMP-WITH-FP-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64IZCMP-WITH-FP-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64IZCMP-WITH-FP-NEXT: ld s4, 8(sp) # 8-byte Folded Reload
; RV64IZCMP-WITH-FP-NEXT: .cfi_restore ra
; RV64IZCMP-WITH-FP-NEXT: .cfi_restore s0
; RV64IZCMP-WITH-FP-NEXT: .cfi_restore s4
; RV64IZCMP-WITH-FP-NEXT: addi sp, sp, 32
; RV64IZCMP-WITH-FP-NEXT: .cfi_def_cfa_offset 0
; RV64IZCMP-WITH-FP-NEXT: ret
entry:
tail call void asm sideeffect "li s4, 0", "~{s4}"()
Expand All @@ -2622,7 +2652,9 @@ define void @bar() {
; RV32I-NEXT: li s11, 0
; RV32I-NEXT: #NO_APP
; RV32I-NEXT: lw s11, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: .cfi_restore s11
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret
;
; RV32I-ILP32E-LABEL: bar:
Expand Down Expand Up @@ -2650,7 +2682,11 @@ define void @bar() {
; RV32I-WITH-FP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: lw s11, 4(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: .cfi_restore ra
; RV32I-WITH-FP-NEXT: .cfi_restore s0
; RV32I-WITH-FP-NEXT: .cfi_restore s11
; RV32I-WITH-FP-NEXT: addi sp, sp, 16
; RV32I-WITH-FP-NEXT: .cfi_def_cfa_offset 0
; RV32I-WITH-FP-NEXT: ret
;
; RV32IZCMP-LABEL: bar:
Expand All @@ -2661,7 +2697,10 @@ define void @bar() {
; RV32IZCMP-NEXT: #APP
; RV32IZCMP-NEXT: li s11, 0
; RV32IZCMP-NEXT: #NO_APP
; RV32IZCMP-NEXT: cm.popret {ra, s0-s11}, 64
; RV32IZCMP-NEXT: cm.pop {ra, s0-s11}, 64
; RV32IZCMP-NEXT: .cfi_def_cfa_offset 0
; RV32IZCMP-NEXT: .cfi_restore s11
; RV32IZCMP-NEXT: ret
;
; RV32IZCMP-WITH-FP-LABEL: bar:
; RV32IZCMP-WITH-FP: # %bb.0: # %entry
Expand All @@ -2681,7 +2720,11 @@ define void @bar() {
; RV32IZCMP-WITH-FP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZCMP-WITH-FP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IZCMP-WITH-FP-NEXT: lw s11, 4(sp) # 4-byte Folded Reload
; RV32IZCMP-WITH-FP-NEXT: .cfi_restore ra
; RV32IZCMP-WITH-FP-NEXT: .cfi_restore s0
; RV32IZCMP-WITH-FP-NEXT: .cfi_restore s11
; RV32IZCMP-WITH-FP-NEXT: addi sp, sp, 16
; RV32IZCMP-WITH-FP-NEXT: .cfi_def_cfa_offset 0
; RV32IZCMP-WITH-FP-NEXT: ret
;
; RV64I-LABEL: bar:
Expand All @@ -2694,7 +2737,9 @@ define void @bar() {
; RV64I-NEXT: li s11, 0
; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s11, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: .cfi_restore s11
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret
;
; RV64I-LP64E-LABEL: bar:
Expand Down Expand Up @@ -2722,7 +2767,11 @@ define void @bar() {
; RV64I-WITH-FP-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: ld s11, 8(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: .cfi_restore ra
; RV64I-WITH-FP-NEXT: .cfi_restore s0
; RV64I-WITH-FP-NEXT: .cfi_restore s11
; RV64I-WITH-FP-NEXT: addi sp, sp, 32
; RV64I-WITH-FP-NEXT: .cfi_def_cfa_offset 0
; RV64I-WITH-FP-NEXT: ret
;
; RV64IZCMP-LABEL: bar:
Expand All @@ -2733,7 +2782,10 @@ define void @bar() {
; RV64IZCMP-NEXT: #APP
; RV64IZCMP-NEXT: li s11, 0
; RV64IZCMP-NEXT: #NO_APP
; RV64IZCMP-NEXT: cm.popret {ra, s0-s11}, 112
; RV64IZCMP-NEXT: cm.pop {ra, s0-s11}, 112
; RV64IZCMP-NEXT: .cfi_def_cfa_offset 0
; RV64IZCMP-NEXT: .cfi_restore s11
; RV64IZCMP-NEXT: ret
;
; RV64IZCMP-WITH-FP-LABEL: bar:
; RV64IZCMP-WITH-FP: # %bb.0: # %entry
Expand All @@ -2753,7 +2805,11 @@ define void @bar() {
; RV64IZCMP-WITH-FP-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64IZCMP-WITH-FP-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64IZCMP-WITH-FP-NEXT: ld s11, 8(sp) # 8-byte Folded Reload
; RV64IZCMP-WITH-FP-NEXT: .cfi_restore ra
; RV64IZCMP-WITH-FP-NEXT: .cfi_restore s0
; RV64IZCMP-WITH-FP-NEXT: .cfi_restore s11
; RV64IZCMP-WITH-FP-NEXT: addi sp, sp, 32
; RV64IZCMP-WITH-FP-NEXT: .cfi_def_cfa_offset 0
; RV64IZCMP-WITH-FP-NEXT: ret
entry:
tail call void asm sideeffect "li s11, 0", "~{s11}"()
Expand All @@ -2777,7 +2833,9 @@ define void @varargs(...) {
; RV32I-NEXT: sw a0, 16(sp)
; RV32I-NEXT: call callee
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret
;
; RV32I-ILP32E-LABEL: varargs:
Expand All @@ -2794,7 +2852,9 @@ define void @varargs(...) {
; RV32I-ILP32E-NEXT: sw a0, 4(sp)
; RV32I-ILP32E-NEXT: call callee
; RV32I-ILP32E-NEXT: lw ra, 0(sp) # 4-byte Folded Reload
; RV32I-ILP32E-NEXT: .cfi_restore ra
; RV32I-ILP32E-NEXT: addi sp, sp, 28
; RV32I-ILP32E-NEXT: .cfi_def_cfa_offset 0
; RV32I-ILP32E-NEXT: ret
;
; RV32I-WITH-FP-LABEL: varargs:
Expand All @@ -2818,7 +2878,10 @@ define void @varargs(...) {
; RV32I-WITH-FP-NEXT: call callee
; RV32I-WITH-FP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: .cfi_restore ra
; RV32I-WITH-FP-NEXT: .cfi_restore s0
; RV32I-WITH-FP-NEXT: addi sp, sp, 48
; RV32I-WITH-FP-NEXT: .cfi_def_cfa_offset 0
; RV32I-WITH-FP-NEXT: ret
;
; RV32IZCMP-LABEL: varargs:
Expand All @@ -2837,7 +2900,9 @@ define void @varargs(...) {
; RV32IZCMP-NEXT: sw a0, 16(sp)
; RV32IZCMP-NEXT: call callee
; RV32IZCMP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZCMP-NEXT: .cfi_restore ra
; RV32IZCMP-NEXT: addi sp, sp, 48
; RV32IZCMP-NEXT: .cfi_def_cfa_offset 0
; RV32IZCMP-NEXT: ret
;
; RV32IZCMP-WITH-FP-LABEL: varargs:
Expand All @@ -2861,7 +2926,10 @@ define void @varargs(...) {
; RV32IZCMP-WITH-FP-NEXT: call callee
; RV32IZCMP-WITH-FP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZCMP-WITH-FP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IZCMP-WITH-FP-NEXT: .cfi_restore ra
; RV32IZCMP-WITH-FP-NEXT: .cfi_restore s0
; RV32IZCMP-WITH-FP-NEXT: addi sp, sp, 48
; RV32IZCMP-WITH-FP-NEXT: .cfi_def_cfa_offset 0
; RV32IZCMP-WITH-FP-NEXT: ret
;
; RV64I-LABEL: varargs:
Expand All @@ -2880,7 +2948,9 @@ define void @varargs(...) {
; RV64I-NEXT: sd a0, 16(sp)
; RV64I-NEXT: call callee
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: addi sp, sp, 80
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret
;
; RV64I-LP64E-LABEL: varargs:
Expand All @@ -2897,7 +2967,9 @@ define void @varargs(...) {
; RV64I-LP64E-NEXT: sd a0, 8(sp)
; RV64I-LP64E-NEXT: call callee
; RV64I-LP64E-NEXT: ld ra, 0(sp) # 8-byte Folded Reload
; RV64I-LP64E-NEXT: .cfi_restore ra
; RV64I-LP64E-NEXT: addi sp, sp, 56
; RV64I-LP64E-NEXT: .cfi_def_cfa_offset 0
; RV64I-LP64E-NEXT: ret
;
; RV64I-WITH-FP-LABEL: varargs:
Expand All @@ -2921,7 +2993,10 @@ define void @varargs(...) {
; RV64I-WITH-FP-NEXT: call callee
; RV64I-WITH-FP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: .cfi_restore ra
; RV64I-WITH-FP-NEXT: .cfi_restore s0
; RV64I-WITH-FP-NEXT: addi sp, sp, 80
; RV64I-WITH-FP-NEXT: .cfi_def_cfa_offset 0
; RV64I-WITH-FP-NEXT: ret
;
; RV64IZCMP-LABEL: varargs:
Expand All @@ -2940,7 +3015,9 @@ define void @varargs(...) {
; RV64IZCMP-NEXT: sd a0, 16(sp)
; RV64IZCMP-NEXT: call callee
; RV64IZCMP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZCMP-NEXT: .cfi_restore ra
; RV64IZCMP-NEXT: addi sp, sp, 80
; RV64IZCMP-NEXT: .cfi_def_cfa_offset 0
; RV64IZCMP-NEXT: ret
;
; RV64IZCMP-WITH-FP-LABEL: varargs:
Expand All @@ -2964,7 +3041,10 @@ define void @varargs(...) {
; RV64IZCMP-WITH-FP-NEXT: call callee
; RV64IZCMP-WITH-FP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZCMP-WITH-FP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64IZCMP-WITH-FP-NEXT: .cfi_restore ra
; RV64IZCMP-WITH-FP-NEXT: .cfi_restore s0
; RV64IZCMP-WITH-FP-NEXT: addi sp, sp, 80
; RV64IZCMP-WITH-FP-NEXT: .cfi_def_cfa_offset 0
; RV64IZCMP-WITH-FP-NEXT: ret
call void @callee()
ret void
Expand Down
181 changes: 181 additions & 0 deletions llvm/test/CodeGen/RISCV/calling-conv-ilp32e.ll
View file

Large diffs are not rendered by default.

12 changes: 8 additions & 4 deletions llvm/test/CodeGen/RISCV/cm_mvas_mvsa.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -43,7 +43,8 @@ define i32 @zcmp_mv(i32 %num, i32 %f) nounwind {
; CHECK32ZCMP-NEXT: cm.mva01s s1, s0
; CHECK32ZCMP-NEXT: call func
; CHECK32ZCMP-NEXT: add a0, s2, s0
; CHECK32ZCMP-NEXT: cm.popret {ra, s0-s2}, 16
; CHECK32ZCMP-NEXT: cm.pop {ra, s0-s2}, 16
; CHECK32ZCMP-NEXT: ret
;
; CHECK64I-LABEL: zcmp_mv:
; CHECK64I: # %bb.0:
Expand Down Expand Up @@ -76,7 +77,8 @@ define i32 @zcmp_mv(i32 %num, i32 %f) nounwind {
; CHECK64ZCMP-NEXT: cm.mva01s s1, s0
; CHECK64ZCMP-NEXT: call func
; CHECK64ZCMP-NEXT: addw a0, s2, s0
; CHECK64ZCMP-NEXT: cm.popret {ra, s0-s2}, 32
; CHECK64ZCMP-NEXT: cm.pop {ra, s0-s2}, 32
; CHECK64ZCMP-NEXT: ret
%call = call i32 @func(i32 %num, i32 %f)
%call1 = call i32 @func(i32 %num, i32 %f)
%res = add i32 %call, %f
Expand Down Expand Up @@ -119,7 +121,8 @@ define i32 @not_zcmp_mv(i32 %num, i32 %f) nounwind {
; CHECK32ZCMP-NEXT: li a0, 1
; CHECK32ZCMP-NEXT: mv a1, s0
; CHECK32ZCMP-NEXT: call func
; CHECK32ZCMP-NEXT: cm.popret {ra, s0-s1}, 16
; CHECK32ZCMP-NEXT: cm.pop {ra, s0-s1}, 16
; CHECK32ZCMP-NEXT: ret
;
; CHECK64I-LABEL: not_zcmp_mv:
; CHECK64I: # %bb.0:
Expand Down Expand Up @@ -156,7 +159,8 @@ define i32 @not_zcmp_mv(i32 %num, i32 %f) nounwind {
; CHECK64ZCMP-NEXT: li a0, 1
; CHECK64ZCMP-NEXT: mv a1, s0
; CHECK64ZCMP-NEXT: call func
; CHECK64ZCMP-NEXT: cm.popret {ra, s0-s1}, 32
; CHECK64ZCMP-NEXT: cm.pop {ra, s0-s1}, 32
; CHECK64ZCMP-NEXT: ret
%call = call i32 @foo(i32 %num)
%call1 = call i32 @foo(i32 %f)
%tmp = call i32 @foo(i32 %call)
Expand Down
8 changes: 8 additions & 0 deletions llvm/test/CodeGen/RISCV/double-intrinsics.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1571,7 +1571,9 @@ define double @maximumnum_double(double %x, double %y) {
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: call fmaximum_num
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret
;
; RV64I-LABEL: maximumnum_double:
Expand All @@ -1582,7 +1584,9 @@ define double @maximumnum_double(double %x, double %y) {
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: call fmaximum_num
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret
%z = call double @llvm.maximumnum.f64(double %x, double %y)
ret double %z
Expand Down Expand Up @@ -1614,7 +1618,9 @@ define double @minimumnum_double(double %x, double %y) {
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: call fminimum_num
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret
;
; RV64I-LABEL: minimumnum_double:
Expand All @@ -1625,7 +1631,9 @@ define double @minimumnum_double(double %x, double %y) {
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: call fminimum_num
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret
%z = call double @llvm.minimumnum.f64(double %x, double %y)
ret double %z
Expand Down
50 changes: 50 additions & 0 deletions llvm/test/CodeGen/RISCV/double-round-conv.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -88,7 +88,9 @@ define i64 @test_floor_si64(double %x) {
; RV32IFD-NEXT: call floor
; RV32IFD-NEXT: call __fixdfdi
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: .cfi_restore ra
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: .cfi_def_cfa_offset 0
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: test_floor_si64:
Expand All @@ -105,7 +107,9 @@ define i64 @test_floor_si64(double %x) {
; RV32IZFINXZDINX-NEXT: call floor
; RV32IZFINXZDINX-NEXT: call __fixdfdi
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: .cfi_restore ra
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 0
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_floor_si64:
Expand Down Expand Up @@ -197,7 +201,9 @@ define i64 @test_floor_ui64(double %x) {
; RV32IFD-NEXT: call floor
; RV32IFD-NEXT: call __fixunsdfdi
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: .cfi_restore ra
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: .cfi_def_cfa_offset 0
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: test_floor_ui64:
Expand All @@ -214,7 +220,9 @@ define i64 @test_floor_ui64(double %x) {
; RV32IZFINXZDINX-NEXT: call floor
; RV32IZFINXZDINX-NEXT: call __fixunsdfdi
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: .cfi_restore ra
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 0
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_floor_ui64:
Expand Down Expand Up @@ -306,7 +314,9 @@ define i64 @test_ceil_si64(double %x) {
; RV32IFD-NEXT: call ceil
; RV32IFD-NEXT: call __fixdfdi
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: .cfi_restore ra
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: .cfi_def_cfa_offset 0
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: test_ceil_si64:
Expand All @@ -323,7 +333,9 @@ define i64 @test_ceil_si64(double %x) {
; RV32IZFINXZDINX-NEXT: call ceil
; RV32IZFINXZDINX-NEXT: call __fixdfdi
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: .cfi_restore ra
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 0
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_ceil_si64:
Expand Down Expand Up @@ -415,7 +427,9 @@ define i64 @test_ceil_ui64(double %x) {
; RV32IFD-NEXT: call ceil
; RV32IFD-NEXT: call __fixunsdfdi
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: .cfi_restore ra
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: .cfi_def_cfa_offset 0
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: test_ceil_ui64:
Expand All @@ -432,7 +446,9 @@ define i64 @test_ceil_ui64(double %x) {
; RV32IZFINXZDINX-NEXT: call ceil
; RV32IZFINXZDINX-NEXT: call __fixunsdfdi
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: .cfi_restore ra
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 0
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_ceil_ui64:
Expand Down Expand Up @@ -524,7 +540,9 @@ define i64 @test_trunc_si64(double %x) {
; RV32IFD-NEXT: call trunc
; RV32IFD-NEXT: call __fixdfdi
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: .cfi_restore ra
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: .cfi_def_cfa_offset 0
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: test_trunc_si64:
Expand All @@ -541,7 +559,9 @@ define i64 @test_trunc_si64(double %x) {
; RV32IZFINXZDINX-NEXT: call trunc
; RV32IZFINXZDINX-NEXT: call __fixdfdi
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: .cfi_restore ra
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 0
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_trunc_si64:
Expand Down Expand Up @@ -633,7 +653,9 @@ define i64 @test_trunc_ui64(double %x) {
; RV32IFD-NEXT: call trunc
; RV32IFD-NEXT: call __fixunsdfdi
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: .cfi_restore ra
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: .cfi_def_cfa_offset 0
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: test_trunc_ui64:
Expand All @@ -650,7 +672,9 @@ define i64 @test_trunc_ui64(double %x) {
; RV32IZFINXZDINX-NEXT: call trunc
; RV32IZFINXZDINX-NEXT: call __fixunsdfdi
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: .cfi_restore ra
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 0
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_trunc_ui64:
Expand Down Expand Up @@ -742,7 +766,9 @@ define i64 @test_round_si64(double %x) {
; RV32IFD-NEXT: call round
; RV32IFD-NEXT: call __fixdfdi
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: .cfi_restore ra
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: .cfi_def_cfa_offset 0
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: test_round_si64:
Expand All @@ -759,7 +785,9 @@ define i64 @test_round_si64(double %x) {
; RV32IZFINXZDINX-NEXT: call round
; RV32IZFINXZDINX-NEXT: call __fixdfdi
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: .cfi_restore ra
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 0
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_round_si64:
Expand Down Expand Up @@ -851,7 +879,9 @@ define i64 @test_round_ui64(double %x) {
; RV32IFD-NEXT: call round
; RV32IFD-NEXT: call __fixunsdfdi
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: .cfi_restore ra
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: .cfi_def_cfa_offset 0
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: test_round_ui64:
Expand All @@ -868,7 +898,9 @@ define i64 @test_round_ui64(double %x) {
; RV32IZFINXZDINX-NEXT: call round
; RV32IZFINXZDINX-NEXT: call __fixunsdfdi
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: .cfi_restore ra
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 0
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_round_ui64:
Expand Down Expand Up @@ -960,7 +992,9 @@ define i64 @test_roundeven_si64(double %x) {
; RV32IFD-NEXT: call roundeven
; RV32IFD-NEXT: call __fixdfdi
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: .cfi_restore ra
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: .cfi_def_cfa_offset 0
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: test_roundeven_si64:
Expand All @@ -977,7 +1011,9 @@ define i64 @test_roundeven_si64(double %x) {
; RV32IZFINXZDINX-NEXT: call roundeven
; RV32IZFINXZDINX-NEXT: call __fixdfdi
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: .cfi_restore ra
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 0
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_roundeven_si64:
Expand Down Expand Up @@ -1069,7 +1105,9 @@ define i64 @test_roundeven_ui64(double %x) {
; RV32IFD-NEXT: call roundeven
; RV32IFD-NEXT: call __fixunsdfdi
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: .cfi_restore ra
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: .cfi_def_cfa_offset 0
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: test_roundeven_ui64:
Expand All @@ -1086,7 +1124,9 @@ define i64 @test_roundeven_ui64(double %x) {
; RV32IZFINXZDINX-NEXT: call roundeven
; RV32IZFINXZDINX-NEXT: call __fixunsdfdi
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: .cfi_restore ra
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 0
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_roundeven_ui64:
Expand Down Expand Up @@ -1125,7 +1165,9 @@ define double @test_floor_double(double %x) {
; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -4
; RV32IZFINXZDINX-NEXT: call floor
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: .cfi_restore ra
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 0
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_floor_double:
Expand Down Expand Up @@ -1172,7 +1214,9 @@ define double @test_ceil_double(double %x) {
; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -4
; RV32IZFINXZDINX-NEXT: call ceil
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: .cfi_restore ra
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 0
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_ceil_double:
Expand Down Expand Up @@ -1219,7 +1263,9 @@ define double @test_trunc_double(double %x) {
; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -4
; RV32IZFINXZDINX-NEXT: call trunc
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: .cfi_restore ra
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 0
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_trunc_double:
Expand Down Expand Up @@ -1266,7 +1312,9 @@ define double @test_round_double(double %x) {
; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -4
; RV32IZFINXZDINX-NEXT: call round
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: .cfi_restore ra
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 0
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_round_double:
Expand Down Expand Up @@ -1313,7 +1361,9 @@ define double @test_roundeven_double(double %x) {
; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -4
; RV32IZFINXZDINX-NEXT: call roundeven
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: .cfi_restore ra
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 0
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_roundeven_double:
Expand Down
2 changes: 2 additions & 0 deletions llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -86,7 +86,9 @@ define void @_Z3foov() {
; CHECK-NEXT: slli a1, a0, 3
; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: ret
entry:
%0 = tail call <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.i64(<vscale x 8 x i16> undef, ptr nonnull @__const._Z3foov.var_49, i64 2)
Expand Down
4 changes: 4 additions & 0 deletions llvm/test/CodeGen/RISCV/eh-dwarf-cfa.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,9 @@ define void @dwarf() {
; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: call foo
; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-NEXT: .cfi_restore ra
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: dwarf:
Expand All @@ -24,7 +26,9 @@ define void @dwarf() {
; RV64-NEXT: addi a0, sp, 16
; RV64-NEXT: call foo
; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64-NEXT: .cfi_restore ra
; RV64-NEXT: addi sp, sp, 16
; RV64-NEXT: .cfi_def_cfa_offset 0
; RV64-NEXT: ret
entry:
%0 = call ptr @llvm.eh.dwarf.cfa(i32 0)
Expand Down
12 changes: 12 additions & 0 deletions llvm/test/CodeGen/RISCV/exception-pointer-register.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -23,6 +23,7 @@ define void @caller(ptr %p) personality ptr @__gxx_personality_v0 {
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: .cfi_offset s0, -8
; RV32I-NEXT: .cfi_offset s1, -12
; RV32I-NEXT: .cfi_remember_state
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: beqz a0, .LBB0_2
; RV32I-NEXT: # %bb.1: # %bb2
Expand All @@ -40,9 +41,14 @@ define void @caller(ptr %p) personality ptr @__gxx_personality_v0 {
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: .cfi_restore s0
; RV32I-NEXT: .cfi_restore s1
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB0_4: # %lpad
; RV32I-NEXT: .cfi_restore_state
; RV32I-NEXT: .Ltmp4:
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: mv a0, s0
Expand All @@ -60,6 +66,7 @@ define void @caller(ptr %p) personality ptr @__gxx_personality_v0 {
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: .cfi_offset s0, -16
; RV64I-NEXT: .cfi_offset s1, -24
; RV64I-NEXT: .cfi_remember_state
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: beqz a0, .LBB0_2
; RV64I-NEXT: # %bb.1: # %bb2
Expand All @@ -77,9 +84,14 @@ define void @caller(ptr %p) personality ptr @__gxx_personality_v0 {
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: .cfi_restore s0
; RV64I-NEXT: .cfi_restore s1
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB0_4: # %lpad
; RV64I-NEXT: .cfi_restore_state
; RV64I-NEXT: .Ltmp4:
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: mv a0, s0
Expand Down
8 changes: 8 additions & 0 deletions llvm/test/CodeGen/RISCV/float-intrinsics.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2216,7 +2216,9 @@ define float @maximumnum_float(float %x, float %y) {
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: call fmaximum_numf
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret
;
; RV64I-LABEL: maximumnum_float:
Expand All @@ -2227,7 +2229,9 @@ define float @maximumnum_float(float %x, float %y) {
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: call fmaximum_numf
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret
%z = call float @llvm.maximumnum.f32(float %x, float %y)
ret float %z
Expand Down Expand Up @@ -2264,7 +2268,9 @@ define float @minimumnum_float(float %x, float %y) {
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: call fminimum_numf
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret
;
; RV64I-LABEL: minimumnum_float:
Expand All @@ -2275,7 +2281,9 @@ define float @minimumnum_float(float %x, float %y) {
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: call fminimum_numf
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret
%z = call float @llvm.minimumnum.f32(float %x, float %y)
ret float %z
Expand Down
40 changes: 40 additions & 0 deletions llvm/test/CodeGen/RISCV/float-round-conv.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -102,7 +102,9 @@ define i64 @test_floor_si64(float %x) {
; RV32IF-NEXT: .cfi_offset ra, -4
; RV32IF-NEXT: call __fixsfdi
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: .cfi_restore ra
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: .cfi_def_cfa_offset 0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: test_floor_si64:
Expand All @@ -127,7 +129,9 @@ define i64 @test_floor_si64(float %x) {
; RV32IZFINX-NEXT: .cfi_offset ra, -4
; RV32IZFINX-NEXT: call __fixsfdi
; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINX-NEXT: .cfi_restore ra
; RV32IZFINX-NEXT: addi sp, sp, 16
; RV32IZFINX-NEXT: .cfi_def_cfa_offset 0
; RV32IZFINX-NEXT: ret
;
; RV64IZFINX-LABEL: test_floor_si64:
Expand Down Expand Up @@ -233,7 +237,9 @@ define i64 @test_floor_ui64(float %x) {
; RV32IF-NEXT: .cfi_offset ra, -4
; RV32IF-NEXT: call __fixunssfdi
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: .cfi_restore ra
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: .cfi_def_cfa_offset 0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: test_floor_ui64:
Expand All @@ -258,7 +264,9 @@ define i64 @test_floor_ui64(float %x) {
; RV32IZFINX-NEXT: .cfi_offset ra, -4
; RV32IZFINX-NEXT: call __fixunssfdi
; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINX-NEXT: .cfi_restore ra
; RV32IZFINX-NEXT: addi sp, sp, 16
; RV32IZFINX-NEXT: .cfi_def_cfa_offset 0
; RV32IZFINX-NEXT: ret
;
; RV64IZFINX-LABEL: test_floor_ui64:
Expand Down Expand Up @@ -364,7 +372,9 @@ define i64 @test_ceil_si64(float %x) {
; RV32IF-NEXT: .cfi_offset ra, -4
; RV32IF-NEXT: call __fixsfdi
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: .cfi_restore ra
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: .cfi_def_cfa_offset 0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: test_ceil_si64:
Expand All @@ -389,7 +399,9 @@ define i64 @test_ceil_si64(float %x) {
; RV32IZFINX-NEXT: .cfi_offset ra, -4
; RV32IZFINX-NEXT: call __fixsfdi
; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINX-NEXT: .cfi_restore ra
; RV32IZFINX-NEXT: addi sp, sp, 16
; RV32IZFINX-NEXT: .cfi_def_cfa_offset 0
; RV32IZFINX-NEXT: ret
;
; RV64IZFINX-LABEL: test_ceil_si64:
Expand Down Expand Up @@ -495,7 +507,9 @@ define i64 @test_ceil_ui64(float %x) {
; RV32IF-NEXT: .cfi_offset ra, -4
; RV32IF-NEXT: call __fixunssfdi
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: .cfi_restore ra
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: .cfi_def_cfa_offset 0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: test_ceil_ui64:
Expand All @@ -520,7 +534,9 @@ define i64 @test_ceil_ui64(float %x) {
; RV32IZFINX-NEXT: .cfi_offset ra, -4
; RV32IZFINX-NEXT: call __fixunssfdi
; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINX-NEXT: .cfi_restore ra
; RV32IZFINX-NEXT: addi sp, sp, 16
; RV32IZFINX-NEXT: .cfi_def_cfa_offset 0
; RV32IZFINX-NEXT: ret
;
; RV64IZFINX-LABEL: test_ceil_ui64:
Expand Down Expand Up @@ -626,7 +642,9 @@ define i64 @test_trunc_si64(float %x) {
; RV32IF-NEXT: .cfi_offset ra, -4
; RV32IF-NEXT: call __fixsfdi
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: .cfi_restore ra
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: .cfi_def_cfa_offset 0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: test_trunc_si64:
Expand All @@ -651,7 +669,9 @@ define i64 @test_trunc_si64(float %x) {
; RV32IZFINX-NEXT: .cfi_offset ra, -4
; RV32IZFINX-NEXT: call __fixsfdi
; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINX-NEXT: .cfi_restore ra
; RV32IZFINX-NEXT: addi sp, sp, 16
; RV32IZFINX-NEXT: .cfi_def_cfa_offset 0
; RV32IZFINX-NEXT: ret
;
; RV64IZFINX-LABEL: test_trunc_si64:
Expand Down Expand Up @@ -757,7 +777,9 @@ define i64 @test_trunc_ui64(float %x) {
; RV32IF-NEXT: .cfi_offset ra, -4
; RV32IF-NEXT: call __fixunssfdi
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: .cfi_restore ra
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: .cfi_def_cfa_offset 0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: test_trunc_ui64:
Expand All @@ -782,7 +804,9 @@ define i64 @test_trunc_ui64(float %x) {
; RV32IZFINX-NEXT: .cfi_offset ra, -4
; RV32IZFINX-NEXT: call __fixunssfdi
; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINX-NEXT: .cfi_restore ra
; RV32IZFINX-NEXT: addi sp, sp, 16
; RV32IZFINX-NEXT: .cfi_def_cfa_offset 0
; RV32IZFINX-NEXT: ret
;
; RV64IZFINX-LABEL: test_trunc_ui64:
Expand Down Expand Up @@ -888,7 +912,9 @@ define i64 @test_round_si64(float %x) {
; RV32IF-NEXT: .cfi_offset ra, -4
; RV32IF-NEXT: call __fixsfdi
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: .cfi_restore ra
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: .cfi_def_cfa_offset 0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: test_round_si64:
Expand All @@ -913,7 +939,9 @@ define i64 @test_round_si64(float %x) {
; RV32IZFINX-NEXT: .cfi_offset ra, -4
; RV32IZFINX-NEXT: call __fixsfdi
; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINX-NEXT: .cfi_restore ra
; RV32IZFINX-NEXT: addi sp, sp, 16
; RV32IZFINX-NEXT: .cfi_def_cfa_offset 0
; RV32IZFINX-NEXT: ret
;
; RV64IZFINX-LABEL: test_round_si64:
Expand Down Expand Up @@ -1019,7 +1047,9 @@ define i64 @test_round_ui64(float %x) {
; RV32IF-NEXT: .cfi_offset ra, -4
; RV32IF-NEXT: call __fixunssfdi
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: .cfi_restore ra
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: .cfi_def_cfa_offset 0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: test_round_ui64:
Expand All @@ -1044,7 +1074,9 @@ define i64 @test_round_ui64(float %x) {
; RV32IZFINX-NEXT: .cfi_offset ra, -4
; RV32IZFINX-NEXT: call __fixunssfdi
; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINX-NEXT: .cfi_restore ra
; RV32IZFINX-NEXT: addi sp, sp, 16
; RV32IZFINX-NEXT: .cfi_def_cfa_offset 0
; RV32IZFINX-NEXT: ret
;
; RV64IZFINX-LABEL: test_round_ui64:
Expand Down Expand Up @@ -1150,7 +1182,9 @@ define i64 @test_roundeven_si64(float %x) {
; RV32IF-NEXT: .cfi_offset ra, -4
; RV32IF-NEXT: call __fixsfdi
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: .cfi_restore ra
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: .cfi_def_cfa_offset 0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: test_roundeven_si64:
Expand All @@ -1175,7 +1209,9 @@ define i64 @test_roundeven_si64(float %x) {
; RV32IZFINX-NEXT: .cfi_offset ra, -4
; RV32IZFINX-NEXT: call __fixsfdi
; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINX-NEXT: .cfi_restore ra
; RV32IZFINX-NEXT: addi sp, sp, 16
; RV32IZFINX-NEXT: .cfi_def_cfa_offset 0
; RV32IZFINX-NEXT: ret
;
; RV64IZFINX-LABEL: test_roundeven_si64:
Expand Down Expand Up @@ -1281,7 +1317,9 @@ define i64 @test_roundeven_ui64(float %x) {
; RV32IF-NEXT: .cfi_offset ra, -4
; RV32IF-NEXT: call __fixunssfdi
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: .cfi_restore ra
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: .cfi_def_cfa_offset 0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: test_roundeven_ui64:
Expand All @@ -1306,7 +1344,9 @@ define i64 @test_roundeven_ui64(float %x) {
; RV32IZFINX-NEXT: .cfi_offset ra, -4
; RV32IZFINX-NEXT: call __fixunssfdi
; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINX-NEXT: .cfi_restore ra
; RV32IZFINX-NEXT: addi sp, sp, 16
; RV32IZFINX-NEXT: .cfi_def_cfa_offset 0
; RV32IZFINX-NEXT: ret
;
; RV64IZFINX-LABEL: test_roundeven_ui64:
Expand Down
176 changes: 176 additions & 0 deletions llvm/test/CodeGen/RISCV/fpclamptosat.ll
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301 changes: 301 additions & 0 deletions llvm/test/CodeGen/RISCV/frame-info.ll
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10 changes: 10 additions & 0 deletions llvm/test/CodeGen/RISCV/half-convert-strict.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -524,7 +524,9 @@ define i32 @fcvt_wu_h_multiple_use(half %x, ptr %y) strictfp {
; CHECK32-D-NEXT: seqz a1, a0
; CHECK32-D-NEXT: add a0, a0, a1
; CHECK32-D-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; CHECK32-D-NEXT: .cfi_restore ra
; CHECK32-D-NEXT: addi sp, sp, 16
; CHECK32-D-NEXT: .cfi_def_cfa_offset 0
; CHECK32-D-NEXT: ret
%a = call i32 @llvm.experimental.constrained.fptoui.i32.f16(half %x, metadata !"fpexcept.strict")
%b = icmp eq i32 %a, 0
Expand Down Expand Up @@ -2359,7 +2361,11 @@ define signext i32 @fcvt_h_w_demanded_bits(i32 signext %0, ptr %1) strictfp {
; CHECK32-D-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; CHECK32-D-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; CHECK32-D-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; CHECK32-D-NEXT: .cfi_restore ra
; CHECK32-D-NEXT: .cfi_restore s0
; CHECK32-D-NEXT: .cfi_restore s1
; CHECK32-D-NEXT: addi sp, sp, 16
; CHECK32-D-NEXT: .cfi_def_cfa_offset 0
; CHECK32-D-NEXT: ret
%3 = add i32 %0, 1
%4 = call half @llvm.experimental.constrained.sitofp.f16.i32(i32 %3, metadata !"round.dynamic", metadata !"fpexcept.strict")
Expand Down Expand Up @@ -2493,7 +2499,11 @@ define signext i32 @fcvt_h_wu_demanded_bits(i32 signext %0, ptr %1) strictfp {
; CHECK32-D-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; CHECK32-D-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; CHECK32-D-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; CHECK32-D-NEXT: .cfi_restore ra
; CHECK32-D-NEXT: .cfi_restore s0
; CHECK32-D-NEXT: .cfi_restore s1
; CHECK32-D-NEXT: addi sp, sp, 16
; CHECK32-D-NEXT: .cfi_def_cfa_offset 0
; CHECK32-D-NEXT: ret
%3 = add i32 %0, 1
%4 = call half @llvm.experimental.constrained.uitofp.f16.i32(i32 %3, metadata !"round.dynamic", metadata !"fpexcept.strict")
Expand Down
20 changes: 20 additions & 0 deletions llvm/test/CodeGen/RISCV/half-intrinsics.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3020,7 +3020,12 @@ define half @maximumnum_half(half %x, half %y) {
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: .cfi_restore s0
; RV32I-NEXT: .cfi_restore s1
; RV32I-NEXT: .cfi_restore s2
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret
;
; RV64I-LABEL: maximumnum_half:
Expand Down Expand Up @@ -3051,7 +3056,12 @@ define half @maximumnum_half(half %x, half %y) {
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: .cfi_restore s0
; RV64I-NEXT: .cfi_restore s1
; RV64I-NEXT: .cfi_restore s2
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret
;
; CHECKIZFHMIN-LABEL: maximumnum_half:
Expand Down Expand Up @@ -3114,7 +3124,12 @@ define half @minimumnum_half(half %x, half %y) {
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: .cfi_restore s0
; RV32I-NEXT: .cfi_restore s1
; RV32I-NEXT: .cfi_restore s2
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret
;
; RV64I-LABEL: minimumnum_half:
Expand Down Expand Up @@ -3145,7 +3160,12 @@ define half @minimumnum_half(half %x, half %y) {
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: .cfi_restore s0
; RV64I-NEXT: .cfi_restore s1
; RV64I-NEXT: .cfi_restore s2
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret
;
; CHECKIZFHMIN-LABEL: minimumnum_half:
Expand Down
80 changes: 80 additions & 0 deletions llvm/test/CodeGen/RISCV/half-round-conv.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -325,7 +325,9 @@ define i64 @test_floor_si64(half %x) {
; RV32IZFH-NEXT: .cfi_offset ra, -4
; RV32IZFH-NEXT: call __fixhfdi
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: .cfi_restore ra
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: .cfi_def_cfa_offset 0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: test_floor_si64:
Expand All @@ -351,7 +353,9 @@ define i64 @test_floor_si64(half %x) {
; RV32IZHINX-NEXT: .cfi_offset ra, -4
; RV32IZHINX-NEXT: call __fixhfdi
; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZHINX-NEXT: .cfi_restore ra
; RV32IZHINX-NEXT: addi sp, sp, 16
; RV32IZHINX-NEXT: .cfi_def_cfa_offset 0
; RV32IZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: test_floor_si64:
Expand Down Expand Up @@ -389,7 +393,9 @@ define i64 @test_floor_si64(half %x) {
; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
; RV32IZFHMIN-NEXT: call __fixhfdi
; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFHMIN-NEXT: .cfi_restore ra
; RV32IZFHMIN-NEXT: addi sp, sp, 16
; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 0
; RV32IZFHMIN-NEXT: ret
;
; RV64IZFHMIN-LABEL: test_floor_si64:
Expand Down Expand Up @@ -429,7 +435,9 @@ define i64 @test_floor_si64(half %x) {
; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
; RV32IZHINXMIN-NEXT: call __fixhfdi
; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZHINXMIN-NEXT: .cfi_restore ra
; RV32IZHINXMIN-NEXT: addi sp, sp, 16
; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 0
; RV32IZHINXMIN-NEXT: ret
;
; RV64IZHINXMIN-LABEL: test_floor_si64:
Expand Down Expand Up @@ -762,7 +770,9 @@ define i64 @test_floor_ui64(half %x) {
; RV32IZFH-NEXT: .cfi_offset ra, -4
; RV32IZFH-NEXT: call __fixunshfdi
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: .cfi_restore ra
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: .cfi_def_cfa_offset 0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: test_floor_ui64:
Expand All @@ -788,7 +798,9 @@ define i64 @test_floor_ui64(half %x) {
; RV32IZHINX-NEXT: .cfi_offset ra, -4
; RV32IZHINX-NEXT: call __fixunshfdi
; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZHINX-NEXT: .cfi_restore ra
; RV32IZHINX-NEXT: addi sp, sp, 16
; RV32IZHINX-NEXT: .cfi_def_cfa_offset 0
; RV32IZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: test_floor_ui64:
Expand Down Expand Up @@ -826,7 +838,9 @@ define i64 @test_floor_ui64(half %x) {
; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
; RV32IZFHMIN-NEXT: call __fixunshfdi
; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFHMIN-NEXT: .cfi_restore ra
; RV32IZFHMIN-NEXT: addi sp, sp, 16
; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 0
; RV32IZFHMIN-NEXT: ret
;
; RV64IZFHMIN-LABEL: test_floor_ui64:
Expand Down Expand Up @@ -866,7 +880,9 @@ define i64 @test_floor_ui64(half %x) {
; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
; RV32IZHINXMIN-NEXT: call __fixunshfdi
; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZHINXMIN-NEXT: .cfi_restore ra
; RV32IZHINXMIN-NEXT: addi sp, sp, 16
; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 0
; RV32IZHINXMIN-NEXT: ret
;
; RV64IZHINXMIN-LABEL: test_floor_ui64:
Expand Down Expand Up @@ -1199,7 +1215,9 @@ define i64 @test_ceil_si64(half %x) {
; RV32IZFH-NEXT: .cfi_offset ra, -4
; RV32IZFH-NEXT: call __fixhfdi
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: .cfi_restore ra
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: .cfi_def_cfa_offset 0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: test_ceil_si64:
Expand All @@ -1225,7 +1243,9 @@ define i64 @test_ceil_si64(half %x) {
; RV32IZHINX-NEXT: .cfi_offset ra, -4
; RV32IZHINX-NEXT: call __fixhfdi
; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZHINX-NEXT: .cfi_restore ra
; RV32IZHINX-NEXT: addi sp, sp, 16
; RV32IZHINX-NEXT: .cfi_def_cfa_offset 0
; RV32IZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: test_ceil_si64:
Expand Down Expand Up @@ -1263,7 +1283,9 @@ define i64 @test_ceil_si64(half %x) {
; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
; RV32IZFHMIN-NEXT: call __fixhfdi
; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFHMIN-NEXT: .cfi_restore ra
; RV32IZFHMIN-NEXT: addi sp, sp, 16
; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 0
; RV32IZFHMIN-NEXT: ret
;
; RV64IZFHMIN-LABEL: test_ceil_si64:
Expand Down Expand Up @@ -1303,7 +1325,9 @@ define i64 @test_ceil_si64(half %x) {
; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
; RV32IZHINXMIN-NEXT: call __fixhfdi
; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZHINXMIN-NEXT: .cfi_restore ra
; RV32IZHINXMIN-NEXT: addi sp, sp, 16
; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 0
; RV32IZHINXMIN-NEXT: ret
;
; RV64IZHINXMIN-LABEL: test_ceil_si64:
Expand Down Expand Up @@ -1636,7 +1660,9 @@ define i64 @test_ceil_ui64(half %x) {
; RV32IZFH-NEXT: .cfi_offset ra, -4
; RV32IZFH-NEXT: call __fixunshfdi
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: .cfi_restore ra
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: .cfi_def_cfa_offset 0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: test_ceil_ui64:
Expand All @@ -1662,7 +1688,9 @@ define i64 @test_ceil_ui64(half %x) {
; RV32IZHINX-NEXT: .cfi_offset ra, -4
; RV32IZHINX-NEXT: call __fixunshfdi
; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZHINX-NEXT: .cfi_restore ra
; RV32IZHINX-NEXT: addi sp, sp, 16
; RV32IZHINX-NEXT: .cfi_def_cfa_offset 0
; RV32IZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: test_ceil_ui64:
Expand Down Expand Up @@ -1700,7 +1728,9 @@ define i64 @test_ceil_ui64(half %x) {
; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
; RV32IZFHMIN-NEXT: call __fixunshfdi
; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFHMIN-NEXT: .cfi_restore ra
; RV32IZFHMIN-NEXT: addi sp, sp, 16
; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 0
; RV32IZFHMIN-NEXT: ret
;
; RV64IZFHMIN-LABEL: test_ceil_ui64:
Expand Down Expand Up @@ -1740,7 +1770,9 @@ define i64 @test_ceil_ui64(half %x) {
; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
; RV32IZHINXMIN-NEXT: call __fixunshfdi
; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZHINXMIN-NEXT: .cfi_restore ra
; RV32IZHINXMIN-NEXT: addi sp, sp, 16
; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 0
; RV32IZHINXMIN-NEXT: ret
;
; RV64IZHINXMIN-LABEL: test_ceil_ui64:
Expand Down Expand Up @@ -2073,7 +2105,9 @@ define i64 @test_trunc_si64(half %x) {
; RV32IZFH-NEXT: .cfi_offset ra, -4
; RV32IZFH-NEXT: call __fixhfdi
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: .cfi_restore ra
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: .cfi_def_cfa_offset 0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: test_trunc_si64:
Expand All @@ -2099,7 +2133,9 @@ define i64 @test_trunc_si64(half %x) {
; RV32IZHINX-NEXT: .cfi_offset ra, -4
; RV32IZHINX-NEXT: call __fixhfdi
; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZHINX-NEXT: .cfi_restore ra
; RV32IZHINX-NEXT: addi sp, sp, 16
; RV32IZHINX-NEXT: .cfi_def_cfa_offset 0
; RV32IZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: test_trunc_si64:
Expand Down Expand Up @@ -2137,7 +2173,9 @@ define i64 @test_trunc_si64(half %x) {
; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
; RV32IZFHMIN-NEXT: call __fixhfdi
; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFHMIN-NEXT: .cfi_restore ra
; RV32IZFHMIN-NEXT: addi sp, sp, 16
; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 0
; RV32IZFHMIN-NEXT: ret
;
; RV64IZFHMIN-LABEL: test_trunc_si64:
Expand Down Expand Up @@ -2177,7 +2215,9 @@ define i64 @test_trunc_si64(half %x) {
; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
; RV32IZHINXMIN-NEXT: call __fixhfdi
; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZHINXMIN-NEXT: .cfi_restore ra
; RV32IZHINXMIN-NEXT: addi sp, sp, 16
; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 0
; RV32IZHINXMIN-NEXT: ret
;
; RV64IZHINXMIN-LABEL: test_trunc_si64:
Expand Down Expand Up @@ -2510,7 +2550,9 @@ define i64 @test_trunc_ui64(half %x) {
; RV32IZFH-NEXT: .cfi_offset ra, -4
; RV32IZFH-NEXT: call __fixunshfdi
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: .cfi_restore ra
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: .cfi_def_cfa_offset 0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: test_trunc_ui64:
Expand All @@ -2536,7 +2578,9 @@ define i64 @test_trunc_ui64(half %x) {
; RV32IZHINX-NEXT: .cfi_offset ra, -4
; RV32IZHINX-NEXT: call __fixunshfdi
; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZHINX-NEXT: .cfi_restore ra
; RV32IZHINX-NEXT: addi sp, sp, 16
; RV32IZHINX-NEXT: .cfi_def_cfa_offset 0
; RV32IZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: test_trunc_ui64:
Expand Down Expand Up @@ -2574,7 +2618,9 @@ define i64 @test_trunc_ui64(half %x) {
; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
; RV32IZFHMIN-NEXT: call __fixunshfdi
; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFHMIN-NEXT: .cfi_restore ra
; RV32IZFHMIN-NEXT: addi sp, sp, 16
; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 0
; RV32IZFHMIN-NEXT: ret
;
; RV64IZFHMIN-LABEL: test_trunc_ui64:
Expand Down Expand Up @@ -2614,7 +2660,9 @@ define i64 @test_trunc_ui64(half %x) {
; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
; RV32IZHINXMIN-NEXT: call __fixunshfdi
; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZHINXMIN-NEXT: .cfi_restore ra
; RV32IZHINXMIN-NEXT: addi sp, sp, 16
; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 0
; RV32IZHINXMIN-NEXT: ret
;
; RV64IZHINXMIN-LABEL: test_trunc_ui64:
Expand Down Expand Up @@ -2947,7 +2995,9 @@ define i64 @test_round_si64(half %x) {
; RV32IZFH-NEXT: .cfi_offset ra, -4
; RV32IZFH-NEXT: call __fixhfdi
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: .cfi_restore ra
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: .cfi_def_cfa_offset 0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: test_round_si64:
Expand All @@ -2973,7 +3023,9 @@ define i64 @test_round_si64(half %x) {
; RV32IZHINX-NEXT: .cfi_offset ra, -4
; RV32IZHINX-NEXT: call __fixhfdi
; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZHINX-NEXT: .cfi_restore ra
; RV32IZHINX-NEXT: addi sp, sp, 16
; RV32IZHINX-NEXT: .cfi_def_cfa_offset 0
; RV32IZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: test_round_si64:
Expand Down Expand Up @@ -3011,7 +3063,9 @@ define i64 @test_round_si64(half %x) {
; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
; RV32IZFHMIN-NEXT: call __fixhfdi
; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFHMIN-NEXT: .cfi_restore ra
; RV32IZFHMIN-NEXT: addi sp, sp, 16
; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 0
; RV32IZFHMIN-NEXT: ret
;
; RV64IZFHMIN-LABEL: test_round_si64:
Expand Down Expand Up @@ -3051,7 +3105,9 @@ define i64 @test_round_si64(half %x) {
; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
; RV32IZHINXMIN-NEXT: call __fixhfdi
; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZHINXMIN-NEXT: .cfi_restore ra
; RV32IZHINXMIN-NEXT: addi sp, sp, 16
; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 0
; RV32IZHINXMIN-NEXT: ret
;
; RV64IZHINXMIN-LABEL: test_round_si64:
Expand Down Expand Up @@ -3384,7 +3440,9 @@ define i64 @test_round_ui64(half %x) {
; RV32IZFH-NEXT: .cfi_offset ra, -4
; RV32IZFH-NEXT: call __fixunshfdi
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: .cfi_restore ra
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: .cfi_def_cfa_offset 0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: test_round_ui64:
Expand All @@ -3410,7 +3468,9 @@ define i64 @test_round_ui64(half %x) {
; RV32IZHINX-NEXT: .cfi_offset ra, -4
; RV32IZHINX-NEXT: call __fixunshfdi
; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZHINX-NEXT: .cfi_restore ra
; RV32IZHINX-NEXT: addi sp, sp, 16
; RV32IZHINX-NEXT: .cfi_def_cfa_offset 0
; RV32IZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: test_round_ui64:
Expand Down Expand Up @@ -3448,7 +3508,9 @@ define i64 @test_round_ui64(half %x) {
; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
; RV32IZFHMIN-NEXT: call __fixunshfdi
; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFHMIN-NEXT: .cfi_restore ra
; RV32IZFHMIN-NEXT: addi sp, sp, 16
; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 0
; RV32IZFHMIN-NEXT: ret
;
; RV64IZFHMIN-LABEL: test_round_ui64:
Expand Down Expand Up @@ -3488,7 +3550,9 @@ define i64 @test_round_ui64(half %x) {
; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
; RV32IZHINXMIN-NEXT: call __fixunshfdi
; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZHINXMIN-NEXT: .cfi_restore ra
; RV32IZHINXMIN-NEXT: addi sp, sp, 16
; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 0
; RV32IZHINXMIN-NEXT: ret
;
; RV64IZHINXMIN-LABEL: test_round_ui64:
Expand Down Expand Up @@ -3821,7 +3885,9 @@ define i64 @test_roundeven_si64(half %x) {
; RV32IZFH-NEXT: .cfi_offset ra, -4
; RV32IZFH-NEXT: call __fixhfdi
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: .cfi_restore ra
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: .cfi_def_cfa_offset 0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: test_roundeven_si64:
Expand All @@ -3847,7 +3913,9 @@ define i64 @test_roundeven_si64(half %x) {
; RV32IZHINX-NEXT: .cfi_offset ra, -4
; RV32IZHINX-NEXT: call __fixhfdi
; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZHINX-NEXT: .cfi_restore ra
; RV32IZHINX-NEXT: addi sp, sp, 16
; RV32IZHINX-NEXT: .cfi_def_cfa_offset 0
; RV32IZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: test_roundeven_si64:
Expand Down Expand Up @@ -3885,7 +3953,9 @@ define i64 @test_roundeven_si64(half %x) {
; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
; RV32IZFHMIN-NEXT: call __fixhfdi
; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFHMIN-NEXT: .cfi_restore ra
; RV32IZFHMIN-NEXT: addi sp, sp, 16
; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 0
; RV32IZFHMIN-NEXT: ret
;
; RV64IZFHMIN-LABEL: test_roundeven_si64:
Expand Down Expand Up @@ -3925,7 +3995,9 @@ define i64 @test_roundeven_si64(half %x) {
; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
; RV32IZHINXMIN-NEXT: call __fixhfdi
; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZHINXMIN-NEXT: .cfi_restore ra
; RV32IZHINXMIN-NEXT: addi sp, sp, 16
; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 0
; RV32IZHINXMIN-NEXT: ret
;
; RV64IZHINXMIN-LABEL: test_roundeven_si64:
Expand Down Expand Up @@ -4258,7 +4330,9 @@ define i64 @test_roundeven_ui64(half %x) {
; RV32IZFH-NEXT: .cfi_offset ra, -4
; RV32IZFH-NEXT: call __fixunshfdi
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: .cfi_restore ra
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: .cfi_def_cfa_offset 0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: test_roundeven_ui64:
Expand All @@ -4284,7 +4358,9 @@ define i64 @test_roundeven_ui64(half %x) {
; RV32IZHINX-NEXT: .cfi_offset ra, -4
; RV32IZHINX-NEXT: call __fixunshfdi
; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZHINX-NEXT: .cfi_restore ra
; RV32IZHINX-NEXT: addi sp, sp, 16
; RV32IZHINX-NEXT: .cfi_def_cfa_offset 0
; RV32IZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: test_roundeven_ui64:
Expand Down Expand Up @@ -4322,7 +4398,9 @@ define i64 @test_roundeven_ui64(half %x) {
; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
; RV32IZFHMIN-NEXT: call __fixunshfdi
; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFHMIN-NEXT: .cfi_restore ra
; RV32IZFHMIN-NEXT: addi sp, sp, 16
; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 0
; RV32IZFHMIN-NEXT: ret
;
; RV64IZFHMIN-LABEL: test_roundeven_ui64:
Expand Down Expand Up @@ -4362,7 +4440,9 @@ define i64 @test_roundeven_ui64(half %x) {
; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
; RV32IZHINXMIN-NEXT: call __fixunshfdi
; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZHINXMIN-NEXT: .cfi_restore ra
; RV32IZHINXMIN-NEXT: addi sp, sp, 16
; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 0
; RV32IZHINXMIN-NEXT: ret
;
; RV64IZHINXMIN-LABEL: test_roundeven_ui64:
Expand Down
2 changes: 2 additions & 0 deletions llvm/test/CodeGen/RISCV/hwasan-check-memaccess.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,9 @@ define ptr @f2(ptr %x0, ptr %x1) {
; CHECK-NEXT: mv t0, a1
; CHECK-NEXT: call __hwasan_check_x10_2_short
; CHECK-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; CHECK-NEXT: .cfi_restore ra
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: ret
call void @llvm.hwasan.check.memaccess.shortgranules(ptr %x1, ptr %x0, i32 2)
ret ptr %x0
Expand Down
3 changes: 3 additions & 0 deletions llvm/test/CodeGen/RISCV/intrinsic-cttz-elts-vscale.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -100,8 +100,11 @@ define i64 @ctz_nxv8i1_no_range(<vscale x 8 x i16> %a) {
; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: slli a2, a2, 1
; RV32-NEXT: add sp, sp, a2
; RV32-NEXT: .cfi_def_cfa sp, 48
; RV32-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
; RV32-NEXT: .cfi_restore ra
; RV32-NEXT: addi sp, sp, 48
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: ctz_nxv8i1_no_range:
Expand Down
2 changes: 2 additions & 0 deletions llvm/test/CodeGen/RISCV/kcfi-mir.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,9 @@ define void @f1(ptr noundef %x) !kcfi_type !1 {
; CHECK-NEXT: PseudoCALLIndirect killed $x10, csr_ilp32_lp64, implicit-def dead $x1, implicit-def $x2
; CHECK-NEXT: }
; CHECK-NEXT: $x1 = LD $x2, 8 :: (load (s64) from %stack.0)
; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $x1
; CHECK-NEXT: $x2 = frame-destroy ADDI $x2, 16
; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 0
; CHECK-NEXT: PseudoRET
call void %x() [ "kcfi"(i32 12345678) ]
ret void
Expand Down
15 changes: 15 additions & 0 deletions llvm/test/CodeGen/RISCV/large-stack.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,6 +16,7 @@ define void @test() {
; RV32I-FPELIM-NEXT: lui a0, 74565
; RV32I-FPELIM-NEXT: addi a0, a0, 1664
; RV32I-FPELIM-NEXT: add sp, sp, a0
; RV32I-FPELIM-NEXT: .cfi_def_cfa_offset 0
; RV32I-FPELIM-NEXT: ret
;
; RV32I-WITHFP-LABEL: test:
Expand All @@ -34,9 +35,13 @@ define void @test() {
; RV32I-WITHFP-NEXT: lui a0, 74565
; RV32I-WITHFP-NEXT: addi a0, a0, -352
; RV32I-WITHFP-NEXT: add sp, sp, a0
; RV32I-WITHFP-NEXT: .cfi_def_cfa_offset 2032
; RV32I-WITHFP-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw s0, 2024(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: .cfi_restore ra
; RV32I-WITHFP-NEXT: .cfi_restore s0
; RV32I-WITHFP-NEXT: addi sp, sp, 2032
; RV32I-WITHFP-NEXT: .cfi_def_cfa_offset 0
; RV32I-WITHFP-NEXT: ret
%tmp = alloca [ 305419896 x i8 ] , align 4
ret void
Expand Down Expand Up @@ -71,9 +76,13 @@ define void @test_emergency_spill_slot(i32 %a) {
; RV32I-FPELIM-NEXT: lui a0, 97
; RV32I-FPELIM-NEXT: addi a0, a0, 672
; RV32I-FPELIM-NEXT: add sp, sp, a0
; RV32I-FPELIM-NEXT: .cfi_def_cfa_offset 2032
; RV32I-FPELIM-NEXT: lw s0, 2028(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: lw s1, 2024(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: .cfi_restore s0
; RV32I-FPELIM-NEXT: .cfi_restore s1
; RV32I-FPELIM-NEXT: addi sp, sp, 2032
; RV32I-FPELIM-NEXT: .cfi_def_cfa_offset 0
; RV32I-FPELIM-NEXT: ret
;
; RV32I-WITHFP-LABEL: test_emergency_spill_slot:
Expand Down Expand Up @@ -108,11 +117,17 @@ define void @test_emergency_spill_slot(i32 %a) {
; RV32I-WITHFP-NEXT: lui a0, 97
; RV32I-WITHFP-NEXT: addi a0, a0, 688
; RV32I-WITHFP-NEXT: add sp, sp, a0
; RV32I-WITHFP-NEXT: .cfi_def_cfa_offset 2032
; RV32I-WITHFP-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw s0, 2024(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw s1, 2020(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw s2, 2016(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: .cfi_restore ra
; RV32I-WITHFP-NEXT: .cfi_restore s0
; RV32I-WITHFP-NEXT: .cfi_restore s1
; RV32I-WITHFP-NEXT: .cfi_restore s2
; RV32I-WITHFP-NEXT: addi sp, sp, 2032
; RV32I-WITHFP-NEXT: .cfi_def_cfa_offset 0
; RV32I-WITHFP-NEXT: ret
%data = alloca [ 100000 x i32 ] , align 4
%ptr = getelementptr inbounds [100000 x i32], ptr %data, i32 0, i32 80000
Expand Down
2 changes: 2 additions & 0 deletions llvm/test/CodeGen/RISCV/live-sp.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -81,7 +81,9 @@ body: |
; CHECK-NEXT: $x10 = COPY $x0
; CHECK-NEXT: PseudoCALL target-flags(riscv-call) @vararg, csr_ilp32_lp64, implicit-def dead $x1, implicit killed $x10, implicit $x11, implicit-def $x2
; CHECK-NEXT: $x1 = LD $x2, 8 :: (load (s64) from %stack.1)
; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $x1
; CHECK-NEXT: $x2 = frame-destroy ADDI $x2, 16
; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 0
; CHECK-NEXT: PseudoRET
SW renamable $x1, %stack.0.a, 0 :: (store (s32) into %ir.a)
renamable $x11 = ADDIW killed renamable $x1, 0
Expand Down
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