diff --git a/llvm/test/CodeGen/AArch64/expand-blr-rvmarker-pseudo.mir b/llvm/test/CodeGen/AArch64/expand-blr-rvmarker-pseudo.mir
@@ -31,6 +31,8 @@
 
 # CHECK-LABEL: : test_1_callsite_info
 # CHECK:       bb.0:
+# CHECK-NEXT: liveins:
+# CHECK-NEXT: {{  $}}
 # CHECK-NEXT:    BUNDLE implicit-def $lr, implicit-def $w30, implicit-def $sp, implicit-def $wsp, implicit-def dead $x0, implicit-def $fp, implicit-def $w29, implicit $x0, implicit $sp, implicit $xzr, implicit $fp {
 # CHECK-NEXT:      BLR $x0, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def dead $x0
 # CHECK-NEXT:      ORRXrs $xzr, $fp, 0
@@ -52,6 +54,8 @@ body:             |
 
 # CHECK-LABEL: : test_bl_pass_x0_arg
 # CHECK:       bb.0:
+# CHECK-NEXT: liveins:
+# CHECK-NEXT: {{  $}}
 # CHECK-NEXT:     BUNDLE implicit-def $lr, implicit-def $w30, implicit-def $sp, implicit-def $wsp, implicit-def dead $x0, implicit-def $fp, implicit-def $w29, implicit $sp, implicit $x0, implicit $xzr, implicit $fp {
 # CHECK-NEXT:      BL @foo, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def dead $x0
 # CHECK-NEXT:      $fp = ORRXrs $xzr, $fp, 0
@@ -70,6 +74,8 @@ body:             |
 
 # CHECK-LABEL: : test_bl_pass_x0_x1_x2_args
 # CHECK:       bb.0:
+# CHECK-NEXT: liveins:
+# CHECK-NEXT: {{  $}}
 # CHECK-NEXT:     BUNDLE implicit-def $lr, implicit-def $w30, implicit-def $sp, implicit-def $wsp, implicit-def $x0, implicit-def $w0, implicit-def $fp, implicit-def $w29, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $xzr, implicit $fp {
 # CHECK-NEXT:      BL @foo, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $x0
 # CHECK-NEXT:      $fp = ORRXrs $xzr, $fp, 0
@@ -88,6 +94,8 @@ body:             |
 
 # CHECK-LABEL: : test_bl_pass_w0_w1_args
 # CHECK:       bb.0:
+# CHECK-NEXT: liveins:
+# CHECK-NEXT: {{  $}}
 # CHECK-NEXT:     BUNDLE implicit-def $lr, implicit-def $w30, implicit-def $sp, implicit-def $wsp, implicit-def dead $x0, implicit-def $fp, implicit-def $w29, implicit $sp, implicit $w0, implicit $w1, implicit $xzr, implicit $fp {
 # CHECK-NEXT:      BL @foo, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit $w1, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def dead $x0
 # CHECK-NEXT:      $fp = ORRXrs $xzr, $fp, 0
@@ -107,6 +115,8 @@ body:             |
 
 # CHECK-LABEL: : test_blr_pass_w0_w1_args
 # CHECK:       bb.0:
+# CHECK-NEXT: liveins:
+# CHECK-NEXT: {{  $}}
 # CHECK-NEXT:     BUNDLE implicit-def $lr, implicit-def $w30, implicit-def $sp, implicit-def $wsp, implicit-def dead $x0, implicit-def $fp, implicit-def $w29, implicit $x8, implicit $sp, implicit $w0, implicit $w1, implicit $xzr, implicit $fp {
 # CHECK-NEXT:      BLR $x8, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit $w1, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def dead $x0
 # CHECK-NEXT:      $fp = ORRXrs $xzr, $fp, 0

diff --git a/llvm/test/CodeGen/AArch64/framelayout-sve.mir b/llvm/test/CodeGen/AArch64/framelayout-sve.mir
@@ -116,6 +116,8 @@ body:             |
 # CHECK:       stackSize: 48
 
 # CHECK:      bb.0.entry:
+# CHECK-NEXT: liveins:
+# CHECK-NEXT: {{  $}}
 # CHECK-NEXT: $sp = frame-setup STRXpre killed $[[SCRATCH:[a-z0-9]+]], $sp, -32
 # CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 32
 # CHECK-NEXT: frame-setup STPXi killed $x21, killed $x20, $sp, 2
@@ -194,6 +196,8 @@ body:             |
 # CHECK:       stackSize: 32
 
 # CHECK:      bb.0.entry:
+# CHECK-NEXT: liveins:
+# CHECK-NEXT: {{  $}}
 # CHECK-NEXT: $sp = frame-setup STPXpre killed $fp, killed $lr, $sp, -2
 # CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16
 # CHECK-NEXT: $fp = frame-setup ADDXri $sp, 0, 0
@@ -257,6 +261,8 @@ body:             |
 # CHECK:       stackSize: 32
 
 # CHECK:      bb.0.entry:
+# CHECK-NEXT: liveins:
+# CHECK-NEXT: {{  $}}
 # CHECK-NEXT: $sp = frame-setup STRXpre killed $[[SCRATCH:[a-z0-9]+]], $sp, -16
 # CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16
 # CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $w29, -16
@@ -338,6 +344,8 @@ body:             |
 # CHECK:       stackSize: 32
 
 # CHECK:      bb.0.entry:
+# CHECK-NEXT: liveins:
+# CHECK-NEXT: {{  $}}
 # CHECK-NEXT: $sp = frame-setup STPXpre killed $fp, killed $lr, $sp, -2
 # CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16
 # CHECK-NEXT: $fp = frame-setup ADDXri $sp, 0, 0
@@ -414,6 +422,8 @@ body:             |
 # CHECK:       stackSize: 32
 
 # CHECK:      bb.0.entry:
+# CHECK-NEXT: liveins:
+# CHECK-NEXT: {{  $}}
 # CHECK-NEXT: $sp = frame-setup STRXpre killed $[[SCRATCH:[a-z0-9]+]], $sp, -16
 # CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16
 # CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $w29, -16
@@ -485,6 +495,8 @@ body:             |
 # CHECK:       stackSize: 16
 
 # CHECK:      bb.0.entry:
+# CHECK-NEXT: liveins:
+# CHECK-NEXT: {{  $}}
 # CHECK-NEXT: $sp = frame-setup STRXpre killed $[[SCRATCH:[a-z0-9]+]], $sp, -16
 # CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16
 # CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $w29, -16
@@ -617,6 +629,8 @@ body:             |
 
 # CHECK-LABEL: name: test_address_gpr_vla
 # CHECK: bb.0.entry:
+# CHECK-NEXT: liveins:
+# CHECK-NEXT: {{  $}}
 # CHECK-NEXT: early-clobber $sp = frame-setup STPXpre killed $fp, killed $lr, $sp, -4
 # CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 32
 # CHECK-NEXT: frame-setup STRXui killed $x19, $sp, 2
@@ -1165,6 +1179,8 @@ body:             |
 # CHECK-NEXT:       stack-id: default, callee-saved-register: '$fp',
 #
 # CHECK:      bb.0.entry:
+# CHECK-NEXT: liveins:
+# CHECK-NEXT: {{  $}}
 # CHECK-NEXT: $sp = frame-setup STRXpre killed $[[SCRATCH:[a-z0-9]+]], $sp, -16
 # CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16
 # CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $w29, -16

diff --git a/llvm/test/CodeGen/AMDGPU/hazard-buffer-store-v-interp.mir b/llvm/test/CodeGen/AMDGPU/hazard-buffer-store-v-interp.mir
@@ -10,8 +10,6 @@
 name:            hazard_buffer_store_v_interp
 body:             |
   bb.0.entry:
-    liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr7, $vgpr8, $vgpr9, $vgpr10
-
     BUFFER_STORE_DWORDX4_OFFSET_exact killed $vgpr7_vgpr8_vgpr9_vgpr10, $sgpr4_sgpr5_sgpr6_sgpr7, 0, 96, 0, 0, 0, implicit $exec
     $vgpr7 = V_INTERP_P1_F32 $vgpr0, 0, 0, implicit $mode, implicit $m0, implicit $exec
     S_ENDPGM 0

diff --git a/llvm/test/CodeGen/AMDGPU/optimize-compare.mir b/llvm/test/CodeGen/AMDGPU/optimize-compare.mir
diff --git a/llvm/test/CodeGen/AMDGPU/v_swap_b32.mir b/llvm/test/CodeGen/AMDGPU/v_swap_b32.mir
diff --git a/llvm/test/CodeGen/MIR/AArch64/mirnamer.mir b/llvm/test/CodeGen/MIR/AArch64/mirnamer.mir
@@ -6,6 +6,8 @@ body:             |
   bb.0:
 
     ;CHECK-LABEL: bb.0
+    ;CHECK-NEXT: liveins
+    ;CHECK-NEXT: {{  $}}
     ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:_(p0) = COPY $d0
     ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:_(<4 x s32>) = COPY $q0
     ;CHECK-NEXT: G_STORE %bb0_{{[0-9]+}}__1(<4 x s32>), %bb0_{{[0-9]+}}__1(p0) :: (store (<4 x s32>))
@@ -74,6 +76,8 @@ body:             |
     liveins: $x0, $x1, $d0, $d1
 
     ;CHECK-LABEL: bb.0:
+    ;CHECK-NEXT: liveins
+    ;CHECK-NEXT: {{  $}}
     ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = LDRWui %stack.0, 0
     ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = COPY %bb0_{{[0-9]+}}__1
     ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = COPY %bb0_{{[0-9]+}}__1

diff --git a/llvm/test/CodeGen/Mips/shrink-wrap-buildpairf64-extractelementf64.mir b/llvm/test/CodeGen/Mips/shrink-wrap-buildpairf64-extractelementf64.mir
@@ -33,7 +33,9 @@ name: testBuildPairF64
 # CHECK-LABEL: name: testBuildPairF64
 # CHECK: bb.0
 # CHECK-NEXT: successors
+# CHECK-NEXT: liveins:
 # CHECK-NEXT: {{[[:space:]]$}}
+
 # CHECK-NEXT: BuildPairF64
 body: |
   bb.0:
@@ -48,6 +50,7 @@ name: testBuildPairF64_64
 # CHECK-LABEL: name: testBuildPairF64_64
 # CHECK: bb.0
 # CHECK-NEXT: successors
+# CHECK-NEXT: liveins:
 # CHECK-NEXT: {{[[:space:]]$}}
 # CHECK-NEXT: BuildPairF64_64
 body: |
@@ -63,6 +66,7 @@ name: testBuildPairF64implicitSp
 # CHECK-LABEL: name: testBuildPairF64implicitSp
 # CHECK: bb.0
 # CHECK-NEXT: successors
+# CHECK-NEXT: liveins:
 # CHECK-NEXT: {{[[:space:]]$}}
 # CHECK-NEXT: $sp = ADDiu $sp, -{{[0-9]+}}
 body: |
@@ -78,6 +82,7 @@ name: testBuildPairF64_64implicitSp
 # CHECK-LABEL: name: testBuildPairF64_64implicitSp
 # CHECK: bb.0
 # CHECK-NEXT: successors
+# CHECK-NEXT: liveins:
 # CHECK-NEXT: {{[[:space:]]$}}
 # CHECK-NEXT: $sp = ADDiu $sp, -{{[0-9]+}}
 body: |
@@ -93,6 +98,7 @@ name: testExtractElementF64
 # CHECK-LABEL: name: testExtractElementF64
 # CHECK: bb.0
 # CHECK-NEXT: successors
+# CHECK-NEXT: liveins:
 # CHECK-NEXT: {{[[:space:]]$}}
 # CHECK-NEXT: ExtractElementF64
 body: |
@@ -108,6 +114,7 @@ name: testExtractElementF64_64
 # CHECK-LABEL: name: testExtractElementF64_64
 # CHECK: bb.0
 # CHECK-NEXT: successors
+# CHECK-NEXT: liveins:
 # CHECK-NEXT: {{[[:space:]]$}}
 # CHECK-NEXT: ExtractElementF64_64
 body: |
@@ -123,6 +130,7 @@ name: testExtractElementF64implicitSp
 # CHECK-LABEL: name: testExtractElementF64implicitSp
 # CHECK: bb.0
 # CHECK-NEXT: successors
+# CHECK-NEXT: liveins:
 # CHECK-NEXT: {{[[:space:]]$}}
 # CHECK-NEXT: $sp = ADDiu $sp, -{{[0-9]+}}
 body: |
@@ -138,6 +146,7 @@ name: testExtractElementF64_64implicitSp
 # CHECK-LABEL: name: testExtractElementF64_64implicitSp
 # CHECK: bb.0
 # CHECK-NEXT: successors
+# CHECK-NEXT: liveins:
 # CHECK-NEXT: {{[[:space:]]$}}
 # CHECK-NEXT: $sp = ADDiu $sp, -{{[0-9]+}}
 body: |

diff --git a/llvm/test/CodeGen/RISCV/copy-frameindex.mir b/llvm/test/CodeGen/RISCV/copy-frameindex.mir
@@ -40,6 +40,7 @@ body: |
   ; CHECK-LABEL: name: sink_addi_fi
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
+  ; CHECK-NEXT:   liveins: $x10
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $x10
   ; CHECK-NEXT:   BEQ killed [[COPY]], $x0, %bb.2

diff --git a/llvm/test/CodeGen/X86/flags-copy-lowering.mir b/llvm/test/CodeGen/X86/flags-copy-lowering.mir
@@ -4,9 +4,9 @@
 
 --- |
   target triple = "x86_64-unknown-unknown"
-  
+
   declare void @foo()
-  
+
   define i32 @test_branch(i64 %a, i64 %b) {
   entry:
     call void @foo()
@@ -106,14 +106,14 @@
 ---
 name:            test_branch
 # CHECK-LABEL: name: test_branch
-liveins:         
+liveins:
   - { reg: '$rdi', virtual-reg: '%0' }
   - { reg: '$rsi', virtual-reg: '%1' }
 body:             |
   bb.0:
     successors: %bb.1, %bb.2, %bb.3
     liveins: $rdi, $rsi
-  
+
     %0:gr64 = COPY $rdi
     %1:gr64 = COPY $rsi
     CMP64rr %0, %1, implicit-def $eflags
@@ -142,17 +142,17 @@ body:             |
   ; CHECK-NEXT:   TEST8rr %[[B_REG]], %[[B_REG]], implicit-def $eflags
   ; CHECK-NEXT:   JCC_1 %bb.2, 5, implicit killed $eflags
   ; CHECK-NEXT:   JMP_1 %bb.3
-  
+
   bb.1:
     %3:gr32 = MOV32ri 42
     $eax = COPY %3
     RET 0, $eax
-  
+
   bb.2:
     %4:gr32 = MOV32ri 43
     $eax = COPY %4
     RET 0, $eax
-  
+
   bb.3:
     %5:gr32 = MOV32r0 implicit-def dead $eflags
     $eax = COPY %5
@@ -162,14 +162,14 @@ body:             |
 ---
 name:            test_branch_fallthrough
 # CHECK-LABEL: name: test_branch_fallthrough
-liveins:         
+liveins:
   - { reg: '$rdi', virtual-reg: '%0' }
   - { reg: '$rsi', virtual-reg: '%1' }
 body:             |
   bb.0:
     successors: %bb.1, %bb.2, %bb.3
     liveins: $rdi, $rsi
-  
+
     %0:gr64 = COPY $rdi
     %1:gr64 = COPY $rsi
     CMP64rr %0, %1, implicit-def $eflags
@@ -203,28 +203,28 @@ body:             |
     %5:gr32 = MOV32r0 implicit-def dead $eflags
     $eax = COPY %5
     RET 0, $eax
-  
+
   bb.2:
     %3:gr32 = MOV32ri 42
     $eax = COPY %3
     RET 0, $eax
-  
+
   bb.3:
     %4:gr32 = MOV32ri 43
     $eax = COPY %4
     RET 0, $eax
-  
+
 ...
 ---
 name:            test_setcc
 # CHECK-LABEL: name: test_setcc
-liveins:         
+liveins:
   - { reg: '$rdi', virtual-reg: '%0' }
   - { reg: '$rsi', virtual-reg: '%1' }
 body:             |
   bb.0:
     liveins: $rdi, $rsi
-  
+
     %0:gr64 = COPY $rdi
     %1:gr64 = COPY $rsi
     CMP64rr %0, %1, implicit-def $eflags
@@ -261,13 +261,13 @@ body:             |
 ---
 name:            test_cmov
 # CHECK-LABEL: name: test_cmov
-liveins:         
+liveins:
   - { reg: '$rdi', virtual-reg: '%0' }
   - { reg: '$rsi', virtual-reg: '%1' }
 body:             |
   bb.0:
     liveins: $rdi, $rsi
-  
+
     %0:gr64 = COPY $rdi
     %1:gr64 = COPY $rsi
     CMP64rr %0, %1, implicit-def $eflags
@@ -307,13 +307,13 @@ body:             |
 ---
 name:            test_adc
 # CHECK-LABEL: name: test_adc
-liveins:         
+liveins:
   - { reg: '$rdi', virtual-reg: '%0' }
   - { reg: '$rsi', virtual-reg: '%1' }
 body:             |
   bb.0:
     liveins: $rdi, $rsi
-  
+
     %0:gr64 = COPY $rdi
     %1:gr64 = COPY $rsi
     %2:gr64 = ADD64rr %0, %1, implicit-def $eflags
@@ -341,13 +341,13 @@ body:             |
 ---
 name:            test_sbb
 # CHECK-LABEL: name: test_sbb
-liveins:         
+liveins:
   - { reg: '$rdi', virtual-reg: '%0' }
   - { reg: '$rsi', virtual-reg: '%1' }
 body:             |
   bb.0:
     liveins: $rdi, $rsi
-  
+
     %0:gr64 = COPY $rdi
     %1:gr64 = COPY $rsi
     %2:gr64 = SUB64rr %0, %1, implicit-def $eflags
@@ -375,13 +375,13 @@ body:             |
 ---
 name:            test_adcx
 # CHECK-LABEL: name: test_adcx
-liveins:         
+liveins:
   - { reg: '$rdi', virtual-reg: '%0' }
   - { reg: '$rsi', virtual-reg: '%1' }
 body:             |
   bb.0:
     liveins: $rdi, $rsi
-  
+
     %0:gr64 = COPY $rdi
     %1:gr64 = COPY $rsi
     %2:gr64 = ADD64rr %0, %1, implicit-def $eflags
@@ -414,13 +414,13 @@ body:             |
 ---
 name:            test_adox
 # CHECK-LABEL: name: test_adox
-liveins:         
+liveins:
   - { reg: '$rdi', virtual-reg: '%0' }
   - { reg: '$rsi', virtual-reg: '%1' }
 body:             |
   bb.0:
     liveins: $rdi, $rsi
-  
+
     %0:gr64 = COPY $rdi
     %1:gr64 = COPY $rsi
     %2:gr64 = ADD64rr %0, %1, implicit-def $eflags
@@ -453,13 +453,13 @@ body:             |
 ---
 name:            test_rcl
 # CHECK-LABEL: name: test_rcl
-liveins:         
+liveins:
   - { reg: '$rdi', virtual-reg: '%0' }
   - { reg: '$rsi', virtual-reg: '%1' }
 body:             |
   bb.0:
     liveins: $rdi, $rsi
-  
+
     %0:gr64 = COPY $rdi
     %1:gr64 = COPY $rsi
     %2:gr64 = ADD64rr %0, %1, implicit-def $eflags
@@ -487,13 +487,13 @@ body:             |
 ---
 name:            test_rcr
 # CHECK-LABEL: name: test_rcr
-liveins:         
+liveins:
   - { reg: '$rdi', virtual-reg: '%0' }
   - { reg: '$rsi', virtual-reg: '%1' }
 body:             |
   bb.0:
     liveins: $rdi, $rsi
-  
+
     %0:gr64 = COPY $rdi
     %1:gr64 = COPY $rsi
     %2:gr64 = ADD64rr %0, %1, implicit-def $eflags
@@ -920,6 +920,7 @@ body:             |
     $rax = COPY %8
     RET 0, $rax
   ; CHECK:      bb.9:
+  ; CHECK-NEXT: liveins: $eflags
   ; CHECK-NOT:     $eflags
   ; CHECK:         %8:gr64 = CMOV64rr %0, %1, 4, implicit killed $eflags
 

diff --git a/llvm/test/CodeGen/X86/optimize-compare.mir b/llvm/test/CodeGen/X86/optimize-compare.mir
@@ -609,6 +609,7 @@ body: |
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.3(0x40000000)
+  ; CHECK-NEXT:   liveins: $eflags
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   JCC_1 %bb.2, 15, implicit $eflags
   ; CHECK-NEXT:   JMP_1 %bb.3
@@ -659,6 +660,7 @@ body: |
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.2:
   ; CHECK-NEXT:   successors: %bb.3(0x80000000)
+  ; CHECK-NEXT:   liveins: $eflags
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   $al = SETCCr 4, implicit $eflags
   ; CHECK-NEXT: {{  $}}
@@ -725,6 +727,8 @@ body: |
   ; CHECK-NEXT:   JMP_1 %bb.1
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   liveins: $eflags
+  ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   $al = SETCCr 14, implicit $eflags
   bb.0:
     %0:gr64 = COPY $rsi

diff --git a/llvm/test/tools/UpdateTestChecks/update_mir_test_checks/Inputs/x86-condbr.mir.expected b/llvm/test/tools/UpdateTestChecks/update_mir_test_checks/Inputs/x86-condbr.mir.expected
@@ -30,6 +30,7 @@ body:             |
   ; CHECK-LABEL: name: test
   ; CHECK: bb.0.entry:
   ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; CHECK-NEXT:   liveins: $edi
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gr32 = COPY $edi
   ; CHECK-NEXT:   [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags

diff --git a/llvm/test/tools/llvm-reduce/mir/reduce-instruction-unreachable-block.mir b/llvm/test/tools/llvm-reduce/mir/reduce-instruction-unreachable-block.mir
@@ -0,0 +1,43 @@
+# REQUIRES: amdgpu-registered-target
+# RUN: llvm-reduce -simplify-mir -mtriple=amdgcn-amd-amdhsa --delta-passes=instructions --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
+# RUN: FileCheck --check-prefix=RESULT %s < %t
+
+# Make sure there's no crash with unreachable blocks.
+
+# CHECK-INTERESTINGNESS: S_NOP
+
+# RESULT: bb.0:
+
+# RESULT: %3:vgpr_32 = IMPLICIT_DEF
+# RESULT-NEXT: %4:sreg_64 = IMPLICIT_DEF
+# RESULT-NEXT: %5:vreg_64 = IMPLICIT_DEF
+# RESULT-NEXT: S_CBRANCH_SCC1 %bb.1, implicit undef $scc
+# RESULT-NEXT: S_BRANCH %bb.3
+
+# RESULT: bb.1:
+# RESULT-NEXT: S_BRANCH %bb.3
+
+# RESULT: bb.2:
+# RESULT-NEXT: S_NOP 0, implicit %3, implicit killed %5, implicit %4
+
+---
+name: unreachable_block
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    S_CBRANCH_SCC1 %bb.1, implicit undef $scc
+    S_BRANCH %bb.3
+
+  bb.1:
+    %1:sreg_64 = S_MOV_B64 0
+    S_BRANCH %bb.3
+
+  bb.2:
+    %2:vreg_64 = IMPLICIT_DEF
+    S_NOP 0, implicit %0, implicit killed %2, implicit %1
+    S_BRANCH %bb.3
+
+  bb.3:
+
+...
diff --git a/llvm/test/tools/llvm-reduce/mir/tracks-reg-liveness.mir b/llvm/test/tools/llvm-reduce/mir/tracks-reg-liveness.mir
@@ -0,0 +1,29 @@
+# REQUIRES: amdgpu-registered-target
+# RUN: llvm-reduce -simplify-mir --delta-passes=instructions -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
+# RUN: FileCheck --check-prefix=RESULT %s < %t
+
+# CHECK-INTERESTINGNESS: V_MOV_B32_e32 $vgpr0
+# CHECK-INTERESTINGNESS: S_NOP 0
+
+# The block liveins list needs to be carried through even though this
+# tracksRegLiveness is false
+
+# RESULT: bb.0:
+# RESULT-NEXT: liveins: $vgpr0, $vgpr1_vgpr2
+# RESULT: %0:vgpr_32 = V_MOV_B32_e32 $vgpr0, implicit $exec
+# RESULT-NEXT: S_NOP 0
+# RESULT-NEXT: S_ENDPGM 0, implicit %0, implicit %0
+
+---
+name: func
+tracksRegLiveness: false
+body:             |
+  bb.0:
+    liveins: $vgpr0, $vgpr1_vgpr2
+    S_WAITCNT 0
+    %0:vgpr_32 = V_MOV_B32_e32 $vgpr0, implicit $exec
+    %1:vgpr_32 = V_MOV_B32_e32 $vgpr1, implicit $exec
+    S_NOP 0
+    S_ENDPGM 0, implicit %0, implicit %1
+...
+
diff --git a/llvm/tools/llvm-reduce/ReducerWorkItem.cpp b/llvm/tools/llvm-reduce/ReducerWorkItem.cpp
@@ -276,7 +276,8 @@ static std::unique_ptr<MachineFunction> cloneMF(MachineFunction *SrcMF,
       auto *DstSuccMBB = Src2DstMBB[SrcSuccMBB];
       DstMBB->addSuccessor(DstSuccMBB, SrcMBB.getSuccProbability(It));
     }
-    for (auto &LI : SrcMBB.liveins())
+
+    for (auto &LI : SrcMBB.liveins_dbg())
       DstMBB->addLiveIn(LI);
 
     // Make sure MRI knows about registers clobbered by unwinder.

diff --git a/llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp b/llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp
@@ -106,14 +106,17 @@ static void extractInstrFromFunction(Oracle &O, MachineFunction &MF) {
         MachineBasicBlock::reverse_iterator RI(*MI);
         MachineBasicBlock *BB = MI->getParent();
         ++RI;
-        while (NewReg == 0 && BB) {
-          NewReg = getPrevDefOfRCInMBB(*BB, RI, RegRC, RegTy, ToDelete);
-          // Prepare for idom(BB).
-          if (auto *IDM = MDT.getNode(BB)->getIDom()) {
-            BB = IDM->getBlock();
-            RI = BB->rbegin();
-          } else {
-            BB = nullptr;
+
+        if (MDT.isReachableFromEntry(BB)) {
+          while (NewReg == 0 && BB) {
+            NewReg = getPrevDefOfRCInMBB(*BB, RI, RegRC, RegTy, ToDelete);
+            // Prepare for idom(BB).
+            if (auto *IDM = MDT.getNode(BB)->getIDom()) {
+              BB = IDM->getBlock();
+              RI = BB->rbegin();
+            } else {
+              BB = nullptr;
+            }
           }
         }
       }