diff --git a/llvm/lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp
@@ -12,8 +12,8 @@
 //===----------------------------------------------------------------------===//
 
 #include "RISCVInstPrinter.h"
-#include "MCTargetDesc/RISCVBaseInfo.h"
 #include "MCTargetDesc/RISCVMCExpr.h"
+#include "Utils/RISCVBaseInfo.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInst.h"
@@ -36,10 +36,9 @@ using namespace llvm;
 #include "RISCVGenCompressInstEmitter.inc"
 
 static cl::opt<bool>
-NoAliases("riscv-no-aliases",
-            cl::desc("Disable the emission of assembler pseudo instructions"),
-            cl::init(false),
-            cl::Hidden);
+    NoAliases("riscv-no-aliases",
+              cl::desc("Disable the emission of assembler pseudo instructions"),
+              cl::init(false), cl::Hidden);
 
 void RISCVInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
                                  StringRef Annot, const MCSubtargetInfo &STI) {
@@ -49,7 +48,7 @@ void RISCVInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
   if (!NoAliases)
     Res = uncompressInst(UncompressedMI, *MI, MRI, STI);
   if (Res)
-    NewMI = const_cast<MCInst*>(&UncompressedMI);
+    NewMI = const_cast<MCInst *>(&UncompressedMI);
   if (NoAliases || !printAliasInstr(NewMI, STI, O))
     printInstruction(NewMI, STI, O);
   printAnnotation(O, Annot);
@@ -60,8 +59,8 @@ void RISCVInstPrinter::printRegName(raw_ostream &O, unsigned RegNo) const {
 }
 
 void RISCVInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
-                                    const MCSubtargetInfo &STI,
-                                    raw_ostream &O, const char *Modifier) {
+                                    const MCSubtargetInfo &STI, raw_ostream &O,
+                                    const char *Modifier) {
   assert((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported");
   const MCOperand &MO = MI->getOperand(OpNo);
 
@@ -79,6 +78,17 @@ void RISCVInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
   MO.getExpr()->print(O, &MAI);
 }
 
+void RISCVInstPrinter::printCSRSystemRegister(const MCInst *MI, unsigned OpNo,
+                                              const MCSubtargetInfo &STI,
+                                              raw_ostream &O) {
+  unsigned Imm = MI->getOperand(OpNo).getImm();
+  auto SysReg = RISCVSysReg::lookupSysRegByEncoding(Imm);
+  if (SysReg && SysReg->haveRequiredFeatures(STI.getFeatureBits()))
+    O << SysReg->Name;
+  else
+    O << Imm;
+}
+
 void RISCVInstPrinter::printFenceArg(const MCInst *MI, unsigned OpNo,
                                      const MCSubtargetInfo &STI,
                                      raw_ostream &O) {
@@ -94,8 +104,7 @@ void RISCVInstPrinter::printFenceArg(const MCInst *MI, unsigned OpNo,
 }
 
 void RISCVInstPrinter::printFRMArg(const MCInst *MI, unsigned OpNo,
-                                   const MCSubtargetInfo &STI,
-                                   raw_ostream &O) {
+                                   const MCSubtargetInfo &STI, raw_ostream &O) {
   auto FRMArg =
       static_cast<RISCVFPRndMode::RoundingMode>(MI->getOperand(OpNo).getImm());
   O << RISCVFPRndMode::roundingModeToString(FRMArg);

diff --git a/llvm/lib/Target/RISCV/InstPrinter/RISCVInstPrinter.h b/llvm/lib/Target/RISCV/InstPrinter/RISCVInstPrinter.h
@@ -32,6 +32,8 @@ class RISCVInstPrinter : public MCInstPrinter {
 
   void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
                     raw_ostream &O, const char *Modifier = nullptr);
+  void printCSRSystemRegister(const MCInst *MI, unsigned OpNo,
+                              const MCSubtargetInfo &STI, raw_ostream &O);
   void printFenceArg(const MCInst *MI, unsigned OpNo,
                      const MCSubtargetInfo &STI, raw_ostream &O);
   void printFRMArg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
@@ -48,6 +50,6 @@ class RISCVInstPrinter : public MCInstPrinter {
   static const char *getRegisterName(unsigned RegNo,
                                      unsigned AltIdx = RISCV::ABIRegAltName);
 };
-}
+} // namespace llvm
 
 #endif
diff --git a/llvm/lib/Target/RISCV/LLVMBuild.txt b/llvm/lib/Target/RISCV/LLVMBuild.txt
@@ -16,7 +16,7 @@
 ;===------------------------------------------------------------------------===;
 
 [common]
-subdirectories = AsmParser Disassembler InstPrinter TargetInfo MCTargetDesc
+subdirectories = AsmParser Disassembler InstPrinter TargetInfo MCTargetDesc Utils
 
 [component_0]
 type = TargetGroup
@@ -31,5 +31,5 @@ type = Library
 name = RISCVCodeGen
 parent = RISCV
 required_libraries = AsmPrinter Core CodeGen MC RISCVAsmPrinter RISCVDesc
-  RISCVInfo SelectionDAG Support Target
+  RISCVInfo RISCVUtils SelectionDAG Support Target
 add_to_library_groups = RISCV
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
@@ -11,10 +11,10 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "MCTargetDesc/RISCVBaseInfo.h"
 #include "MCTargetDesc/RISCVFixupKinds.h"
 #include "MCTargetDesc/RISCVMCExpr.h"
 #include "MCTargetDesc/RISCVMCTargetDesc.h"
+#include "Utils/RISCVBaseInfo.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCCodeEmitter.h"

diff --git a/llvm/lib/Target/RISCV/RISCV.h b/llvm/lib/Target/RISCV/RISCV.h
@@ -15,7 +15,7 @@
 #ifndef LLVM_LIB_TARGET_RISCV_RISCV_H
 #define LLVM_LIB_TARGET_RISCV_RISCV_H
 
-#include "MCTargetDesc/RISCVBaseInfo.h"
+#include "Utils/RISCVBaseInfo.h"
 #include "llvm/Target/TargetMachine.h"
 
 namespace llvm {

diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
@@ -67,6 +67,12 @@ include "RISCVRegisterInfo.td"
 include "RISCVCallingConv.td"
 include "RISCVInstrInfo.td"
 
+//===----------------------------------------------------------------------===//
+// Named operands for CSR instructions.
+//===----------------------------------------------------------------------===//
+
+include "RISCVSystemOperands.td"
+
 //===----------------------------------------------------------------------===//
 // RISC-V processors supported.
 //===----------------------------------------------------------------------===//

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -125,11 +125,6 @@ def simm12 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<12>(Imm);}]> {
   }];
 }
 
-def uimm12 : Operand<XLenVT> {
-  let ParserMatchClass = UImmAsmOperand<12>;
-  let DecoderMethod = "decodeUImmOperand<12>";
-}
-
 // A 13-bit signed immediate where the least significant bit is zero.
 def simm13_lsb0 : Operand<OtherVT> {
   let ParserMatchClass = SImmAsmOperand<13, "Lsb0">;
@@ -190,6 +185,18 @@ def bare_symbol : Operand<XLenVT> {
   let ParserMatchClass = BareSymbol;
 }
 
+def CSRSystemRegister : AsmOperandClass {
+  let Name = "CSRSystemRegister";
+  let ParserMethod = "parseCSRSystemRegister";
+  let DiagnosticType = "InvalidCSRSystemRegister";
+}
+
+def csr_sysreg : Operand<XLenVT> {
+  let ParserMatchClass = CSRSystemRegister;
+  let PrintMethod = "printCSRSystemRegister";
+  let DecoderMethod = "decodeUImmOperand<12>";
+}
+
 // A parameterized register class alternative to i32imm/i64imm from Target.td.
 def ixlenimm : Operand<XLenVT> {
   let ParserMatchClass = ImmXLenAsmOperand<"">;
@@ -263,13 +270,13 @@ class ALU_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
 
 let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
 class CSR_ir<bits<3> funct3, string opcodestr>
-    : RVInstI<funct3, OPC_SYSTEM, (outs GPR:$rd), (ins uimm12:$imm12, GPR:$rs1),
+    : RVInstI<funct3, OPC_SYSTEM, (outs GPR:$rd), (ins csr_sysreg:$imm12, GPR:$rs1),
               opcodestr, "$rd, $imm12, $rs1">;
 
 let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
 class CSR_ii<bits<3> funct3, string opcodestr>
     : RVInstI<funct3, OPC_SYSTEM, (outs GPR:$rd),
-              (ins uimm12:$imm12, uimm5:$rs1),
+              (ins csr_sysreg:$imm12, uimm5:$rs1),
               opcodestr, "$rd, $imm12, $rs1">;
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
@@ -546,14 +553,14 @@ def : InstAlias<"rdcycleh $rd",   (CSRRS GPR:$rd, 0xC80, X0)>;
 def : InstAlias<"rdtimeh $rd",    (CSRRS GPR:$rd, 0xC81, X0)>;
 } // Predicates = [IsRV32]
 
-def : InstAlias<"csrr $rd, $csr", (CSRRS GPR:$rd, uimm12:$csr,      X0)>;
-def : InstAlias<"csrw $csr, $rs", (CSRRW      X0, uimm12:$csr, GPR:$rs)>;
-def : InstAlias<"csrs $csr, $rs", (CSRRS      X0, uimm12:$csr, GPR:$rs)>;
-def : InstAlias<"csrc $csr, $rs", (CSRRC      X0, uimm12:$csr, GPR:$rs)>;
+def : InstAlias<"csrr $rd, $csr", (CSRRS GPR:$rd, csr_sysreg:$csr,      X0)>;
+def : InstAlias<"csrw $csr, $rs", (CSRRW      X0, csr_sysreg:$csr, GPR:$rs)>;
+def : InstAlias<"csrs $csr, $rs", (CSRRS      X0, csr_sysreg:$csr, GPR:$rs)>;
+def : InstAlias<"csrc $csr, $rs", (CSRRC      X0, csr_sysreg:$csr, GPR:$rs)>;
 
-def : InstAlias<"csrwi $csr, $imm", (CSRRWI X0, uimm12:$csr, uimm5:$imm)>;
-def : InstAlias<"csrsi $csr, $imm", (CSRRSI X0, uimm12:$csr, uimm5:$imm)>;
-def : InstAlias<"csrci $csr, $imm", (CSRRCI X0, uimm12:$csr, uimm5:$imm)>;
+def : InstAlias<"csrwi $csr, $imm", (CSRRWI X0, csr_sysreg:$csr, uimm5:$imm)>;
+def : InstAlias<"csrsi $csr, $imm", (CSRRSI X0, csr_sysreg:$csr, uimm5:$imm)>;
+def : InstAlias<"csrci $csr, $imm", (CSRRCI X0, csr_sysreg:$csr, uimm5:$imm)>;
 
 def : InstAlias<"sfence.vma",     (SFENCE_VMA      X0, X0)>;
 def : InstAlias<"sfence.vma $rs", (SFENCE_VMA GPR:$rs, X0)>;

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -0,0 +1,352 @@
+//===- RISCVSystemOperands.td ----------------------------*- tablegen -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the symbolic operands permitted for various kinds of
+// RISC-V system instruction.
+//
+//===----------------------------------------------------------------------===//
+
+include "llvm/TableGen/SearchableTable.td"
+
+//===----------------------------------------------------------------------===//
+// CSR (control and status register read/write) instruction options.
+//===----------------------------------------------------------------------===//
+
+class SysReg<string name, bits<12> op> {
+  string Name = name;
+  bits<12> Encoding = op;
+  // FIXME: add these additional fields when needed.
+  // Privilege Access: Read and Write = 0, 1, 2; Read-Only = 3.
+  // Privilege Mode: User = 0, System = 1 or Machine = 3.
+  // bits<2> ReadWrite = op{11 - 10};
+  // bits<2> XMode = op{9 - 8};
+  // Check Extra field name and what bits 7-6 correspond to.
+  // bits<2> Extra = op{7 - 6};
+  // Register number without the privilege bits.
+  // bits<6> Number = op{5 - 0};
+  code FeaturesRequired = [{ {} }];
+  bit isRV32Only = 0;
+}
+
+def SysRegsList : GenericTable {
+  let FilterClass = "SysReg";
+  // FIXME: add "ReadWrite", "Mode", "Extra", "Number" fields when needed.
+  let Fields = [ "Name", "Encoding", "FeaturesRequired", "isRV32Only" ];
+
+  let PrimaryKey = [ "Encoding" ];
+  let PrimaryKeyName = "lookupSysRegByEncoding";
+}
+
+def lookupSysRegByName : SearchIndex {
+  let Table = SysRegsList;
+  let Key = [ "Name" ];
+}
+
+// The following CSR encodings match those given in Tables 2.2,
+// 2.3, 2.4 and  2.5 in the RISC-V Instruction Set Manual
+// Volume II: Privileged Architecture.
+
+//===--------------------------
+// User Trap Setup
+//===--------------------------
+def : SysReg<"ustatus", 0x000>;
+def : SysReg<"uie", 0x004>;
+def : SysReg<"utvec", 0x005>;
+
+//===--------------------------
+// User Trap Handling
+//===--------------------------
+def : SysReg<"uscratch", 0x040>;
+def : SysReg<"uepc", 0x041>;
+def : SysReg<"ucause", 0x042>;
+def : SysReg<"utval", 0x043>;
+def : SysReg<"uip", 0x044>;
+
+//===--------------------------
+// User Floating-Point CSRs
+//===--------------------------
+
+let FeaturesRequired = [{ {RISCV::FeatureStdExtF} }] in {
+def : SysReg<"fflags", 0x001>;
+def : SysReg<"frm", 0x002>;
+def : SysReg<"fcsr", 0x003>;
+}
+
+//===--------------------------
+// User Counter/Timers
+//===--------------------------
+def : SysReg<"cycle", 0xC00>;
+def : SysReg<"time", 0xC01>;
+def : SysReg<"instret", 0xC02>;
+
+def : SysReg<"hpmcounter3", 0xC03>;
+def : SysReg<"hpmcounter4", 0xC04>;
+def : SysReg<"hpmcounter5", 0xC05>;
+def : SysReg<"hpmcounter6", 0xC06>;
+def : SysReg<"hpmcounter7", 0xC07>;
+def : SysReg<"hpmcounter8", 0xC08>;
+def : SysReg<"hpmcounter9", 0xC09>;
+def : SysReg<"hpmcounter10", 0xC0A>;
+def : SysReg<"hpmcounter11", 0xC0B>;
+def : SysReg<"hpmcounter12", 0xC0C>;
+def : SysReg<"hpmcounter13", 0xC0D>;
+def : SysReg<"hpmcounter14", 0xC0E>;
+def : SysReg<"hpmcounter15", 0xC0F>;
+def : SysReg<"hpmcounter16", 0xC10>;
+def : SysReg<"hpmcounter17", 0xC11>;
+def : SysReg<"hpmcounter18", 0xC12>;
+def : SysReg<"hpmcounter19", 0xC13>;
+def : SysReg<"hpmcounter20", 0xC14>;
+def : SysReg<"hpmcounter21", 0xC15>;
+def : SysReg<"hpmcounter22", 0xC16>;
+def : SysReg<"hpmcounter23", 0xC17>;
+def : SysReg<"hpmcounter24", 0xC18>;
+def : SysReg<"hpmcounter25", 0xC19>;
+def : SysReg<"hpmcounter26", 0xC1A>;
+def : SysReg<"hpmcounter27", 0xC1B>;
+def : SysReg<"hpmcounter28", 0xC1C>;
+def : SysReg<"hpmcounter29", 0xC1D>;
+def : SysReg<"hpmcounter30", 0xC1E>;
+def : SysReg<"hpmcounter31", 0xC1F>;
+
+let isRV32Only = 1 in {
+def: SysReg<"cycleh", 0xC80>;
+def: SysReg<"timeh", 0xC81>;
+def: SysReg<"instreth", 0xC82>;
+
+def: SysReg<"hpmcounter3h", 0xC83>;
+def: SysReg<"hpmcounter4h", 0xC84>;
+def: SysReg<"hpmcounter5h", 0xC85>;
+def: SysReg<"hpmcounter6h", 0xC86>;
+def: SysReg<"hpmcounter7h", 0xC87>;
+def: SysReg<"hpmcounter8h", 0xC88>;
+def: SysReg<"hpmcounter9h", 0xC89>;
+def: SysReg<"hpmcounter10h", 0xC8A>;
+def: SysReg<"hpmcounter11h", 0xC8B>;
+def: SysReg<"hpmcounter12h", 0xC8C>;
+def: SysReg<"hpmcounter13h", 0xC8D>;
+def: SysReg<"hpmcounter14h", 0xC8E>;
+def: SysReg<"hpmcounter15h", 0xC8F>;
+def: SysReg<"hpmcounter16h", 0xC90>;
+def: SysReg<"hpmcounter17h", 0xC91>;
+def: SysReg<"hpmcounter18h", 0xC92>;
+def: SysReg<"hpmcounter19h", 0xC93>;
+def: SysReg<"hpmcounter20h", 0xC94>;
+def: SysReg<"hpmcounter21h", 0xC95>;
+def: SysReg<"hpmcounter22h", 0xC96>;
+def: SysReg<"hpmcounter23h", 0xC97>;
+def: SysReg<"hpmcounter24h", 0xC98>;
+def: SysReg<"hpmcounter25h", 0xC99>;
+def: SysReg<"hpmcounter26h", 0xC9A>;
+def: SysReg<"hpmcounter27h", 0xC9B>;
+def: SysReg<"hpmcounter28h", 0xC9C>;
+def: SysReg<"hpmcounter29h", 0xC9D>;
+def: SysReg<"hpmcounter30h", 0xC9E>;
+def: SysReg<"hpmcounter31h", 0xC9F>;
+}
+
+//===--------------------------
+// Supervisor Trap Setup
+//===--------------------------
+def : SysReg<"sstatus", 0x100>;
+def : SysReg<"sedeleg", 0x102>;
+def : SysReg<"sideleg", 0x103>;
+def : SysReg<"sie", 0x104>;
+def : SysReg<"stvec", 0x105>;
+def : SysReg<"scounteren", 0x106>;
+
+//===--------------------------
+// Supervisor Trap Handling
+//===--------------------------
+def : SysReg<"sscratch", 0x140>;
+def : SysReg<"sepc", 0x141>;
+def : SysReg<"scause", 0x142>;
+def : SysReg<"stval", 0x143>;
+def : SysReg<"sip", 0x144>;
+
+//===-------------------------------------
+// Supervisor Protection and Translation
+//===-------------------------------------
+def : SysReg<"satp", 0x180>;
+
+//===-----------------------------
+// Machine Information Registers
+//===-----------------------------
+
+def : SysReg<"mvendorid", 0xF11>;
+def : SysReg<"marchid", 0xF12>;
+def : SysReg<"mimpid", 0xF13>;
+def : SysReg<"mhartid", 0xF14>;
+
+//===-----------------------------
+// Machine Trap Setup
+//===-----------------------------
+def : SysReg<"mstatus", 0x300>;
+def : SysReg<"misa", 0x301>;
+def : SysReg<"medeleg", 0x302>;
+def : SysReg<"mideleg", 0x303>;
+def : SysReg<"mie", 0x304>;
+def : SysReg<"mtvec", 0x305>;
+def : SysReg<"mcounteren", 0x306>;
+
+//===-----------------------------
+// Machine Trap Handling
+//===-----------------------------
+def : SysReg<"mscratch", 0x340>;
+def : SysReg<"mepc", 0x341>;
+def : SysReg<"mcause", 0x342>;
+def : SysReg<"mtval", 0x343>;
+def : SysReg<"mip", 0x344>;
+
+//===----------------------------------
+// Machine Protection and Translation
+//===----------------------------------
+def : SysReg<"pmpcfg0", 0x3A0>;
+def : SysReg<"pmpcfg2", 0x3A2>;
+let isRV32Only = 1 in {
+def : SysReg<"pmpcfg1", 0x3A1>;
+def : SysReg<"pmpcfg3", 0x3A3>;
+}
+
+def : SysReg<"pmpaddr0", 0x3B0>;
+def : SysReg<"pmpaddr1", 0x3B1>;
+def : SysReg<"pmpaddr2", 0x3B2>;
+def : SysReg<"pmpaddr3", 0x3B3>;
+def : SysReg<"pmpaddr4", 0x3B4>;
+def : SysReg<"pmpaddr5", 0x3B5>;
+def : SysReg<"pmpaddr6", 0x3B6>;
+def : SysReg<"pmpaddr7", 0x3B7>;
+def : SysReg<"pmpaddr8", 0x3B8>;
+def : SysReg<"pmpaddr9", 0x3B9>;
+def : SysReg<"pmpaddr10", 0x3BA>;
+def : SysReg<"pmpaddr11", 0x3BB>;
+def : SysReg<"pmpaddr12", 0x3BC>;
+def : SysReg<"pmpaddr13", 0x3BD>;
+def : SysReg<"pmpaddr14", 0x3BE>;
+def : SysReg<"pmpaddr15", 0x3BF>;
+
+
+//===--------------------------
+// Machine Counter and Timers
+//===--------------------------
+def : SysReg<"mcycle", 0xB00>;
+def : SysReg<"minstret", 0xB02>;
+
+def : SysReg<"mhpmcounter3", 0xB03>;
+def : SysReg<"mhpmcounter4", 0xB04>;
+def : SysReg<"mhpmcounter5", 0xB05>;
+def : SysReg<"mhpmcounter6", 0xB06>;
+def : SysReg<"mhpmcounter7", 0xB07>;
+def : SysReg<"mhpmcounter8", 0xB08>;
+def : SysReg<"mhpmcounter9", 0xB09>;
+def : SysReg<"mhpmcounter10", 0xB0A>;
+def : SysReg<"mhpmcounter11", 0xB0B>;
+def : SysReg<"mhpmcounter12", 0xB0C>;
+def : SysReg<"mhpmcounter13", 0xB0D>;
+def : SysReg<"mhpmcounter14", 0xB0E>;
+def : SysReg<"mhpmcounter15", 0xB0F>;
+def : SysReg<"mhpmcounter16", 0xB10>;
+def : SysReg<"mhpmcounter17", 0xB11>;
+def : SysReg<"mhpmcounter18", 0xB12>;
+def : SysReg<"mhpmcounter19", 0xB13>;
+def : SysReg<"mhpmcounter20", 0xB14>;
+def : SysReg<"mhpmcounter21", 0xB15>;
+def : SysReg<"mhpmcounter22", 0xB16>;
+def : SysReg<"mhpmcounter23", 0xB17>;
+def : SysReg<"mhpmcounter24", 0xB18>;
+def : SysReg<"mhpmcounter25", 0xB19>;
+def : SysReg<"mhpmcounter26", 0xB1A>;
+def : SysReg<"mhpmcounter27", 0xB1B>;
+def : SysReg<"mhpmcounter28", 0xB1C>;
+def : SysReg<"mhpmcounter29", 0xB1D>;
+def : SysReg<"mhpmcounter30", 0xB1E>;
+def : SysReg<"mhpmcounter31", 0xB1F>;
+
+let isRV32Only = 1 in {
+def: SysReg<"mcycleh", 0xB80>;
+def: SysReg<"minstreth", 0xB82>;
+
+def: SysReg<"mhpmcounter3h", 0xB83>;
+def: SysReg<"mhpmcounter4h", 0xB84>;
+def: SysReg<"mhpmcounter5h", 0xB85>;
+def: SysReg<"mhpmcounter6h", 0xB86>;
+def: SysReg<"mhpmcounter7h", 0xB87>;
+def: SysReg<"mhpmcounter8h", 0xB88>;
+def: SysReg<"mhpmcounter9h", 0xB89>;
+def: SysReg<"mhpmcounter10h", 0xB8A>;
+def: SysReg<"mhpmcounter11h", 0xB8B>;
+def: SysReg<"mhpmcounter12h", 0xB8C>;
+def: SysReg<"mhpmcounter13h", 0xB8D>;
+def: SysReg<"mhpmcounter14h", 0xB8E>;
+def: SysReg<"mhpmcounter15h", 0xB8F>;
+def: SysReg<"mhpmcounter16h", 0xB90>;
+def: SysReg<"mhpmcounter17h", 0xB91>;
+def: SysReg<"mhpmcounter18h", 0xB92>;
+def: SysReg<"mhpmcounter19h", 0xB93>;
+def: SysReg<"mhpmcounter20h", 0xB94>;
+def: SysReg<"mhpmcounter21h", 0xB95>;
+def: SysReg<"mhpmcounter22h", 0xB96>;
+def: SysReg<"mhpmcounter23h", 0xB97>;
+def: SysReg<"mhpmcounter24h", 0xB98>;
+def: SysReg<"mhpmcounter25h", 0xB99>;
+def: SysReg<"mhpmcounter26h", 0xB9A>;
+def: SysReg<"mhpmcounter27h", 0xB9B>;
+def: SysReg<"mhpmcounter28h", 0xB9C>;
+def: SysReg<"mhpmcounter29h", 0xB9D>;
+def: SysReg<"mhpmcounter30h", 0xB9E>;
+def: SysReg<"mhpmcounter31h", 0xB9F>;
+}
+
+//===--------------------------
+// Machine Counter Setup
+//===--------------------------
+def : SysReg<"mhpmevent3", 0x323>;
+def : SysReg<"mhpmevent4", 0x324>;
+def : SysReg<"mhpmevent5", 0x325>;
+def : SysReg<"mhpmevent6", 0x326>;
+def : SysReg<"mhpmevent7", 0x327>;
+def : SysReg<"mhpmevent8", 0x328>;
+def : SysReg<"mhpmevent9", 0x329>;
+def : SysReg<"mhpmevent10", 0x32A>;
+def : SysReg<"mhpmevent11", 0x32B>;
+def : SysReg<"mhpmevent12", 0x32C>;
+def : SysReg<"mhpmevent13", 0x32D>;
+def : SysReg<"mhpmevent14", 0x32E>;
+def : SysReg<"mhpmevent15", 0x32F>;
+def : SysReg<"mhpmevent16", 0x330>;
+def : SysReg<"mhpmevent17", 0x331>;
+def : SysReg<"mhpmevent18", 0x332>;
+def : SysReg<"mhpmevent19", 0x333>;
+def : SysReg<"mhpmevent20", 0x334>;
+def : SysReg<"mhpmevent21", 0x335>;
+def : SysReg<"mhpmevent22", 0x336>;
+def : SysReg<"mhpmevent23", 0x337>;
+def : SysReg<"mhpmevent24", 0x338>;
+def : SysReg<"mhpmevent25", 0x339>;
+def : SysReg<"mhpmevent26", 0x33A>;
+def : SysReg<"mhpmevent27", 0x33B>;
+def : SysReg<"mhpmevent28", 0x33C>;
+def : SysReg<"mhpmevent29", 0x33D>;
+def : SysReg<"mhpmevent30", 0x33E>;
+def : SysReg<"mhpmevent31", 0x33F>;
+
+//===-----------------------------------------------
+// Debug/ Trace Registers (shared with Debug Mode)
+//===-----------------------------------------------
+def : SysReg<"tselect", 0x7A0>;
+def : SysReg<"tdata1", 0x7A1>;
+def : SysReg<"tdata2", 0x7A2>;
+def : SysReg<"tdata3", 0x7A3>;
+
+//===-----------------------------------------------
+// Debug Mode Registers
+//===-----------------------------------------------
+def : SysReg<"dcsr", 0x7B0>;
+def : SysReg<"dpc", 0x7B1>;
+def : SysReg<"dscratch", 0x7B2>;
diff --git a/llvm/lib/Target/RISCV/Utils/CMakeLists.txt b/llvm/lib/Target/RISCV/Utils/CMakeLists.txt
@@ -0,0 +1,3 @@
+add_llvm_library(LLVMRISCVUtils
+  RISCVBaseInfo.cpp
+  )
diff --git a/llvm/lib/Target/RISCV/Utils/LLVMBuild.txt b/llvm/lib/Target/RISCV/Utils/LLVMBuild.txt
@@ -0,0 +1,24 @@
+;===- ./lib/Target/RISCV/Utils/LLVMBuild.txt ----------------*- Conf -*--===;
+;
+;                     The LLVM Compiler Infrastructure
+;
+; This file is distributed under the University of Illinois Open Source
+; License. See LICENSE.TXT for details.
+;
+;===------------------------------------------------------------------------===;
+;
+; This is an LLVMBuild description file for the components in this subdirectory.
+;
+; For more information on the LLVMBuild system, please see:
+;
+;   http://llvm.org/docs/LLVMBuild.html
+;
+;===------------------------------------------------------------------------===;
+
+[component_0]
+type = Library
+name = RISCVUtils
+parent = RISCV
+required_libraries = Support
+add_to_library_groups = RISCV
+
diff --git a/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp b/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp
@@ -0,0 +1,9 @@
+#include "RISCVBaseInfo.h"
+#include "llvm/ADT/ArrayRef.h"
+
+namespace llvm {
+namespace RISCVSysReg {
+#define GET_SysRegsList_IMPL
+#include "RISCVGenSystemOperands.inc"
+} // namespace RISCVSysReg
+} // namespace llvm
diff --git a/...Target/RISCV/MCTargetDesc/RISCVBaseInfo.h → llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h b/...Target/RISCV/MCTargetDesc/RISCVBaseInfo.h → llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
@@ -14,9 +14,10 @@
 #ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
 #define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
 
-#include "RISCVMCTargetDesc.h"
+#include "MCTargetDesc/RISCVMCTargetDesc.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/ADT/StringSwitch.h"
+#include "llvm/MC/SubtargetFeature.h"
 
 namespace llvm {
 
@@ -118,8 +119,39 @@ inline static bool isValidRoundingMode(unsigned Mode) {
     return true;
   }
 }
-
 } // namespace RISCVFPRndMode
+
+namespace RISCVSysReg {
+struct SysReg {
+  const char *Name;
+  unsigned Encoding;
+  // FIXME: add these additional fields when needed.
+  // Privilege Access: Read, Write, Read-Only.
+  // unsigned ReadWrite;
+  // Privilege Mode: User, System or Machine.
+  // unsigned Mode;
+  // Check field name.
+  // unsigned Extra;
+  // Register number without the privilege bits.
+  // unsigned Number;
+  FeatureBitset FeaturesRequired;
+  bool isRV32Only;
+
+  bool haveRequiredFeatures(FeatureBitset ActiveFeatures) const {
+    // Not in 32-bit mode.
+    if (isRV32Only && ActiveFeatures[RISCV::Feature64Bit])
+      return false;
+    // No required feature associated with the system register.
+    if (FeaturesRequired.none())
+      return true;
+    return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
+  }
+};
+
+#define GET_SysRegsList_DECL
+#include "RISCVGenSystemOperands.inc"
+} // end namespace RISCVSysReg
+
 } // namespace llvm
 
 #endif
diff --git a/llvm/test/MC/RISCV/csr-aliases.s b/llvm/test/MC/RISCV/csr-aliases.s
@@ -37,79 +37,79 @@
 # RUN:     | FileCheck -check-prefix=CHECK-EXT-F-OFF %s
 
 
-# CHECK-INST: csrrs t0, 3, zero
+# CHECK-INST: csrrs t0, fcsr, zero
 # CHECK-ALIAS: frcsr t0
 # CHECK-EXT-F:  frcsr t0
 # CHECK-EXT-F-OFF: csrr t0, 3
 csrrs t0, 3, zero
 
-# CHECK-INST: csrrw t1, 3, t2
+# CHECK-INST: csrrw t1, fcsr, t2
 # CHECK-ALIAS: fscsr t1, t2
 # CHECK-EXT-F-ON: fscsr t1, t2
 # CHECK-EXT-F-OFF: csrrw t1, 3, t2
 csrrw t1, 3, t2
 
-# CHECK-INST: csrrw zero, 3, t2
+# CHECK-INST: csrrw zero, fcsr, t2
 # CHECK-ALIAS: fscsr t2
 # CHECK-EXT-F-ON: fscsr t2
 # CHECK-EXT-F-OFF: csrw 3, t2
 csrrw zero, 3, t2
 
-# CHECK-INST: csrrw zero, 3, t2
+# CHECK-INST: csrrw zero, fcsr, t2
 # CHECK-ALIAS: fscsr t2
 # CHECK-EXT-F-ON: fscsr t2
 # CHECK-EXT-F-OFF: csrw 3, t2
 csrrw zero, 3, t2
 
-# CHECK-INST: csrrw t0, 2, zero
+# CHECK-INST: csrrw t0, frm, zero
 # CHECK-ALIAS: fsrm  t0, zero
 # CHECK-EXT-F-ON: fsrm t0, zero
 # CHECK-EXT-F-OFF: csrrw t0, 2, zero
 csrrw t0, 2, zero
 
-# CHECK-INST: csrrw t0, 2, t1
+# CHECK-INST: csrrw t0, frm, t1
 # CHECK-ALIAS: fsrm t0, t1
 # CHECK-EXT-F-ON: fsrm t0, t1
 # CHECK-EXT-F-OFF: csrrw t0, 2, t1
 csrrw t0, 2, t1
 
-# CHECK-INST: csrrwi t0, 2, 31
+# CHECK-INST: csrrwi t0, frm, 31
 # CHECK-ALIAS: fsrmi t0, 31
 # CHECK-EXT-F-ON: fsrmi t0, 31
 # CHECK-EXT-F-OFF: csrrwi t0, 2, 31
 csrrwi t0, 2, 31
 
-# CHECK-INST: csrrwi zero, 2, 31
+# CHECK-INST: csrrwi zero, frm, 31
 # CHECK-ALIAS: fsrmi 31
 # CHECK-EXT-F-ON: fsrmi 31
 # CHECK-EXT-F-OFF:  csrwi 2, 31
 csrrwi zero, 2, 31
 
-# CHECK-INST: csrrs t0, 1, zero
+# CHECK-INST: csrrs t0, fflags, zero
 # CHECK-ALIAS: frflags t0
 # CHECK-EXT-F-ON: frflags t0
 # CHECK-EXT-F-OFF: csrr t0, 1
 csrrs t0, 1, zero
 
-# CHECK-INST: csrrw t0, 1, t2
+# CHECK-INST: csrrw t0, fflags, t2
 # CHECK-ALIAS: fsflags t0, t2
 # CHECK-EXT-F-ON: fsflags t0, t2
 # CHECK-EXT-F-OFF: csrrw t0, 1, t2
 csrrw t0, 1, t2
 
-# CHECK-INST: csrrw zero, 1, t2
+# CHECK-INST: csrrw zero, fflags, t2
 # CHECK-ALIAS: fsflags t2
 # CHECK-EXT-F-ON: fsflags t2
 # CHECK-EXT-F-OFF: csrw 1, t2
 csrrw zero, 1, t2
 
-# CHECK-INST: csrrwi t0, 1, 31
+# CHECK-INST: csrrwi t0, fflags, 31
 # CHECK-ALIAS: fsflagsi t0, 31
 # CHECK-EXT-F: fsflagsi t0, 31
 # CHECK-EXT-F-OFF: csrrwi t0, 1, 31
 csrrwi t0, 1, 31
 
-# CHECK-INST: csrrwi zero, 1, 31
+# CHECK-INST: csrrwi zero, fflags, 31
 # CHECK-ALIAS: fsflagsi 31
 # CHECK-EXT-F: fsflagsi 31
 # CHECK-EXT-F-OFF: csrwi 1, 31

diff --git a/llvm/test/MC/RISCV/function-call.s b/llvm/test/MC/RISCV/function-call.s
@@ -37,3 +37,9 @@ call ra
 # INSTR: auipc ra, 0
 # INSTR: jalr  ra
 # FIXUP: fixup A - offset: 0, value: ra, kind: fixup_riscv_call
+
+call mstatus
+# RELOC: R_RISCV_CALL mstatus 0x0
+# INSTR: auipc ra, 0
+# INSTR: jalr  ra
+# FIXUP: fixup A - offset: 0, value: mstatus, kind: fixup_riscv_call
diff --git a/llvm/test/MC/RISCV/machine-csr-names-invalid.s b/llvm/test/MC/RISCV/machine-csr-names-invalid.s
@@ -0,0 +1,40 @@
+# RUN: not llvm-mc -triple riscv64 < %s 2>&1 \
+# RUN:  | FileCheck -check-prefixes=CHECK-NEED-RV32 %s
+
+# These machine mode CSR register names are RV32 only.
+
+csrrs t1, pmpcfg1, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, pmpcfg3, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+
+csrrs t1, mcycleh, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, minstreth, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+
+csrrs t1, mhpmcounter3h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmcounter4h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmcounter5h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmcounter6h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmcounter7h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmcounter8h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmcounter9h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmcounter10h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmcounter11h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmcounter12h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmcounter13h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmcounter14h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmcounter15h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmcounter16h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmcounter17h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmcounter18h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmcounter19h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmcounter20h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmcounter21h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmcounter22h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmcounter23h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmcounter24h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmcounter25h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmcounter26h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmcounter27h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmcounter28h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmcounter29h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmcounter30h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mhpmcounter31h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
diff --git a/llvm/test/MC/RISCV/machine-csr-names.s b/llvm/test/MC/RISCV/machine-csr-names.s
diff --git a/llvm/test/MC/RISCV/rv32-machine-csr-names.s b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
diff --git a/llvm/test/MC/RISCV/rv32-user-csr-names.s b/llvm/test/MC/RISCV/rv32-user-csr-names.s
diff --git a/llvm/test/MC/RISCV/rv32i-aliases-valid.s b/llvm/test/MC/RISCV/rv32i-aliases-valid.s
@@ -69,12 +69,12 @@ li x12, 0x80000000
 # CHECK-EXPAND: addi a2, zero, -1
 li x12, 0xFFFFFFFF
 
-# CHECK-INST: csrrs t4, 3202, zero
+# CHECK-INST: csrrs t4, instreth, zero
 # CHECK-ALIAS: rdinstreth t4
 rdinstreth x29
-# CHECK-INST: csrrs s11, 3200, zero
+# CHECK-INST: csrrs s11, cycleh, zero
 # CHECK-ALIAS: rdcycleh s11
 rdcycleh x27
-# CHECK-INST: csrrs t3, 3201, zero
+# CHECK-INST: csrrs t3, timeh, zero
 # CHECK-ALIAS: rdtimeh t3
 rdtimeh x28
diff --git a/llvm/test/MC/RISCV/rv32i-invalid.s b/llvm/test/MC/RISCV/rv32i-invalid.s
@@ -82,6 +82,16 @@ csrrsi a0, %pcrel_hi(c), a0 # CHECK: :[[@LINE]]:12: error: immediate must be an
 csrrwi a0, %pcrel_lo(4), 0 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [0, 4095]
 csrrsi a0, %pcrel_lo(d), a0 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [0, 4095]
 
+## named csr in place of uimm12
+csrrw a0, foos, a0 # CHECK: :[[@LINE]]:11: error: operand must be a valid system register name or an integer in the range [0, 4095]
+csrrs a0, mstatusx, a0 # CHECK: :[[@LINE]]:11: error: operand must be a valid system register name or an integer in the range [0, 4095]
+csrrs a0, xmstatus, a0 # CHECK: :[[@LINE]]:11: error: operand must be a valid system register name or an integer in the range [0, 4095]
+csrrc a0, m12status, a0 # CHECK: :[[@LINE]]:11: error: operand must be a valid system register name or an integer in the range [0, 4095]
+csrrwi a0, mstatus12, 0 # CHECK: :[[@LINE]]:12: error: operand must be a valid system register name or an integer in the range [0, 4095]
+csrrsi a0, mhpm12counter, a0 # CHECK: :[[@LINE]]:12: error: operand must be a valid system register name or an integer in the range [0, 4095]
+csrrwi a0, mhpmcounter32, 0 # CHECK: :[[@LINE]]:12: error: operand must be a valid system register name or an integer in the range [0, 4095]
+csrrsi a0, A, a0 # CHECK: :[[@LINE]]:12: error: operand must be a valid system register name or an integer in the range [0, 4095]
+
 ## simm13_lsb0
 beq t0, t1, %lo(1) # CHECK: :[[@LINE]]:13: error: immediate must be a multiple of 2 bytes in the range [-4096, 4094]
 bne t0, t1, %lo(a) # CHECK: :[[@LINE]]:13: error: immediate must be a multiple of 2 bytes in the range [-4096, 4094]

diff --git a/llvm/test/MC/RISCV/rv32i-valid.s b/llvm/test/MC/RISCV/rv32i-valid.s
@@ -252,21 +252,21 @@ ebreak
 # CHECK-ASM-AND-OBJ: csrrw t0, 4095, t1
 # CHECK-ASM: encoding: [0xf3,0x12,0xf3,0xff]
 csrrw t0, 0xfff, t1
-# CHECK-ASM-AND-OBJ: csrrs s0, 3072, zero
+# CHECK-ASM-AND-OBJ: csrrs s0, cycle, zero
 # CHECK-ASM: encoding: [0x73,0x24,0x00,0xc0]
 csrrs s0, 0xc00, x0
 # CHECK-ASM-AND-OBJ: csrrs s3, 1, s5
 # CHECK-ASM: encoding: [0xf3,0xa9,0x1a,0x00]
 csrrs s3, 0x001, s5
-# CHECK-ASM-AND-OBJ: csrrc sp, 0, ra
+# CHECK-ASM-AND-OBJ: csrrc sp, ustatus, ra
 # CHECK-ASM: encoding: [0x73,0xb1,0x00,0x00]
 csrrc sp, 0x000, ra
-# CHECK-ASM-AND-OBJ: csrrwi a5, 0, 0
+# CHECK-ASM-AND-OBJ: csrrwi a5, ustatus, 0
 # CHECK-ASM: encoding: [0xf3,0x57,0x00,0x00]
 csrrwi a5, 0x000, 0
 # CHECK-ASM-AND-OBJ: csrrsi t2, 4095, 31
 # CHECK-ASM: encoding: [0xf3,0xe3,0xff,0xff]
 csrrsi t2, 0xfff, 31
-# CHECK-ASM-AND-OBJ: csrrci t1, 320, 5
+# CHECK-ASM-AND-OBJ: csrrci t1, sscratch, 5
 # CHECK-ASM: encoding: [0x73,0xf3,0x02,0x14]
 csrrci t1, 0x140, 5
diff --git a/llvm/test/MC/RISCV/rv64-machine-csr-names.s b/llvm/test/MC/RISCV/rv64-machine-csr-names.s
@@ -0,0 +1,246 @@
+# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
+# RUN:     | llvm-objdump -d - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS %s
+
+# These machine mode CSR register names are RV32 only, but RV64
+# can encode and disassemble these registers if given their value.
+
+######################################
+# Machine Protection and Translation
+######################################
+
+# pmpcfg1
+# uimm12
+# CHECK-INST: csrrs t2, 929, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x3a]
+# CHECK-INST-ALIAS: csrr t2, 929
+csrrs t2, 0x3A1, zero
+
+# pmpcfg3
+# uimm12
+# CHECK-INST: csrrs t2, 931, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x30,0x3a]
+# CHECK-INST-ALIAS: csrr t2, 931
+csrrs t2, 0x3A3, zero
+
+######################################
+# Machine Counter and Timers
+######################################
+# mcycleh
+# uimm12
+# CHECK-INST: csrrs t2, 2944, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x00,0xb8]
+# CHECK-INST-ALIAS: csrr t2, 2944
+csrrs t2, 0xB80, zero
+
+# minstreth
+# uimm12
+# CHECK-INST: csrrs t2, 2946, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0xb8]
+# CHECK-INST-ALIAS: csrr t2, 2946
+csrrs t2, 0xB82, zero
+
+# mhpmcounter3h
+# uimm12
+# CHECK-INST: csrrs t2, 2947, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x30,0xb8]
+# CHECK-INST-ALIAS: csrr t2, 2947
+csrrs t2, 0xB83, zero
+
+# mhpmcounter4h
+# uimm12
+# CHECK-INST: csrrs t2, 2948, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x40,0xb8]
+# CHECK-INST-ALIAS: csrr t2, 2948
+csrrs t2, 0xB84, zero
+
+# mhpmcounter5h
+# uimm12
+# CHECK-INST: csrrs t2, 2949, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x50,0xb8]
+# CHECK-INST-ALIAS: csrr t2, 2949
+csrrs t2, 0xB85, zero
+
+# mhpmcounter6h
+# uimm12
+# CHECK-INST: csrrs t2, 2950, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x60,0xb8]
+# CHECK-INST-ALIAS: csrr t2, 2950
+csrrs t2, 0xB86, zero
+
+# mhpmcounter7h
+# uimm12
+# CHECK-INST: csrrs t2, 2951, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x70,0xb8]
+# CHECK-INST-ALIAS: csrr t2, 2951
+csrrs t2, 0xB87, zero
+
+# mhpmcounter8h
+# uimm12
+# CHECK-INST: csrrs t2, 2952, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x80,0xb8]
+# CHECK-INST-ALIAS: csrr t2, 2952
+csrrs t2, 0xB88, zero
+
+# mhpmcounter9h
+# uimm12
+# CHECK-INST: csrrs t2, 2953, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x90,0xb8]
+# CHECK-INST-ALIAS: csrr t2, 2953
+csrrs t2, 0xB89, zero
+
+# mhpmcounter10h
+# uimm12
+# CHECK-INST: csrrs t2, 2954, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0xa0,0xb8]
+# CHECK-INST-ALIAS: csrr t2, 2954
+csrrs t2, 0xB8A, zero
+
+# mhpmcounter11h
+# uimm12
+# CHECK-INST: csrrs t2, 2955, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0xb0,0xb8]
+# CHECK-INST-ALIAS: csrr t2, 2955
+csrrs t2, 0xB8B, zero
+
+# mhpmcounter12h
+# uimm12
+# CHECK-INST: csrrs t2, 2956, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0xc0,0xb8]
+# CHECK-INST-ALIAS: csrr t2, 2956
+csrrs t2, 0xB8C, zero
+
+# mhpmcounter13h
+# uimm12
+# CHECK-INST: csrrs t2, 2957, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0xd0,0xb8]
+# CHECK-INST-ALIAS: csrr t2, 2957
+csrrs t2, 0xB8D, zero
+
+# mhpmcounter14h
+# uimm12
+# CHECK-INST: csrrs t2, 2958, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0xe0,0xb8]
+# CHECK-INST-ALIAS: csrr t2, 2958
+csrrs t2, 0xB8E, zero
+
+# mhpmcounter15h
+# uimm12
+# CHECK-INST: csrrs t2, 2959, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0xf0,0xb8]
+# CHECK-INST-ALIAS: csrr t2, 2959
+csrrs t2, 0xB8F, zero
+
+# mhpmcounter16h
+# uimm12
+# CHECK-INST: csrrs t2, 2960, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x00,0xb9]
+# CHECK-INST-ALIAS: csrr t2, 2960
+csrrs t2, 0xB90, zero
+
+# mhpmcounter17h
+# uimm12
+# CHECK-INST: csrrs t2, 2961, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x10,0xb9]
+# CHECK-INST-ALIAS: csrr t2, 2961
+csrrs t2, 0xB91, zero
+
+# mhpmcounter18h
+# uimm12
+# CHECK-INST: csrrs t2, 2962, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x20,0xb9]
+# CHECK-INST-ALIAS: csrr t2, 2962
+csrrs t2, 0xB92, zero
+
+# mhpmcounter19h
+# uimm12
+# CHECK-INST: csrrs t2, 2963, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x30,0xb9]
+# CHECK-INST-ALIAS: csrr t2, 2963
+csrrs t2, 0xB93, zero
+
+# mhpmcounter20h
+# uimm12
+# CHECK-INST: csrrs t2, 2964, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x40,0xb9]
+# CHECK-INST-ALIAS: csrr t2, 2964
+csrrs t2, 0xB94, zero
+
+# mhpmcounter21h
+# uimm12
+# CHECK-INST: csrrs t2, 2965, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x50,0xb9]
+# CHECK-INST-ALIAS: csrr t2, 2965
+csrrs t2, 0xB95, zero
+
+# mhpmcounter22h
+# uimm12
+# CHECK-INST: csrrs t2, 2966, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x60,0xb9]
+# CHECK-INST-ALIAS: csrr t2, 2966
+csrrs t2, 0xB96, zero
+
+# mhpmcounter23h
+# uimm12
+# CHECK-INST: csrrs t2, 2967, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x70,0xb9]
+# CHECK-INST-ALIAS: csrr t2, 2967
+csrrs t2, 0xB97, zero
+
+# mhpmcounter24h
+# uimm12
+# CHECK-INST: csrrs t2, 2968, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x80,0xb9]
+# CHECK-INST-ALIAS: csrr t2, 2968
+csrrs t2, 0xB98, zero
+
+# mhpmcounter25h
+# uimm12
+# CHECK-INST: csrrs t2, 2969, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x90,0xb9]
+# CHECK-INST-ALIAS: csrr t2, 2969
+csrrs t2, 0xB99, zero
+
+# mhpmcounter26h
+# uimm12
+# CHECK-INST: csrrs t2, 2970, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0xa0,0xb9]
+# CHECK-INST-ALIAS: csrr t2, 2970
+csrrs t2, 0xB9A, zero
+
+# mhpmcounter27h
+# uimm12
+# CHECK-INST: csrrs t2, 2971, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0xb0,0xb9]
+# CHECK-INST-ALIAS: csrr t2, 2971
+csrrs t2, 0xB9B, zero
+
+# mhpmcounter28h
+# uimm12
+# CHECK-INST: csrrs t2, 2972, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0xc0,0xb9]
+# CHECK-INST-ALIAS: csrr t2, 2972
+csrrs t2, 0xB9C, zero
+
+# mhpmcounter29h
+# uimm12
+# CHECK-INST: csrrs t2, 2973, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0xd0,0xb9]
+# CHECK-INST-ALIAS: csrr t2, 2973
+csrrs t2, 0xB9D, zero
+
+# mhpmcounter30h
+# uimm12
+# CHECK-INST: csrrs t2, 2974, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0xe0,0xb9]
+# CHECK-INST-ALIAS: csrr t2, 2974
+csrrs t2, 0xB9E, zero
+
+# mhpmcounter31h
+# uimm12
+# CHECK-INST: csrrs t2, 2975, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0xf0,0xb9]
+# CHECK-INST-ALIAS: csrr t2, 2975
+csrrs t2, 0xB9F, zero
diff --git a/llvm/test/MC/RISCV/rv64-user-csr-names.s b/llvm/test/MC/RISCV/rv64-user-csr-names.s
@@ -0,0 +1,236 @@
+# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
+# RUN:     | llvm-objdump -d - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS %s
+
+# These user mode CSR register names are RV32 only, but RV64
+# can encode and disassemble these registers if given their value.
+
+##################################
+# User Counter and Timers
+##################################
+
+# cycleh
+# uimm12
+# CHECK-INST: csrrs t2, 3200, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x00,0xc8]
+# CHECK-INST-ALIAS: csrr t2, 3200
+csrrs t2, 0xC80, zero
+
+# timeh
+# uimm12
+# CHECK-INST: csrrs t2, 3201, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x10,0xc8]
+# CHECK-INST-ALIAS: csrr t2, 3201
+csrrs t2, 0xC81, zero
+
+# instreth
+# uimm12
+# CHECK-INST: csrrs t2, 3202, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x20,0xc8]
+# CHECK-INST-ALIAS: csrr t2, 3202
+csrrs t2, 0xC82, zero
+
+# hpmcounter3h
+# uimm12
+# CHECK-INST: csrrs t2, 3203, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x30,0xc8]
+# CHECK-INST-ALIAS: csrr t2, 3203
+csrrs t2, 0xC83, zero
+
+# hpmcounter4h
+# uimm12
+# CHECK-INST: csrrs t2, 3204, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x40,0xc8]
+# CHECK-INST-ALIAS: csrr t2, 3204
+csrrs t2, 0xC84, zero
+
+# hpmcounter5h
+# uimm12
+# CHECK-INST: csrrs t2, 3205, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x50,0xc8]
+# CHECK-INST-ALIAS: csrr t2, 3205
+csrrs t2, 0xC85, zero
+
+# hpmcounter6h
+# uimm12
+# CHECK-INST: csrrs t2, 3206, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x60,0xc8]
+# CHECK-INST-ALIAS: csrr t2, 3206
+csrrs t2, 0xC86, zero
+
+# hpmcounter7h
+# uimm12
+# CHECK-INST: csrrs t2, 3207, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x70,0xc8]
+# CHECK-INST-ALIAS: csrr t2, 3207
+csrrs t2, 0xC87, zero
+
+# hpmcounter8h
+# uimm12
+# CHECK-INST: csrrs t2, 3208, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x80,0xc8]
+# CHECK-INST-ALIAS: csrr t2, 3208
+csrrs t2, 0xC88, zero
+
+# hpmcounter9h
+# uimm12
+# CHECK-INST: csrrs t2, 3209, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x90,0xc8]
+# CHECK-INST-ALIAS: csrr t2, 3209
+csrrs t2, 0xC89, zero
+
+# hpmcounter10h
+# uimm12
+# CHECK-INST: csrrs t2, 3210, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0xa0,0xc8]
+# CHECK-INST-ALIAS: csrr t2, 3210
+csrrs t2, 0xC8A, zero
+
+# hpmcounter11h
+# uimm12
+# CHECK-INST: csrrs t2, 3211, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0xb0,0xc8]
+# CHECK-INST-ALIAS: csrr t2, 3211
+csrrs t2, 0xC8B, zero
+
+# hpmcounter12h
+# uimm12
+# CHECK-INST: csrrs t2, 3212, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0xc0,0xc8]
+# CHECK-INST-ALIAS: csrr t2, 3212
+csrrs t2, 0xC8C, zero
+
+# hpmcounter13h
+# uimm12
+# CHECK-INST: csrrs t2, 3213, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0xd0,0xc8]
+# CHECK-INST-ALIAS: csrr t2, 3213
+csrrs t2, 0xC8D, zero
+
+# hpmcounter14h
+# uimm12
+# CHECK-INST: csrrs t2, 3214, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0xe0,0xc8]
+# CHECK-INST-ALIAS: csrr t2, 3214
+csrrs t2, 0xC8E, zero
+
+# hpmcounter15h
+# uimm12
+# CHECK-INST: csrrs t2, 3215, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0xf0,0xc8]
+# CHECK-INST-ALIAS: csrr t2, 3215
+csrrs t2, 0xC8F, zero
+
+# hpmcounter16h
+# uimm12
+# CHECK-INST: csrrs t2, 3216, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x00,0xc9]
+# CHECK-INST-ALIAS: csrr t2, 3216
+csrrs t2, 0xC90, zero
+
+# hpmcounter17h
+# uimm12
+# CHECK-INST: csrrs t2, 3217, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x10,0xc9]
+# CHECK-INST-ALIAS: csrr t2, 3217
+csrrs t2, 0xC91, zero
+
+# hpmcounter18h
+# uimm12
+# CHECK-INST: csrrs t2, 3218, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x20,0xc9]
+# CHECK-INST-ALIAS: csrr t2, 3218
+csrrs t2, 0xC92, zero
+
+# hpmcounter19h
+# uimm12
+# CHECK-INST: csrrs t2, 3219, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x30,0xc9]
+# CHECK-INST-ALIAS: csrr t2, 3219
+csrrs t2, 0xC93, zero
+
+# hpmcounter20h
+# uimm12
+# CHECK-INST: csrrs t2, 3220, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x40,0xc9]
+# CHECK-INST-ALIAS: csrr t2, 3220
+csrrs t2, 0xC94, zero
+
+# hpmcounter21h
+# uimm12
+# CHECK-INST: csrrs t2, 3221, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x50,0xc9]
+# CHECK-INST-ALIAS: csrr t2, 3221
+csrrs t2, 0xC95, zero
+
+# hpmcounter22h
+# uimm12
+# CHECK-INST: csrrs t2, 3222, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x60,0xc9]
+# CHECK-INST-ALIAS: csrr t2, 3222
+csrrs t2, 0xC96, zero
+
+# hpmcounter23h
+# uimm12
+# CHECK-INST: csrrs t2, 3223, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x70,0xc9]
+# CHECK-INST-ALIAS: csrr t2, 3223
+csrrs t2, 0xC97, zero
+
+# hpmcounter24h
+# uimm12
+# CHECK-INST: csrrs t2, 3224, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x80,0xc9]
+# CHECK-INST-ALIAS: csrr t2, 3224
+csrrs t2, 0xC98, zero
+
+# hpmcounter25h
+# uimm12
+# CHECK-INST: csrrs t2, 3225, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x90,0xc9]
+# CHECK-INST-ALIAS: csrr t2, 3225
+csrrs t2, 0xC99, zero
+
+# hpmcounter26h
+# uimm12
+# CHECK-INST: csrrs t2, 3226, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0xa0,0xc9]
+# CHECK-INST-ALIAS: csrr t2, 3226
+csrrs t2, 0xC9A, zero
+
+# hpmcounter27h
+# uimm12
+# CHECK-INST: csrrs t2, 3227, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0xb0,0xc9]
+# CHECK-INST-ALIAS: csrr t2, 3227
+csrrs t2, 0xC9B, zero
+
+# hpmcounter28h
+# uimm12
+# CHECK-INST: csrrs t2, 3228, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0xc0,0xc9]
+# CHECK-INST-ALIAS: csrr t2, 3228
+csrrs t2, 0xC9C, zero
+
+# hpmcounter29h
+# uimm12
+# CHECK-INST: csrrs t2, 3229, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0xd0,0xc9]
+# CHECK-INST-ALIAS: csrr t2, 3229
+csrrs t2, 0xC9D, zero
+
+# hpmcounter30h
+# uimm12
+# CHECK-INST: csrrs t2, 3230, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0xe0,0xc9]
+# CHECK-INST-ALIAS: csrr t2, 3230
+csrrs t2, 0xC9E, zero
+
+# hpmcounter31h
+# uimm12
+# CHECK-INST: csrrs t2, 3231, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0xf0,0xc9]
+# CHECK-INST-ALIAS: csrr t2, 3231
+csrrs t2, 0xC9F, zero
diff --git a/llvm/test/MC/RISCV/rvf-aliases-valid.s b/llvm/test/MC/RISCV/rvf-aliases-valid.s
@@ -45,45 +45,45 @@ fge.s x7, f8, f9
 
 # The following instructions actually alias instructions from the base ISA.
 # However, it only makes sense to support them when the F extension is enabled.
-# CHECK-INST: csrrs t0, 3, zero
+# CHECK-INST: csrrs t0, fcsr, zero
 # CHECK-ALIAS: frcsr t0
 frcsr x5
-# CHECK-INST: csrrw t1, 3, t2
+# CHECK-INST: csrrw t1, fcsr, t2
 # CHECK-ALIAS: fscsr t1, t2
 fscsr x6, x7
-# CHECK-INST: csrrw  zero, 3, t3
+# CHECK-INST: csrrw  zero, fcsr, t3
 # CHECK-ALIAS: fscsr t3
 fscsr x28
 
-# CHECK-INST: csrrs t4, 2, zero
+# CHECK-INST: csrrs t4, frm, zero
 # CHECK-ALIAS: frrm t4
 frrm x29
-# CHECK-INST: csrrw  t5, 2, t4
+# CHECK-INST: csrrw  t5, frm, t4
 # CHECK-ALIAS: fsrm t5, t4
 fsrm x30, x29
-# CHECK-INST: csrrw  zero, 2, t6
+# CHECK-INST: csrrw  zero, frm, t6
 # CHECK-ALIAS: fsrm t6
 fsrm x31
-# CHECK-INST: csrrwi a0, 2, 31
+# CHECK-INST: csrrwi a0, frm, 31
 # CHECK-ALIAS: fsrmi a0, 31
 fsrmi x10, 0x1f
-# CHECK-INST: csrrwi  zero, 2, 30
+# CHECK-INST: csrrwi  zero, frm, 30
 # CHECK-ALIAS: fsrmi 30
 fsrmi 0x1e
 
-# CHECK-INST: csrrs a1, 1, zero
+# CHECK-INST: csrrs a1, fflags, zero
 # CHECK-ALIAS: frflags a1
 frflags x11
-# CHECK-INST: csrrw a2, 1, a1
+# CHECK-INST: csrrw a2, fflags, a1
 # CHECK-ALIAS: fsflags a2, a1
 fsflags x12, x11
-# CHECK-INST: csrrw zero, 1, a3
+# CHECK-INST: csrrw zero, fflags, a3
 # CHECK-ALIAS: fsflags a3
 fsflags x13
-# CHECK-INST: csrrwi a4, 1, 29
+# CHECK-INST: csrrwi a4, fflags, 29
 # CHECK-ALIAS: fsflagsi a4, 29
 fsflagsi x14, 0x1d
-# CHECK-INST: csrrwi zero, 1, 28
+# CHECK-INST: csrrwi zero, fflags, 28
 # CHECK-ALIAS: fsflagsi 28
 fsflagsi 0x1c
 

diff --git a/llvm/test/MC/RISCV/rvf-user-csr-names.s b/llvm/test/MC/RISCV/rvf-user-csr-names.s
@@ -0,0 +1,71 @@
+# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -mattr=+f -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \
+# RUN:     | llvm-objdump -d -mattr=+f - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \
+# RUN:     | llvm-objdump -d - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS-NO-F %s
+#
+# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -mattr=+f -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \
+# RUN:     | llvm-objdump -d -mattr=+f - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \
+# RUN:     | llvm-objdump -d - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS-NO-F %s
+
+##################################
+# User Floating Pont CSRs
+##################################
+
+# fflags
+# name
+# CHECK-INST: csrrs t1, fflags, zero
+# CHECK-ENC:  encoding: [0x73,0x23,0x10,0x00]
+# CHECK-INST-ALIAS: frflags t1
+# CHECK-INST-ALIAS-NO-F: csrr t1, 1
+# uimm12
+# CHECK-INST: csrrs t2, fflags, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x10,0x00]
+# CHECK-INST-ALIAS: frflags t2
+# CHECK-INST-ALIAS-NO-F: csrr t2, 1
+# name
+csrrs t1, fflags, zero
+# uimm12
+csrrs t2, 0x001, zero
+
+# frm
+# name
+# CHECK-INST: csrrs t1, frm, zero
+# CHECK-ENC:  encoding: [0x73,0x23,0x20,0x00]
+# CHECK-INST-ALIAS: frrm t1
+# CHECK-INST-ALIAS-NO-F: csrr t1, 2
+# uimm12
+# CHECK-INST: csrrs t2, frm, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x20,0x00]
+# CHECK-INST-ALIAS: frrm t2
+# CHECK-INST-ALIAS-NO-F: csrr t2, 2
+# name
+csrrs t1, frm, zero
+# uimm12
+csrrs t2, 0x002, zero
+
+# fcsr
+# name
+# CHECK-INST: csrrs t1, fcsr, zero
+# CHECK-ENC:  encoding: [0x73,0x23,0x30,0x00]
+# CHECK-INST-ALIAS: frcsr t1
+# CHECK-INST-ALIAS-NO-F: csrr t1, 3
+# uimm12
+# CHECK-INST: csrrs t2, fcsr, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x30,0x00]
+# CHECK-INST-ALIAS: frcsr t2
+# CHECK-INST-ALIAS-NO-F: csrr t2, 3
+# name
+csrrs t1, fcsr, zero
+# uimm12
+csrrs t2, 0x003, zero
+
+
diff --git a/llvm/test/MC/RISCV/rvi-aliases-valid.s b/llvm/test/MC/RISCV/rvi-aliases-valid.s
@@ -148,21 +148,21 @@ ret
 # CHECK-S-OBJ: fence
 fence
 
-# CHECK-S-OBJ-NOALIAS: csrrs s10, 3074, zero
+# CHECK-S-OBJ-NOALIAS: csrrs s10, instret, zero
 # CHECK-S-OBJ: rdinstret s10
 rdinstret x26
-# CHECK-S-OBJ-NOALIAS: csrrs s8, 3072, zero
+# CHECK-S-OBJ-NOALIAS: csrrs s8, cycle, zero
 # CHECK-S-OBJ: rdcycle s8
 rdcycle x24
-# CHECK-S-OBJ-NOALIAS: csrrs s9, 3073, zero
+# CHECK-S-OBJ-NOALIAS: csrrs s9, time, zero
 # CHECK-S-OBJ: rdtime s9
 rdtime x25
 
 # CHECK-S-OBJ-NOALIAS: csrrs  s0, 336, zero
 # CHECK-S-OBJ: csrr s0, 336
 csrr x8, 0x150
-# CHECK-S-OBJ-NOALIAS: csrrw zero, 320, s1
-# CHECK-S-OBJ: csrw 320, s1
+# CHECK-S-OBJ-NOALIAS: csrrw zero, sscratch, s1
+# CHECK-S-OBJ: csrw sscratch, s1
 csrw 0x140, x9
 # CHECK-S-OBJ-NOALIAS: csrrs zero, 4095, s6
 # CHECK-S-OBJ: csrs 4095, s6
@@ -177,8 +177,8 @@ csrwi 0x150, 0xf
 # CHECK-S-OBJ-NOALIAS: csrrsi zero, 4095, 16
 # CHECK-S-OBJ: csrsi 4095, 16
 csrsi 0xfff, 0x10
-# CHECK-S-OBJ-NOALIAS: csrrci zero, 320, 17
-# CHECK-S-OBJ: csrci 320, 17
+# CHECK-S-OBJ-NOALIAS: csrrci zero, sscratch, 17
+# CHECK-S-OBJ: csrci sscratch, 17
 csrci 0x140, 0x11
 
 # CHECK-S-OBJ-NOALIAS: sfence.vma zero, zero

diff --git a/llvm/test/MC/RISCV/supervisor-csr-names.s b/llvm/test/MC/RISCV/supervisor-csr-names.s
@@ -0,0 +1,193 @@
+# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
+# RUN:     | llvm-objdump -d - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS %s
+#
+# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
+# RUN:     | llvm-objdump -d - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS %s
+
+##################################
+# Supervisor Trap Setup
+##################################
+
+# sstatus
+# name
+# CHECK-INST: csrrs t1, sstatus, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x00,0x10]
+# CHECK-INST-ALIAS: csrr t1, sstatus
+# uimm12
+# CHECK-INST: csrrs t2, sstatus, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x10]
+# CHECK-INST-ALIAS: csrr t2, sstatus
+# name
+csrrs t1, sstatus, zero
+# uimm12
+csrrs t2, 0x100, zero
+
+# sedeleg
+# name
+# CHECK-INST: csrrs t1, sedeleg, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x10]
+# CHECK-INST-ALIAS: csrr t1, sedeleg
+# uimm12
+# CHECK-INST: csrrs t2, sedeleg, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x10]
+# CHECK-INST-ALIAS: csrr t2, sedeleg
+# name
+csrrs t1, sedeleg, zero
+# uimm12
+csrrs t2, 0x102, zero
+
+# sideleg
+# name
+# CHECK-INST: csrrs t1, sideleg, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x30,0x10]
+# CHECK-INST-ALIAS: csrr t1, sideleg
+# uimm12
+# CHECK-INST: csrrs t2, sideleg, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x30,0x10]
+# CHECK-INST-ALIAS: csrr t2, sideleg
+# name
+csrrs t1, sideleg, zero
+# uimm12
+csrrs t2, 0x103, zero
+
+# sie
+# name
+# CHECK-INST: csrrs t1, sie, zero
+# CHECK-ENC: [0x73,0x23,0x40,0x10]
+# CHECK-INST-ALIAS: csrr t1, sie
+# uimm12
+# CHECK-INST: csrrs t2, sie, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x10]
+# CHECK-INST-ALIAS: csrr t2, sie
+# name
+csrrs t1, sie, zero
+# uimm12
+csrrs t2, 0x104, zero
+
+# stvec
+# name
+# CHECK-INST: csrrs t1, stvec, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x50,0x10]
+# CHECK-INST-ALIAS: csrr t1, stvec
+# uimm12
+# CHECK-INST: csrrs t2, stvec, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x50,0x10]
+# CHECK-INST-ALIAS: csrr t2, stvec
+# name
+csrrs t1, stvec, zero
+# uimm12
+csrrs t2, 0x105, zero
+
+# scounteren
+# name
+# CHECK-INST: csrrs t1, scounteren, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x60,0x10]
+# CHECK-INST-ALIAS: csrr t1, scounteren
+# uimm12
+# CHECK-INST: csrrs t2, scounteren, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x60,0x10]
+# CHECK-INST-ALIAS: csrr t2, scounteren
+# name
+csrrs t1, scounteren, zero
+# uimm12
+csrrs t2, 0x106, zero
+
+##################################
+# Supervisor Trap Handling
+##################################
+
+# sscratch
+# name
+# CHECK-INST: csrrs t1, sscratch, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x00,0x14]
+# CHECK-INST-ALIAS: csrr t1, sscratch
+# uimm12
+# CHECK-INST: csrrs t2, sscratch, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x14]
+# CHECK-INST-ALIAS: csrr t2, sscratch
+# name
+csrrs t1, sscratch, zero
+# uimm12
+csrrs t2, 0x140, zero
+
+# sepc
+# name
+# CHECK-INST: csrrs t1, sepc, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x10,0x14]
+# CHECK-INST-ALIAS: csrr t1, sepc
+# uimm12
+# CHECK-INST: csrrs t2, sepc, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x14]
+# CHECK-INST-ALIAS: csrr t2, sepc
+# name
+csrrs t1, sepc, zero
+# uimm12
+csrrs t2, 0x141, zero
+
+# scause
+# name
+# CHECK-INST: csrrs t1, scause, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x14]
+# CHECK-INST-ALIAS: csrr t1, scause
+# uimm12
+# CHECK-INST: csrrs t2, scause, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x14]
+# CHECK-INST-ALIAS: csrr t2, scause
+# name
+csrrs t1, scause, zero
+# uimm12
+csrrs t2, 0x142, zero
+
+# stval
+# name
+# CHECK-INST: csrrs t1, stval, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x30,0x14]
+# CHECK-INST-ALIAS: csrr t1, stval
+# uimm12
+# CHECK-INST: csrrs t2, stval, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x30,0x14]
+# CHECK-INST-ALIAS: csrr t2, stval
+# aliases
+# aliases with uimm12
+# name
+csrrs t1, stval, zero
+# uimm12
+csrrs t2, 0x143, zero
+
+# sip
+# name
+# CHECK-INST: csrrs t1, sip, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x40,0x14]
+# CHECK-INST-ALIAS: csrr t1, sip
+# uimm12
+# CHECK-INST: csrrs t2, sip, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x14]
+# CHECK-INST-ALIAS: csrr t2, sip
+csrrs t1, sip, zero
+# uimm12
+csrrs t2, 0x144, zero
+
+
+#########################################
+# Supervisor Protection and Translation
+#########################################
+
+# satp
+# name
+# CHECK-INST: csrrs t1, satp, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x00,0x18]
+# CHECK-INST-ALIAS: csrr t1, satp
+# uimm12
+# CHECK-INST: csrrs t2, satp, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x18]
+# CHECK-INST-ALIAS: csrr t2, satp
+# name
+csrrs t1, satp, zero
+# uimm12
+csrrs t2, 0x180, zero
diff --git a/llvm/test/MC/RISCV/user-csr-names-invalid.s b/llvm/test/MC/RISCV/user-csr-names-invalid.s
@@ -0,0 +1,47 @@
+# RUN: not llvm-mc -triple riscv32 < %s 2>&1 \
+# RUN:  | FileCheck -check-prefix=CHECK-NEED-F %s
+# RUN: not llvm-mc -triple riscv64 < %s 2>&1 \
+# RUN:  | FileCheck -check-prefixes=CHECK-NEED-RV32,CHECK-NEED-F %s
+
+# These user mode CSR register names are RV32 only.
+
+csrrs t1, cycleh, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, timeh, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, instreth, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+
+csrrs t1, hpmcounter3h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, hpmcounter4h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, hpmcounter5h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, hpmcounter6h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, hpmcounter7h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, hpmcounter8h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, hpmcounter9h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, hpmcounter10h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, hpmcounter11h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, hpmcounter12h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, hpmcounter13h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, hpmcounter14h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, hpmcounter15h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, hpmcounter16h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, hpmcounter17h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, hpmcounter18h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, hpmcounter19h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, hpmcounter20h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, hpmcounter21h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, hpmcounter22h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, hpmcounter23h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, hpmcounter24h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, hpmcounter25h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, hpmcounter26h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, hpmcounter27h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, hpmcounter28h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, hpmcounter29h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, hpmcounter30h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, hpmcounter31h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+
+# These user mode CSR register names require F extension.
+
+csrrs t1, fflags, zero # CHECK-NEED-F: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, frm, zero # CHECK-NEED-F: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, fcsr, zero # CHECK-NEED-F: :[[@LINE]]:11: error: system register use requires an option to be enabled
+
diff --git a/llvm/test/MC/RISCV/user-csr-names.s b/llvm/test/MC/RISCV/user-csr-names.s