35 changes: 27 additions & 8 deletions clang/lib/Serialization/ASTReader.cpp
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Expand Up @@ -8963,15 +8963,34 @@ void ASTReader::ReadLateParsedTemplates(
LateParsedTemplates.clear();
}

void ASTReader::AssignedLambdaNumbering(const CXXRecordDecl *Lambda) {
if (Lambda->getLambdaContextDecl()) {
// Keep track of this lambda so it can be merged with another lambda that
// is loaded later.
LambdaDeclarationsForMerging.insert(
{{Lambda->getLambdaContextDecl()->getCanonicalDecl(),
Lambda->getLambdaIndexInContext()},
const_cast<CXXRecordDecl *>(Lambda)});
void ASTReader::AssignedLambdaNumbering(CXXRecordDecl *Lambda) {
if (!Lambda->getLambdaContextDecl())
return;

auto LambdaInfo =
std::make_pair(Lambda->getLambdaContextDecl()->getCanonicalDecl(),
Lambda->getLambdaIndexInContext());

// Handle the import and then include case for lambdas.
if (auto Iter = LambdaDeclarationsForMerging.find(LambdaInfo);
Iter != LambdaDeclarationsForMerging.end() &&
Iter->second->isFromASTFile() && Lambda->getFirstDecl() == Lambda) {
CXXRecordDecl *Previous =
cast<CXXRecordDecl>(Iter->second)->getMostRecentDecl();
Lambda->setPreviousDecl(Previous);
// FIXME: It will be best to use the Previous type when we creating the
// lambda directly. But that requires us to get the lambda context decl and
// lambda index before creating the lambda, which needs a drastic change in
// the parser.
const_cast<QualType &>(Lambda->TypeForDecl->CanonicalType) =
Previous->TypeForDecl->CanonicalType;
return;
}

// Keep track of this lambda so it can be merged with another lambda that
// is loaded later.
LambdaDeclarationsForMerging.insert(
{LambdaInfo, const_cast<CXXRecordDecl *>(Lambda)});
}

void ASTReader::LoadSelector(Selector Sel) {
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3 changes: 3 additions & 0 deletions clang/lib/Serialization/ASTWriter.cpp
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Expand Up @@ -3963,6 +3963,9 @@ void ASTWriter::WriteIdentifierTable(Preprocessor &PP,
}

void ASTWriter::handleVTable(CXXRecordDecl *RD) {
if (!RD->isInNamedModule())
return;

PendingEmittingVTables.push_back(RD);
}

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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesef.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesem.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf1.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf2.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesz.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vandn.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev8.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmul.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmulh.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclz.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpopv.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vctz.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vghsh.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vgmul.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrev8.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrol.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vror.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ch.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2cl.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ms.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3c.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3me.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4k.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4r.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsll.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdf.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdm.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesef.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesem.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf1.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf2.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesz.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vandn.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev8.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmul.c
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// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmulh.c
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// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclz.c
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// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpopv.c
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// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vctz.c
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// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vghsh.c
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// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vgmul.c
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// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrev8.c
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// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrol.c
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// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vror.c
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// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2ch.c
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// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2cl.c
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// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2ms.c
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// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm3c.c
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// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm3me.c
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// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm4k.c
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// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm4r.c
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// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsll.c
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// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdf.c
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// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdm.c
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// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesef.c
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// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesem.c
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// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaeskf1.c
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// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaeskf2.c
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// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesz.c
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// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vandn.c
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// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vbrev.c
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// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vbrev8.c
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// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclmul.c
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// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclmulh.c
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// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclz.c
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// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcpopv.c
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// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vctz.c
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// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vghsh.c
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// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vgmul.c
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// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrev8.c
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// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrol.c
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// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vror.c
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// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2ch.c
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// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2cl.c
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// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2ms.c
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// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm3c.c
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// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm3me.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm4k.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm4r.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsll.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdf.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdm.c
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Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesef.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesem.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaeskf1.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaeskf2.c
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Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesz.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vandn.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vbrev.c
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Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vbrev8.c
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Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclmul.c
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Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclmulh.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclz.c
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Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcpopv.c
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Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vctz.c
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Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vghsh.c
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Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vgmul.c
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Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrev8.c
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Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrol.c
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Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vror.c
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Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsha2ch.c
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Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsha2cl.c
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Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsha2ms.c
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Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm3c.c
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Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm3me.c
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Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm4k.c
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Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm4r.c
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Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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1 change: 0 additions & 1 deletion clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsll.c
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Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,6 @@
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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4 changes: 4 additions & 0 deletions clang/test/Driver/print-multi-selection-flags.c
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Original file line number Diff line number Diff line change
Expand Up @@ -59,6 +59,10 @@
// CHECK-SVE2: --target=aarch64-unknown-none-elf
// CHECK-SVE2: -march=armv{{.*}}-a{{.*}}+simd{{.*}}+sve{{.*}}+sve2{{.*}}

// RUN: %clang -print-multi-flags-experimental --target=arm-none-eabi -mbranch-protection=standard | FileCheck --check-prefix=CHECK-BRANCH-PROTECTION %s
// RUN: %clang -print-multi-flags-experimental --target=aarch64-none-elf -mbranch-protection=standard | FileCheck --check-prefix=CHECK-BRANCH-PROTECTION %s
// CHECK-BRANCH-PROTECTION: -mbranch-protection=standard

// RUN: %clang -print-multi-flags-experimental --target=riscv32-none-elf -march=rv32g | FileCheck --check-prefix=CHECK-RV32 %s
// CHECK-RV32: --target=riscv32-unknown-none-elf
// CHECK-RV32: -mabi=ilp32d
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8 changes: 6 additions & 2 deletions clang/test/Modules/no-local-decl-in-reduced-bmi.cppm
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Original file line number Diff line number Diff line change
Expand Up @@ -6,11 +6,11 @@
//
// RUN: %clang_cc1 -std=c++20 %t/a.cppm -emit-reduced-module-interface -o %t/a.pcm
// RUN: llvm-bcanalyzer --dump --disable-histogram --show-binary-blobs %t/a.pcm > %t/a.dump
// RUN: cat %t/a.dump | FileCheck %t/a.cppm
// RUN: cat %t/a.dump | FileCheck %t/a.check
//
// RUN: %clang_cc1 -std=c++20 %t/b.cppm -emit-reduced-module-interface -o %t/b.pcm
// RUN: llvm-bcanalyzer --dump --disable-histogram --show-binary-blobs %t/b.pcm > %t/b.dump
// RUN: cat %t/b.dump | FileCheck %t/b.cppm
// RUN: cat %t/b.dump | FileCheck %t/b.check

//--- a.cppm
export module a;
Expand All @@ -19,6 +19,9 @@ export int func() {
return 43;
}

//--- a.check
// Use a standalone check file since now we're going to embed all source files in the BMI
// so we will check the `CHECK-NOT: <DECL_VAR` in the source file otherwise.
// Test that the variable declaration is not recorded completely.
// CHECK-NOT: <DECL_VAR

Expand All @@ -29,5 +32,6 @@ export inline int func() {
return v;
}

//--- b.check
// Check that we still records the declaration from inline functions.
// CHECK: <DECL_VAR
33 changes: 33 additions & 0 deletions clang/test/Modules/pr102721.cppm
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@@ -0,0 +1,33 @@
// RUN: rm -rf %t
// RUN: mkdir -p %t
// RUN: split-file %s %t
//
// RUN: %clang_cc1 -std=c++20 %t/a.cppm -emit-module-interface -o %t/a.pcm
// RUN: %clang_cc1 -std=c++20 %t/b.cppm -emit-module-interface -o %t/b.pcm \
// RUN: -fprebuilt-module-path=%t
// RUN: %clang_cc1 -std=c++20 %t/test.cc -fsyntax-only -verify \
// RUN: -fprebuilt-module-path=%t

//--- foo.h
inline auto x = []{};

//--- a.cppm
module;
#include "foo.h"
export module a;
export using ::x;

//--- b.cppm
module;
import a;
#include "foo.h"
export module b;
export using ::x;

//--- test.cc
// expected-no-diagnostics
import a;
import b;
void test() {
x();
}
41 changes: 41 additions & 0 deletions clang/test/Modules/pr106483.cppm
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@@ -0,0 +1,41 @@
// RUN: rm -rf %t
// RUN: mkdir -p %t
// RUN: split-file %s %t
//
// RUN: %clang_cc1 -std=c++23 %t/a.cppm -emit-module-interface -o %t/a.pcm
// RUN: %clang_cc1 -std=c++23 %t/b.cppm -emit-module-interface -o %t/b.pcm \
// RUN: -fprebuilt-module-path=%t
// RUN: %clang_cc1 -std=c++23 -fprebuilt-module-path=%t %t/b.pcm -emit-llvm \
// RUN: -disable-llvm-passes -o - | FileCheck %t/b.cppm

//--- a.cppm
module;

struct base {
virtual void f() const;
};

inline void base::f() const {
}

export module a;
export using ::base;

//--- b.cppm
module;

struct base {
virtual void f() const;
};

inline void base::f() const {
}

export module b;
import a;
export using ::base;

export extern "C" void func() {}

// We only need to check that the IR are successfully emitted instead of crash.
// CHECK: func
4 changes: 3 additions & 1 deletion clang/test/Modules/reduced-bmi-empty-module-purview-std.cppm
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Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@
//
// RUN: %clang_cc1 -std=c++20 %t/A.cppm -emit-reduced-module-interface -o %t/A.pcm
// RUN: llvm-bcanalyzer --dump --disable-histogram --show-binary-blobs %t/A.pcm > %t/A.dump
// RUN: cat %t/A.dump | FileCheck %t/A.cppm
// RUN: cat %t/A.dump | FileCheck %t/A.check

//--- std.h
namespace std {
Expand All @@ -22,6 +22,8 @@ module;
#include "std.h"
export module A;


//--- A.check
// CHECK-NOT: <DECL_NAMESPACE
// CHECK-NOT: <DECL_CONTEXT_LEXICAL
// CHECK-NOT: <DELAYED_NAMESPACE_LEXICAL_VISIBLE_RECORD
6 changes: 4 additions & 2 deletions clang/test/Modules/reduced-bmi-empty-module-purview.cppm
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Original file line number Diff line number Diff line change
Expand Up @@ -9,12 +9,12 @@
// RUN: %clang_cc1 -std=c++20 %t/A.cppm -emit-reduced-module-interface -o %t/A.pcm \
// RUN: -fmodule-file=M=%t/M.pcm
// RUN: llvm-bcanalyzer --dump --disable-histogram --show-binary-blobs %t/A.pcm > %t/A.dump
// RUN: cat %t/A.dump | FileCheck %t/A.cppm
// RUN: cat %t/A.dump | FileCheck %t/A.check
//
// RUN: %clang_cc1 -std=c++20 %t/A1.cppm -emit-reduced-module-interface -o %t/A1.pcm \
// RUN: -fmodule-file=M=%t/M.pcm
// RUN: llvm-bcanalyzer --dump --disable-histogram --show-binary-blobs %t/A1.pcm > %t/A1.dump
// RUN: cat %t/A1.dump | FileCheck %t/A1.cppm
// RUN: cat %t/A1.dump | FileCheck %t/A1.check

//--- foo.h
namespace ns {
Expand Down Expand Up @@ -82,6 +82,7 @@ module;
export module A;
import M;

//--- A.check
// CHECK-NOT: <DECL_CXX_RECORD
// CHECK-NOT: <DECL_UPDATE_OFFSETS

Expand All @@ -91,6 +92,7 @@ import M;
#include "foo.h"
export module A;

//--- A1.check
// CHECK-NOT: <DECL_CXX_RECORD
// CHECK-NOT: <DECL_UPDATE_OFFSETS

7 changes: 5 additions & 2 deletions clang/test/Modules/unreached-static-entities.cppm
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,11 +3,13 @@
//
// RUN: rm -rf %t
// RUN: mkdir -p %t
// RUN: split-file %s %t
//
// RUN: %clang_cc1 -std=c++20 %s -emit-reduced-module-interface -o %t/S.pcm
// RUN: %clang_cc1 -std=c++20 %t/S.cppm -emit-reduced-module-interface -o %t/S.pcm
// RUN: llvm-bcanalyzer --dump --disable-histogram --show-binary-blobs %t/S.pcm > %t/S.dump
// RUN: cat %t/S.dump | FileCheck %s
// RUN: cat %t/S.dump | FileCheck %t/S.check

//--- S.cppm
export module S;
static int static_func() {
return 43;
Expand All @@ -17,6 +19,7 @@ export int func() {
return static_func();
}

//--- S.check
// CHECK: <DECL_FUNCTION
// Checks that we won't see a second function
// CHECK-NOT: <DECL_FUNCTION
4 changes: 2 additions & 2 deletions clang/tools/clang-repl/CMakeLists.txt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9,6 +9,8 @@ set( LLVM_LINK_COMPONENTS

add_clang_tool(clang-repl
ClangRepl.cpp

EXPORT_SYMBOLS
)

if(MSVC)
Expand Down Expand Up @@ -61,8 +63,6 @@ clang_target_link_libraries(clang-repl PRIVATE
clangInterpreter
)

export_executable_symbols_for_plugins(clang-repl)

# The clang-repl binary can get huge with static linking in debug mode.
# Some 32-bit targets use PLT slots with limited branch range by default and we
# start to exceed this limit, e.g. when linking for arm-linux-gnueabihf with
Expand Down
7 changes: 1 addition & 6 deletions lld/COFF/Chunks.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -842,14 +842,9 @@ const uint8_t arm64Thunk[] = {
0x00, 0x02, 0x1f, 0xd6, // br x16
};

size_t RangeExtensionThunkARM64::getSize() const {
assert(ctx.config.machine == ARM64);
(void)&ctx;
return sizeof(arm64Thunk);
}
size_t RangeExtensionThunkARM64::getSize() const { return sizeof(arm64Thunk); }

void RangeExtensionThunkARM64::writeTo(uint8_t *buf) const {
assert(ctx.config.machine == ARM64);
memcpy(buf, arm64Thunk, sizeof(arm64Thunk));
applyArm64Addr(buf + 0, target->getRVA(), rva, 12);
applyArm64Imm(buf + 4, target->getRVA() & 0xfff, 0);
Expand Down
10 changes: 6 additions & 4 deletions lld/COFF/Chunks.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -615,20 +615,22 @@ class RangeExtensionThunkARM : public NonSectionCodeChunk {
COFFLinkerContext &ctx;
};

// A ragnge extension thunk used for both ARM64EC and ARM64 machine types.
class RangeExtensionThunkARM64 : public NonSectionCodeChunk {
public:
explicit RangeExtensionThunkARM64(COFFLinkerContext &ctx, Defined *t)
: target(t), ctx(ctx) {
explicit RangeExtensionThunkARM64(MachineTypes machine, Defined *t)
: target(t), machine(machine) {
setAlignment(4);
assert(llvm::COFF::isAnyArm64(machine));
}
size_t getSize() const override;
void writeTo(uint8_t *buf) const override;
MachineTypes getMachine() const override { return ARM64; }
MachineTypes getMachine() const override { return machine; }

Defined *target;

private:
COFFLinkerContext &ctx;
MachineTypes machine;
};

// Windows-specific.
Expand Down
38 changes: 22 additions & 16 deletions lld/COFF/Writer.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -219,10 +219,12 @@ class Writer {
void sortECChunks();
void removeUnusedSections();
void assignAddresses();
bool isInRange(uint16_t relType, uint64_t s, uint64_t p, int margin);
bool isInRange(uint16_t relType, uint64_t s, uint64_t p, int margin,
MachineTypes machine);
std::pair<Defined *, bool> getThunk(DenseMap<uint64_t, Defined *> &lastThunks,
Defined *target, uint64_t p,
uint16_t type, int margin);
uint16_t type, int margin,
MachineTypes machine);
bool createThunks(OutputSection *os, int margin);
bool verifyRanges(const std::vector<Chunk *> chunks);
void createECCodeMap();
Expand Down Expand Up @@ -396,8 +398,9 @@ void OutputSection::addContributingPartialSection(PartialSection *sec) {

// Check whether the target address S is in range from a relocation
// of type relType at address P.
bool Writer::isInRange(uint16_t relType, uint64_t s, uint64_t p, int margin) {
if (ctx.config.machine == ARMNT) {
bool Writer::isInRange(uint16_t relType, uint64_t s, uint64_t p, int margin,
MachineTypes machine) {
if (machine == ARMNT) {
int64_t diff = AbsoluteDifference(s, p + 4) + margin;
switch (relType) {
case IMAGE_REL_ARM_BRANCH20T:
Expand All @@ -408,7 +411,7 @@ bool Writer::isInRange(uint16_t relType, uint64_t s, uint64_t p, int margin) {
default:
return true;
}
} else if (ctx.config.machine == ARM64) {
} else if (isAnyArm64(machine)) {
int64_t diff = AbsoluteDifference(s, p) + margin;
switch (relType) {
case IMAGE_REL_ARM64_BRANCH26:
Expand All @@ -421,25 +424,25 @@ bool Writer::isInRange(uint16_t relType, uint64_t s, uint64_t p, int margin) {
return true;
}
} else {
llvm_unreachable("Unexpected architecture");
return true;
}
}

// Return the last thunk for the given target if it is in range,
// or create a new one.
std::pair<Defined *, bool>
Writer::getThunk(DenseMap<uint64_t, Defined *> &lastThunks, Defined *target,
uint64_t p, uint16_t type, int margin) {
uint64_t p, uint16_t type, int margin, MachineTypes machine) {
Defined *&lastThunk = lastThunks[target->getRVA()];
if (lastThunk && isInRange(type, lastThunk->getRVA(), p, margin))
if (lastThunk && isInRange(type, lastThunk->getRVA(), p, margin, machine))
return {lastThunk, false};
Chunk *c;
switch (ctx.config.machine) {
case ARMNT:
switch (getMachineArchType(machine)) {
case Triple::thumb:
c = make<RangeExtensionThunkARM>(ctx, target);
break;
case ARM64:
c = make<RangeExtensionThunkARM64>(ctx, target);
case Triple::aarch64:
c = make<RangeExtensionThunkARM64>(machine, target);
break;
default:
llvm_unreachable("Unexpected architecture");
Expand Down Expand Up @@ -471,6 +474,7 @@ bool Writer::createThunks(OutputSection *os, int margin) {
SectionChunk *sc = dyn_cast_or_null<SectionChunk>(os->chunks[i]);
if (!sc)
continue;
MachineTypes machine = sc->getMachine();
size_t thunkInsertionSpot = i + 1;

// Try to get a good enough estimate of where new thunks will be placed.
Expand All @@ -497,11 +501,12 @@ bool Writer::createThunks(OutputSection *os, int margin) {

uint64_t s = sym->getRVA();

if (isInRange(rel.Type, s, p, margin))
if (isInRange(rel.Type, s, p, margin, machine))
continue;

// If the target isn't in range, hook it up to an existing or new thunk.
auto [thunk, wasNew] = getThunk(lastThunks, sym, p, rel.Type, margin);
auto [thunk, wasNew] =
getThunk(lastThunks, sym, p, rel.Type, margin, machine);
if (wasNew) {
Chunk *thunkChunk = thunk->getChunk();
thunkChunk->setRVA(
Expand Down Expand Up @@ -603,6 +608,7 @@ bool Writer::verifyRanges(const std::vector<Chunk *> chunks) {
SectionChunk *sc = dyn_cast_or_null<SectionChunk>(c);
if (!sc)
continue;
MachineTypes machine = sc->getMachine();

ArrayRef<coff_relocation> relocs = sc->getRelocs();
for (const coff_relocation &rel : relocs) {
Expand All @@ -615,7 +621,7 @@ bool Writer::verifyRanges(const std::vector<Chunk *> chunks) {
uint64_t p = sc->getRVA() + rel.VirtualAddress;
uint64_t s = sym->getRVA();

if (!isInRange(rel.Type, s, p, 0))
if (!isInRange(rel.Type, s, p, 0, machine))
return false;
}
}
Expand All @@ -625,7 +631,7 @@ bool Writer::verifyRanges(const std::vector<Chunk *> chunks) {
// Assign addresses and add thunks if necessary.
void Writer::finalizeAddresses() {
assignAddresses();
if (ctx.config.machine != ARMNT && ctx.config.machine != ARM64)
if (ctx.config.machine != ARMNT && !isAnyArm64(ctx.config.machine))
return;

size_t origNumChunks = 0;
Expand Down
186 changes: 186 additions & 0 deletions lld/test/COFF/arm64ec-range-thunks.s
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,186 @@
# REQUIRES: aarch64, x86
# RUN: split-file %s %t.dir && cd %t.dir

# RUN: llvm-mc -filetype=obj -triple=arm64ec-windows funcs.s -o funcs-arm64ec.obj
# RUN: llvm-mc -filetype=obj -triple=aarch64-windows native-funcs.s -o funcs-aarch64.obj
# RUN: llvm-mc -filetype=obj -triple=x86_64-windows space.s -o space-x86_64.obj
# RUN: llvm-mc -filetype=obj -triple=aarch64-windows space.s -o space-aarch64.obj
# RUN: llvm-mc -filetype=obj -triple=arm64ec-windows %S/Inputs/loadconfig-arm64ec.s -o loadconfig-arm64ec.obj


# Test generating range extension thunks for ARM64EC code. Place some x86_64 chunks in a middle
# and make sure that thunks stay in ARM64EC code range.

# RUN: lld-link -machine:arm64ec -noentry -dll funcs-arm64ec.obj space-x86_64.obj loadconfig-arm64ec.obj -out:test.dll \
# RUN: -verbose 2>&1 | FileCheck -check-prefix=VERBOSE %s
# VERBOSE: Added 3 thunks with margin {{.*}} in 1 passes

# RUN: llvm-objdump -d test.dll | FileCheck --check-prefix=DISASM %s

# DISASM: Disassembly of section .code1:
# DISASM-EMPTY:
# DISASM-NEXT: 0000000180003000 <.code1>:
# DISASM-NEXT: 180003000: 36000040 tbz w0, #0x0, 0x180003008 <.code1+0x8>
# DISASM-NEXT: 180003004: d65f03c0 ret
# DISASM-NEXT: 180003008: b0000050 adrp x16, 0x18000c000
# DISASM-NEXT: 18000300c: 91000210 add x16, x16, #0x0
# DISASM-NEXT: 180003010: d61f0200 br x16
# DISASM-EMPTY:
# DISASM-NEXT: Disassembly of section .code2:
# DISASM-EMPTY:
# DISASM-NEXT: 0000000180004000 <.code2>:
# DISASM-NEXT: ...
# DISASM-EMPTY:
# DISASM-NEXT: Disassembly of section .code3:
# DISASM-EMPTY:
# DISASM-NEXT: 0000000180005000 <.code3>:
# DISASM-NEXT: ...
# DISASM-NEXT: 18000c000: 36000060 tbz w0, #0x0, 0x18000c00c <.code3+0x700c>
# DISASM-NEXT: 18000c004: d65f03c0 ret
# DISASM-NEXT: 18000c008: 00000000 udf #0x0
# DISASM-NEXT: 18000c00c: 90000050 adrp x16, 0x180014000 <.code3+0xf000>
# DISASM-NEXT: 18000c010: 91006210 add x16, x16, #0x18
# DISASM-NEXT: 18000c014: d61f0200 br x16
# DISASM-NEXT: ...
# DISASM-NEXT: 180014018: 36000040 tbz w0, #0x0, 0x180014020 <.code3+0xf020>
# DISASM-NEXT: 18001401c: d65f03c0 ret
# DISASM-NEXT: 180014020: f0ffff70 adrp x16, 0x180003000 <.code1>
# DISASM-NEXT: 180014024: 91000210 add x16, x16, #0x0
# DISASM-NEXT: 180014028: d61f0200 br x16

# RUN: llvm-readobj --coff-load-config test.dll | FileCheck --check-prefix=LOADCFG %s

# LOADCFG: CodeMap [
# LOADCFG-NEXT: 0x3000 - 0x3014 ARM64EC
# LOADCFG-NEXT: 0x4000 - 0x4300 X64
# LOADCFG-NEXT: 0x5000 - 0x1402C ARM64EC
# LOADCFG-NEXT: ]


# A similar test using a hybrid binary and native placeholder chunks.

# RUN: lld-link -machine:arm64x -noentry -dll funcs-arm64ec.obj space-aarch64.obj loadconfig-arm64ec.obj -out:testx.dll \
# RUN: -verbose 2>&1 | FileCheck -check-prefix=VERBOSE %s
# RUN: llvm-objdump -d testx.dll | FileCheck --check-prefix=DISASM %s

# RUN: llvm-readobj --coff-load-config testx.dll | FileCheck --check-prefix=LOADCFGX %s

# LOADCFGX: CodeMap [
# LOADCFGX-NEXT: 0x3000 - 0x3014 ARM64EC
# LOADCFGX-NEXT: 0x4000 - 0x4300 ARM64
# LOADCFGX-NEXT: 0x5000 - 0x1402C ARM64EC
# LOADCFGX-NEXT: ]


# Test a hybrid ARM64X binary which requires range extension thunks for both native and EC relocations.

# RUN: lld-link -machine:arm64x -noentry -dll funcs-arm64ec.obj funcs-aarch64.obj loadconfig-arm64ec.obj -out:testx2.dll \
# RUN: -verbose 2>&1 | FileCheck -check-prefix=VERBOSEX %s
# VERBOSEX: Added 5 thunks with margin {{.*}} in 1 passes

# RUN: llvm-objdump -d testx2.dll | FileCheck --check-prefix=DISASMX %s

# DISASMX: Disassembly of section .code1:
# DISASMX-EMPTY:
# DISASMX-NEXT: 0000000180003000 <.code1>:
# DISASMX-NEXT: 180003000: 36000040 tbz w0, #0x0, 0x180003008 <.code1+0x8>
# DISASMX-NEXT: 180003004: d65f03c0 ret
# DISASMX-NEXT: 180003008: b0000050 adrp x16, 0x18000c000
# DISASMX-NEXT: 18000300c: 91000210 add x16, x16, #0x0
# DISASMX-NEXT: 180003010: d61f0200 br x16
# DISASMX-EMPTY:
# DISASMX-NEXT: Disassembly of section .code2:
# DISASMX-EMPTY:
# DISASMX-NEXT: 0000000180004000 <.code2>:
# DISASMX-NEXT: 180004000: 36000040 tbz w0, #0x0, 0x180004008 <.code2+0x8>
# DISASMX-NEXT: 180004004: d65f03c0 ret
# DISASMX-NEXT: 180004008: b0000090 adrp x16, 0x180015000
# DISASMX-NEXT: 18000400c: 91000210 add x16, x16, #0x0
# DISASMX-NEXT: 180004010: d61f0200 br x16
# DISASMX-EMPTY:
# DISASMX-NEXT: Disassembly of section .code3:
# DISASMX-EMPTY:
# DISASMX-NEXT: 0000000180005000 <.code3>:
# DISASMX-NEXT: ...
# DISASMX-NEXT: 18000c000: 36000060 tbz w0, #0x0, 0x18000c00c <.code3+0x700c>
# DISASMX-NEXT: 18000c004: d65f03c0 ret
# DISASMX-NEXT: 18000c008: 00000000 udf #0x0
# DISASMX-NEXT: 18000c00c: 90000050 adrp x16, 0x180014000 <.code3+0xf000>
# DISASMX-NEXT: 18000c010: 91006210 add x16, x16, #0x18
# DISASMX-NEXT: 18000c014: d61f0200 br x16
# DISASMX-NEXT: ...
# DISASMX-NEXT: 180014018: 36000040 tbz w0, #0x0, 0x180014020 <.code3+0xf020>
# DISASMX-NEXT: 18001401c: d65f03c0 ret
# DISASMX-NEXT: 180014020: f0ffff70 adrp x16, 0x180003000 <.code1>
# DISASMX-NEXT: 180014024: 91000210 add x16, x16, #0x0
# DISASMX-NEXT: 180014028: d61f0200 br x16
# DISASMX-EMPTY:
# DISASMX-NEXT: Disassembly of section .code4:
# DISASMX-EMPTY:
# DISASMX-NEXT: 0000000180015000 <.code4>:
# DISASMX-NEXT: 180015000: 36000040 tbz w0, #0x0, 0x180015008 <.code4+0x8>
# DISASMX-NEXT: 180015004: d65f03c0 ret
# DISASMX-NEXT: 180015008: f0ffff70 adrp x16, 0x180004000 <.code2>
# DISASMX-NEXT: 18001500c: 91000210 add x16, x16, #0x0
# DISASMX-NEXT: 180015010: d61f0200 br x16

# RUN: llvm-readobj --coff-load-config testx2.dll | FileCheck --check-prefix=LOADCFGX2 %s

# LOADCFGX2: CodeMap [
# LOADCFGX2-NEXT: 0x3000 - 0x3014 ARM64EC
# LOADCFGX2-NEXT: 0x4000 - 0x4014 ARM64
# LOADCFGX2-NEXT: 0x5000 - 0x1402C ARM64EC
# LOADCFGX2-NEXT: 0x15000 - 0x15014 ARM64
# LOADCFGX2-NEXT: ]


#--- funcs.s
.globl main
.globl func1
.globl func2

.section .code1, "xr"
main:
tbz w0, #0, func1
ret

.section .code3$a, "xr"
.space 0x7000

.section .code3$b, "xr"
func1:
tbz w0, #0, func2
ret
.space 1

.section .code3$c, "xr"
.space 0x8000

.section .code3$d, "xr"
.align 2
func2:
tbz w0, #0, main
ret

#--- space.s
.section .code2$a, "xr"
.space 0x100
.section .code2$b, "xr"
.space 0x100
.section .code2$c, "xr"
.space 0x100

#--- native-funcs.s
.globl nmain
.globl nfunc

.section .code2, "xr"
nmain:
tbz w0, #0, nfunc
ret

.section .code4, "xr"
.align 2
nfunc:
tbz w0, #0, nmain
ret
14 changes: 8 additions & 6 deletions lldb/source/Plugins/ObjectFile/Minidump/MinidumpFileBuilder.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -491,12 +491,14 @@ GetThreadContext_x86_64(RegisterContext *reg_ctx) {
thread_context.r14 = read_register_u64(reg_ctx, "r14");
thread_context.r15 = read_register_u64(reg_ctx, "r15");
thread_context.rip = read_register_u64(reg_ctx, "rip");
thread_context.eflags = read_register_u32(reg_ctx, "rflags");
thread_context.cs = read_register_u16(reg_ctx, "cs");
thread_context.fs = read_register_u16(reg_ctx, "fs");
thread_context.gs = read_register_u16(reg_ctx, "gs");
thread_context.ss = read_register_u16(reg_ctx, "ss");
thread_context.ds = read_register_u16(reg_ctx, "ds");
// To make our code agnostic to whatever type the register value identifies
// itself as, we read as a u64 and truncate to u32/u16 ourselves.
thread_context.eflags = read_register_u64(reg_ctx, "rflags");
thread_context.cs = read_register_u64(reg_ctx, "cs");
thread_context.fs = read_register_u64(reg_ctx, "fs");
thread_context.gs = read_register_u64(reg_ctx, "gs");
thread_context.ss = read_register_u64(reg_ctx, "ss");
thread_context.ds = read_register_u64(reg_ctx, "ds");
return thread_context;
}

Expand Down
36 changes: 34 additions & 2 deletions lldb/test/API/functionalities/process_save_core_minidump/TestProcessSaveCoreMinidump.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -17,6 +17,7 @@ def verify_core_file(
expected_modules,
expected_threads,
stacks_to_sps_map,
stacks_to_registers_map,
):
# To verify, we'll launch with the mini dump
target = self.dbg.CreateTarget(None)
Expand Down Expand Up @@ -62,6 +63,17 @@ def verify_core_file(
# Try to read just past the red zone and fail
process.ReadMemory(sp - red_zone - 1, 1, error)
self.assertTrue(error.Fail(), "No failure when reading past the red zone")
# Verify the registers are the same
self.assertIn(thread_id, stacks_to_registers_map)
register_val_list = stacks_to_registers_map[thread_id]
frame_register_list = frame.GetRegisters()
for x in register_val_list:
self.assertEqual(
x.GetValueAsUnsigned(),
frame_register_list.GetFirstValueByName(
x.GetName()
).GetValueAsUnsigned(),
)

self.dbg.DeleteTarget(target)

Expand Down Expand Up @@ -93,12 +105,16 @@ def test_save_linux_mini_dump(self):
expected_number_of_threads = process.GetNumThreads()
expected_threads = []
stacks_to_sp_map = {}
stakcs_to_registers_map = {}

for thread_idx in range(process.GetNumThreads()):
thread = process.GetThreadAtIndex(thread_idx)
thread_id = thread.GetThreadID()
expected_threads.append(thread_id)
stacks_to_sp_map[thread_id] = thread.GetFrameAtIndex(0).GetSP()
stakcs_to_registers_map[thread_id] = thread.GetFrameAtIndex(
0
).GetRegisters()

# save core and, kill process and verify corefile existence
base_command = "process save-core --plugin-name=minidump "
Expand All @@ -110,6 +126,7 @@ def test_save_linux_mini_dump(self):
expected_modules,
expected_threads,
stacks_to_sp_map,
stakcs_to_registers_map,
)

self.runCmd(base_command + " --style=modified-memory '%s'" % (core_dirty))
Expand All @@ -120,6 +137,7 @@ def test_save_linux_mini_dump(self):
expected_modules,
expected_threads,
stacks_to_sp_map,
stakcs_to_registers_map,
)

self.runCmd(base_command + " --style=full '%s'" % (core_full))
Expand All @@ -130,6 +148,7 @@ def test_save_linux_mini_dump(self):
expected_modules,
expected_threads,
stacks_to_sp_map,
stakcs_to_registers_map,
)

options = lldb.SBSaveCoreOptions()
Expand All @@ -147,6 +166,7 @@ def test_save_linux_mini_dump(self):
expected_modules,
expected_threads,
stacks_to_sp_map,
stakcs_to_registers_map,
)

options = lldb.SBSaveCoreOptions()
Expand All @@ -163,6 +183,7 @@ def test_save_linux_mini_dump(self):
expected_modules,
expected_threads,
stacks_to_sp_map,
stakcs_to_registers_map,
)

# Minidump can now save full core files, but they will be huge and
Expand All @@ -181,6 +202,7 @@ def test_save_linux_mini_dump(self):
expected_modules,
expected_threads,
stacks_to_sp_map,
stakcs_to_registers_map,
)

self.assertSuccess(process.Kill())
Expand Down Expand Up @@ -276,13 +298,16 @@ def test_save_linux_mini_dump_default_options(self):
expected_threads = []
stacks_to_sp_map = {}
expected_pid = process.GetProcessInfo().GetProcessID()
stacks_to_registers_map = {}

for thread_idx in range(process.GetNumThreads()):
thread = process.GetThreadAtIndex(thread_idx)
thread_id = thread.GetThreadID()
expected_threads.append(thread_id)
stacks_to_sp_map[thread_id] = thread.GetFrameAtIndex(0).GetSP()

stacks_to_registers_map[thread_id] = thread.GetFrameAtIndex(
0
).GetRegisters()

# This is almost identical to the single thread test case because
# minidump defaults to stacks only, so we want to see if the
Expand All @@ -294,7 +319,14 @@ def test_save_linux_mini_dump_default_options(self):
error = process.SaveCore(options)
self.assertTrue(error.Success())

self.verify_core_file(default_value_file, expected_pid, expected_modules, expected_threads, stacks_to_sp_map)
self.verify_core_file(
default_value_file,
expected_pid,
expected_modules,
expected_threads,
stacks_to_sp_map,
stacks_to_registers_map,
)

finally:
self.assertTrue(self.dbg.DeleteTarget(target))
Expand Down
4 changes: 0 additions & 4 deletions lldb/test/API/tools/lldb-dap/console/TestDAP_console.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -37,7 +37,6 @@ def check_lldb_command(
),
)

@skipIfWindows
def test_scopes_variables_setVariable_evaluate(self):
"""
Tests that the "scopes" request causes the currently selected
Expand Down Expand Up @@ -80,7 +79,6 @@ def test_scopes_variables_setVariable_evaluate(self):

self.check_lldb_command("frame select", "frame #1", "frame 1 is selected")

@skipIfWindows
def test_custom_escape_prefix(self):
program = self.getBuildArtifact("a.out")
self.build_and_launch(program, commandEscapePrefix="::")
Expand All @@ -96,7 +94,6 @@ def test_custom_escape_prefix(self):
command_escape_prefix="::",
)

@skipIfWindows
def test_empty_escape_prefix(self):
program = self.getBuildArtifact("a.out")
self.build_and_launch(program, commandEscapePrefix="")
Expand Down Expand Up @@ -151,7 +148,6 @@ def test_exit_status_message_sigterm(self):
"Exit status does not contain message 'exited with status'",
)

@skipIfWindows
def test_exit_status_message_ok(self):
program = self.getBuildArtifact("a.out")
self.build_and_launch(program, commandEscapePrefix="")
Expand Down
7 changes: 3 additions & 4 deletions llvm/docs/TestSuiteGuide.md
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,10 +16,9 @@ Quickstart
environment:

```bash
% mkdir venv
% virtualenv venv
% . venv/bin/activate
% pip install svn+https://llvm.org/svn/llvm-project/llvm/trunk/utils/lit
% python3 -m venv .venv
% . .venv/bin/activate
% pip install git+https://github.com/llvm/llvm-project.git#subdirectory=llvm/utils/lit
% lit --version
lit 0.8.0dev
```
Expand Down
21 changes: 13 additions & 8 deletions llvm/include/llvm/Transforms/IPO/Attributor.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -294,11 +294,16 @@ struct RangeTy {
return *this;
}

/// Comparison for sorting ranges by offset.
/// Comparison for sorting ranges.
///
/// Returns true if the offset \p L is less than that of \p R.
inline static bool OffsetLessThan(const RangeTy &L, const RangeTy &R) {
return L.Offset < R.Offset;
/// Returns true if the offset of \p L is less than that of \p R. If the two
/// offsets are same, compare the sizes instead.
inline static bool LessThan(const RangeTy &L, const RangeTy &R) {
if (L.Offset < R.Offset)
return true;
if (L.Offset == R.Offset)
return L.Size < R.Size;
return false;
}

/// Constants used to represent special offsets or sizes.
Expand Down Expand Up @@ -5809,7 +5814,7 @@ struct AAPointerInfo : public AbstractAttribute {
// Helpers required for std::set_difference
using value_type = RangeTy;
void push_back(const RangeTy &R) {
assert((Ranges.empty() || RangeTy::OffsetLessThan(Ranges.back(), R)) &&
assert((Ranges.empty() || RangeTy::LessThan(Ranges.back(), R)) &&
"Ensure the last element is the greatest.");
Ranges.push_back(R);
}
Expand All @@ -5818,7 +5823,7 @@ struct AAPointerInfo : public AbstractAttribute {
static void set_difference(const RangeList &L, const RangeList &R,
RangeList &D) {
std::set_difference(L.begin(), L.end(), R.begin(), R.end(),
std::back_inserter(D), RangeTy::OffsetLessThan);
std::back_inserter(D), RangeTy::LessThan);
}

unsigned size() const { return Ranges.size(); }
Expand Down Expand Up @@ -5856,7 +5861,7 @@ struct AAPointerInfo : public AbstractAttribute {

/// Insert \p R at the given iterator \p Pos, and merge if necessary.
///
/// This assumes that all ranges before \p Pos are OffsetLessThan \p R, and
/// This assumes that all ranges before \p Pos are LessThan \p R, and
/// then maintains the sorted order for the suffix list.
///
/// \return The place of insertion and true iff anything changed.
Expand All @@ -5868,7 +5873,7 @@ struct AAPointerInfo : public AbstractAttribute {
}

// Maintain this as a sorted vector of unique entries.
auto LB = std::lower_bound(Pos, Ranges.end(), R, RangeTy::OffsetLessThan);
auto LB = std::lower_bound(Pos, Ranges.end(), R, RangeTy::LessThan);
if (LB == Ranges.end() || LB->Offset != R.Offset)
return std::make_pair(Ranges.insert(LB, R), true);
bool Changed = *LB != R;
Expand Down
59 changes: 42 additions & 17 deletions llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -27096,21 +27096,37 @@ AArch64TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
: AtomicExpansionKind::LLSC;
}

// Return true if the atomic operation expansion will lower to use a library
// call, and is thus ineligible to use an LLSC expansion.
static bool rmwOpMayLowerToLibcall(const AArch64Subtarget &Subtarget,
const AtomicRMWInst *RMW) {
if (!RMW->isFloatingPointOperation())
return false;
switch (RMW->getType()->getScalarType()->getTypeID()) {
case Type::FloatTyID:
case Type::DoubleTyID:
case Type::HalfTyID:
case Type::BFloatTyID:
// Will use soft float
return !Subtarget.hasFPARMv8();
default:
// fp128 will emit library calls.
return true;
}

llvm_unreachable("covered type switch");
}

// The "default" for integer RMW operations is to expand to an LL/SC loop.
// However, with the LSE instructions (or outline-atomics mode, which provides
// library routines in place of the LSE-instructions), we can directly emit many
// operations instead.
//
// Floating-point operations are always emitted to a cmpxchg loop, because they
// may trigger a trap which aborts an LLSC sequence.
TargetLowering::AtomicExpansionKind
AArch64TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
unsigned Size = AI->getType()->getPrimitiveSizeInBits();
Type *Ty = AI->getType();
unsigned Size = Ty->getPrimitiveSizeInBits();
assert(Size <= 128 && "AtomicExpandPass should've handled larger sizes.");

if (AI->isFloatingPointOperation())
return AtomicExpansionKind::CmpXChg;

bool CanUseLSE128 = Subtarget->hasLSE128() && Size == 128 &&
(AI->getOperation() == AtomicRMWInst::Xchg ||
AI->getOperation() == AtomicRMWInst::Or ||
Expand All @@ -27120,7 +27136,8 @@ AArch64TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {

// Nand is not supported in LSE.
// Leave 128 bits to LLSC or CmpXChg.
if (AI->getOperation() != AtomicRMWInst::Nand && Size < 128) {
if (AI->getOperation() != AtomicRMWInst::Nand && Size < 128 &&
!AI->isFloatingPointOperation()) {
if (Subtarget->hasLSE())
return AtomicExpansionKind::None;
if (Subtarget->outlineAtomics()) {
Expand All @@ -27146,7 +27163,7 @@ AArch64TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
// succeed. So at -O0 lower this operation to a CAS loop. Also worthwhile if
// we have a single CAS instruction that can replace the loop.
if (getTargetMachine().getOptLevel() == CodeGenOptLevel::None ||
Subtarget->hasLSE())
Subtarget->hasLSE() || rmwOpMayLowerToLibcall(*Subtarget, AI))
return AtomicExpansionKind::CmpXChg;

return AtomicExpansionKind::LLSC;
Expand Down Expand Up @@ -27193,10 +27210,14 @@ Value *AArch64TargetLowering::emitLoadLinked(IRBuilderBase &Builder,

Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");
Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");
Lo = Builder.CreateZExt(Lo, ValueTy, "lo64");
Hi = Builder.CreateZExt(Hi, ValueTy, "hi64");
return Builder.CreateOr(
Lo, Builder.CreateShl(Hi, ConstantInt::get(ValueTy, 64)), "val64");

auto *Int128Ty = Type::getInt128Ty(Builder.getContext());
Lo = Builder.CreateZExt(Lo, Int128Ty, "lo64");
Hi = Builder.CreateZExt(Hi, Int128Ty, "hi64");

Value *Or = Builder.CreateOr(
Lo, Builder.CreateShl(Hi, ConstantInt::get(Int128Ty, 64)), "val64");
return Builder.CreateBitCast(Or, ValueTy);
}

Type *Tys[] = { Addr->getType() };
Expand All @@ -27207,8 +27228,8 @@ Value *AArch64TargetLowering::emitLoadLinked(IRBuilderBase &Builder,
const DataLayout &DL = M->getDataLayout();
IntegerType *IntEltTy = Builder.getIntNTy(DL.getTypeSizeInBits(ValueTy));
CallInst *CI = Builder.CreateCall(Ldxr, Addr);
CI->addParamAttr(
0, Attribute::get(Builder.getContext(), Attribute::ElementType, ValueTy));
CI->addParamAttr(0, Attribute::get(Builder.getContext(),
Attribute::ElementType, IntEltTy));
Value *Trunc = Builder.CreateTrunc(CI, IntEltTy);

return Builder.CreateBitCast(Trunc, ValueTy);
Expand All @@ -27234,9 +27255,13 @@ Value *AArch64TargetLowering::emitStoreConditional(IRBuilderBase &Builder,
IsRelease ? Intrinsic::aarch64_stlxp : Intrinsic::aarch64_stxp;
Function *Stxr = Intrinsic::getDeclaration(M, Int);
Type *Int64Ty = Type::getInt64Ty(M->getContext());
Type *Int128Ty = Type::getInt128Ty(M->getContext());

Value *CastVal = Builder.CreateBitCast(Val, Int128Ty);

Value *Lo = Builder.CreateTrunc(Val, Int64Ty, "lo");
Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 64), Int64Ty, "hi");
Value *Lo = Builder.CreateTrunc(CastVal, Int64Ty, "lo");
Value *Hi =
Builder.CreateTrunc(Builder.CreateLShr(CastVal, 64), Int64Ty, "hi");
return Builder.CreateCall(Stxr, {Lo, Hi, Addr});
}

Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/AMDGPU/AMDGPU.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -35,7 +35,7 @@ void initializeAMDGPURegBankSelectPass(PassRegistry &);
// SI Passes
FunctionPass *createGCNDPPCombinePass();
FunctionPass *createSIAnnotateControlFlowLegacyPass();
FunctionPass *createSIFoldOperandsPass();
FunctionPass *createSIFoldOperandsLegacyPass();
FunctionPass *createSIPeepholeSDWAPass();
FunctionPass *createSILowerI1CopiesLegacyPass();
FunctionPass *createAMDGPUGlobalISelDivergenceLoweringPass();
Expand Down Expand Up @@ -160,8 +160,8 @@ extern char &AMDGPURewriteOutArgumentsID;
void initializeGCNDPPCombinePass(PassRegistry &);
extern char &GCNDPPCombineID;

void initializeSIFoldOperandsPass(PassRegistry &);
extern char &SIFoldOperandsID;
void initializeSIFoldOperandsLegacyPass(PassRegistry &);
extern char &SIFoldOperandsLegacyID;

void initializeSIPeepholeSDWAPass(PassRegistry &);
extern char &SIPeepholeSDWAID;
Expand Down
1 change: 1 addition & 0 deletions llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
View file
Original file line number Diff line number Diff line change
Expand Up @@ -97,4 +97,5 @@ FUNCTION_PASS_WITH_PARAMS(
MACHINE_FUNCTION_PASS("amdgpu-isel", AMDGPUISelDAGToDAGPass(*this))
MACHINE_FUNCTION_PASS("si-fix-sgpr-copies", SIFixSGPRCopiesPass())
MACHINE_FUNCTION_PASS("si-i1-copies", SILowerI1CopiesPass())
MACHINE_FUNCTION_PASS("si-fold-operands", SIFoldOperandsPass());
#undef MACHINE_FUNCTION_PASS
1,802 changes: 1,272 additions & 530 deletions llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp
View file

Large diffs are not rendered by default.

7 changes: 4 additions & 3 deletions llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -34,6 +34,7 @@
#include "R600.h"
#include "R600TargetMachine.h"
#include "SIFixSGPRCopies.h"
#include "SIFoldOperands.h"
#include "SIMachineFunctionInfo.h"
#include "SIMachineScheduler.h"
#include "TargetInfo/AMDGPUTargetInfo.h"
Expand Down Expand Up @@ -410,7 +411,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
initializeSILowerSGPRSpillsPass(*PR);
initializeSIFixSGPRCopiesLegacyPass(*PR);
initializeSIFixVGPRCopiesPass(*PR);
initializeSIFoldOperandsPass(*PR);
initializeSIFoldOperandsLegacyPass(*PR);
initializeSIPeepholeSDWAPass(*PR);
initializeSIShrinkInstructionsPass(*PR);
initializeSIOptimizeExecMaskingPreRAPass(*PR);
Expand Down Expand Up @@ -1270,15 +1271,15 @@ void GCNPassConfig::addMachineSSAOptimization() {
// instructions leftover after the operands are folded as well.
//
// XXX - Can we get away without running DeadMachineInstructionElim again?
addPass(&SIFoldOperandsID);
addPass(&SIFoldOperandsLegacyID);
if (EnableDPPCombine)
addPass(&GCNDPPCombineID);
addPass(&SILoadStoreOptimizerID);
if (isPassEnabled(EnableSDWAPeephole)) {
addPass(&SIPeepholeSDWAID);
addPass(&EarlyMachineLICMID);
addPass(&MachineCSEID);
addPass(&SIFoldOperandsID);
addPass(&SIFoldOperandsLegacyID);
}
addPass(&DeadMachineInstructionElimID);
addPass(createSIShrinkInstructionsPass());
Expand Down
116 changes: 67 additions & 49 deletions llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,6 +8,7 @@
//===----------------------------------------------------------------------===//
//

#include "SIFoldOperands.h"
#include "AMDGPU.h"
#include "GCNSubtarget.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
Expand Down Expand Up @@ -66,9 +67,8 @@ struct FoldCandidate {
bool needsShrink() const { return ShrinkOpcode != -1; }
};

class SIFoldOperands : public MachineFunctionPass {
class SIFoldOperandsImpl {
public:
static char ID;
MachineRegisterInfo *MRI;
const SIInstrInfo *TII;
const SIRegisterInfo *TRI;
Expand Down Expand Up @@ -121,11 +121,22 @@ class SIFoldOperands : public MachineFunctionPass {
bool tryOptimizeAGPRPhis(MachineBasicBlock &MBB);

public:
SIFoldOperands() : MachineFunctionPass(ID) {
initializeSIFoldOperandsPass(*PassRegistry::getPassRegistry());
}
SIFoldOperandsImpl() = default;

bool run(MachineFunction &MF);
};

bool runOnMachineFunction(MachineFunction &MF) override;
class SIFoldOperandsLegacy : public MachineFunctionPass {
public:
static char ID;

SIFoldOperandsLegacy() : MachineFunctionPass(ID) {}

bool runOnMachineFunction(MachineFunction &MF) override {
if (skipFunction(MF.getFunction()))
return false;
return SIFoldOperandsImpl().run(MF);
}

StringRef getPassName() const override { return "SI Fold Operands"; }

Expand All @@ -137,12 +148,12 @@ class SIFoldOperands : public MachineFunctionPass {

} // End anonymous namespace.

INITIALIZE_PASS(SIFoldOperands, DEBUG_TYPE,
"SI Fold Operands", false, false)
INITIALIZE_PASS(SIFoldOperandsLegacy, DEBUG_TYPE, "SI Fold Operands", false,
false)

char SIFoldOperands::ID = 0;
char SIFoldOperandsLegacy::ID = 0;

char &llvm::SIFoldOperandsID = SIFoldOperands::ID;
char &llvm::SIFoldOperandsLegacyID = SIFoldOperandsLegacy::ID;

static const TargetRegisterClass *getRegOpRC(const MachineRegisterInfo &MRI,
const TargetRegisterInfo &TRI,
Expand Down Expand Up @@ -177,8 +188,8 @@ static unsigned macToMad(unsigned Opc) {

// TODO: Add heuristic that the frame index might not fit in the addressing mode
// immediate offset to avoid materializing in loops.
bool SIFoldOperands::frameIndexMayFold(const MachineInstr &UseMI, int OpNo,
const MachineOperand &OpToFold) const {
bool SIFoldOperandsImpl::frameIndexMayFold(
const MachineInstr &UseMI, int OpNo, const MachineOperand &OpToFold) const {
if (!OpToFold.isFI())
return false;

Expand All @@ -196,11 +207,11 @@ bool SIFoldOperands::frameIndexMayFold(const MachineInstr &UseMI, int OpNo,
return OpNo == VIdx && SIdx == -1;
}

FunctionPass *llvm::createSIFoldOperandsPass() {
return new SIFoldOperands();
FunctionPass *llvm::createSIFoldOperandsLegacyPass() {
return new SIFoldOperandsLegacy();
}

bool SIFoldOperands::canUseImmWithOpSel(FoldCandidate &Fold) const {
bool SIFoldOperandsImpl::canUseImmWithOpSel(FoldCandidate &Fold) const {
MachineInstr *MI = Fold.UseMI;
MachineOperand &Old = MI->getOperand(Fold.UseOpNo);
const uint64_t TSFlags = MI->getDesc().TSFlags;
Expand Down Expand Up @@ -230,7 +241,7 @@ bool SIFoldOperands::canUseImmWithOpSel(FoldCandidate &Fold) const {
return true;
}

bool SIFoldOperands::tryFoldImmWithOpSel(FoldCandidate &Fold) const {
bool SIFoldOperandsImpl::tryFoldImmWithOpSel(FoldCandidate &Fold) const {
MachineInstr *MI = Fold.UseMI;
MachineOperand &Old = MI->getOperand(Fold.UseOpNo);
unsigned Opcode = MI->getOpcode();
Expand Down Expand Up @@ -354,7 +365,7 @@ bool SIFoldOperands::tryFoldImmWithOpSel(FoldCandidate &Fold) const {
return false;
}

bool SIFoldOperands::updateOperand(FoldCandidate &Fold) const {
bool SIFoldOperandsImpl::updateOperand(FoldCandidate &Fold) const {
MachineInstr *MI = Fold.UseMI;
MachineOperand &Old = MI->getOperand(Fold.UseOpNo);
assert(Old.isReg());
Expand Down Expand Up @@ -464,9 +475,9 @@ static void appendFoldCandidate(SmallVectorImpl<FoldCandidate> &FoldList,
FoldList.emplace_back(MI, OpNo, FoldOp, Commuted, ShrinkOp);
}

bool SIFoldOperands::tryAddToFoldList(SmallVectorImpl<FoldCandidate> &FoldList,
MachineInstr *MI, unsigned OpNo,
MachineOperand *OpToFold) const {
bool SIFoldOperandsImpl::tryAddToFoldList(
SmallVectorImpl<FoldCandidate> &FoldList, MachineInstr *MI, unsigned OpNo,
MachineOperand *OpToFold) const {
const unsigned Opc = MI->getOpcode();

auto tryToFoldAsFMAAKorMK = [&]() {
Expand Down Expand Up @@ -645,16 +656,16 @@ bool SIFoldOperands::tryAddToFoldList(SmallVectorImpl<FoldCandidate> &FoldList,
return true;
}

bool SIFoldOperands::isUseSafeToFold(const MachineInstr &MI,
const MachineOperand &UseMO) const {
bool SIFoldOperandsImpl::isUseSafeToFold(const MachineInstr &MI,
const MachineOperand &UseMO) const {
// Operands of SDWA instructions must be registers.
return !TII->isSDWA(MI);
}

// Find a def of the UseReg, check if it is a reg_sequence and find initializers
// for each subreg, tracking it to foldable inline immediate if possible.
// Returns true on success.
bool SIFoldOperands::getRegSeqInit(
bool SIFoldOperandsImpl::getRegSeqInit(
SmallVectorImpl<std::pair<MachineOperand *, unsigned>> &Defs,
Register UseReg, uint8_t OpTy) const {
MachineInstr *Def = MRI->getVRegDef(UseReg);
Expand Down Expand Up @@ -686,7 +697,7 @@ bool SIFoldOperands::getRegSeqInit(
return true;
}

bool SIFoldOperands::tryToFoldACImm(
bool SIFoldOperandsImpl::tryToFoldACImm(
const MachineOperand &OpToFold, MachineInstr *UseMI, unsigned UseOpIdx,
SmallVectorImpl<FoldCandidate> &FoldList) const {
const MCInstrDesc &Desc = UseMI->getDesc();
Expand Down Expand Up @@ -752,12 +763,10 @@ bool SIFoldOperands::tryToFoldACImm(
return true;
}

void SIFoldOperands::foldOperand(
MachineOperand &OpToFold,
MachineInstr *UseMI,
int UseOpIdx,
SmallVectorImpl<FoldCandidate> &FoldList,
SmallVectorImpl<MachineInstr *> &CopiesToReplace) const {
void SIFoldOperandsImpl::foldOperand(
MachineOperand &OpToFold, MachineInstr *UseMI, int UseOpIdx,
SmallVectorImpl<FoldCandidate> &FoldList,
SmallVectorImpl<MachineInstr *> &CopiesToReplace) const {
const MachineOperand *UseOp = &UseMI->getOperand(UseOpIdx);

if (!isUseSafeToFold(*UseMI, *UseOp))
Expand Down Expand Up @@ -1187,7 +1196,7 @@ static void mutateCopyOp(MachineInstr &MI, const MCInstrDesc &NewDesc) {
}

MachineOperand *
SIFoldOperands::getImmOrMaterializedImm(MachineOperand &Op) const {
SIFoldOperandsImpl::getImmOrMaterializedImm(MachineOperand &Op) const {
// If this has a subregister, it obviously is a register source.
if (!Op.isReg() || Op.getSubReg() != AMDGPU::NoSubRegister ||
!Op.getReg().isVirtual())
Expand All @@ -1206,7 +1215,7 @@ SIFoldOperands::getImmOrMaterializedImm(MachineOperand &Op) const {
// Try to simplify operations with a constant that may appear after instruction
// selection.
// TODO: See if a frame index with a fixed offset can fold.
bool SIFoldOperands::tryConstantFoldOp(MachineInstr *MI) const {
bool SIFoldOperandsImpl::tryConstantFoldOp(MachineInstr *MI) const {
if (!MI->allImplicitDefsAreDead())
return false;

Expand Down Expand Up @@ -1307,7 +1316,7 @@ bool SIFoldOperands::tryConstantFoldOp(MachineInstr *MI) const {
}

// Try to fold an instruction into a simpler one
bool SIFoldOperands::tryFoldCndMask(MachineInstr &MI) const {
bool SIFoldOperandsImpl::tryFoldCndMask(MachineInstr &MI) const {
unsigned Opc = MI.getOpcode();
if (Opc != AMDGPU::V_CNDMASK_B32_e32 && Opc != AMDGPU::V_CNDMASK_B32_e64 &&
Opc != AMDGPU::V_CNDMASK_B64_PSEUDO)
Expand Down Expand Up @@ -1346,7 +1355,7 @@ bool SIFoldOperands::tryFoldCndMask(MachineInstr &MI) const {
return true;
}

bool SIFoldOperands::tryFoldZeroHighBits(MachineInstr &MI) const {
bool SIFoldOperandsImpl::tryFoldZeroHighBits(MachineInstr &MI) const {
if (MI.getOpcode() != AMDGPU::V_AND_B32_e64 &&
MI.getOpcode() != AMDGPU::V_AND_B32_e32)
return false;
Expand All @@ -1368,8 +1377,8 @@ bool SIFoldOperands::tryFoldZeroHighBits(MachineInstr &MI) const {
return true;
}

bool SIFoldOperands::foldInstOperand(MachineInstr &MI,
MachineOperand &OpToFold) const {
bool SIFoldOperandsImpl::foldInstOperand(MachineInstr &MI,
MachineOperand &OpToFold) const {
// We need mutate the operands of new mov instructions to add implicit
// uses of EXEC, but adding them invalidates the use_iterator, so defer
// this.
Expand Down Expand Up @@ -1442,7 +1451,7 @@ bool SIFoldOperands::foldInstOperand(MachineInstr &MI,
return true;
}

bool SIFoldOperands::tryFoldFoldableCopy(
bool SIFoldOperandsImpl::tryFoldFoldableCopy(
MachineInstr &MI, MachineOperand *&CurrentKnownM0Val) const {
// Specially track simple redefs of m0 to the same value in a block, so we
// can erase the later ones.
Expand Down Expand Up @@ -1519,7 +1528,8 @@ bool SIFoldOperands::tryFoldFoldableCopy(

// Clamp patterns are canonically selected to v_max_* instructions, so only
// handle them.
const MachineOperand *SIFoldOperands::isClamp(const MachineInstr &MI) const {
const MachineOperand *
SIFoldOperandsImpl::isClamp(const MachineInstr &MI) const {
unsigned Op = MI.getOpcode();
switch (Op) {
case AMDGPU::V_MAX_F32_e64:
Expand Down Expand Up @@ -1567,7 +1577,7 @@ const MachineOperand *SIFoldOperands::isClamp(const MachineInstr &MI) const {
}

// FIXME: Clamp for v_mad_mixhi_f16 handled during isel.
bool SIFoldOperands::tryFoldClamp(MachineInstr &MI) {
bool SIFoldOperandsImpl::tryFoldClamp(MachineInstr &MI) {
const MachineOperand *ClampSrc = isClamp(MI);
if (!ClampSrc || !MRI->hasOneNonDBGUser(ClampSrc->getReg()))
return false;
Expand Down Expand Up @@ -1662,7 +1672,7 @@ static int getOModValue(unsigned Opc, int64_t Val) {
// FIXME: Does this need to check IEEE mode bit? SNaNs are generally not
// handled, so will anything other than that break?
std::pair<const MachineOperand *, int>
SIFoldOperands::isOMod(const MachineInstr &MI) const {
SIFoldOperandsImpl::isOMod(const MachineInstr &MI) const {
unsigned Op = MI.getOpcode();
switch (Op) {
case AMDGPU::V_MUL_F64_e64:
Expand Down Expand Up @@ -1740,7 +1750,7 @@ SIFoldOperands::isOMod(const MachineInstr &MI) const {
}

// FIXME: Does this need to check IEEE bit on function?
bool SIFoldOperands::tryFoldOMod(MachineInstr &MI) {
bool SIFoldOperandsImpl::tryFoldOMod(MachineInstr &MI) {
const MachineOperand *RegOp;
int OMod;
std::tie(RegOp, OMod) = isOMod(MI);
Expand Down Expand Up @@ -1779,7 +1789,7 @@ bool SIFoldOperands::tryFoldOMod(MachineInstr &MI) {

// Try to fold a reg_sequence with vgpr output and agpr inputs into an
// instruction which can take an agpr. So far that means a store.
bool SIFoldOperands::tryFoldRegSequence(MachineInstr &MI) {
bool SIFoldOperandsImpl::tryFoldRegSequence(MachineInstr &MI) {
assert(MI.isRegSequence());
auto Reg = MI.getOperand(0).getReg();

Expand Down Expand Up @@ -1926,7 +1936,7 @@ static bool isAGPRCopy(const SIRegisterInfo &TRI,
// loop:
// %3:areg = PHI %2:areg, %entry, %X:areg,
// %4:areg = (instr using %3:areg)
bool SIFoldOperands::tryFoldPhiAGPR(MachineInstr &PHI) {
bool SIFoldOperandsImpl::tryFoldPhiAGPR(MachineInstr &PHI) {
assert(PHI.isPHI());

Register PhiOut = PHI.getOperand(0).getReg();
Expand Down Expand Up @@ -2030,7 +2040,7 @@ bool SIFoldOperands::tryFoldPhiAGPR(MachineInstr &PHI) {
}

// Attempt to convert VGPR load to an AGPR load.
bool SIFoldOperands::tryFoldLoad(MachineInstr &MI) {
bool SIFoldOperandsImpl::tryFoldLoad(MachineInstr &MI) {
assert(MI.mayLoad());
if (!ST->hasGFX90AInsts() || MI.getNumExplicitDefs() != 1)
return false;
Expand Down Expand Up @@ -2117,7 +2127,7 @@ bool SIFoldOperands::tryFoldLoad(MachineInstr &MI) {
// %0:areg = PHI %tmp_agpr, %a, %x, %c
// %1:areg = PHI %tmp_agpr, %a, %y, %c
// %2:areg = PHI %tmp_agpr, %a, %z, %c
bool SIFoldOperands::tryOptimizeAGPRPhis(MachineBasicBlock &MBB) {
bool SIFoldOperandsImpl::tryOptimizeAGPRPhis(MachineBasicBlock &MBB) {
// This is only really needed on GFX908 where AGPR-AGPR copies are
// unreasonably difficult.
if (ST->hasGFX90AInsts())
Expand Down Expand Up @@ -2182,10 +2192,7 @@ bool SIFoldOperands::tryOptimizeAGPRPhis(MachineBasicBlock &MBB) {
return Changed;
}

bool SIFoldOperands::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(MF.getFunction()))
return false;

bool SIFoldOperandsImpl::run(MachineFunction &MF) {
MRI = &MF.getRegInfo();
ST = &MF.getSubtarget<GCNSubtarget>();
TII = ST->getInstrInfo();
Expand Down Expand Up @@ -2246,3 +2253,14 @@ bool SIFoldOperands::runOnMachineFunction(MachineFunction &MF) {

return Changed;
}

PreservedAnalyses SIFoldOperandsPass::run(MachineFunction &MF,
MachineFunctionAnalysisManager &) {
bool Changed = SIFoldOperandsImpl().run(MF);
if (!Changed) {
return PreservedAnalyses::all();
}
auto PA = getMachineFunctionPassPreservedAnalyses();
PA.preserveSet<CFGAnalyses>();
return PA;
}
23 changes: 23 additions & 0 deletions llvm/lib/Target/AMDGPU/SIFoldOperands.h
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Original file line number Diff line number Diff line change
@@ -0,0 +1,23 @@
//===- SIFoldOperands.h -----------------------------------------*- C++- *-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//

#ifndef LLVM_LIB_TARGET_AMDGPU_SIFOLDOPERANDS_H
#define LLVM_LIB_TARGET_AMDGPU_SIFOLDOPERANDS_H

#include "llvm/CodeGen/MachinePassManager.h"

namespace llvm {
class SIFoldOperandsPass : public PassInfoMixin<SIFoldOperandsPass> {
public:
SIFoldOperandsPass() = default;
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
};
} // namespace llvm

#endif // LLVM_LIB_TARGET_AMDGPU_SIFOLDOPERANDS_H
9 changes: 7 additions & 2 deletions llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -122,8 +122,13 @@ bool AVRDAGToDAGISel::SelectAddr(SDNode *Op, SDValue N, SDValue &Base,
// offset allowed.
MVT VT = cast<MemSDNode>(Op)->getMemoryVT().getSimpleVT();

// We only accept offsets that fit in 6 bits (unsigned).
if (isUInt<6>(RHSC) && (VT == MVT::i8 || VT == MVT::i16)) {
// We only accept offsets that fit in 6 bits (unsigned), with the exception
// of 16-bit loads - those can only go up to 62, because we desugar them
// into a pair of 8-bit loads like `ldd rx, RHSC` + `ldd ry, RHSC + 1`.
bool OkI8 = VT == MVT::i8 && RHSC <= 63;
bool OkI16 = VT == MVT::i16 && RHSC <= 62;

if (OkI8 || OkI16) {
Base = N.getOperand(0);
Disp = CurDAG->getTargetConstant(RHSC, dl, MVT::i8);

Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -172,7 +172,7 @@ void RISCVMCCodeEmitter::expandTLSDESCCall(const MCInst &MI,
const RISCVMCExpr *Expr = dyn_cast<RISCVMCExpr>(SrcSymbol.getExpr());
MCRegister Link = MI.getOperand(0).getReg();
MCRegister Dest = MI.getOperand(1).getReg();
MCRegister Imm = MI.getOperand(2).getImm();
int64_t Imm = MI.getOperand(2).getImm();
Fixups.push_back(MCFixup::create(
0, Expr, MCFixupKind(RISCV::fixup_riscv_tlsdesc_call), MI.getLoc()));
MCInst Call =
Expand Down
47 changes: 44 additions & 3 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -10328,6 +10328,50 @@ SDValue RISCVTargetLowering::lowerVECTOR_REVERSE(SDValue Op,
Vec = convertToScalableVector(ContainerVT, Vec, DAG, Subtarget);
}

MVT XLenVT = Subtarget.getXLenVT();
auto [Mask, VL] = getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget);

// On some uarchs vrgather.vv will read from every input register for each
// output register, regardless of the indices. However to reverse a vector
// each output register only needs to read from one register. So decompose it
// into LMUL * M1 vrgather.vvs, so we get O(LMUL) performance instead of
// O(LMUL^2).
//
// vsetvli a1, zero, e64, m4, ta, ma
// vrgatherei16.vv v12, v8, v16
// ->
// vsetvli a1, zero, e64, m1, ta, ma
// vrgather.vv v15, v8, v16
// vrgather.vv v14, v9, v16
// vrgather.vv v13, v10, v16
// vrgather.vv v12, v11, v16
if (ContainerVT.bitsGT(getLMUL1VT(ContainerVT)) &&
ContainerVT.getVectorElementCount().isKnownMultipleOf(2)) {
auto [Lo, Hi] = DAG.SplitVector(Vec, DL);
Lo = DAG.getNode(ISD::VECTOR_REVERSE, DL, Lo.getSimpleValueType(), Lo);
Hi = DAG.getNode(ISD::VECTOR_REVERSE, DL, Hi.getSimpleValueType(), Hi);
SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, DL, ContainerVT, Hi, Lo);

// Fixed length vectors might not fit exactly into their container, and so
// leave a gap in the front of the vector after being reversed. Slide this
// away.
//
// x x x x 3 2 1 0 <- v4i16 @ vlen=128
// 0 1 2 3 x x x x <- reverse
// x x x x 0 1 2 3 <- vslidedown.vx
if (VecVT.isFixedLengthVector()) {
SDValue Offset = DAG.getNode(
ISD::SUB, DL, XLenVT,
DAG.getElementCount(DL, XLenVT, ContainerVT.getVectorElementCount()),
DAG.getElementCount(DL, XLenVT, VecVT.getVectorElementCount()));
Concat =
getVSlidedown(DAG, Subtarget, DL, ContainerVT,
DAG.getUNDEF(ContainerVT), Concat, Offset, Mask, VL);
Concat = convertFromScalableVector(VecVT, Concat, DAG, Subtarget);
}
return Concat;
}

unsigned EltSize = ContainerVT.getScalarSizeInBits();
unsigned MinSize = ContainerVT.getSizeInBits().getKnownMinValue();
unsigned VectorBitsMax = Subtarget.getRealMaxVLen();
Expand Down Expand Up @@ -10375,9 +10419,6 @@ SDValue RISCVTargetLowering::lowerVECTOR_REVERSE(SDValue Op,
IntVT = IntVT.changeVectorElementType(MVT::i16);
}

MVT XLenVT = Subtarget.getXLenVT();
auto [Mask, VL] = getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget);

// Calculate VLMAX-1 for the desired SEW.
SDValue VLMinus1 = DAG.getNode(
ISD::SUB, DL, XLenVT,
Expand Down
2 changes: 2 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfoV.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1665,13 +1665,15 @@ defm VSLIDEUP_V : VSLD_IV_X_I<"vslideup", 0b001110, /*slidesUp=*/true>;
defm VSLIDE1UP_V : VSLD1_MV_X<"vslide1up", 0b001110>;
} // Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp
defm VSLIDEDOWN_V : VSLD_IV_X_I<"vslidedown", 0b001111, /*slidesUp=*/false>;
let ActiveElementsAffectResult = 1 in
defm VSLIDE1DOWN_V : VSLD1_MV_X<"vslide1down", 0b001111>;
} // Predicates = [HasVInstructions]

let Predicates = [HasVInstructionsAnyF] in {
let Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp in {
defm VFSLIDE1UP_V : VSLD1_FV_F<"vfslide1up", 0b001110>;
} // Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp
let ActiveElementsAffectResult = 1 in
defm VFSLIDE1DOWN_V : VSLD1_FV_F<"vfslide1down", 0b001111>;
} // Predicates = [HasVInstructionsAnyF]

Expand Down
26 changes: 15 additions & 11 deletions llvm/lib/Transforms/Utils/SCCPSolver.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -820,19 +820,21 @@ class SCCPInstVisitor : public InstVisitor<SCCPInstVisitor> {
markOverdefined(ValueState[V], V);
}

void trackValueOfArgument(Argument *A) {
ValueLatticeElement getArgAttributeVL(Argument *A) {
if (A->getType()->isIntOrIntVectorTy()) {
if (std::optional<ConstantRange> Range = A->getRange()) {
markConstantRange(ValueState[A], A, *Range);
return;
}
}
if (A->hasNonNullAttr()) {
markNotNull(ValueState[A], A);
return;
if (std::optional<ConstantRange> Range = A->getRange())
return ValueLatticeElement::getRange(*Range);
}
if (A->hasNonNullAttr())
return ValueLatticeElement::getNot(Constant::getNullValue(A->getType()));
// Assume nothing about the incoming arguments without attributes.
markOverdefined(A);
return ValueLatticeElement::getOverdefined();
}

void trackValueOfArgument(Argument *A) {
if (A->getType()->isStructTy())
return (void)markOverdefined(A);
mergeInValue(A, getArgAttributeVL(A));
}

bool isStructLatticeConstant(Function *F, StructType *STy);
Expand Down Expand Up @@ -1800,7 +1802,9 @@ void SCCPInstVisitor::handleCallArguments(CallBase &CB) {
getMaxWidenStepsOpts());
}
} else
mergeInValue(&*AI, getValueState(*CAI), getMaxWidenStepsOpts());
mergeInValue(&*AI,
getValueState(*CAI).intersect(getArgAttributeVL(&*AI)),
getMaxWidenStepsOpts());
}
}
}
Expand Down
115 changes: 0 additions & 115 deletions llvm/test/CodeGen/AArch64/atomicrmw-fadd-fp-vector.ll
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