diff --git a/llvm/lib/Target/Mips/MipsMachineFunction.cpp b/llvm/lib/Target/Mips/MipsMachineFunction.cpp
@@ -22,6 +22,13 @@ static cl::opt<bool>
 FixGlobalBaseReg("mips-fix-global-base-reg", cl::Hidden, cl::init(true),
                  cl::desc("Always use $gp as the global base register."));
 
+MachineFunctionInfo *
+MipsFunctionInfo::clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+                        const DenseMap<MachineBasicBlock *, MachineBasicBlock *>
+                            &Src2DstMBB) const {
+  return DestMF.cloneInfo<MipsFunctionInfo>(*this);
+}
+
 MipsFunctionInfo::~MipsFunctionInfo() = default;
 
 bool MipsFunctionInfo::globalBaseRegSet() const {

diff --git a/llvm/lib/Target/Mips/MipsMachineFunction.h b/llvm/lib/Target/Mips/MipsMachineFunction.h
@@ -26,6 +26,11 @@ class MipsFunctionInfo : public MachineFunctionInfo {
 public:
   MipsFunctionInfo(MachineFunction &MF) {}
 
+  MachineFunctionInfo *
+  clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+        const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+      const override;
+
   ~MipsFunctionInfo() override;
 
   unsigned getSRetReturnReg() const { return SRetReturnReg; }

diff --git a/llvm/lib/Target/NVPTX/NVPTXMachineFunctionInfo.h b/llvm/lib/Target/NVPTX/NVPTXMachineFunctionInfo.h
@@ -26,6 +26,13 @@ class NVPTXMachineFunctionInfo : public MachineFunctionInfo {
 public:
   NVPTXMachineFunctionInfo(MachineFunction &MF) {}
 
+  MachineFunctionInfo *
+  clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+        const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+      const override {
+    return DestMF.cloneInfo<NVPTXMachineFunctionInfo>(*this);
+  }
+
   /// Returns the index for the symbol \p Symbol. If the symbol was previously,
   /// added, the same index is returned. Otherwise, the symbol is added and the
   /// new index is returned.

diff --git a/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp b/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp
@@ -23,6 +23,13 @@ void PPCFunctionInfo::anchor() {}
 PPCFunctionInfo::PPCFunctionInfo(const MachineFunction &MF)
     : DisableNonVolatileCR(PPCDisableNonVolatileCR) {}
 
+MachineFunctionInfo *
+PPCFunctionInfo::clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+                       const DenseMap<MachineBasicBlock *, MachineBasicBlock *>
+                           &Src2DstMBB) const {
+  return DestMF.cloneInfo<PPCFunctionInfo>(*this);
+}
+
 MCSymbol *PPCFunctionInfo::getPICOffsetSymbol(MachineFunction &MF) const {
   const DataLayout &DL = MF.getDataLayout();
   return MF.getContext().getOrCreateSymbol(Twine(DL.getPrivateGlobalPrefix()) +

diff --git a/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h b/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h
@@ -153,6 +153,11 @@ class PPCFunctionInfo : public MachineFunctionInfo {
 public:
   explicit PPCFunctionInfo(const MachineFunction &MF);
 
+  MachineFunctionInfo *
+  clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+        const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+      const override;
+
   int getFramePointerSaveIndex() const { return FramePointerSaveIndex; }
   void setFramePointerSaveIndex(int Idx) { FramePointerSaveIndex = Idx; }
 

diff --git a/llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.cpp b/llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.cpp
@@ -19,6 +19,13 @@ yaml::RISCVMachineFunctionInfo::RISCVMachineFunctionInfo(
     : VarArgsFrameIndex(MFI.getVarArgsFrameIndex()),
       VarArgsSaveSize(MFI.getVarArgsSaveSize()) {}
 
+MachineFunctionInfo *RISCVMachineFunctionInfo::clone(
+    BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+    const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+    const {
+  return DestMF.cloneInfo<RISCVMachineFunctionInfo>(*this);
+}
+
 void yaml::RISCVMachineFunctionInfo::mappingImpl(yaml::IO &YamlIO) {
   MappingTraits<RISCVMachineFunctionInfo>::mapping(YamlIO, *this);
 }

diff --git a/llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h b/llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
@@ -67,6 +67,11 @@ class RISCVMachineFunctionInfo : public MachineFunctionInfo {
 public:
   RISCVMachineFunctionInfo(const MachineFunction &MF) {}
 
+  MachineFunctionInfo *
+  clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+        const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+      const override;
+
   int getVarArgsFrameIndex() const { return VarArgsFrameIndex; }
   void setVarArgsFrameIndex(int Index) { VarArgsFrameIndex = Index; }
 

diff --git a/llvm/lib/Target/Sparc/SparcMachineFunctionInfo.cpp b/llvm/lib/Target/Sparc/SparcMachineFunctionInfo.cpp
@@ -11,3 +11,10 @@
 using namespace llvm;
 
 void SparcMachineFunctionInfo::anchor() { }
+
+MachineFunctionInfo *SparcMachineFunctionInfo::clone(
+    BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+    const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+    const {
+  return DestMF.cloneInfo<SparcMachineFunctionInfo>(*this);
+}
diff --git a/llvm/lib/Target/Sparc/SparcMachineFunctionInfo.h b/llvm/lib/Target/Sparc/SparcMachineFunctionInfo.h
@@ -38,6 +38,11 @@ namespace llvm {
       : GlobalBaseReg(0), VarArgsFrameOffset(0), SRetReturnReg(0),
         IsLeafProc(false) {}
 
+    MachineFunctionInfo *
+    clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+          const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+        const override;
+
     Register getGlobalBaseReg() const { return GlobalBaseReg; }
     void setGlobalBaseReg(Register Reg) { GlobalBaseReg = Reg; }
 

diff --git a/llvm/lib/Target/SystemZ/SystemZMachineFunctionInfo.cpp b/llvm/lib/Target/SystemZ/SystemZMachineFunctionInfo.cpp
@@ -14,3 +14,9 @@ using namespace llvm;
 // pin vtable to this file
 void SystemZMachineFunctionInfo::anchor() {}
 
+MachineFunctionInfo *SystemZMachineFunctionInfo::clone(
+    BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+    const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+    const {
+  return DestMF.cloneInfo<SystemZMachineFunctionInfo>(*this);
+}
diff --git a/llvm/lib/Target/SystemZ/SystemZMachineFunctionInfo.h b/llvm/lib/Target/SystemZ/SystemZMachineFunctionInfo.h
@@ -41,6 +41,11 @@ class SystemZMachineFunctionInfo : public MachineFunctionInfo {
     : VarArgsFirstGPR(0), VarArgsFirstFPR(0), VarArgsFrameIndex(0),
       RegSaveFrameIndex(0), FramePointerSaveIndex(0), NumLocalDynamics(0) {}
 
+  MachineFunctionInfo *
+  clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+        const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+      const override;
+
   // Get and set the first and last call-saved GPR that should be saved by
   // this function and the SP offset for the STMG.  These are 0 if no GPRs
   // need to be saved or restored.

diff --git a/llvm/lib/Target/VE/VEMachineFunctionInfo.cpp b/llvm/lib/Target/VE/VEMachineFunctionInfo.cpp
@@ -11,3 +11,10 @@
 using namespace llvm;
 
 void VEMachineFunctionInfo::anchor() {}
+
+MachineFunctionInfo *VEMachineFunctionInfo::clone(
+    BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+    const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+    const {
+  return DestMF.cloneInfo<VEMachineFunctionInfo>(*this);
+}
diff --git a/llvm/lib/Target/VE/VEMachineFunctionInfo.h b/llvm/lib/Target/VE/VEMachineFunctionInfo.h
@@ -33,6 +33,11 @@ class VEMachineFunctionInfo : public MachineFunctionInfo {
   explicit VEMachineFunctionInfo(MachineFunction &MF)
       : VarArgsFrameOffset(0), IsLeafProc(false) {}
 
+  MachineFunctionInfo *
+  clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+        const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+      const override;
+
   Register getGlobalBaseReg() const { return GlobalBaseReg; }
   void setGlobalBaseReg(Register Reg) { GlobalBaseReg = Reg; }
 

diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.cpp
@@ -24,6 +24,16 @@ using namespace llvm;
 
 WebAssemblyFunctionInfo::~WebAssemblyFunctionInfo() = default; // anchor.
 
+MachineFunctionInfo *WebAssemblyFunctionInfo::clone(
+    BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+    const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+    const {
+  WebAssemblyFunctionInfo *Clone =
+      DestMF.cloneInfo<WebAssemblyFunctionInfo>(*this);
+  Clone->MF = &DestMF;
+  return Clone;
+}
+
 void WebAssemblyFunctionInfo::initWARegs(MachineRegisterInfo &MRI) {
   assert(WARegs.empty());
   unsigned Reg = UnusedReg;
@@ -153,7 +163,7 @@ void WebAssemblyFunctionInfo::initializeBaseYamlFields(
     addResult(WebAssembly::parseMVT(VT.Value));
   if (WasmEHInfo) {
     for (auto KV : YamlMFI.SrcToUnwindDest)
-      WasmEHInfo->setUnwindDest(MF.getBlockNumbered(KV.first),
-                                MF.getBlockNumbered(KV.second));
+      WasmEHInfo->setUnwindDest(MF->getBlockNumbered(KV.first),
+                                MF->getBlockNumbered(KV.second));
   }
 }
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h b/llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h
@@ -31,7 +31,7 @@ struct WebAssemblyFunctionInfo;
 /// This class is derived from MachineFunctionInfo and contains private
 /// WebAssembly-specific information for each MachineFunction.
 class WebAssemblyFunctionInfo final : public MachineFunctionInfo {
-  const MachineFunction &MF;
+  const MachineFunction *MF;
 
   std::vector<MVT> Params;
   std::vector<MVT> Results;
@@ -70,11 +70,16 @@ class WebAssemblyFunctionInfo final : public MachineFunctionInfo {
   WasmEHFuncInfo *WasmEHInfo = nullptr;
 
 public:
-  explicit WebAssemblyFunctionInfo(MachineFunction &MF)
-      : MF(MF), WasmEHInfo(MF.getWasmEHFuncInfo()) {}
+  explicit WebAssemblyFunctionInfo(MachineFunction &MF_)
+      : MF(&MF_), WasmEHInfo(MF_.getWasmEHFuncInfo()) {}
   ~WebAssemblyFunctionInfo() override;
 
-  const MachineFunction &getMachineFunction() const { return MF; }
+  MachineFunctionInfo *
+  clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+        const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+      const override;
+
+  const MachineFunction &getMachineFunction() const { return *MF; }
 
   void initializeBaseYamlFields(const yaml::WebAssemblyFunctionInfo &YamlMFI);
 

diff --git a/llvm/lib/Target/X86/X86MachineFunctionInfo.cpp b/llvm/lib/Target/X86/X86MachineFunctionInfo.cpp
@@ -13,6 +13,13 @@
 
 using namespace llvm;
 
+MachineFunctionInfo *X86MachineFunctionInfo::clone(
+    BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+    const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+    const {
+  return DestMF.cloneInfo<X86MachineFunctionInfo>(*this);
+}
+
 void X86MachineFunctionInfo::anchor() { }
 
 void X86MachineFunctionInfo::setRestoreBasePointer(const MachineFunction *MF) {

diff --git a/llvm/lib/Target/X86/X86MachineFunctionInfo.h b/llvm/lib/Target/X86/X86MachineFunctionInfo.h
@@ -134,6 +134,12 @@ class X86MachineFunctionInfo : public MachineFunctionInfo {
   X86MachineFunctionInfo() = default;
 
   explicit X86MachineFunctionInfo(MachineFunction &MF) {}
+  explicit X86MachineFunctionInfo(const X86MachineFunctionInfo &) = default;
+
+  MachineFunctionInfo *
+  clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+        const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+      const override;
 
   bool getForceFramePointer() const { return ForceFramePointer;}
   void setForceFramePointer(bool forceFP) { ForceFramePointer = forceFP; }

diff --git a/llvm/lib/Target/XCore/XCoreMachineFunctionInfo.cpp b/llvm/lib/Target/XCore/XCoreMachineFunctionInfo.cpp
@@ -15,6 +15,13 @@ using namespace llvm;
 
 void XCoreFunctionInfo::anchor() { }
 
+MachineFunctionInfo *XCoreFunctionInfo::clone(
+    BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+    const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+    const {
+  return DestMF.cloneInfo<XCoreFunctionInfo>(*this);
+}
+
 bool XCoreFunctionInfo::isLargeFrame(const MachineFunction &MF) const {
   if (CachedEStackSize == -1) {
     CachedEStackSize = MF.getFrameInfo().estimateStackSize(MF);

diff --git a/llvm/lib/Target/XCore/XCoreMachineFunctionInfo.h b/llvm/lib/Target/XCore/XCoreMachineFunctionInfo.h
@@ -45,6 +45,11 @@ class XCoreFunctionInfo : public MachineFunctionInfo {
 
   explicit XCoreFunctionInfo(MachineFunction &MF) {}
 
+  MachineFunctionInfo *
+  clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+        const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+      const override;
+
   ~XCoreFunctionInfo() override = default;
 
   void setVarArgsFrameIndex(int off) { VarArgsFrameIndex = off; }

diff --git a/llvm/test/tools/llvm-reduce/mir/preserve-machine-function-info-amdgpu.mir b/llvm/test/tools/llvm-reduce/mir/preserve-machine-function-info-amdgpu.mir
@@ -0,0 +1,125 @@
+# REQUIRES: amdgpu-registered-target
+# RUN: llvm-reduce -simplify-mir -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
+# RUN: FileCheck --check-prefix=RESULT %s < %t
+
+# CHECK-INTERESTINGNESS-COUNT-6: S_NOP
+
+# RESULT: name: func
+
+--- |
+  define void @func() {
+    ret void
+  }
+
+...
+
+# RESULT: machineFunctionInfo:
+# RESULT-NEXT: explicitKernArgSize: 108
+# RESULT-NEXT: maxKernArgAlign: 32
+# RESULT-NEXT: ldsSize:         256
+# RESULT-NEXT: gdsSize:         128
+# RESULT-NEXT: dynLDSAlign:     16
+# RESULT-NEXT: isEntryFunction: true
+# RESULT-NEXT: noSignedZerosFPMath: true
+# RESULT-NEXT: memoryBound:     true
+# RESULT-NEXT: waveLimiter:     true
+# RESULT-NEXT: hasSpilledSGPRs: true
+# RESULT-NEXT: hasSpilledVGPRs: true
+# RESULT-NEXT: scratchRSrcReg:  '$sgpr48_sgpr49_sgpr50_sgpr51'
+# RESULT-NEXT: frameOffsetReg:  '$sgpr44'
+# RESULT-NEXT: stackPtrOffsetReg: '$sgpr45'
+# RESULT-NEXT: bytesInStackArgArea: 112
+# RESULT-NEXT: returnsVoid:     false
+# RESULT-NEXT: argumentInfo:
+# RESULT-NEXT: privateSegmentBuffer: { reg: '$sgpr60_sgpr61_sgpr62_sgpr63' }
+# RESULT-NEXT: dispatchPtr:     { reg: '$sgpr6_sgpr7' }
+# RESULT-NEXT: queuePtr:        { reg: '$sgpr4_sgpr5' }
+# RESULT-NEXT: dispatchID:      { reg: '$sgpr12_sgpr13' }
+# RESULT-NEXT: workGroupIDX:    { reg: '$sgpr20' }
+# RESULT-NEXT: workGroupIDY:    { reg: '$sgpr19' }
+# RESULT-NEXT: workGroupIDZ:    { reg: '$sgpr18' }
+# RESULT-NEXT: implicitArgPtr:  { reg: '$sgpr10_sgpr11' }
+# RESULT-NEXT: workItemIDX:     { reg: '$vgpr34', mask: 1023 }
+# RESULT-NEXT: workItemIDY:     { reg: '$vgpr34', mask: 1047552 }
+# RESULT-NEXT: workItemIDZ:     { reg: '$vgpr34', mask: 1072693248 }
+# RESULT-NEXT: mode:
+# RESULT-NEXT: ieee:            false
+# RESULT-NEXT: dx10-clamp:      false
+# RESULT-NEXT: fp32-input-denormals: false
+# RESULT-NEXT: fp32-output-denormals: false
+# RESULT-NEXT: fp64-fp16-input-denormals: false
+# RESULT-NEXT: fp64-fp16-output-denormals: false
+# RESULT-NEXT: highBitsOf32BitAddress: 4276993775
+# RESULT-NEXT: occupancy:       8
+# RESULT-NEXT: wwmReservedRegs:
+# RESULT-NEXT: - '$vgpr2'
+# RESULT-NEXT: - '$vgpr3'
+# RESULT-NEXT: vgprForAGPRCopy: '$vgpr33'
+
+# RESULT: S_NOP 0, implicit $sgpr48_sgpr49_sgpr50_sgpr51
+# RESULT: S_NOP 0, implicit $vgpr33
+# RESULT: S_NOP 0, implicit $sgpr44
+# RESULT: S_NOP 0, implicit $sgpr45
+# RESULT: S_NOP 0, implicit $vgpr2
+# RESULT: S_NOP 0, implicit $vgpr3
+
+---
+name: func
+tracksRegLiveness: true
+machineFunctionInfo:
+  explicitKernArgSize: 108
+  maxKernArgAlign: 32
+  ldsSize:         256
+  gdsSize:         128
+  dynLDSAlign:     16
+  isEntryFunction: true
+  noSignedZerosFPMath: true
+  memoryBound:     true
+  waveLimiter:     true
+  hasSpilledSGPRs: true
+  hasSpilledVGPRs: true
+  scratchRSrcReg:  '$sgpr48_sgpr49_sgpr50_sgpr51'
+  frameOffsetReg:  '$sgpr44'
+  stackPtrOffsetReg: '$sgpr45'
+  bytesInStackArgArea: 112
+  returnsVoid:     false
+  argumentInfo:
+    privateSegmentBuffer: { reg: '$sgpr60_sgpr61_sgpr62_sgpr63' }
+    dispatchPtr:     { reg: '$sgpr6_sgpr7' }
+    queuePtr:        { reg: '$sgpr4_sgpr5' }
+    dispatchID:      { reg: '$sgpr12_sgpr13' }
+    workGroupIDX:    { reg: '$sgpr20' }
+    workGroupIDY:    { reg: '$sgpr19' }
+    workGroupIDZ:    { reg: '$sgpr18' }
+    implicitArgPtr:  { reg: '$sgpr10_sgpr11' }
+    workItemIDX:     { reg: '$vgpr34', mask: 1023 }
+    workItemIDY:     { reg: '$vgpr34', mask: 1047552 }
+    workItemIDZ:     { reg: '$vgpr34', mask: 1072693248 }
+  mode:
+    ieee:            false
+    dx10-clamp:      false
+    fp32-input-denormals: false
+    fp32-output-denormals: false
+    fp64-fp16-input-denormals: false
+    fp64-fp16-output-denormals: false
+  highBitsOf32BitAddress: 0xfeedbeef
+  occupancy:       8
+  wwmReservedRegs:
+    - '$vgpr2'
+    - '$vgpr3'
+  vgprForAGPRCopy: '$vgpr33'
+body:             |
+  bb.0:
+    S_WAITCNT 0
+    %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+
+    ; Test some register uses that are undef unless the reserved
+    ; registers are respected.
+    S_NOP 0, implicit $sgpr48_sgpr49_sgpr50_sgpr51
+    S_NOP 0, implicit $vgpr33
+    S_NOP 0, implicit $sgpr44
+    S_NOP 0, implicit $sgpr45
+    S_NOP 0, implicit $vgpr2
+    S_NOP 0, implicit $vgpr3
+    S_ENDPGM 0, implicit %0
+...
diff --git a/llvm/test/tools/llvm-reduce/mir/preserve-machine-function-info-riscv.mir b/llvm/test/tools/llvm-reduce/mir/preserve-machine-function-info-riscv.mir
@@ -0,0 +1,42 @@
+# REQUIRES: riscv-registered-target
+# RUN: llvm-reduce -simplify-mir -mtriple=riscv64-- --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
+# RUN: FileCheck --check-prefix=RESULT %s < %t
+
+# CHECK-INTERESTINGNESS: ADDW
+
+# RESULT: name: func
+# RESULT: stack:
+# RESULT-NEXT: - { id: 0, offset: 16, size: 16, alignment: 8 }
+
+# RESULT: machineFunctionInfo:
+# RESULT-NEXT: varArgsFrameIndex: 4
+# RESULT-NEXT: varArgsSaveSize: 12
+
+# RESULT: $x10 = ADDW %stack.0, renamable $x10
+--- |
+  define i32 @func(i32 %arg) {
+    ret i32 undef
+  }
+
+...
+
+# Note the frame index value changes during printing/parsing, not the
+# clone.
+---
+name: func
+tracksRegLiveness: true
+machineFunctionInfo:
+  varArgsFrameIndex: 4
+  varArgsSaveSize: 12
+stack:
+  - { id: 4, offset: 16, size: 16, alignment: 8 }
+
+body:             |
+  bb.0:
+    liveins: $x10
+
+    renamable $x10 = ADDW %stack.4, renamable $x10
+    renamable $x10 = ADDIW killed renamable $x10, -4
+    PseudoRET implicit $x10
+
+...
diff --git a/llvm/tools/llvm-reduce/ReducerWorkItem.cpp b/llvm/tools/llvm-reduce/ReducerWorkItem.cpp
@@ -240,8 +240,6 @@ static std::unique_ptr<MachineFunction> cloneMF(MachineFunction *SrcMF,
   // Remap the debug info frame index references.
   DstMF->VariableDbgInfos = SrcMF->VariableDbgInfos;
 
-  // FIXME: Need to clone MachineFunctionInfo, which may also depend on frame
-  // index and block mapping.
   // Clone virtual registers
   for (unsigned I = 0, E = SrcMRI->getNumVirtRegs(); I != E; ++I) {
     Register Reg = Register::index2VirtReg(I);
@@ -345,6 +343,11 @@ static std::unique_ptr<MachineFunction> cloneMF(MachineFunction *SrcMF,
 
   DstMF->setDebugInstrNumberingCount(SrcMF->DebugInstrNumberingCount);
 
+  if (!DstMF->cloneInfoFrom(*SrcMF, Src2DstMBB))
+    report_fatal_error("target does not implement MachineFunctionInfo cloning");
+
+  DstMRI->freezeReservedRegs(*DstMF);
+
   DstMF->verify(nullptr, "", /*AbortOnError=*/true);
   return DstMF;
 }