6 changes: 3 additions & 3 deletions llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@ declare i32 @llvm.amdgcn.workgroup.id.x() #0
declare i32 @llvm.amdgcn.workgroup.id.y() #0
declare i32 @llvm.amdgcn.workgroup.id.z() #0

; ALL-LABEL {{^}}test_workgroup_id_x:
; ALL-LABEL: {{^}}test_workgroup_id_x:

; CO-V2: .amd_kernel_code_t
; CO-V2: user_sgpr_count = 6
Expand Down Expand Up @@ -40,7 +40,7 @@ define amdgpu_kernel void @test_workgroup_id_x(i32 addrspace(1)* %out) #1 {
ret void
}

; ALL-LABEL {{^}}test_workgroup_id_y:
; ALL-LABEL: {{^}}test_workgroup_id_y:
; CO-V2: user_sgpr_count = 6
; CO-V2: enable_sgpr_workgroup_id_x = 1
; CO-V2: enable_sgpr_workgroup_id_y = 1
Expand All @@ -67,7 +67,7 @@ define amdgpu_kernel void @test_workgroup_id_y(i32 addrspace(1)* %out) #1 {
ret void
}

; ALL-LABEL {{^}}test_workgroup_id_z:
; ALL-LABEL: {{^}}test_workgroup_id_z:
; CO-V2: user_sgpr_count = 6
; CO-V2: enable_sgpr_workgroup_id_x = 1
; CO-V2: enable_sgpr_workgroup_id_y = 0
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@ declare i32 @llvm.amdgcn.workitem.id.z() #0
; MESA: .long 47180
; MESA-NEXT: .long 132{{$}}

; ALL-LABEL {{^}}test_workitem_id_x:
; ALL-LABEL: {{^}}test_workitem_id_x:
; CO-V2: enable_vgpr_workitem_id = 0

; ALL-NOT: v0
Expand All @@ -28,7 +28,7 @@ define amdgpu_kernel void @test_workitem_id_x(i32 addrspace(1)* %out) #1 {
; MESA: .long 47180
; MESA-NEXT: .long 2180{{$}}

; ALL-LABEL {{^}}test_workitem_id_y:
; ALL-LABEL: {{^}}test_workitem_id_y:
; CO-V2: enable_vgpr_workitem_id = 1

; ALL-NOT: v1
Expand All @@ -43,7 +43,7 @@ define amdgpu_kernel void @test_workitem_id_y(i32 addrspace(1)* %out) #1 {
; MESA: .long 47180
; MESA-NEXT: .long 4228{{$}}

; ALL-LABEL {{^}}test_workitem_id_z:
; ALL-LABEL: {{^}}test_workitem_id_z:
; CO-V2: enable_vgpr_workitem_id = 2

; ALL-NOT: v2
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -95,14 +95,14 @@ define amdgpu_kernel void @fmuladd_f16_imm_a(

; VI-DENORM: s_movk_i32 [[KA:s[0-9]+]], 0x4200
; VI-DENORM: v_fma_f16 [[RESULT:v[0-9]+]], v[[A_F16]], [[KA]], v[[C_F16]]
; VI-DENORM buffer_store_short [[RESULT]]
; VI-DENORM: buffer_store_short [[RESULT]]

; GFX10-FLUSH: v_mul_f16_e32 [[MUL:v[0-9]+]], 0x4200, v[[A_F16]]
; GFX10-FLUSH: v_add_f16_e32 [[ADD:v[0-9]+]], [[MUL]], v[[C_F16]]
; GFX10-FLUSH: buffer_store_short [[ADD]]

; GFX10-DENORM: v_fmac_f16_e32 v[[C_F16]], 0x4200, v[[A_F16]]
; GFX10-DENORM buffer_store_short v[[C_F16]],
; GFX10-DENORM: buffer_store_short v[[C_F16]],

; GCN: s_endpgm
define amdgpu_kernel void @fmuladd_f16_imm_b(
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/llvm.rint.f64.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@

; SI-DAG: v_add_f64
; SI-DAG: v_add_f64
; SI-DAG v_cmp_gt_f64_e64
; SI-DAG: v_cmp_gt_f64_e64
; SI: v_cndmask_b32
; SI: v_cndmask_b32
; SI: s_endpgm
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/merge-m0.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -242,7 +242,7 @@ body: |
...

# GCN-LABEL: name: move-m0-with-prologue
# GCN $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
# GCN: $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
# GCN: $m0 = S_MOV_B32 -1
# GCN-NEXT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
# GCN-NEXT: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -28,7 +28,7 @@
# W64: {{[0-9]+}}:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN %4, killed [[SRSRC]], 0, 0, 0, 0, 0, 0, 0, implicit $exec
# W64: $exec = S_XOR_B64_term $exec, [[TMPEXEC]], implicit-def $scc
# W64: S_CBRANCH_EXECNZ %bb.1, implicit $exec
# W64-LABEL bb.2:
# W64-LABEL: bb.2:
# W64: $exec = S_MOV_B64 [[SAVEEXEC]]

# W32-LABEL: name: idxen
Expand All @@ -51,7 +51,7 @@
# TODO: S_XOR_B32_term should be `implicit-def $scc`
# W32: $exec_lo = S_XOR_B32_term $exec_lo, [[TMPEXEC]]
# W32: S_CBRANCH_EXECNZ %bb.1, implicit $exec
# W32-LABEL bb.2:
# W32-LABEL: bb.2:
# W32: $exec_lo = S_MOV_B32 [[SAVEEXEC]]
---
name: idxen
Expand Down Expand Up @@ -97,7 +97,7 @@ body: |
# W64: {{[0-9]+}}:vgpr_32 = BUFFER_LOAD_FORMAT_X_OFFEN %4, killed [[SRSRC]], 0, 0, 0, 0, 0, 0, 0, implicit $exec
# W64: $exec = S_XOR_B64_term $exec, [[TMPEXEC]], implicit-def $scc
# W64: S_CBRANCH_EXECNZ %bb.1, implicit $exec
# W64-LABEL bb.2:
# W64-LABEL: bb.2:
# W64: $exec = S_MOV_B64 [[SAVEEXEC]]

# W32-LABEL: name: offen
Expand All @@ -120,7 +120,7 @@ body: |
# TODO: S_XOR_B32_term should be `implicit-def $scc`
# W32: $exec_lo = S_XOR_B32_term $exec_lo, [[TMPEXEC]]
# W32: S_CBRANCH_EXECNZ %bb.1, implicit $exec
# W32-LABEL bb.2:
# W32-LABEL: bb.2:
# W32: $exec_lo = S_MOV_B32 [[SAVEEXEC]]
---
name: offen
Expand Down Expand Up @@ -166,7 +166,7 @@ body: |
# W64: {{[0-9]+}}:vgpr_32 = BUFFER_LOAD_FORMAT_X_BOTHEN %4, killed [[SRSRC]], 0, 0, 0, 0, 0, 0, 0, implicit $exec
# W64: $exec = S_XOR_B64_term $exec, [[TMPEXEC]], implicit-def $scc
# W64: S_CBRANCH_EXECNZ %bb.1, implicit $exec
# W64-LABEL bb.2:
# W64-LABEL: bb.2:
# W64: $exec = S_MOV_B64 [[SAVEEXEC]]

# W32-LABEL: name: bothen
Expand All @@ -189,7 +189,7 @@ body: |
# TODO: S_XOR_B32_term should be `implicit-def $scc`
# W32: $exec_lo = S_XOR_B32_term $exec_lo, [[TMPEXEC]]
# W32: S_CBRANCH_EXECNZ %bb.1, implicit $exec
# W32-LABEL bb.2:
# W32-LABEL: bb.2:
# W32: $exec_lo = S_MOV_B32 [[SAVEEXEC]]
---
name: bothen
Expand Down Expand Up @@ -272,7 +272,7 @@ body: |
# W64-NO-ADDR64: {{[0-9]+}}:vgpr_32 = BUFFER_LOAD_FORMAT_X_OFFSET killed [[SRSRC]], 0, 0, 0, 0, 0, 0, 0, implicit $exec
# W64-NO-ADDR64: $exec = S_XOR_B64_term $exec, [[TMPEXEC]], implicit-def $scc
# W64-NO-ADDR64: S_CBRANCH_EXECNZ %bb.1, implicit $exec
# W64-NO-ADDR64-LABEL bb.2:
# W64-NO-ADDR64-LABEL: bb.2:
# W64-NO-ADDR64: $exec = S_MOV_B64 [[SAVEEXEC]]

# W32: successors: %bb.1({{.*}})
Expand All @@ -293,7 +293,7 @@ body: |
# TODO: S_XOR_B32_term should be `implicit-def $scc`
# W32: $exec_lo = S_XOR_B32_term $exec_lo, [[TMPEXEC]]
# W32: S_CBRANCH_EXECNZ %bb.1, implicit $exec
# W32-LABEL bb.2:
# W32-LABEL: bb.2:
# W32: $exec_lo = S_MOV_B32 [[SAVEEXEC]]

# ADDR64: [[VRSRC:%[0-9]+]]:vreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AMDGPU/promote-alloca-no-opts.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@

; ALL-LABEL: {{^}}promote_alloca_i32_array_array:
; NOOPTS: workgroup_group_segment_byte_size = 0{{$}}
; NOOPTS-NOT ds_write
; NOOPTS-NOT: ds_write
; OPTS: ds_write
define amdgpu_kernel void @promote_alloca_i32_array_array(i32 addrspace(1)* %out, i32 %index) #0 {
entry:
Expand All @@ -20,7 +20,7 @@ entry:

; ALL-LABEL: {{^}}optnone_promote_alloca_i32_array_array:
; ALL: workgroup_group_segment_byte_size = 0{{$}}
; ALL-NOT ds_write
; ALL-NOT: ds_write
define amdgpu_kernel void @optnone_promote_alloca_i32_array_array(i32 addrspace(1)* %out, i32 %index) #1 {
entry:
%alloca = alloca [2 x [2 x i32]], addrspace(5)
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/rewrite-out-arguments.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -325,7 +325,7 @@ define i32 @i32_one_out_arg_i32_1_use(i32* %val) #0 {
; CHECK-NEXT: %3 = call %unused_different_type @unused_different_type.body(i32* %0, float* undef)
; CHECK-NEXT: %4 = extractvalue %unused_different_type %3, 0
; CHECK-NEXT: store float %4, float* %1, align 4
; CHECK-NEXT ret void
; CHECK-NEXT: ret void
define void @unused_different_type(i32* %arg0, float* nocapture %arg1) #0 {
store float 4.0, float* %arg1, align 4
ret void
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/salu-to-valu.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -265,7 +265,7 @@ entry:

; GCN-LABEL: {{^}}smrd_valu2_max_smrd_offset:
; GCN-NOHSA: buffer_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:1020{{$}}
; GCN-HSA flat_load_dword v{{[0-9]}}, v{{[0-9]+:[0-9]+}}
; GCN-HSA: flat_load_dword v{{[0-9]}}, v[{{[0-9]+:[0-9]+}}]
define amdgpu_kernel void @smrd_valu2_max_smrd_offset(i32 addrspace(1)* %out, [1024 x i32] addrspace(4)* %in) #1 {
entry:
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -58,7 +58,7 @@ body: |
---

# GCN-LABEL: name: dead_illegal_physreg_copy
# GCN %2:vgpr_32 = COPY $vgpr0
# GCN: %2:vgpr_32 = COPY $vgpr0
# GCN: %1:sreg_32_xm0 = IMPLICIT_DEF
# GCN: S_ENDPGM 0, implicit %2

Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/si-scheduler.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -65,7 +65,7 @@ attributes #2 = { nounwind readonly }


; CHECK-LABEL: amdgpu_ps_main:
; CHECK s_buffer_load_dword
; CHECK: s_buffer_load_dword
define amdgpu_ps void @_amdgpu_ps_main(i32 %arg) local_unnamed_addr {
.entry:
%tmp = insertelement <2 x i32> zeroinitializer, i32 %arg, i32 0
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@
; GFX900: buffer_load_dword v{{[0-9]}},
; GFX900: buffer_load_dword v{{[0-9]}},
; GFX908-NOT: buffer_
; GFX908-DAG v_accvgpr_read_b32 v{{[0-9]}}, a0
; GFX908-DAG: v_accvgpr_read_b32 v{{[0-9]}}, a0
; GFX908-DAG: v_accvgpr_read_b32 v{{[0-9]}}, a1

; GCN: NumVgprs: 10
Expand Down Expand Up @@ -126,7 +126,7 @@ define amdgpu_kernel void @max_10_vgprs_used_9a(i32 addrspace(1)* %p) #0 {
; GCN-DAG: buffer_store_dword v{{[0-9]}},
; GFX900: buffer_load_dword v{{[0-9]}},
; GCN-DAG: buffer_load_dword v{{[0-9]}},
; GFX908-DAG v_accvgpr_read_b32 v{{[0-9]}}, a1
; GFX908-DAG: v_accvgpr_read_b32 v{{[0-9]}}, a1
; GFX908-DAG: v_accvgpr_read_b32 v{{[0-9]}}, a2
; GFX908-DAG: v_accvgpr_read_b32 v{{[0-9]}}, a3
; GFX908-DAG: v_accvgpr_read_b32 v{{[0-9]}}, a4
Expand Down Expand Up @@ -192,7 +192,7 @@ define amdgpu_kernel void @max_10_vgprs_spill_v32(<32 x float> addrspace(1)* %p)
; GFX900: buffer_store_dword v
; GFX900: buffer_load_dword v
; GFX908-NOT: buffer_
; GFX908-DAG v_accvgpr_read_b32
; GFX908-DAG: v_accvgpr_read_b32

; GCN: NumVgprs: 256
; GFX900: ScratchSize: 148
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/AMDGPU/udivrem24.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -122,7 +122,7 @@ define amdgpu_kernel void @udiv23_i32(i32 addrspace(1)* %out, i32 addrspace(1)*

; FUNC-LABEL: {{^}}udiv24_i32:
; SI: v_rcp_iflag
; SI-NOT v_rcp_f32
; SI-NOT: v_rcp_f32
; EG-NOT: RECIP_IEEE
define amdgpu_kernel void @udiv24_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
%den_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
Expand All @@ -139,7 +139,7 @@ define amdgpu_kernel void @udiv24_i32(i32 addrspace(1)* %out, i32 addrspace(1)*

; FUNC-LABEL: {{^}}no_udiv24_u23_u24_i32:
; SI: v_rcp_iflag
; SI-NOT v_rcp_f32
; SI-NOT: v_rcp_f32
; EG-NOT: RECIP_IEEE
define amdgpu_kernel void @no_udiv24_u23_u24_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
%den_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
Expand All @@ -156,7 +156,7 @@ define amdgpu_kernel void @no_udiv24_u23_u24_i32(i32 addrspace(1)* %out, i32 add

; FUNC-LABEL: {{^}}no_udiv24_u24_u23_i32:
; SI: v_rcp_iflag
; SI-NOT v_rcp_f32
; SI-NOT: v_rcp_f32
; EG-NOT: RECIP_IEEE
define amdgpu_kernel void @no_udiv24_u24_u23_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
%den_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/ARM/acle-intrinsics.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -71,7 +71,7 @@ define i32 @pack_unpack(i32 %a, i32 %b) nounwind {

define i32 @sel(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: sel
; CHECK sel r0, r0, r1
; CHECK: sel r0, r0, r1
%tmp = call i32 @llvm.arm.sel(i32 %a, i32 %b)
ret i32 %tmp
}
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/ARM/debug-segmented-stacks.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -35,8 +35,8 @@ define void @test_basic() #0 !dbg !4 {

; ARM-linux: pop {r4, r5}
; ARM-linux: .cfi_def_cfa_offset 0
; ARM-linux .cfi_same_value r4
; ARM-linux .cfi_same_value r5
; ARM-linux: .cfi_same_value r4
; ARM-linux: .cfi_same_value r5
}

!0 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5 ", isOptimized: false, emissionKind: FullDebug, file: !1, enums: !2, retainedTypes: !2, globals: !2, imports: !2)
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/BPF/rodata_4.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -34,7 +34,7 @@ entry:
; CHECK: *(u16 *)(r1 + 0) = r2
ret i32 0
}
; CHECK .section .rodata,"a",@progbits
; CHECK: .section .rodata,"a",@progbits

; Function Attrs: argmemonly nounwind
declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i1) #1
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Hexagon/constant_compound.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@
; rb = xor(rb, ra)

; CHECK: and(##65280,lsr(r
; CHECK-NOT : ^= and
; CHECK-NOT: ^= and

define dso_local zeroext i16 @test_compound(i16 zeroext %varA, i16 zeroext %varB) local_unnamed_addr #0 {
entry:
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Hexagon/intrinsics/v65.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@ define i32 @A6_vcmpbeq_notany(i64 %a, i64 %b) {
%c = call i32 @llvm.hexagon.A6.vcmpbeq.notany(i64 %a, i64 %b)
ret i32 %c
}
; CHECK = !any8(vcmpb.eq(r1:0,r3:2))
; CHECK: = !any8(vcmpb.eq(r1:0,r3:2))

declare <16 x i32> @llvm.hexagon.V6.vabsb(<16 x i32>)
define <16 x i32> @V6_vabsb(<16 x i32> %a) {
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/Mips/nmadd.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@ entry:
; CHECK-NM-64: nmadd.s $f0, $f14, $f12, $f13
; CHECK-NM: nmadd.s $f0, $f0, $f12, $f14
; CHECK-MM: NMADD_S_MM
; CHECK-NOT-NM-64 mul.s $f0, $f12, $f13
; CHECK-NOT-NM-64: mul.s $f0, $f12, $f13
; CHECK-NOT-NM-64: neg.s $f0, $f0
; CHECK-NOT-NM: mul.s $f0, $f12, $f14
; CHECK-NOT-NM: neg.s $f0, $f0
Expand All @@ -36,7 +36,7 @@ entry:
; CHECK-NM-64: nmadd.d $f0, $f14, $f12, $f13
; CHECK-NM: nmadd.d $f0, $f0, $f12, $f14
; CHECK-MM: NMADD_D32_MM
; CHECK-NOT-NM-64 mul.d $f0, $f12, $f13
; CHECK-NOT-NM-64: mul.d $f0, $f12, $f13
; CHECK-NOT-NM-64: neg.d $f0, $f0
; CHECK-NOT-NM: mul.d $f0, $f12, $f14
; CHECK-NOT-NM: neg.d $f0, $f0
Expand All @@ -54,7 +54,7 @@ entry:
; CHECK-NM-64: nmsub.s $f0, $f14, $f12, $f13
; CHECK-NM: nmsub.s $f0, $f0, $f12, $f14
; CHECK-MM: NMSUB_S_MM
; CHECK-NOT-NM-64 mul.s $f0, $f12, $f13
; CHECK-NOT-NM-64: mul.s $f0, $f12, $f13
; CHECK-NOT-NM-64: neg.s $f0, $f0
; CHECK-NOT-NM: mul.s $f0, $f12, $f14
; CHECK-NOT-NM: neg.s $f0, $f0
Expand All @@ -72,7 +72,7 @@ entry:
; CHECK-NM-64: nmsub.d $f0, $f14, $f12, $f13
; CHECK-NM: nmsub.d $f0, $f0, $f12, $f14
; CHECK-MM: NMSUB_D32_MM
; CHECK-NOT-NM-64 mul.d $f0, $f12, $f13
; CHECK-NOT-NM-64: mul.d $f0, $f12, $f13
; CHECK-NOT-NM-64: neg.d $f0, $f0
; CHECK-NOT-NM: mul.d $f0, $f12, $f14
; CHECK-NOT-NM: neg.d $f0, $f0
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/NVPTX/atomics-sm60.ll
View file
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=nvptx -mcpu=sm_60 | FileCheck %s
; RUN: llc < %s -march=nvptx64 -mcpu=sm_60 | FileCheck %s

; CHECK-LABEL .func test(
; CHECK-LABEL: .func test(
define void @test(double* %dp0, double addrspace(1)* %dp1, double addrspace(3)* %dp3, double %d) {
; CHECK: atom.add.f64
%r1 = call double @llvm.nvvm.atomic.load.add.f64.p0f64(double* %dp0, double %d)
Expand All @@ -12,7 +12,7 @@ define void @test(double* %dp0, double addrspace(1)* %dp1, double addrspace(3)*
ret void
}

; CHECK-LABEL .func test2(
; CHECK-LABEL: .func test2(
define void @test2(double* %dp0, double addrspace(1)* %dp1, double addrspace(3)* %dp3, double %d) {
; CHECK: atom.add.f64
%r1 = atomicrmw fadd double* %dp0, double %d seq_cst
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/NVPTX/intrinsics.ll
View file
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s

; CHECK-LABEL test_fabsf(
; CHECK-LABEL: test_fabsf(
define float @test_fabsf(float %f) {
; CHECK: abs.f32
%x = call float @llvm.fabs.f32(float %f)
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/NVPTX/param-load-store.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -210,7 +210,7 @@ define <4 x i8> @test_v4i8(<4 x i8> %a) {
; CHECK-LABEL: test_v5i8(
; CHECK-NEXT: .param .align 8 .b8 test_v5i8_param_0[8]
; CHECK-DAG: ld.param.u8 [[E4:%rs[0-9]+]], [test_v5i8_param_0+4];
; CHECK-DAG ld.param.v4.u8 {[[E0:%rs[0-9]+]], [[E1:%rs[0-9]+]], [[E2:%rs[0-9]+]], [[E3:%rs[0-9]+]]}, [test_v5i8_param_0]
; CHECK-DAG: ld.param.v4.u8 {[[E0:%rs[0-9]+]], [[E1:%rs[0-9]+]], [[E2:%rs[0-9]+]], [[E3:%rs[0-9]+]]}, [test_v5i8_param_0]
; CHECK: .param .align 8 .b8 param0[8];
; CHECK-DAG: st.param.v4.b8 [param0+0], {[[E0]], [[E1]], [[E2]], [[E3]]};
; CHECK-DAG: st.param.b8 [param0+4], [[E4]];
Expand Down Expand Up @@ -307,7 +307,7 @@ define <4 x i16> @test_v4i16(<4 x i16> %a) {
; CHECK-LABEL: test_v5i16(
; CHECK-NEXT: .param .align 16 .b8 test_v5i16_param_0[16]
; CHECK-DAG: ld.param.u16 [[E4:%rs[0-9]+]], [test_v5i16_param_0+8];
; CHECK-DAG ld.param.v4.u16 {[[E0:%rs[0-9]+]], [[E1:%rs[0-9]+]], [[E2:%rs[0-9]+]], [[E3:%rs[0-9]+]]}, [test_v5i16_param_0]
; CHECK-DAG: ld.param.v4.u16 {[[E0:%rs[0-9]+]], [[E1:%rs[0-9]+]], [[E2:%rs[0-9]+]], [[E3:%rs[0-9]+]]}, [test_v5i16_param_0]
; CHECK: .param .align 16 .b8 param0[16];
; CHECK-DAG: st.param.v4.b16 [param0+0], {[[E0]], [[E1]], [[E2]], [[E3]]};
; CHECK-DAG: st.param.b16 [param0+8], [[E4]];
Expand Down Expand Up @@ -526,7 +526,7 @@ define <4 x i32> @test_v4i32(<4 x i32> %a) {
; CHECK-LABEL: test_v5i32(
; CHECK-NEXT: .param .align 32 .b8 test_v5i32_param_0[32]
; CHECK-DAG: ld.param.u32 [[E4:%r[0-9]+]], [test_v5i32_param_0+16];
; CHECK-DAG ld.param.v4.u32 {[[E0:%r[0-9]+]], [[E1:%r[0-9]+]], [[E2:%r[0-9]+]], [[E3:%r[0-9]+]]}, [test_v5i32_param_0]
; CHECK-DAG: ld.param.v4.u32 {[[E0:%r[0-9]+]], [[E1:%r[0-9]+]], [[E2:%r[0-9]+]], [[E3:%r[0-9]+]]}, [test_v5i32_param_0]
; CHECK: .param .align 32 .b8 param0[32];
; CHECK-DAG: st.param.v4.b32 [param0+0], {[[E0]], [[E1]], [[E2]], [[E3]]};
; CHECK-DAG: st.param.b32 [param0+16], [[E4]];
Expand Down
24 changes: 12 additions & 12 deletions llvm/test/CodeGen/NVPTX/sqrt-approx.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,31 +8,31 @@ declare double @llvm.sqrt.f64(double)

; -- reciprocal sqrt --

; CHECK-LABEL test_rsqrt32
; CHECK-LABEL: test_rsqrt32
define float @test_rsqrt32(float %a) #0 {
; CHECK: rsqrt.approx.f32
%val = tail call float @llvm.sqrt.f32(float %a)
%ret = fdiv float 1.0, %val
ret float %ret
}

; CHECK-LABEL test_rsqrt_ftz
; CHECK-LABEL: test_rsqrt_ftz
define float @test_rsqrt_ftz(float %a) #0 #1 {
; CHECK: rsqrt.approx.ftz.f32
%val = tail call float @llvm.sqrt.f32(float %a)
%ret = fdiv float 1.0, %val
ret float %ret
}

; CHECK-LABEL test_rsqrt64
; CHECK-LABEL: test_rsqrt64
define double @test_rsqrt64(double %a) #0 {
; CHECK: rsqrt.approx.f64
%val = tail call double @llvm.sqrt.f64(double %a)
%ret = fdiv double 1.0, %val
ret double %ret
}

; CHECK-LABEL test_rsqrt64_ftz
; CHECK-LABEL: test_rsqrt64_ftz
define double @test_rsqrt64_ftz(double %a) #0 #1 {
; There's no rsqrt.approx.ftz.f64 instruction; we just use the non-ftz version.
; CHECK: rsqrt.approx.f64
Expand All @@ -43,42 +43,42 @@ define double @test_rsqrt64_ftz(double %a) #0 #1 {

; -- sqrt --

; CHECK-LABEL test_sqrt32
; CHECK-LABEL: test_sqrt32
define float @test_sqrt32(float %a) #0 {
; CHECK: sqrt.rn.f32
%ret = tail call float @llvm.sqrt.f32(float %a)
ret float %ret
}

; CHECK-LABEL test_sqrt32_ninf
; CHECK-LABEL: test_sqrt32_ninf
define float @test_sqrt32_ninf(float %a) #0 {
; CHECK: sqrt.approx.f32
%ret = tail call ninf float @llvm.sqrt.f32(float %a)
ret float %ret
}

; CHECK-LABEL test_sqrt_ftz
; CHECK-LABEL: test_sqrt_ftz
define float @test_sqrt_ftz(float %a) #0 #1 {
; CHECK: sqrt.rn.ftz.f32
%ret = tail call float @llvm.sqrt.f32(float %a)
ret float %ret
}

; CHECK-LABEL test_sqrt_ftz_ninf
; CHECK-LABEL: test_sqrt_ftz_ninf
define float @test_sqrt_ftz_ninf(float %a) #0 #1 {
; CHECK: sqrt.approx.ftz.f32
%ret = tail call ninf float @llvm.sqrt.f32(float %a)
ret float %ret
}

; CHECK-LABEL test_sqrt64
; CHECK-LABEL: test_sqrt64
define double @test_sqrt64(double %a) #0 {
; CHECK: sqrt.rn.f64
%ret = tail call double @llvm.sqrt.f64(double %a)
ret double %ret
}

; CHECK-LABEL test_sqrt64_ninf
; CHECK-LABEL: test_sqrt64_ninf
define double @test_sqrt64_ninf(double %a) #0 {
; There's no sqrt.approx.f64 instruction; we emit
; reciprocal(rsqrt.approx.f64(x)). There's no non-ftz approximate reciprocal,
Expand All @@ -89,14 +89,14 @@ define double @test_sqrt64_ninf(double %a) #0 {
ret double %ret
}

; CHECK-LABEL test_sqrt64_ftz
; CHECK-LABEL: test_sqrt64_ftz
define double @test_sqrt64_ftz(double %a) #0 #1 {
; CHECK: sqrt.rn.f64
%ret = tail call double @llvm.sqrt.f64(double %a)
ret double %ret
}

; CHECK-LABEL test_sqrt64_ftz_ninf
; CHECK-LABEL: test_sqrt64_ftz_ninf
define double @test_sqrt64_ftz_ninf(double %a) #0 #1 {
; There's no sqrt.approx.ftz.f64 instruction; we just use the non-ftz version.
; CHECK: rsqrt.approx.f64
Expand Down
14 changes: 7 additions & 7 deletions llvm/test/CodeGen/NVPTX/vector-loads.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@
;
; which will load two floats at once into scalar registers.

; CHECK-LABEL foo
; CHECK-LABEL: foo
define void @foo(<2 x float>* %a) {
; CHECK: ld.v2.f32 {%f{{[0-9]+}}, %f{{[0-9]+}}}
%t1 = load <2 x float>, <2 x float>* %a
Expand All @@ -16,7 +16,7 @@ define void @foo(<2 x float>* %a) {
ret void
}

; CHECK-LABEL foo2
; CHECK-LABEL: foo2
define void @foo2(<4 x float>* %a) {
; CHECK: ld.v4.f32 {%f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}}
%t1 = load <4 x float>, <4 x float>* %a
Expand All @@ -25,7 +25,7 @@ define void @foo2(<4 x float>* %a) {
ret void
}

; CHECK-LABEL foo3
; CHECK-LABEL: foo3
define void @foo3(<8 x float>* %a) {
; CHECK: ld.v4.f32 {%f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}}
; CHECK-NEXT: ld.v4.f32 {%f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}}
Expand All @@ -37,7 +37,7 @@ define void @foo3(<8 x float>* %a) {



; CHECK-LABEL foo4
; CHECK-LABEL: foo4
define void @foo4(<2 x i32>* %a) {
; CHECK: ld.v2.u32 {%r{{[0-9]+}}, %r{{[0-9]+}}}
%t1 = load <2 x i32>, <2 x i32>* %a
Expand All @@ -46,7 +46,7 @@ define void @foo4(<2 x i32>* %a) {
ret void
}

; CHECK-LABEL foo5
; CHECK-LABEL: foo5
define void @foo5(<4 x i32>* %a) {
; CHECK: ld.v4.u32 {%r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}}
%t1 = load <4 x i32>, <4 x i32>* %a
Expand All @@ -55,7 +55,7 @@ define void @foo5(<4 x i32>* %a) {
ret void
}

; CHECK-LABEL foo6
; CHECK-LABEL: foo6
define void @foo6(<8 x i32>* %a) {
; CHECK: ld.v4.u32 {%r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}}
; CHECK-NEXT: ld.v4.u32 {%r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}}
Expand All @@ -69,7 +69,7 @@ define void @foo6(<8 x i32>* %a) {
; computation was still too complex when LSV was called.
declare i32 @llvm.nvvm.read.ptx.sreg.ctaid.x() #0
declare i32 @llvm.nvvm.read.ptx.sreg.tid.x() #0
; CHECK-LABEL foo_complex
; CHECK-LABEL: foo_complex
define void @foo_complex(i8* nocapture readonly align 16 dereferenceable(134217728) %alloc0) {
%targ0.1.typed = bitcast i8* %alloc0 to [1024 x [131072 x i8]]*
%t0 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !range !1
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-kill-flag.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@
---
# LI + XFORM -> DFORM, no killed/dead flag fixup.
name: testKillPassUpLI1
#CHECK : name : testKillPassUpLI1
#CHECK: name: testKillPassUpLI1
tracksRegLiveness: true
body: |
bb.0.entry:
Expand All @@ -19,7 +19,7 @@ body: |
---
# LI + XFORM -> DFORM, fixup killed/dead flag for $x3, find no use, set def as
# dead(LI8 is deleted).
name : testKillPassUpLI2
name: testKillPassUpLI2
# CHECK: name: testKillPassUpLI2
tracksRegLiveness: true
body: |
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/PowerPC/f128-arith.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -71,7 +71,7 @@ entry:
; CHECK-LABEL: testLdNSt
; CHECK: lxvx
; CHECK: stxvx
; CHECK-NEXT blr
; CHECK-NEXT: blr
}

define void @qpSqrt(fp128* nocapture readonly %a, fp128* nocapture %res) {
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/PowerPC/fastcc_stacksize.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -44,7 +44,7 @@ entry:
i32 signext 7, i32 signext 8) ret void
ret void

; CHECK-LABEL : WithoutParamArea3
; CHECK-LABEL: WithoutParamArea3
; CHECK: stdu 1, -32(1)
; CHECK: blr
}
Expand All @@ -63,7 +63,7 @@ entry:
call fastcc void @PassByValue(%"myClass::Mem"* byval nonnull align 8 undef);
ret void

; CHECK-LABEL : PassByValue
; CHECK-LABEL: PassByValue
; CHECK: stdu 1, -32(1)
; CHECK: blr
}
Expand Down Expand Up @@ -131,7 +131,7 @@ entry:
byval nonnull align 8 undef);
ret void

; CHECK-LABEL : AggMemExprEmitter
; CHECK-LABEL: AggMemExprEmitter
; CHECK: stdu 1, -144(1)
; CHECK: blr
}
Expand Down
5 changes: 0 additions & 5 deletions llvm/test/CodeGen/PowerPC/spe.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -43,7 +43,6 @@ define float @test_fmul(float %a, float %b) {
entry:
%v = fmul float %a, %b
ret float %v
; CHECK-LABEL @test_fmul
}

define float @test_fadd(float %a, float %b) {
Expand All @@ -54,7 +53,6 @@ define float @test_fadd(float %a, float %b) {
entry:
%v = fadd float %a, %b
ret float %v
; CHECK-LABEL @test_fadd
}

define float @test_fsub(float %a, float %b) {
Expand All @@ -65,7 +63,6 @@ define float @test_fsub(float %a, float %b) {
entry:
%v = fsub float %a, %b
ret float %v
; CHECK-LABEL @test_fsub
}

define float @test_fneg(float %a) {
Expand All @@ -76,8 +73,6 @@ define float @test_fneg(float %a) {
entry:
%v = fsub float -0.0, %a
ret float %v

; CHECK-LABEL @test_fneg
}

define float @test_dtos(double %a) {
Expand Down
2 changes: 0 additions & 2 deletions llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,6 @@
; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu | FileCheck %s --check-prefixes=PPC32

define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 {
; PPC64-LABEL muloti_test:
; PPC64-LABEL: muloti_test:
; PPC64: # %bb.0: # %start
; PPC64-NEXT: mulld 8, 5, 4
Expand Down Expand Up @@ -151,7 +150,6 @@ define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 {
; PPC32-NEXT: addi 1, 1, 80
; PPC32-NEXT: mtlr 0
; PPC32-NEXT: blr
; PPC32-LABEL muloti_test:
start:
%0 = tail call { i128, i1 } @llvm.umul.with.overflow.i128(i128 %l, i128 %r) #2
%1 = extractvalue { i128, i1 } %0, 0
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/PowerPC/xray-ret-is-terminator.ll
View file
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
; RUN: llc -verify-machineinstrs -o - -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s

define void @ILLBeBack() #0 {
; CHECK-LABEL @ILLBeBack
; CHECK-LABEL: @ILLBeBack
; CHECK: bne {{[0-9]+}}, [[LABEL:\.[a-zA-Z0-9_]+]]
; CHECK: [[LABEL]]:
; CHECK: bl __xray_FunctionExit
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Thumb2/float-ops.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -277,7 +277,7 @@ define float @select_f(float %a, float %b, i1 %c) {
define double @select_d(double %a, double %b, i1 %c) {
; CHECK-LABEL: select_d:
; NONE: ldr{{(.w)?}} [[REG:r[0-9]+]], [sp]
; NONE ands [[REG]], [[REG]], #1
; NONE: ands [[REG]], [[REG]], #1
; NONE-DAG: moveq r0, r2
; NONE-DAG: moveq r1, r3
; SP: ands r0, r0, #1
Expand Down
1 change: 0 additions & 1 deletion llvm/test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -315,7 +315,6 @@ entry:
}

define i32 * @test_memop_i32(i32 * %p1) {
;X64 liveins: $rdi
; X32-LABEL: name: test_memop_i32
; X32: bb.1 (%ir-block.0):
; X32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
Expand Down
1 change: 0 additions & 1 deletion llvm/test/CodeGen/X86/avx-vzeroupper.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -83,7 +83,6 @@ define <8 x float> @test01(<4 x float> %a, <4 x float> %b, <8 x float> %c) nounw
; BTVER2-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
; BTVER2-NEXT: addq $56, %rsp
; BTVER2-NEXT: retq
; DISABLE-VZ # %bb.0:
%tmp = load <4 x float>, <4 x float>* @x, align 16
%call = tail call <4 x float> @do_sse(<4 x float> %tmp) nounwind
store <4 x float> %call, <4 x float>* @x, align 16
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/X86/inline-0bh.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@ define i32 @PR31007() {
; CHECK-LABEL: PR31007:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: #APP
; CHECK : addb $11, %al
; CHECK: addb $11, %al
; CHECK: #NO_APP
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: retq
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/X86/scavenger.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -44,6 +44,6 @@ name: func3
tracksRegLiveness: true
body: |
bb.0:
; CHECK dead {{\$e[a-z]+}} = MOV32ri 42
; CHECK: dead {{\$e[a-z]+}} = MOV32ri 42
dead %0 : gr32 = MOV32ri 42
...
4 changes: 2 additions & 2 deletions llvm/test/DebugInfo/MIR/X86/live-debug-values-fragments.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -42,12 +42,12 @@
# CHECK-NEXT: MOV32rr
# CHECK-NEXT: ADD32ri8
# CHECK-NEXT: DBG_VALUE $ebx, $noreg, !{{[0-9]+}},
# CHECK-SAME !DIExpression(DW_OP_LLVM_fragment, 32, 32)
# CHECK-SAME: !DIExpression(DW_OP_LLVM_fragment, 32, 32)
# CHECK-NEXT: JMP_1

# CHECK-LABEL: bb.3.bb3:
# CHECK: DBG_VALUE $ebx, $noreg, !{{[0-9]+}},
# CHECK-SAME !DIExpression(DW_OP_LLVM_fragment, 32, 32)
# CHECK-SAME: !DIExpression(DW_OP_LLVM_fragment, 32, 32)
# CHECK-NEXT: DBG_VALUE $ax, $noreg, !{{[0-9]+}},
# CHECK-SAME: !DIExpression(DW_OP_LLVM_fragment, 8, 16)
# CHECK-NEXT: XOR32rr
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/DebugInfo/X86/objc-property-void.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@
; CHECK: DW_TAG_structure_type
; CHECK: DW_AT_APPLE_objc_complete_type
; CHECK: DW_AT_name [DW_FORM_strp] ( .debug_str[0x{{[0-9a-fA-F]+}}] = "Foo")
; CHECK DW_AT_APPLE_runtime_class [DW_FORM_data1] (DW_LANG_ObjC)
; CHECK: DW_AT_APPLE_runtime_class [DW_FORM_data1] (DW_LANG_ObjC)
; CHECK: DW_TAG_APPLE_property
; CHECK: DW_AT_APPLE_property_name [DW_FORM_strp] ( .debug_str[0x{{[0-9a-fA-F]+}}] = "foo")

Expand Down
2 changes: 1 addition & 1 deletion llvm/test/Instrumentation/AddressSanitizer/basic-msvc64.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@ define i32 @test_load(i32* %a) sanitize_address {
; CHECK-NEXT: %[[SHADOW:[^ ]*]] = load i64, i64* @__asan_shadow_memory_dynamic_address

; Shadow address is loaded and added into the whole offset computation.
; CHECK add i64 %{{.*}}, %[[SHADOW] ]
; CHECK: add i64 %{{.*}}, %[[SHADOW]]

entry:
%tmp1 = load i32, i32* %a, align 4
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/Instrumentation/AddressSanitizer/force-dynamic-shadow.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,7 @@ define i32 @test_load(i32* %a) sanitize_address {
; CHECK-NDS-NOT: __asan_shadow_memory_dynamic_address

; Shadow address is loaded and added into the whole offset computation.
; CHECK-FDS add i64 %{{.*}}, %[[SHADOW] ]
; CHECK-FDS: add i64 %{{.*}}, %[[SHADOW]]

entry:
%tmp1 = load i32, i32* %a, align 4
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -953,7 +953,7 @@ entry:

attributes #0 = { "target-features"="+fxsr,+x87,-sse" }

; CHECK call void @llvm.memcpy.p0i8.p0i8.i64{{.*}}@__msan_va_arg_tls {{.*}}, i64 48
; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64{{.*}}@__msan_va_arg_tls {{.*}}, i64 48

declare i32 @InnerTailCall(i32 %a)

Expand Down
2 changes: 1 addition & 1 deletion llvm/test/Instrumentation/SanitizerCoverage/const-cmp-tracing.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,7 @@ entry:
; compare (const, const) - should not be instrumented
icmp slt i32 1, 0
; CHECK-NOT: call void @__sanitizer_cov_trace
; CHECK icmp slt i32 1, 0
; CHECK: icmp slt i32 1, 0

; compare variables of byte size
%x = trunc i32 %a to i8
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/MC/AArch64/tme-error.s
View file
Original file line number Diff line number Diff line change
Expand Up @@ -37,10 +37,10 @@ tcommit sp

tcancel
// CHECK: error: too few operands for instruction
// CHECK-NEXT tcancel
// CHECK-NEXT: tcancel
tcancel x0
// CHECK: error: immediate must be an integer in range [0, 65535]
// CHECK-NEXT tcancel
// CHECK-NEXT: tcancel
tcancel #65536
// CHECK: error: immediate must be an integer in range [0, 65535]
// CHECK-NEXT: tcancel #65536
Expand Down
30 changes: 15 additions & 15 deletions llvm/test/MC/Disassembler/ARM/vstrldr_sys.txt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -92,7 +92,7 @@
# CHECK: vldrhi fpscr, [r0] @ encoding: [0x90,0xed,0x80,0x2f]
[0x90,0xed,0x80,0x2f]

# ERROR-NOSEC invalid instruction encoding
# ERROR-NOSEC: invalid instruction encoding
# CHECK-NOMVE: vstr fpcxts, [r12, #508] @ encoding: [0xcc,0xed,0xff,0xef]
# CHECK-NOVFP: vstr fpcxts, [r12, #508] @ encoding: [0xcc,0xed,0xff,0xef]
# CHECK: vstr fpcxts, [r12, #508] @ encoding: [0xcc,0xed,0xff,0xef]
Expand Down Expand Up @@ -213,85 +213,85 @@
[0x7d,0xec,0x86,0xcf]

# CHECK-NOSEC: vstr vpr, [r6, #500] @ encoding: [0xc6,0xed,0xfd,0x8f]
# ERROR-NOMVE invalid instruction encoding
# ERROR-NOMVE: invalid instruction encoding
# CHECK-NOVFP: vstr vpr, [r6, #500] @ encoding: [0xc6,0xed,0xfd,0x8f]
# CHECK: vstr vpr, [r6, #500] @ encoding: [0xc6,0xed,0xfd,0x8f]
[0xc6,0xed,0xfd,0x8f]

# CHECK-NOSEC: vstr p0, [lr, #-508] @ encoding: [0x4e,0xed,0xff,0xaf]
# ERROR-NOMVE invalid instruction encoding
# ERROR-NOMVE: invalid instruction encoding
# CHECK-NOVFP: vstr p0, [lr, #-508] @ encoding: [0x4e,0xed,0xff,0xaf]
# CHECK: vstr p0, [lr, #-508] @ encoding: [0x4e,0xed,0xff,0xaf]
[0x4e,0xed,0xff,0xaf]

# CHECK-NOSEC: vstr vpr, [r6, #500]! @ encoding: [0xe6,0xed,0xfd,0x8f]
# ERROR-NOMVE invalid instruction encoding
# ERROR-NOMVE: invalid instruction encoding
# CHECK-NOVFP: vstr vpr, [r6, #500]! @ encoding: [0xe6,0xed,0xfd,0x8f]
# CHECK: vstr vpr, [r6, #500]! @ encoding: [0xe6,0xed,0xfd,0x8f]
[0xe6,0xed,0xfd,0x8f]

# CHECK-NOSEC: vstr p0, [lr, #-508]! @ encoding: [0x6e,0xed,0xff,0xaf]
# ERROR-NOMVE invalid instruction encoding
# ERROR-NOMVE: invalid instruction encoding
# CHECK-NOVFP: vstr p0, [lr, #-508]! @ encoding: [0x6e,0xed,0xff,0xaf]
# CHECK: vstr p0, [lr, #-508]! @ encoding: [0x6e,0xed,0xff,0xaf]
[0x6e,0xed,0xff,0xaf]

# CHECK-NOSEC: vstr vpr, [r6], #500 @ encoding: [0xe6,0xec,0xfd,0x8f]
# ERROR-NOMVE invalid instruction encoding
# ERROR-NOMVE: invalid instruction encoding
# CHECK-NOVFP: vstr vpr, [r6], #500 @ encoding: [0xe6,0xec,0xfd,0x8f]
# CHECK: vstr vpr, [r6], #500 @ encoding: [0xe6,0xec,0xfd,0x8f]
[0xe6,0xec,0xfd,0x8f]

# CHECK-NOSEC: vstr p0, [lr], #-508 @ encoding: [0x6e,0xec,0xff,0xaf]
# ERROR-NOMVE invalid instruction encoding
# ERROR-NOMVE: invalid instruction encoding
# CHECK-NOVFP: vstr p0, [lr], #-508 @ encoding: [0x6e,0xec,0xff,0xaf]
# CHECK: vstr p0, [lr], #-508 @ encoding: [0x6e,0xec,0xff,0xaf]
[0x6e,0xec,0xff,0xaf]

# CHECK-NOSEC: vstr p0, [sp], #-24 @ encoding: [0x6d,0xec,0x86,0xaf]
# ERROR-NOMVE invalid instruction encoding
# ERROR-NOMVE: invalid instruction encoding
# CHECK-NOVFP: vstr p0, [sp], #-24 @ encoding: [0x6d,0xec,0x86,0xaf]
# CHECK: vstr p0, [sp], #-24 @ encoding: [0x6d,0xec,0x86,0xaf]
[0x6d,0xec,0x86,0xaf]

# CHECK-NOSEC: vldr vpr, [r6, #500] @ encoding: [0xd6,0xed,0xfd,0x8f]
# ERROR-NOMVE invalid instruction encoding
# ERROR-NOMVE: invalid instruction encoding
# CHECK-NOVFP: vldr vpr, [r6, #500] @ encoding: [0xd6,0xed,0xfd,0x8f]
# CHECK: vldr vpr, [r6, #500] @ encoding: [0xd6,0xed,0xfd,0x8f]
[0xd6,0xed,0xfd,0x8f]

# CHECK-NOSEC: vldr p0, [lr, #-508] @ encoding: [0x5e,0xed,0xff,0xaf]
# ERROR-NOMVE invalid instruction encoding
# ERROR-NOMVE: invalid instruction encoding
# CHECK-NOVFP: vldr p0, [lr, #-508] @ encoding: [0x5e,0xed,0xff,0xaf]
# CHECK: vldr p0, [lr, #-508] @ encoding: [0x5e,0xed,0xff,0xaf]
[0x5e,0xed,0xff,0xaf]

# CHECK-NOSEC: vldr vpr, [r6, #500]! @ encoding: [0xf6,0xed,0xfd,0x8f]
# ERROR-NOMVE invalid instruction encoding
# ERROR-NOMVE: invalid instruction encoding
# CHECK-NOVFP: vldr vpr, [r6, #500]! @ encoding: [0xf6,0xed,0xfd,0x8f]
# CHECK: vldr vpr, [r6, #500]! @ encoding: [0xf6,0xed,0xfd,0x8f]
[0xf6,0xed,0xfd,0x8f]

# CHECK-NOSEC: vldr p0, [lr, #-508]! @ encoding: [0x7e,0xed,0xff,0xaf]
# ERROR-NOMVE invalid instruction encoding
# ERROR-NOMVE: invalid instruction encoding
# CHECK-NOVFP: vldr p0, [lr, #-508]! @ encoding: [0x7e,0xed,0xff,0xaf]
# CHECK: vldr p0, [lr, #-508]! @ encoding: [0x7e,0xed,0xff,0xaf]
[0x7e,0xed,0xff,0xaf]

# CHECK-NOSEC: vldr vpr, [r6], #500 @ encoding: [0xf6,0xec,0xfd,0x8f]
# ERROR-NOMVE invalid instruction encoding
# ERROR-NOMVE: invalid instruction encoding
# CHECK-NOVFP: vldr vpr, [r6], #500 @ encoding: [0xf6,0xec,0xfd,0x8f]
# CHECK: vldr vpr, [r6], #500 @ encoding: [0xf6,0xec,0xfd,0x8f]
[0xf6,0xec,0xfd,0x8f]

# CHECK-NOSEC: vldr p0, [lr], #-508 @ encoding: [0x7e,0xec,0xff,0xaf]
# ERROR-NOMVE invalid instruction encoding
# ERROR-NOMVE: invalid instruction encoding
# CHECK-NOVFP: vldr p0, [lr], #-508 @ encoding: [0x7e,0xec,0xff,0xaf]
# CHECK: vldr p0, [lr], #-508 @ encoding: [0x7e,0xec,0xff,0xaf]
[0x7e,0xec,0xff,0xaf]

# CHECK-NOSEC: vldr p0, [sp], #-24 @ encoding: [0x7d,0xec,0x86,0xaf]
# ERROR-NOMVE invalid instruction encoding
# ERROR-NOMVE: invalid instruction encoding
# CHECK-NOVFP: vldr p0, [sp], #-24 @ encoding: [0x7d,0xec,0x86,0xaf]
# CHECK: vldr p0, [sp], #-24 @ encoding: [0x7d,0xec,0x86,0xaf]
[0x7d,0xec,0x86,0xaf]
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -841,10 +841,10 @@
#CHECK: vabsdub 2, 3, 4
0x10 0x43 0x24 0x03

#CHECK vabsduh 2, 3, 4
#CHECK: vabsduh 2, 3, 4
0x10 0x43 0x24 0x43

#CHECK vabsduw 2, 3, 4
#CHECK: vabsduw 2, 3, 4
0x10 0x43 0x24 0x83

# CHECK: bcdcfn. 27, 31, 1
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/MC/Mips/mul-macro-variants.s
View file
Original file line number Diff line number Diff line change
Expand Up @@ -117,7 +117,7 @@ text_label:
dmul $4, $5, $6
# CHECK: dmultu $5, $6 # encoding: [0x00,0xa6,0x00,0x1d]
# CHECK: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
# CHECK-TRAP dmultu $5, $6 # encoding: [0x00,0xa6,0x00,0x1d]
# CHECK-TRAP: dmultu $5, $6 # encoding: [0x00,0xa6,0x00,0x1d]
# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
dmul $4, $5, 1
# CHECK: addiu $1, $zero, 1 # encoding: [0x24,0x01,0x00,0x01]
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/ObjectYAML/MachO/fat_macho_i386_x86_64.yaml
View file
Original file line number Diff line number Diff line change
Expand Up @@ -53,7 +53,7 @@ Slices:
#CHECK: align: 12
#CHECK: Slices:
#CHECK: - !mach-o
#CHECK FileHeader:
#CHECK: FileHeader:
#CHECK: magic: 0xFEEDFACE
#CHECK: cputype: 0x00000007
#CHECK: cpusubtype: 0x00000003
Expand All @@ -62,7 +62,7 @@ Slices:
#CHECK: sizeofcmds: 0
#CHECK: flags: 0x01218085
#CHECK: - !mach-o
#CHECK FileHeader:
#CHECK: FileHeader:
#CHECK: magic: 0xFEEDFACF
#CHECK: cputype: 0x01000007
#CHECK: cpusubtype: 0x80000003
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/Transforms/AtomicExpand/SPARC/libcalls.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -86,7 +86,7 @@ define i128 @test_load_i128(i128* %arg) {
ret i128 %ret
}

; CHECK-LABEL @test_store_i128(
; CHECK-LABEL: @test_store_i128(
; CHECK: %1 = bitcast i128* %arg to i8*
; CHECK: %2 = alloca i128, align 8
; CHECK: %3 = bitcast i128* %2 to i8*
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/Transforms/Attributor/nofree.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -51,7 +51,7 @@ define void @only_free(i8* nocapture %0) local_unnamed_addr #0 {

; ATTRIBUTOR: Function Attrs: noinline nounwind uwtable
; ATTRIBUTOR-NOT: nofree
; ATTRIBUTOR-NEXT :define void @free_in_scc1(i8* nocapture %0) local_unnamed_addr
; ATTRIBUTOR-NEXT: define void @free_in_scc1(i8* nocapture %0) local_unnamed_addr
define void @free_in_scc1(i8* nocapture %0) local_unnamed_addr #0 {
tail call void @free_in_scc2(i8* %0) #1
ret void
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/Transforms/CallSiteSplitting/callsite-instructions-before-call.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -201,7 +201,7 @@ End:
; CHECK-LABEL: TBB.split:
; CHECK-NEXT: store i32 %v, i32* %a
; CHECK-NEXT: %[[CALL2:.*]] = call i32 @callee(i32* nonnull %a, i32 1, i32 2)
; CHECK-NEXT br label %Tail
; CHECK-NEXT: br label %Tail
; CHECK-LABEL: Tail:
; CHECK: %[[MERGED:.*]] = phi i32 [ %[[CALL1]], %Header.split ], [ %[[CALL2]], %TBB.split ]
; CHECK: ret i32 %[[MERGED]]
Expand Down Expand Up @@ -239,7 +239,7 @@ End: ; preds = %CallSite, %TBB
; CHECK-NEXT: br label %CallSite
; CHECK-LABEL: TBB.split:
; CHECK: call void @bar(i32* nonnull %ptrarg, i32 %l2)
; CHECK-NEXT br label %CallSite
; CHECK-NEXT: br label %CallSite
; CHECK-LABEL: CallSite:
; CHECK-NEXT: %l = phi i32 [ %l1, %Header.split ], [ %l2, %TBB.split ]
; CHECK: call void @bari(i32 %l)
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/Transforms/CodeExtractor/PartialInlineLiveAcross.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -38,7 +38,7 @@ define i32 @dummy_caller(i32 %arg) local_unnamed_addr #0 {
; CHECK: codeRepl.i:
; CHECK: call void @test.1.bb2()
; CHECK-NOT: load
; CHECK br
; CHECK: br

bb:
%tmp = tail call i32 @test(i32 %arg)
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/Transforms/CodeExtractor/PartialInlineNoLiveOut.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -41,7 +41,7 @@ define i32 @dummy_caller(i32 %arg) local_unnamed_addr #0 {
; CHECK: codeRepl.i:
; CHECK: call void @test.1.bb2()
; CHECK-NOT: load
; CHECK br
; CHECK: br
bb:
%tmp = tail call i32 @test(i32 %arg)
ret i32 %tmp
Expand Down
20 changes: 10 additions & 10 deletions llvm/test/Transforms/EntryExitInstrumenter/mcount.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -30,18 +30,18 @@ entry:
; CHECK: entry:
; CHECK-NEXT: call void @mcount()

; CHECK-NEXT %0 = call i8* @llvm.returnaddress(i32 0)
; CHECK-NEXT call void @__cyg_profile_func_enter(i8* bitcast (void ()* @root_function to i8*), i8* %0)
; CHECK-NEXT: %0 = call i8* @llvm.returnaddress(i32 0)
; CHECK-NEXT: call void @__cyg_profile_func_enter(i8* bitcast (void ()* @root_function to i8*), i8* %0)

; Entry and exit calls, inlined from @leaf_function()
; CHECK-NEXT %1 = call i8* @llvm.returnaddress(i32 0)
; CHECK-NEXT call void @__cyg_profile_func_enter(i8* bitcast (void ()* @leaf_function to i8*), i8* %1)
; CHECK-NEXT %2 = call i8* @llvm.returnaddress(i32 0)
; CHECK-NEXT call void @__cyg_profile_func_exit(i8* bitcast (void ()* @leaf_function to i8*), i8* %2)
; CHECK-NEXT %3 = call i8* @llvm.returnaddress(i32 0)

; CHECK-NEXT call void @__cyg_profile_func_exit(i8* bitcast (void ()* @root_function to i8*), i8* %3)
; CHECK-NEXT ret void
; CHECK-NEXT: %1 = call i8* @llvm.returnaddress(i32 0)
; CHECK-NEXT: call void @__cyg_profile_func_enter(i8* bitcast (void ()* @leaf_function to i8*), i8* %1)
; CHECK-NEXT: %2 = call i8* @llvm.returnaddress(i32 0)
; CHECK-NEXT: call void @__cyg_profile_func_exit(i8* bitcast (void ()* @leaf_function to i8*), i8* %2)
; CHECK-NEXT: %3 = call i8* @llvm.returnaddress(i32 0)

; CHECK-NEXT: call void @__cyg_profile_func_exit(i8* bitcast (void ()* @root_function to i8*), i8* %3)
; CHECK-NEXT: ret void
}


Expand Down
4 changes: 2 additions & 2 deletions llvm/test/Transforms/GuardWidening/loop-schedule.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@
declare void @llvm.experimental.guard(i1,...)

define void @iter(i32 %a, i32 %b, i1* %c_p) {
; CHECK-LABEL @iter
; CHECK-LABEL: @iter
; CHECK: %cond_0 = icmp ult i32 %a, 10
; CHECK: %cond_1 = icmp ult i32 %b, 10
; CHECK: %wide.chk = and i1 %cond_0, %cond_1
Expand All @@ -37,7 +37,7 @@ leave: ; preds = %leave.loopexit, %en
}

define void @within_loop(i32 %a, i32 %b, i1* %c_p) {
; CHECK-LABEL @within_loop
; CHECK-LABEL: @within_loop
; CHECK: %cond_0 = icmp ult i32 %a, 10
; CHECK: %cond_1 = icmp ult i32 %b, 10
; CHECK: %wide.chk = and i1 %cond_0, %cond_1
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/Transforms/InferFunctionAttrs/norecurse_debug.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -53,4 +53,4 @@ attributes #1 = { nounwind readnone speculatable }
!29 = !DILocation(line: 10, column: 1, scope: !2)

; CHECK: attributes #0 = { nofree norecurse nounwind }
; CHECK-NOT foo.coefficient1
; CHECK-NOT: foo.coefficient1
2 changes: 1 addition & 1 deletion llvm/test/Transforms/InstCombine/atomic.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -314,7 +314,7 @@ define void @pr27490b(i8** %p1, i8** %p2) {
;; not representable in the IR. This was pr29121. The right long term
;; solution is to extend the IR to handle this case.
define <2 x float> @no_atomic_vector_load(i64* %p) {
; CHECK-LABEL @no_atomic_vector_load
; CHECK-LABEL: @no_atomic_vector_load
; CHECK: load atomic i64, i64* %p unordered, align 8
%load = load atomic i64, i64* %p unordered, align 8
%.cast = bitcast i64 %load to <2 x float>
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/Transforms/InstCombine/debuginfo-dce2.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -31,7 +31,7 @@ entry:
; CHECK-NOT: bitcast
; CHECK: call void @llvm.dbg.value(metadata i8* %p, metadata ![[Q_VAR:[0-9]+]], metadata !DIExpression())
; CHECK-NOT: bitcast
; CHECK ret void
; CHECK: ret void

; CHECK: ![[P_VAR]] = !DILocalVariable(name: "p", {{.*}})
; CHECK: ![[Q_VAR]] = !DILocalVariable(name: "q", {{.*}})
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/Transforms/InstCombine/intptr1.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -27,7 +27,7 @@ for.body: ; preds = %for.body, %for.body
store float %mul.i, float* %a.addr.03, align 4
%add = getelementptr inbounds float, float* %tmp, i64 1
%add.int = ptrtoint float* %add to i64
; CHECK %add = getelementptr
; CHECK: %add = getelementptr
; CHECK-NOT: ptrtoint float*
%incdec.ptr = getelementptr inbounds float, float* %a.addr.03, i64 1
; CHECK: %incdec.ptr =
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/Transforms/LoopUnroll/peel-loop-negative.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@
; to zero.
define i32 @invariant_backedge_neg_1(i32 %a, i32 %b) {
; CHECK-LABEL: @invariant_backedge_neg_1
; CHECK-NOT loop.peel{{.*}}:
; CHECK-NOT: loop.peel{{.*}}:
; CHECK: loop:
; CHECK: %i = phi
; CHECK: %sum = phi
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/Transforms/LoopVectorize/ARM/prefer-tail-loop-folding.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -200,9 +200,9 @@ define void @narrowing_load_not_allowed(i8* noalias nocapture %A, i8* noalias no
; PREFER-FOLDING: br i1 %{{.*}}, label %{{.*}}, label %vector.body

; FOLDING-OPT: vector.body:
; FOLDING-OPT call <8 x i16> @llvm.masked.load.v8i16.p0v8i16
; FOLDING-OPT call <8 x i8> @llvm.masked.load.v8i8.p0v8i8
; FOLDING-OPT call void @llvm.masked.store.v8i8.p0v8i8
; FOLDING-OPT: call <8 x i16> @llvm.masked.load.v8i16.p0v8i16
; FOLDING-OPT: call <8 x i8> @llvm.masked.load.v8i8.p0v8i8
; FOLDING-OPT: call void @llvm.masked.store.v8i8.p0v8i8
; FOLDING-OPT: br i1 %{{.*}}, label %{{.*}}, label %vector.body
entry:
br label %for.body
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/Transforms/LoopVectorize/debugloc.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
; CHECK: add <2 x i32> %{{.*}}, %rdx.shuf, !dbg ![[BR_LOC:[0-9]+]]
; CHECK: extractelement <2 x i32> %bin.rdx, i32 0, !dbg ![[BR_LOC]]
; CHECK: for.body
; CHECK br i1{{.*}}, label %for.body,{{.*}}, !dbg ![[BR_LOC]],
; CHECK: br i1{{.*}}, label %for.body,{{.*}}, !dbg ![[BR_LOC]],
; CHECK: ![[BR_LOC]] = !DILocation(line: 5,

define i32 @f(i32* nocapture %a, i32 %size) #0 !dbg !4 {
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/Transforms/LoopVectorize/first-order-recurrence-complex.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -129,7 +129,7 @@ define void @cannot_sink_with_additional_user(i32 %x, i32* %ptr, i64 %tc) {
; CHECK: br label %for

; CHECK-LABEL: for: ; preds = %for, %preheader
; CHECK br i1 %exitcond, label %exit, label %for
; CHECK: br i1 %exitcond, label %exit, label %for

; CHECK-LABEL: exit:
; CHECK-NEXT: ret void
Expand Down Expand Up @@ -172,7 +172,7 @@ define void @cannot_sink_store(i32 %x, i32* %ptr, i64 %tc) {
; CHECK: br label %for

; CHECK-LABEL: for: ; preds = %for, %preheader
; CHECK br i1 %exitcond, label %exit, label %for
; CHECK: br i1 %exitcond, label %exit, label %for

; CHECK-LABEL: exit:
; CHECK-NEXT: ret void
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/Transforms/LoopVectorize/followup.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -29,7 +29,7 @@ for.end:
!5 = !{!"llvm.loop.vectorize.followup_all", !{!"FollowupAll"}}


; CHECK-LABEL @followup(
; CHECK-LABEL: @followup(

; CHECK-LABEL: vector.body:
; CHECK: br i1 %13, label %middle.block, label %vector.body, !llvm.loop ![[LOOP_VECTOR:[0-9]+]]
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/Transforms/PGOProfile/icp_invoke.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -101,6 +101,6 @@ declare void @__cxa_end_catch()
!1 = !{!"invoke.ll:_ZL4bar2v"}
!2 = !{!"VP", i32 0, i64 1, i64 -2732222848796217051, i64 1}
!3 = !{!"VP", i32 0, i64 1, i64 -6116256810522035449, i64 1}
; ICP-NOT !3 = !{!"VP", i32 0, i64 1, i64 -2732222848796217051, i64 1}
; ICP-NOT !4 = !{!"VP", i32 0, i64 1, i64 -6116256810522035449, i64 1}
; ICP-NOT: !3 = !{!"VP", i32 0, i64 1, i64 -2732222848796217051, i64 1}
; ICP-NOT: !4 = !{!"VP", i32 0, i64 1, i64 -6116256810522035449, i64 1}
; ICP: [[BRANCH_WEIGHT]] = !{!"branch_weights", i32 1, i32 0}
2 changes: 1 addition & 1 deletion llvm/test/Transforms/PGOProfile/memop_clone.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@ define i32 @test(i8* %a, i8* %b) !prof !1 {
; CHECK: tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* undef, i8* %a, i32 undef, i1 false)
; CHECK: MemOP.Case.33:
; CHECK: tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* undef, i8* %b, i64 3, i1 false)
; CHECK MemOP.Case.24:
; CHECK: MemOP.Case.24:
; CHECK: tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* undef, i8* %b, i64 2, i1 false)
; CHECK: MemOP.Default2:
; CHECK: tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* undef, i8* %b, i64 undef, i1 false)
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/Transforms/SimplifyCFG/Hexagon/switch-to-lookup-table.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@

; ENABLE: @{{.*}} = private unnamed_addr constant [6 x i32] [i32 9, i32 20, i32 14, i32 22, i32 12, i32 5]
; DISABLE-NOT: @{{.*}} = private unnamed_addr constant [6 x i32] [i32 9, i32 20, i32 14, i32 22, i32 12, i32 5]
; DISABLE : = phi i32 [ 19, %{{.*}} ], [ 5, %{{.*}} ], [ 12, %{{.*}} ], [ 22, %{{.*}} ], [ 14, %{{.*}} ], [ 20, %{{.*}} ], [ 9, %{{.*}} ]
; DISABLE: = phi i32 [ 19, %{{.*}} ], [ 5, %{{.*}} ], [ 12, %{{.*}} ], [ 22, %{{.*}} ], [ 14, %{{.*}} ], [ 20, %{{.*}} ], [ 9, %{{.*}} ]

target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
target triple = "hexagon-unknown--elf"
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/Transforms/SimplifyCFG/pr33605.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -27,7 +27,7 @@
; CHECK: br label %if.end
; CHECK-NOT: br label %for.cond
; CHECK: if.end:
; CHECK br label %for.cond
; CHECK: br label %for.cond
define i1 @test(i32 %a, i32 %b, i32* %c) {
entry:
br label %for.cond
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/tools/llvm-dwarfdump/X86/statistics.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -44,7 +44,7 @@
; Because of the dbg.value in the middle of the function, the pc range coverage
; must be below 100%.
; CHECK-NOT: "scope bytes covered":0
; CHECK-NOT "scope bytes covered":[[BYTES]]
; CHECK-NOT: "scope bytes covered":[[BYTES]]
; CHECK: "scope bytes covered":
; CHECK: "total function size":[[FUNCSIZE:[0-9]+]]
; CHECK: "total inlined function size":[[INLINESIZE:[0-9]+]]
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/tools/llvm-profdata/value-prof.proftext
View file
Original file line number Diff line number Diff line change
Expand Up @@ -77,5 +77,5 @@ bar
#ICSUM: Total number of sites with values: 2
#ICSUM: Total number of profiled values: 3
#ICSUM: NumTargets, SiteCount
#ICSUM 1, 1
#ICSUM 2, 1
#ICSUM: 1, 1
#ICSUM: 2, 1
2 changes: 1 addition & 1 deletion llvm/test/tools/llvm-symbolizer/sym.test
View file
Original file line number Diff line number Diff line change
Expand Up @@ -56,7 +56,7 @@ RUN: llvm-addr2line -pafi -obj=%p/Inputs/addr.exe < %p/Inputs/addr.inp | FileChe
#PRETTY: some text
#PRETTY: {{[0x]+}}40054d: inctwo at {{[/\]+}}tmp{{[/\]+}}x.c:3:3
#PRETTY: (inlined by) inc at {{[/\]+}}tmp{{[/\]+}}x.c:7:0
#PRETTY (inlined by) main at {{[/\]+}}tmp{{[/\]+}}x.c:14:0
#PRETTY: (inlined by) main at {{[/\]+}}tmp{{[/\]+}}x.c:14:0
#PRETTY: some text2
#
#ZERO: ??
Expand Down
2 changes: 1 addition & 1 deletion llvm/tools/llvm-objdump/XCOFFDump.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@

namespace llvm {

class SymbolInfoTy;
struct SymbolInfoTy;

namespace objdump {
Optional<XCOFF::StorageMappingClass>
Expand Down