18 changes: 9 additions & 9 deletions llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v128.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -26,9 +26,9 @@ alignment: 16
legalized: false
regBankSelected: false
# ALL: registers:
# ALL-NEXT: - { id: 0, class: _, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: _, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: _, preferred-register: '' }
# ALL-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] }
# ALL-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] }
# ALL-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
Expand Down Expand Up @@ -56,9 +56,9 @@ alignment: 16
legalized: false
regBankSelected: false
# ALL: registers:
# ALL-NEXT: - { id: 0, class: _, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: _, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: _, preferred-register: '' }
# ALL-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] }
# ALL-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] }
# ALL-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
Expand Down Expand Up @@ -86,9 +86,9 @@ alignment: 16
legalized: false
regBankSelected: false
# ALL: registers:
# ALL-NEXT: - { id: 0, class: _, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: _, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: _, preferred-register: '' }
# ALL-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] }
# ALL-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] }
# ALL-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
Expand Down
18 changes: 9 additions & 9 deletions llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v256.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -26,9 +26,9 @@ alignment: 16
legalized: false
regBankSelected: false
# ALL: registers:
# ALL-NEXT: - { id: 0, class: _, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: _, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: _, preferred-register: '' }
# ALL-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] }
# ALL-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] }
# ALL-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
Expand Down Expand Up @@ -56,9 +56,9 @@ alignment: 16
legalized: false
regBankSelected: false
# ALL: registers:
# ALL-NEXT: - { id: 0, class: _, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: _, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: _, preferred-register: '' }
# ALL-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] }
# ALL-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] }
# ALL-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
Expand Down Expand Up @@ -86,9 +86,9 @@ alignment: 16
legalized: false
regBankSelected: false
# ALL: registers:
# ALL-NEXT: - { id: 0, class: _, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: _, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: _, preferred-register: '' }
# ALL-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] }
# ALL-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] }
# ALL-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
Expand Down
18 changes: 9 additions & 9 deletions llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v512.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -28,9 +28,9 @@ alignment: 16
legalized: false
regBankSelected: false
# ALL: registers:
# ALL-NEXT: - { id: 0, class: _, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: _, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: _, preferred-register: '' }
# ALL-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] }
# ALL-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] }
# ALL-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
Expand Down Expand Up @@ -58,9 +58,9 @@ alignment: 16
legalized: false
regBankSelected: false
# ALL: registers:
# ALL-NEXT: - { id: 0, class: _, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: _, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: _, preferred-register: '' }
# ALL-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] }
# ALL-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] }
# ALL-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
Expand Down Expand Up @@ -88,9 +88,9 @@ alignment: 16
legalized: false
regBankSelected: false
# ALL: registers:
# ALL-NEXT: - { id: 0, class: _, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: _, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: _, preferred-register: '' }
# ALL-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] }
# ALL-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] }
# ALL-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
Expand Down
20 changes: 10 additions & 10 deletions llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -33,8 +33,8 @@ selected: false
tracksRegLiveness: true
# CHECK-LABEL: name: test_mul_vec256
# CHECK: registers:
# CHECK: - { id: 0, class: vecr, preferred-register: '' }
# CHECK: - { id: 1, class: vecr, preferred-register: '' }
# CHECK: - { id: 0, class: vecr, preferred-register: '', flags: [ ] }
# CHECK: - { id: 1, class: vecr, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
Expand All @@ -56,8 +56,8 @@ selected: false
tracksRegLiveness: true
# CHECK-LABEL: name: test_add_vec256
# CHECK: registers:
# CHECK: - { id: 0, class: vecr, preferred-register: '' }
# CHECK: - { id: 1, class: vecr, preferred-register: '' }
# CHECK: - { id: 0, class: vecr, preferred-register: '', flags: [ ] }
# CHECK: - { id: 1, class: vecr, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
Expand All @@ -79,8 +79,8 @@ selected: false
tracksRegLiveness: true
# CHECK-LABEL: name: test_sub_vec256
# CHECK: registers:
# CHECK: - { id: 0, class: vecr, preferred-register: '' }
# CHECK: - { id: 1, class: vecr, preferred-register: '' }
# CHECK: - { id: 0, class: vecr, preferred-register: '', flags: [ ] }
# CHECK: - { id: 1, class: vecr, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
Expand All @@ -100,8 +100,8 @@ alignment: 16
legalized: true
regBankSelected: false
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' }
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '', flags: [ ] }
# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
Expand All @@ -122,8 +122,8 @@ alignment: 16
legalized: true
regBankSelected: false
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '', flags: [ ] }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
Expand Down
20 changes: 10 additions & 10 deletions llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -33,8 +33,8 @@ alignment: 16
legalized: true
regBankSelected: false
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' }
# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '', flags: [ ] }
# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
Expand All @@ -53,8 +53,8 @@ alignment: 16
legalized: true
regBankSelected: false
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' }
# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '', flags: [ ] }
# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
Expand All @@ -73,8 +73,8 @@ alignment: 16
legalized: true
regBankSelected: false
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' }
# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '', flags: [ ] }
# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
Expand All @@ -93,8 +93,8 @@ alignment: 16
legalized: true
regBankSelected: false
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' }
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '', flags: [ ] }
# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
Expand All @@ -115,8 +115,8 @@ alignment: 16
legalized: true
regBankSelected: false
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '', flags: [ ] }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/X86/GlobalISel/regbankselect-X32.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -14,11 +14,11 @@ alignment: 16
legalized: true
regBankSelected: false
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 4, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '', flags: [ ] }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '', flags: [ ] }
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '', flags: [ ] }
# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '', flags: [ ] }
# CHECK-NEXT: - { id: 4, class: gpr, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/X86/GlobalISel/select-GV-32.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -25,12 +25,12 @@ alignment: 16
legalized: true
regBankSelected: true
# X32: registers:
# X32-NEXT: - { id: 0, class: gr32, preferred-register: '' }
# X32-NEXT: - { id: 1, class: gr32, preferred-register: '' }
# X32-NEXT: - { id: 0, class: gr32, preferred-register: '', flags: [ ] }
# X32-NEXT: - { id: 1, class: gr32, preferred-register: '', flags: [ ] }
#
# X32ABI: registers:
# X32ABI-NEXT: - { id: 0, class: low32_addr_access, preferred-register: '' }
# X32ABI-NEXT: - { id: 1, class: gr32, preferred-register: '' }
# X32ABI-NEXT: - { id: 0, class: low32_addr_access, preferred-register: '', flags: [ ] }
# X32ABI-NEXT: - { id: 1, class: gr32, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: gpr, preferred-register: '' }
- { id: 1, class: gpr, preferred-register: '' }
Expand Down Expand Up @@ -60,8 +60,8 @@ alignment: 16
legalized: true
regBankSelected: true
# X32ALL: registers:
# X32ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' }
# X32ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
# X32ALL-NEXT: - { id: 0, class: gr32, preferred-register: '', flags: [ ] }
# X32ALL-NEXT: - { id: 1, class: gr32, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: gpr, preferred-register: '' }
- { id: 1, class: gpr, preferred-register: '' }
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/X86/GlobalISel/select-GV-64.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -25,8 +25,8 @@ alignment: 16
legalized: true
regBankSelected: true
# X64ALL: registers:
# X64ALL-NEXT: - { id: 0, class: gr64, preferred-register: '' }
# X64ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' }
# X64ALL-NEXT: - { id: 0, class: gr64, preferred-register: '', flags: [ ] }
# X64ALL-NEXT: - { id: 1, class: gr64, preferred-register: '', flags: [ ] }
#
registers:
- { id: 0, class: gpr, preferred-register: '' }
Expand Down Expand Up @@ -58,8 +58,8 @@ alignment: 16
legalized: true
regBankSelected: true
# X64ALL: registers:
# X64ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' }
# X64ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' }
# X64ALL-NEXT: - { id: 0, class: gr32, preferred-register: '', flags: [ ] }
# X64ALL-NEXT: - { id: 1, class: gr64, preferred-register: '', flags: [ ] }
#
registers:
- { id: 0, class: gpr, preferred-register: '' }
Expand Down
72 changes: 36 additions & 36 deletions llvm/test/CodeGen/X86/GlobalISel/select-add-v128.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -32,19 +32,19 @@ alignment: 16
legalized: true
regBankSelected: true
# NOVL: registers:
# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' }
# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' }
# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' }
# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '', flags: [ ] }
# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '', flags: [ ] }
# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '', flags: [ ] }
#
# AVX512VL: registers:
# AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '' }
# AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '' }
# AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '' }
# AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '', flags: [ ] }
# AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '', flags: [ ] }
# AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '', flags: [ ] }
#
# AVX512BWVL: registers:
# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '', flags: [ ] }
# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '', flags: [ ] }
# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
Expand Down Expand Up @@ -74,19 +74,19 @@ alignment: 16
legalized: true
regBankSelected: true
# NOVL: registers:
# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' }
# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' }
# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' }
# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '', flags: [ ] }
# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '', flags: [ ] }
# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '', flags: [ ] }
#
# AVX512VL: registers:
# AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '' }
# AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '' }
# AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '' }
# AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '', flags: [ ] }
# AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '', flags: [ ] }
# AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '', flags: [ ] }
#
# AVX512BWVL: registers:
# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '', flags: [ ] }
# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '', flags: [ ] }
# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
Expand Down Expand Up @@ -116,19 +116,19 @@ alignment: 16
legalized: true
regBankSelected: true
# NOVL: registers:
# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' }
# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' }
# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' }
# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '', flags: [ ] }
# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '', flags: [ ] }
# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '', flags: [ ] }
#
# AVX512VL: registers:
# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '', flags: [ ] }
# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '', flags: [ ] }
# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '', flags: [ ] }
#
# AVX512BWVL: registers:
# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '', flags: [ ] }
# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '', flags: [ ] }
# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
Expand Down Expand Up @@ -158,19 +158,19 @@ alignment: 16
legalized: true
regBankSelected: true
# NOVL: registers:
# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' }
# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' }
# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' }
# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '', flags: [ ] }
# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '', flags: [ ] }
# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '', flags: [ ] }
#
# AVX512VL: registers:
# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '', flags: [ ] }
# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '', flags: [ ] }
# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '', flags: [ ] }
#
# AVX512BWVL: registers:
# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '', flags: [ ] }
# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '', flags: [ ] }
# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
Expand Down
72 changes: 36 additions & 36 deletions llvm/test/CodeGen/X86/GlobalISel/select-add-v256.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -30,19 +30,19 @@ alignment: 16
legalized: true
regBankSelected: true
# AVX2: registers:
# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' }
# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' }
# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' }
# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '', flags: [ ] }
# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '', flags: [ ] }
# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '', flags: [ ] }
#
# AVX512VL: registers:
# AVX512VL-NEXT: - { id: 0, class: vr256, preferred-register: '' }
# AVX512VL-NEXT: - { id: 1, class: vr256, preferred-register: '' }
# AVX512VL-NEXT: - { id: 2, class: vr256, preferred-register: '' }
# AVX512VL-NEXT: - { id: 0, class: vr256, preferred-register: '', flags: [ ] }
# AVX512VL-NEXT: - { id: 1, class: vr256, preferred-register: '', flags: [ ] }
# AVX512VL-NEXT: - { id: 2, class: vr256, preferred-register: '', flags: [ ] }
#
# AVX512BWVL: registers:
# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '', flags: [ ] }
# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '', flags: [ ] }
# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
Expand Down Expand Up @@ -70,19 +70,19 @@ alignment: 16
legalized: true
regBankSelected: true
# AVX2: registers:
# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' }
# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' }
# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' }
# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '', flags: [ ] }
# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '', flags: [ ] }
# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '', flags: [ ] }
#
# AVX512VL: registers:
# AVX512VL-NEXT: - { id: 0, class: vr256, preferred-register: '' }
# AVX512VL-NEXT: - { id: 1, class: vr256, preferred-register: '' }
# AVX512VL-NEXT: - { id: 2, class: vr256, preferred-register: '' }
# AVX512VL-NEXT: - { id: 0, class: vr256, preferred-register: '', flags: [ ] }
# AVX512VL-NEXT: - { id: 1, class: vr256, preferred-register: '', flags: [ ] }
# AVX512VL-NEXT: - { id: 2, class: vr256, preferred-register: '', flags: [ ] }
#
# AVX512BWVL: registers:
# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '', flags: [ ] }
# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '', flags: [ ] }
# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
Expand Down Expand Up @@ -110,19 +110,19 @@ alignment: 16
legalized: true
regBankSelected: true
# AVX2: registers:
# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' }
# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' }
# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' }
# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '', flags: [ ] }
# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '', flags: [ ] }
# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '', flags: [ ] }
#
# AVX512VL: registers:
# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
# AVX512VL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '', flags: [ ] }
# AVX512VL-NEXT: - { id: 1, class: vr256x, preferred-register: '', flags: [ ] }
# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: '', flags: [ ] }
#
# AVX512BWVL: registers:
# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '', flags: [ ] }
# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '', flags: [ ] }
# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
Expand Down Expand Up @@ -150,19 +150,19 @@ alignment: 16
legalized: true
regBankSelected: true
# AVX2: registers:
# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' }
# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' }
# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' }
# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '', flags: [ ] }
# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '', flags: [ ] }
# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '', flags: [ ] }
#
# AVX512VL: registers:
# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
# AVX512VL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '', flags: [ ] }
# AVX512VL-NEXT: - { id: 1, class: vr256x, preferred-register: '', flags: [ ] }
# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: '', flags: [ ] }
#
# AVX512BWVL: registers:
# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '', flags: [ ] }
# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '', flags: [ ] }
# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
Expand Down
38 changes: 19 additions & 19 deletions llvm/test/CodeGen/X86/GlobalISel/select-copy.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -35,8 +35,8 @@ alignment: 16
legalized: true
regBankSelected: true
# ALL: registers:
# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '', flags: [ ] }
# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: gpr, preferred-register: '' }
- { id: 1, class: gpr, preferred-register: '' }
Expand All @@ -61,8 +61,8 @@ alignment: 16
legalized: true
regBankSelected: true
# ALL: registers:
# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '', flags: [ ] }
# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: gpr, preferred-register: '' }
- { id: 1, class: gpr, preferred-register: '' }
Expand All @@ -87,10 +87,10 @@ alignment: 16
legalized: true
regBankSelected: true
# ALL: registers:
# ALL-NEXT: - { id: 0, class: gr16[[ABCD:(_abcd)?]], preferred-register: '' }
# X32-NEXT: - { id: 1, class: gr8_abcd_l, preferred-register: '' }
# X64-NEXT: - { id: 1, class: gr8, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' }
# ALL-NEXT: - { id: 0, class: gr16[[ABCD:(_abcd)?]], preferred-register: '', flags: [ ] }
# X32-NEXT: - { id: 1, class: gr8_abcd_l, preferred-register: '', flags: [ ] }
# X64-NEXT: - { id: 1, class: gr8, preferred-register: '', flags: [ ] }
# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: gpr, preferred-register: '' }
- { id: 1, class: gpr, preferred-register: '' }
Expand Down Expand Up @@ -120,9 +120,9 @@ alignment: 16
legalized: true
regBankSelected: true
# ALL: registers:
# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: gr16, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' }
# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '', flags: [ ] }
# ALL-NEXT: - { id: 1, class: gr16, preferred-register: '', flags: [ ] }
# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: gpr, preferred-register: '' }
- { id: 1, class: gpr, preferred-register: '' }
Expand Down Expand Up @@ -150,10 +150,10 @@ alignment: 16
legalized: true
regBankSelected: true
# ALL: registers:
# ALL-NEXT: - { id: 0, class: gr32[[ABCD:(_abcd)?]], preferred-register: '' }
# X32-NEXT: - { id: 1, class: gr8_abcd_l, preferred-register: '' }
# X64-NEXT: - { id: 1, class: gr8, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' }
# ALL-NEXT: - { id: 0, class: gr32[[ABCD:(_abcd)?]], preferred-register: '', flags: [ ] }
# X32-NEXT: - { id: 1, class: gr8_abcd_l, preferred-register: '', flags: [ ] }
# X64-NEXT: - { id: 1, class: gr8, preferred-register: '', flags: [ ] }
# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: gpr, preferred-register: '' }
- { id: 1, class: gpr, preferred-register: '' }
Expand Down Expand Up @@ -183,10 +183,10 @@ alignment: 16
legalized: true
regBankSelected: true
# ALL: registers:
# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: gr16, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: low32_addr_access_rbp, preferred-register: '' }
# ALL-NEXT: - { id: 3, class: low32_addr_access_rbp, preferred-register: '' }
# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '', flags: [ ] }
# ALL-NEXT: - { id: 1, class: gr16, preferred-register: '', flags: [ ] }
# ALL-NEXT: - { id: 2, class: low32_addr_access_rbp, preferred-register: '', flags: [ ] }
# ALL-NEXT: - { id: 3, class: low32_addr_access_rbp, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: gpr, preferred-register: '' }
- { id: 1, class: gpr, preferred-register: '' }
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/X86/GlobalISel/select-extract-vec256.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -18,12 +18,12 @@ alignment: 16
legalized: true
regBankSelected: true
# AVX: registers:
# AVX-NEXT: - { id: 0, class: vr256, preferred-register: '' }
# AVX-NEXT: - { id: 1, class: vr128, preferred-register: '' }
# AVX-NEXT: - { id: 0, class: vr256, preferred-register: '', flags: [ ] }
# AVX-NEXT: - { id: 1, class: vr128, preferred-register: '', flags: [ ] }
#
# AVX512VL: registers:
# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '', flags: [ ] }
# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
Expand All @@ -50,12 +50,12 @@ alignment: 16
legalized: true
regBankSelected: true
# AVX: registers:
# AVX-NEXT: - { id: 0, class: vr256, preferred-register: '' }
# AVX-NEXT: - { id: 1, class: vr128, preferred-register: '' }
# AVX-NEXT: - { id: 0, class: vr256, preferred-register: '', flags: [ ] }
# AVX-NEXT: - { id: 1, class: vr128, preferred-register: '', flags: [ ] }
#
# AVX512VL: registers:
# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '', flags: [ ] }
# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/X86/GlobalISel/select-extract-vec512.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -27,8 +27,8 @@ alignment: 16
legalized: true
regBankSelected: true
# ALL: registers:
# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '', flags: [ ] }
# ALL-NEXT: - { id: 1, class: vr128x, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
Expand All @@ -53,8 +53,8 @@ alignment: 16
legalized: true
regBankSelected: true
# ALL: registers:
# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '', flags: [ ] }
# ALL-NEXT: - { id: 1, class: vr128x, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
Expand All @@ -79,8 +79,8 @@ alignment: 16
legalized: true
regBankSelected: true
# ALL: registers:
# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '', flags: [ ] }
# ALL-NEXT: - { id: 1, class: vr256x, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
Expand All @@ -105,8 +105,8 @@ alignment: 16
legalized: true
regBankSelected: true
# ALL: registers:
# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '', flags: [ ] }
# ALL-NEXT: - { id: 1, class: vr256x, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/X86/GlobalISel/select-inc.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,10 +13,10 @@ name: test_add_i8
legalized: true
regBankSelected: true
# ALL: registers:
# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' }
# INC-NEXT: - { id: 1, class: gpr, preferred-register: '' }
# ADD-NEXT: - { id: 1, class: gpr, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: gr8, preferred-register: '' }
# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '', flags: [ ] }
# INC-NEXT: - { id: 1, class: gpr, preferred-register: '', flags: [ ] }
# ADD-NEXT: - { id: 1, class: gpr, preferred-register: '', flags: [ ] }
# ALL-NEXT: - { id: 2, class: gr8, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
Expand Down
24 changes: 12 additions & 12 deletions llvm/test/CodeGen/X86/GlobalISel/select-memop-v256.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -33,12 +33,12 @@ alignment: 16
legalized: true
regBankSelected: true
# NO_AVX512F: registers:
# NO_AVX512F-NEXT: - { id: 0, class: gr64, preferred-register: '' }
# NO_AVX512F-NEXT: - { id: 1, class: vr256, preferred-register: '' }
# NO_AVX512F-NEXT: - { id: 0, class: gr64, preferred-register: '', flags: [ ] }
# NO_AVX512F-NEXT: - { id: 1, class: vr256, preferred-register: '', flags: [ ] }
#
# AVX512ALL: registers:
# AVX512ALL-NEXT: - { id: 0, class: gr64, preferred-register: '' }
# AVX512ALL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
# AVX512ALL-NEXT: - { id: 0, class: gr64, preferred-register: '', flags: [ ] }
# AVX512ALL-NEXT: - { id: 1, class: vr256x, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: gpr }
- { id: 1, class: vecr }
Expand Down Expand Up @@ -106,12 +106,12 @@ alignment: 16
legalized: true
regBankSelected: true
# NO_AVX512F: registers:
# NO_AVX512F-NEXT: - { id: 0, class: vr256, preferred-register: '' }
# NO_AVX512F-NEXT: - { id: 1, class: gr64, preferred-register: '' }
# NO_AVX512F-NEXT: - { id: 0, class: vr256, preferred-register: '', flags: [ ] }
# NO_AVX512F-NEXT: - { id: 1, class: gr64, preferred-register: '', flags: [ ] }
#
# AVX512ALL: registers:
# AVX512ALL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
# AVX512ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' }
# AVX512ALL-NEXT: - { id: 0, class: vr256x, preferred-register: '', flags: [ ] }
# AVX512ALL-NEXT: - { id: 1, class: gr64, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: vecr }
- { id: 1, class: gpr }
Expand Down Expand Up @@ -146,12 +146,12 @@ alignment: 16
legalized: true
regBankSelected: true
# NO_AVX512F: registers:
# NO_AVX512F-NEXT: - { id: 0, class: vr256, preferred-register: '' }
# NO_AVX512F-NEXT: - { id: 1, class: gr64, preferred-register: '' }
# NO_AVX512F-NEXT: - { id: 0, class: vr256, preferred-register: '', flags: [ ] }
# NO_AVX512F-NEXT: - { id: 1, class: gr64, preferred-register: '', flags: [ ] }
#
# AVX512ALL: registers:
# AVX512ALL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
# AVX512ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' }
# AVX512ALL-NEXT: - { id: 0, class: vr256x, preferred-register: '', flags: [ ] }
# AVX512ALL-NEXT: - { id: 1, class: gr64, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: vecr }
- { id: 1, class: gpr }
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/X86/GlobalISel/x86-legalize-GV.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,7 @@ alignment: 16
legalized: false
regBankSelected: false
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: _, preferred-register: '' }
# CHECK-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _, preferred-register: '' }
# CHECK: %0:_(p0) = G_GLOBAL_VALUE @g_int
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-GV.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,7 @@ alignment: 16
legalized: false
regBankSelected: false
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: _, preferred-register: '' }
# CHECK-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _, preferred-register: '' }
# CHECK: %0:_(p0) = G_GLOBAL_VALUE @g_int
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/tools/llvm-reduce/mir/preserve-reg-hints.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,11 +7,11 @@
# Make sure that register hints are preserved in the cloned function.

# RESULT: registers:
# RESULT-NEXT: - { id: 0, class: vgpr_32, preferred-register: '$vgpr0' }
# RESULT-NEXT: - { id: 1, class: vgpr_32, preferred-register: '' }
# RESULT-NEXT: - { id: 2, class: vgpr_32, preferred-register: '%1' }
# RESULT-NEXT: - { id: 3, class: vgpr_32, preferred-register: '%4' }
# RESULT-NEXT: - { id: 4, class: vgpr_32, preferred-register: '%3' }
# RESULT-NEXT: - { id: 0, class: vgpr_32, preferred-register: '$vgpr0', flags: [ ] }
# RESULT-NEXT: - { id: 1, class: vgpr_32, preferred-register: '', flags: [ ] }
# RESULT-NEXT: - { id: 2, class: vgpr_32, preferred-register: '%1', flags: [ ] }
# RESULT-NEXT: - { id: 3, class: vgpr_32, preferred-register: '%4', flags: [ ] }
# RESULT-NEXT: - { id: 4, class: vgpr_32, preferred-register: '%3', flags: [ ] }
---
name: register_hints
tracksRegLiveness: true
Expand Down
3 changes: 0 additions & 3 deletions mlir/include/mlir/Dialect/Linalg/IR/CMakeLists.txt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,13 +15,10 @@ function(add_linalg_ods_yaml_gen yaml_ast_file output_file)
MAIN_DEPENDENCY
${YAML_AST_SOURCE}
DEPENDS
${MLIR_LINALG_ODS_YAML_GEN_EXE}
${MLIR_LINALG_ODS_YAML_GEN_TARGET})
add_custom_target(
MLIR${output_file}YamlIncGen
DEPENDS
${MLIR_LINALG_ODS_YAML_GEN_EXE}
${MLIR_LINALG_ODS_YAML_GEN_TARGET}
${GEN_ODS_FILE} ${GEN_CPP_FILE})
set_target_properties(MLIR${output_file}YamlIncGen PROPERTIES FOLDER "MLIR/Tablegenning")
list(APPEND LLVM_TARGET_DEPENDS ${GEN_ODS_FILE})
Expand Down