11 changes: 11 additions & 0 deletions llvm/lib/Target/SystemZ/SystemZInstrFormats.td
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Original file line number Diff line number Diff line change
Expand Up @@ -473,6 +473,17 @@ class InstSS<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{15-0} = BD2;
}

class InstS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<4, outs, ins, asmstr, pattern> {
field bits<32> Inst;
field bits<32> SoftFail = 0;

bits<16> BD2;

let Inst{31-16} = op;
let Inst{15-0} = BD2;
}

//===----------------------------------------------------------------------===//
// Instruction definitions with semantics
//===----------------------------------------------------------------------===//
Expand Down
54 changes: 54 additions & 0 deletions llvm/lib/Target/SystemZ/SystemZInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1361,6 +1361,60 @@ let Defs = [CC] in {
def CSG : CmpSwapRSY<"csg", 0xEB30, atomic_cmp_swap_64, GR64>;
}

//===----------------------------------------------------------------------===//
// Transactional execution
//===----------------------------------------------------------------------===//

let Predicates = [FeatureTransactionalExecution] in {
// Transaction Begin
let hasSideEffects = 1, mayStore = 1,
usesCustomInserter = 1, Defs = [CC] in {
def TBEGIN : InstSIL<0xE560,
(outs), (ins bdaddr12only:$BD1, imm32zx16:$I2),
"tbegin\t$BD1, $I2",
[(z_tbegin bdaddr12only:$BD1, imm32zx16:$I2)]>;
def TBEGIN_nofloat : Pseudo<(outs), (ins bdaddr12only:$BD1, imm32zx16:$I2),
[(z_tbegin_nofloat bdaddr12only:$BD1,
imm32zx16:$I2)]>;
def TBEGINC : InstSIL<0xE561,
(outs), (ins bdaddr12only:$BD1, imm32zx16:$I2),
"tbeginc\t$BD1, $I2",
[(int_s390_tbeginc bdaddr12only:$BD1,
imm32zx16:$I2)]>;
}

// Transaction End
let hasSideEffects = 1, Defs = [CC], BD2 = 0 in
def TEND : InstS<0xB2F8, (outs), (ins), "tend", [(z_tend)]>;

// Transaction Abort
let hasSideEffects = 1, isTerminator = 1, isBarrier = 1 in
def TABORT : InstS<0xB2FC, (outs), (ins bdaddr12only:$BD2),
"tabort\t$BD2",
[(int_s390_tabort bdaddr12only:$BD2)]>;

// Nontransactional Store
let hasSideEffects = 1 in
def NTSTG : StoreRXY<"ntstg", 0xE325, int_s390_ntstg, GR64, 8>;

// Extract Transaction Nesting Depth
let hasSideEffects = 1 in
def ETND : InherentRRE<"etnd", 0xB2EC, GR32, (int_s390_etnd)>;
}

//===----------------------------------------------------------------------===//
// Processor assist
//===----------------------------------------------------------------------===//

let Predicates = [FeatureProcessorAssist] in {
let hasSideEffects = 1, R4 = 0 in
def PPA : InstRRF<0xB2E8, (outs), (ins GR64:$R1, GR64:$R2, imm32zx4:$R3),
"ppa\t$R1, $R2, $R3", []>;
def : Pat<(int_s390_ppa_txassist GR32:$src),
(PPA (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32),
0, 1)>;
}

//===----------------------------------------------------------------------===//
// Miscellaneous Instructions.
//===----------------------------------------------------------------------===//
Expand Down
12 changes: 12 additions & 0 deletions llvm/lib/Target/SystemZ/SystemZOperators.td
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Original file line number Diff line number Diff line change
Expand Up @@ -79,6 +79,9 @@ def SDT_ZI32Intrinsic : SDTypeProfile<1, 0, [SDTCisVT<0, i32>]>;
def SDT_ZPrefetch : SDTypeProfile<0, 2,
[SDTCisVT<0, i32>,
SDTCisPtrTy<1>]>;
def SDT_ZTBegin : SDTypeProfile<0, 2,
[SDTCisPtrTy<0>,
SDTCisVT<1, i32>]>;

//===----------------------------------------------------------------------===//
// Node definitions
Expand Down Expand Up @@ -180,6 +183,15 @@ def z_prefetch : SDNode<"SystemZISD::PREFETCH", SDT_ZPrefetch,
[SDNPHasChain, SDNPMayLoad, SDNPMayStore,
SDNPMemOperand]>;

def z_tbegin : SDNode<"SystemZISD::TBEGIN", SDT_ZTBegin,
[SDNPHasChain, SDNPOutGlue, SDNPMayStore,
SDNPSideEffect]>;
def z_tbegin_nofloat : SDNode<"SystemZISD::TBEGIN_NOFLOAT", SDT_ZTBegin,
[SDNPHasChain, SDNPOutGlue, SDNPMayStore,
SDNPSideEffect]>;
def z_tend : SDNode<"SystemZISD::TEND", SDTNone,
[SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;

//===----------------------------------------------------------------------===//
// Pattern fragments
//===----------------------------------------------------------------------===//
Expand Down
13 changes: 12 additions & 1 deletion llvm/lib/Target/SystemZ/SystemZProcessors.td
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Original file line number Diff line number Diff line change
Expand Up @@ -60,6 +60,16 @@ def FeatureMiscellaneousExtensions : SystemZFeature<
"Assume that the miscellaneous-extensions facility is installed"
>;

def FeatureTransactionalExecution : SystemZFeature<
"transactional-execution", "TransactionalExecution",
"Assume that the transactional-execution facility is installed"
>;

def FeatureProcessorAssist : SystemZFeature<
"processor-assist", "ProcessorAssist",
"Assume that the processor-assist facility is installed"
>;

def : Processor<"generic", NoItineraries, []>;
def : Processor<"z10", NoItineraries, []>;
def : Processor<"z196", NoItineraries,
Expand All @@ -70,4 +80,5 @@ def : Processor<"zEC12", NoItineraries,
[FeatureDistinctOps, FeatureLoadStoreOnCond, FeatureHighWord,
FeatureFPExtension, FeaturePopulationCount,
FeatureFastSerialization, FeatureInterlockedAccess1,
FeatureMiscellaneousExtensions]>;
FeatureMiscellaneousExtensions,
FeatureTransactionalExecution, FeatureProcessorAssist]>;
1 change: 1 addition & 0 deletions llvm/lib/Target/SystemZ/SystemZSubtarget.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -40,6 +40,7 @@ SystemZSubtarget::SystemZSubtarget(const std::string &TT,
HasLoadStoreOnCond(false), HasHighWord(false), HasFPExtension(false),
HasPopulationCount(false), HasFastSerialization(false),
HasInterlockedAccess1(false), HasMiscellaneousExtensions(false),
HasTransactionalExecution(false), HasProcessorAssist(false),
TargetTriple(TT), InstrInfo(initializeSubtargetDependencies(CPU, FS)),
TLInfo(TM, *this), TSInfo(*TM.getDataLayout()), FrameLowering() {}

Expand Down
8 changes: 8 additions & 0 deletions llvm/lib/Target/SystemZ/SystemZSubtarget.h
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Original file line number Diff line number Diff line change
Expand Up @@ -42,6 +42,8 @@ class SystemZSubtarget : public SystemZGenSubtargetInfo {
bool HasFastSerialization;
bool HasInterlockedAccess1;
bool HasMiscellaneousExtensions;
bool HasTransactionalExecution;
bool HasProcessorAssist;

private:
Triple TargetTriple;
Expand Down Expand Up @@ -102,6 +104,12 @@ class SystemZSubtarget : public SystemZGenSubtargetInfo {
return HasMiscellaneousExtensions;
}

// Return true if the target has the transactional-execution facility.
bool hasTransactionalExecution() const { return HasTransactionalExecution; }

// Return true if the target has the processor-assist facility.
bool hasProcessorAssist() const { return HasProcessorAssist; }

// Return true if GV can be accessed using LARL for reloc model RM
// and code model CM.
bool isPC32DBLSymbol(const GlobalValue *GV, Reloc::Model RM,
Expand Down
352 changes: 352 additions & 0 deletions llvm/test/CodeGen/SystemZ/htm-intrinsics.ll
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Original file line number Diff line number Diff line change
@@ -0,0 +1,352 @@
; Test transactional-execution intrinsics.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 | FileCheck %s

declare i32 @llvm.s390.tbegin(i8 *, i32)
declare i32 @llvm.s390.tbegin.nofloat(i8 *, i32)
declare void @llvm.s390.tbeginc(i8 *, i32)
declare i32 @llvm.s390.tend()
declare void @llvm.s390.tabort(i64)
declare void @llvm.s390.ntstg(i64, i64 *)
declare i32 @llvm.s390.etnd()
declare void @llvm.s390.ppa.txassist(i32)

; TBEGIN.
define void @test_tbegin() {
; CHECK-LABEL: test_tbegin:
; CHECK-NOT: stmg
; CHECK: std %f8,
; CHECK: std %f9,
; CHECK: std %f10,
; CHECK: std %f11,
; CHECK: std %f12,
; CHECK: std %f13,
; CHECK: std %f14,
; CHECK: std %f15,
; CHECK: tbegin 0, 65292
; CHECK: ld %f8,
; CHECK: ld %f9,
; CHECK: ld %f10,
; CHECK: ld %f11,
; CHECK: ld %f12,
; CHECK: ld %f13,
; CHECK: ld %f14,
; CHECK: ld %f15,
; CHECK: br %r14
call i32 @llvm.s390.tbegin(i8 *null, i32 65292)
ret void
}

; TBEGIN (nofloat).
define void @test_tbegin_nofloat1() {
; CHECK-LABEL: test_tbegin_nofloat1:
; CHECK-NOT: stmg
; CHECK-NOT: std
; CHECK: tbegin 0, 65292
; CHECK: br %r14
call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292)
ret void
}

; TBEGIN (nofloat) with integer CC return value.
define i32 @test_tbegin_nofloat2() {
; CHECK-LABEL: test_tbegin_nofloat2:
; CHECK-NOT: stmg
; CHECK-NOT: std
; CHECK: tbegin 0, 65292
; CHECK: ipm %r2
; CHECK: srl %r2, 28
; CHECK: br %r14
%res = call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292)
ret i32 %res
}

; TBEGIN (nofloat) with implicit CC check.
define void @test_tbegin_nofloat3(i32 *%ptr) {
; CHECK-LABEL: test_tbegin_nofloat3:
; CHECK-NOT: stmg
; CHECK-NOT: std
; CHECK: tbegin 0, 65292
; CHECK: jnh {{\.L*}}
; CHECK: mvhi 0(%r2), 0
; CHECK: br %r14
%res = call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292)
%cmp = icmp eq i32 %res, 2
br i1 %cmp, label %if.then, label %if.end

if.then: ; preds = %entry
store i32 0, i32* %ptr, align 4
br label %if.end

if.end: ; preds = %if.then, %entry
ret void
}

; TBEGIN (nofloat) with dual CC use.
define i32 @test_tbegin_nofloat4(i32 %pad, i32 *%ptr) {
; CHECK-LABEL: test_tbegin_nofloat4:
; CHECK-NOT: stmg
; CHECK-NOT: std
; CHECK: tbegin 0, 65292
; CHECK: ipm %r2
; CHECK: srl %r2, 28
; CHECK: cijlh %r2, 2, {{\.L*}}
; CHECK: mvhi 0(%r3), 0
; CHECK: br %r14
%res = call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292)
%cmp = icmp eq i32 %res, 2
br i1 %cmp, label %if.then, label %if.end

if.then: ; preds = %entry
store i32 0, i32* %ptr, align 4
br label %if.end

if.end: ; preds = %if.then, %entry
ret i32 %res
}

; TBEGIN (nofloat) with register.
define void @test_tbegin_nofloat5(i8 *%ptr) {
; CHECK-LABEL: test_tbegin_nofloat5:
; CHECK-NOT: stmg
; CHECK-NOT: std
; CHECK: tbegin 0(%r2), 65292
; CHECK: br %r14
call i32 @llvm.s390.tbegin.nofloat(i8 *%ptr, i32 65292)
ret void
}

; TBEGIN (nofloat) with GRSM 0x0f00.
define void @test_tbegin_nofloat6() {
; CHECK-LABEL: test_tbegin_nofloat6:
; CHECK: stmg %r6, %r15,
; CHECK-NOT: std
; CHECK: tbegin 0, 3840
; CHECK: br %r14
call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 3840)
ret void
}

; TBEGIN (nofloat) with GRSM 0xf100.
define void @test_tbegin_nofloat7() {
; CHECK-LABEL: test_tbegin_nofloat7:
; CHECK: stmg %r8, %r15,
; CHECK-NOT: std
; CHECK: tbegin 0, 61696
; CHECK: br %r14
call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 61696)
ret void
}

; TBEGIN (nofloat) with GRSM 0xfe00 -- stack pointer added automatically.
define void @test_tbegin_nofloat8() {
; CHECK-LABEL: test_tbegin_nofloat8:
; CHECK-NOT: stmg
; CHECK-NOT: std
; CHECK: tbegin 0, 65280
; CHECK: br %r14
call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65024)
ret void
}

; TBEGIN (nofloat) with GRSM 0xfb00 -- no frame pointer needed.
define void @test_tbegin_nofloat9() {
; CHECK-LABEL: test_tbegin_nofloat9:
; CHECK: stmg %r10, %r15,
; CHECK-NOT: std
; CHECK: tbegin 0, 64256
; CHECK: br %r14
call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 64256)
ret void
}

; TBEGIN (nofloat) with GRSM 0xfb00 -- frame pointer added automatically.
define void @test_tbegin_nofloat10(i64 %n) {
; CHECK-LABEL: test_tbegin_nofloat10:
; CHECK: stmg %r11, %r15,
; CHECK-NOT: std
; CHECK: tbegin 0, 65280
; CHECK: br %r14
%buf = alloca i8, i64 %n
call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 64256)
ret void
}

; TBEGINC.
define void @test_tbeginc() {
; CHECK-LABEL: test_tbeginc:
; CHECK-NOT: stmg
; CHECK-NOT: std
; CHECK: tbeginc 0, 65288
; CHECK: br %r14
call void @llvm.s390.tbeginc(i8 *null, i32 65288)
ret void
}

; TEND with integer CC return value.
define i32 @test_tend1() {
; CHECK-LABEL: test_tend1:
; CHECK: tend
; CHECK: ipm %r2
; CHECK: srl %r2, 28
; CHECK: br %r14
%res = call i32 @llvm.s390.tend()
ret i32 %res
}

; TEND with implicit CC check.
define void @test_tend3(i32 *%ptr) {
; CHECK-LABEL: test_tend3:
; CHECK: tend
; CHECK: je {{\.L*}}
; CHECK: mvhi 0(%r2), 0
; CHECK: br %r14
%res = call i32 @llvm.s390.tend()
%cmp = icmp eq i32 %res, 2
br i1 %cmp, label %if.then, label %if.end

if.then: ; preds = %entry
store i32 0, i32* %ptr, align 4
br label %if.end

if.end: ; preds = %if.then, %entry
ret void
}

; TEND with dual CC use.
define i32 @test_tend2(i32 %pad, i32 *%ptr) {
; CHECK-LABEL: test_tend2:
; CHECK: tend
; CHECK: ipm %r2
; CHECK: srl %r2, 28
; CHECK: cijlh %r2, 2, {{\.L*}}
; CHECK: mvhi 0(%r3), 0
; CHECK: br %r14
%res = call i32 @llvm.s390.tend()
%cmp = icmp eq i32 %res, 2
br i1 %cmp, label %if.then, label %if.end

if.then: ; preds = %entry
store i32 0, i32* %ptr, align 4
br label %if.end

if.end: ; preds = %if.then, %entry
ret i32 %res
}

; TABORT with register only.
define void @test_tabort1(i64 %val) {
; CHECK-LABEL: test_tabort1:
; CHECK: tabort 0(%r2)
; CHECK: br %r14
call void @llvm.s390.tabort(i64 %val)
ret void
}

; TABORT with immediate only.
define void @test_tabort2(i64 %val) {
; CHECK-LABEL: test_tabort2:
; CHECK: tabort 1234
; CHECK: br %r14
call void @llvm.s390.tabort(i64 1234)
ret void
}

; TABORT with register + immediate.
define void @test_tabort3(i64 %val) {
; CHECK-LABEL: test_tabort3:
; CHECK: tabort 1234(%r2)
; CHECK: br %r14
%sum = add i64 %val, 1234
call void @llvm.s390.tabort(i64 %sum)
ret void
}

; TABORT with out-of-range immediate.
define void @test_tabort4(i64 %val) {
; CHECK-LABEL: test_tabort4:
; CHECK: tabort 0({{%r[1-5]}})
; CHECK: br %r14
call void @llvm.s390.tabort(i64 4096)
ret void
}

; NTSTG with base pointer only.
define void @test_ntstg1(i64 *%ptr, i64 %val) {
; CHECK-LABEL: test_ntstg1:
; CHECK: ntstg %r3, 0(%r2)
; CHECK: br %r14
call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
ret void
}

; NTSTG with base and index.
; Check that VSTL doesn't allow an index.
define void @test_ntstg2(i64 *%base, i64 %index, i64 %val) {
; CHECK-LABEL: test_ntstg2:
; CHECK: sllg [[REG:%r[1-5]]], %r3, 3
; CHECK: ntstg %r4, 0([[REG]],%r2)
; CHECK: br %r14
%ptr = getelementptr i64, i64 *%base, i64 %index
call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
ret void
}

; NTSTG with the highest in-range displacement.
define void @test_ntstg3(i64 *%base, i64 %val) {
; CHECK-LABEL: test_ntstg3:
; CHECK: ntstg %r3, 524280(%r2)
; CHECK: br %r14
%ptr = getelementptr i64, i64 *%base, i64 65535
call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
ret void
}

; NTSTG with an out-of-range positive displacement.
define void @test_ntstg4(i64 *%base, i64 %val) {
; CHECK-LABEL: test_ntstg4:
; CHECK: ntstg %r3, 0({{%r[1-5]}})
; CHECK: br %r14
%ptr = getelementptr i64, i64 *%base, i64 65536
call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
ret void
}

; NTSTG with the lowest in-range displacement.
define void @test_ntstg5(i64 *%base, i64 %val) {
; CHECK-LABEL: test_ntstg5:
; CHECK: ntstg %r3, -524288(%r2)
; CHECK: br %r14
%ptr = getelementptr i64, i64 *%base, i64 -65536
call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
ret void
}

; NTSTG with an out-of-range negative displacement.
define void @test_ntstg6(i64 *%base, i64 %val) {
; CHECK-LABEL: test_ntstg6:
; CHECK: ntstg %r3, 0({{%r[1-5]}})
; CHECK: br %r14
%ptr = getelementptr i64, i64 *%base, i64 -65537
call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
ret void
}

; ETND.
define i32 @test_etnd() {
; CHECK-LABEL: test_etnd:
; CHECK: etnd %r2
; CHECK: br %r14
%res = call i32 @llvm.s390.etnd()
ret i32 %res
}

; PPA (Transaction-Abort Assist)
define void @test_ppa_txassist(i32 %val) {
; CHECK-LABEL: test_ppa_txassist:
; CHECK: ppa %r2, 0, 1
; CHECK: br %r14
call void @llvm.s390.ppa.txassist(i32 %val)
ret void
}

141 changes: 141 additions & 0 deletions llvm/test/MC/Disassembler/SystemZ/insns.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -2503,6 +2503,15 @@
# CHECK: ear %r15, %a15
0xb2 0x4f 0x00 0xff

# CHECK: etnd %r0
0xb2 0xec 0x00 0x00

# CHECK: etnd %r15
0xb2 0xec 0x00 0xf0

# CHECK: etnd %r7
0xb2 0xec 0x00 0x70

# CHECK: fidbr %f0, 0, %f0
0xb3 0x5f 0x00 0x00

Expand Down Expand Up @@ -6034,6 +6043,36 @@
# CHECK: ny %r15, 0
0xe3 0xf0 0x00 0x00 0x00 0x54

# CHECK: ntstg %r0, -524288
0xe3 0x00 0x00 0x00 0x80 0x25

# CHECK: ntstg %r0, -1
0xe3 0x00 0x0f 0xff 0xff 0x25

# CHECK: ntstg %r0, 0
0xe3 0x00 0x00 0x00 0x00 0x25

# CHECK: ntstg %r0, 1
0xe3 0x00 0x00 0x01 0x00 0x25

# CHECK: ntstg %r0, 524287
0xe3 0x00 0x0f 0xff 0x7f 0x25

# CHECK: ntstg %r0, 0(%r1)
0xe3 0x00 0x10 0x00 0x00 0x25

# CHECK: ntstg %r0, 0(%r15)
0xe3 0x00 0xf0 0x00 0x00 0x25

# CHECK: ntstg %r0, 524287(%r1,%r15)
0xe3 0x01 0xff 0xff 0x7f 0x25

# CHECK: ntstg %r0, 524287(%r15,%r1)
0xe3 0x0f 0x1f 0xff 0x7f 0x25

# CHECK: ntstg %r15, 0
0xe3 0xf0 0x00 0x00 0x00 0x25

# CHECK: oc 0(1), 0
0xd6 0x00 0x00 0x00 0x00 0x00

Expand Down Expand Up @@ -6346,6 +6385,21 @@
# CHECK: popcnt %r7, %r8
0xb9 0xe1 0x00 0x78

# CHECK: ppa %r0, %r0, 0
0xb2 0xe8 0x00 0x00

# CHECK: ppa %r0, %r0, 15
0xb2 0xe8 0xf0 0x00

# CHECK: ppa %r0, %r15, 0
0xb2 0xe8 0x00 0x0f

# CHECK: ppa %r4, %r6, 7
0xb2 0xe8 0x70 0x46

# CHECK: ppa %r15, %r0, 0
0xb2 0xe8 0x00 0xf0

# CHECK: risbg %r0, %r0, 0, 0, 0
0xec 0x00 0x00 0x00 0x00 0x55

Expand Down Expand Up @@ -8062,6 +8116,93 @@
# CHECK: sy %r15, 0
0xe3 0xf0 0x00 0x00 0x00 0x5b

# CHECK: tabort 0
0xb2 0xfc 0x00 0x00

# CHECK: tabort 0(%r1)
0xb2 0xfc 0x10 0x00

# CHECK: tabort 0(%r15)
0xb2 0xfc 0xf0 0x00

# CHECK: tabort 4095
0xb2 0xfc 0x0f 0xff

# CHECK: tabort 4095(%r1)
0xb2 0xfc 0x1f 0xff

# CHECK: tabort 4095(%r15)
0xb2 0xfc 0xff 0xff

# CHECK: tbegin 0, 0
0xe5 0x60 0x00 0x00 0x00 0x00

# CHECK: tbegin 4095, 0
0xe5 0x60 0x0f 0xff 0x00 0x00

# CHECK: tbegin 0, 0
0xe5 0x60 0x00 0x00 0x00 0x00

# CHECK: tbegin 0, 1
0xe5 0x60 0x00 0x00 0x00 0x01

# CHECK: tbegin 0, 32767
0xe5 0x60 0x00 0x00 0x7f 0xff

# CHECK: tbegin 0, 32768
0xe5 0x60 0x00 0x00 0x80 0x00

# CHECK: tbegin 0, 65535
0xe5 0x60 0x00 0x00 0xff 0xff

# CHECK: tbegin 0(%r1), 42
0xe5 0x60 0x10 0x00 0x00 0x2a

# CHECK: tbegin 0(%r15), 42
0xe5 0x60 0xf0 0x00 0x00 0x2a

# CHECK: tbegin 4095(%r1), 42
0xe5 0x60 0x1f 0xff 0x00 0x2a

# CHECK: tbegin 4095(%r15), 42
0xe5 0x60 0xff 0xff 0x00 0x2a

# CHECK: tbeginc 0, 0
0xe5 0x61 0x00 0x00 0x00 0x00

# CHECK: tbeginc 4095, 0
0xe5 0x61 0x0f 0xff 0x00 0x00

# CHECK: tbeginc 0, 0
0xe5 0x61 0x00 0x00 0x00 0x00

# CHECK: tbeginc 0, 1
0xe5 0x61 0x00 0x00 0x00 0x01

# CHECK: tbeginc 0, 32767
0xe5 0x61 0x00 0x00 0x7f 0xff

# CHECK: tbeginc 0, 32768
0xe5 0x61 0x00 0x00 0x80 0x00

# CHECK: tbeginc 0, 65535
0xe5 0x61 0x00 0x00 0xff 0xff

# CHECK: tbeginc 0(%r1), 42
0xe5 0x61 0x10 0x00 0x00 0x2a

# CHECK: tbeginc 0(%r15), 42
0xe5 0x61 0xf0 0x00 0x00 0x2a

# CHECK: tbeginc 4095(%r1), 42
0xe5 0x61 0x1f 0xff 0x00 0x2a

# CHECK: tbeginc 4095(%r15), 42
0xe5 0x61 0xff 0xff 0x00 0x2a

# CHECK: tend
0xb2 0xf8 0x00 0x00

# CHECK: tm 0, 0
0x91 0x00 0x00 0x00

Expand Down
36 changes: 36 additions & 0 deletions llvm/test/MC/SystemZ/insn-bad-z196.s
View file
Original file line number Diff line number Diff line change
Expand Up @@ -244,6 +244,11 @@
cxlgbr %f0, 16, %r0, 0
cxlgbr %f2, 0, %r0, 0

#CHECK: error: {{(instruction requires: transactional-execution)?}}
#CHECK: etnd %r7

etnd %r7

#CHECK: error: invalid operand
#CHECK: fidbra %f0, 0, %f0, -1
#CHECK: error: invalid operand
Expand Down Expand Up @@ -546,6 +551,16 @@
locr %r0,%r0,-1
locr %r0,%r0,16

#CHECK: error: {{(instruction requires: transactional-execution)?}}
#CHECK: ntstg %r0, 524287(%r1,%r15)

ntstg %r0, 524287(%r1,%r15)

#CHECK: error: {{(instruction requires: processor-assist)?}}
#CHECK: ppa %r4, %r6, 7

ppa %r4, %r6, 7

#CHECK: error: {{(instruction requires: miscellaneous-extensions)?}}
#CHECK: risbgn %r1, %r2, 0, 0, 0

Expand Down Expand Up @@ -690,3 +705,24 @@
stocg %r0,-524289,1
stocg %r0,524288,1
stocg %r0,0(%r1,%r2),1

#CHECK: error: {{(instruction requires: transactional-execution)?}}
#CHECK: tabort 4095(%r1)

tabort 4095(%r1)

#CHECK: error: {{(instruction requires: transactional-execution)?}}
#CHECK: tbegin 4095(%r1), 42

tbegin 4095(%r1), 42

#CHECK: error: {{(instruction requires: transactional-execution)?}}
#CHECK: tbeginc 4095(%r1), 42

tbeginc 4095(%r1), 42

#CHECK: error: {{(instruction requires: transactional-execution)?}}
#CHECK: tend

tend

60 changes: 60 additions & 0 deletions llvm/test/MC/SystemZ/insn-bad-zEC12.s
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2,6 +2,22 @@
# RUN: not llvm-mc -triple s390x-linux-gnu -mcpu=zEC12 < %s 2> %t
# RUN: FileCheck < %t %s

#CHECK: error: invalid operand
#CHECK: ntstg %r0, -524289
#CHECK: error: invalid operand
#CHECK: ntstg %r0, 524288

ntstg %r0, -524289
ntstg %r0, 524288

#CHECK: error: invalid operand
#CHECK: ppa %r0, %r0, -1
#CHECK: error: invalid operand
#CHECK: ppa %r0, %r0, 16

ppa %r0, %r0, -1
ppa %r0, %r0, 16

#CHECK: error: invalid operand
#CHECK: risbgn %r0,%r0,0,0,-1
#CHECK: error: invalid operand
Expand All @@ -22,3 +38,47 @@
risbgn %r0,%r0,-1,0,0
risbgn %r0,%r0,256,0,0

#CHECK: error: invalid operand
#CHECK: tabort -1
#CHECK: error: invalid operand
#CHECK: tabort 4096
#CHECK: error: invalid use of indexed addressing
#CHECK: tabort 0(%r1,%r2)

tabort -1
tabort 4096
tabort 0(%r1,%r2)

#CHECK: error: invalid operand
#CHECK: tbegin -1, 0
#CHECK: error: invalid operand
#CHECK: tbegin 4096, 0
#CHECK: error: invalid use of indexed addressing
#CHECK: tbegin 0(%r1,%r2), 0
#CHECK: error: invalid operand
#CHECK: tbegin 0, -1
#CHECK: error: invalid operand
#CHECK: tbegin 0, 65536

tbegin -1, 0
tbegin 4096, 0
tbegin 0(%r1,%r2), 0
tbegin 0, -1
tbegin 0, 65536

#CHECK: error: invalid operand
#CHECK: tbeginc -1, 0
#CHECK: error: invalid operand
#CHECK: tbeginc 4096, 0
#CHECK: error: invalid use of indexed addressing
#CHECK: tbeginc 0(%r1,%r2), 0
#CHECK: error: invalid operand
#CHECK: tbeginc 0, -1
#CHECK: error: invalid operand
#CHECK: tbeginc 0, 65536

tbeginc -1, 0
tbeginc 4096, 0
tbeginc 0(%r1,%r2), 0
tbeginc 0, -1
tbeginc 0, 65536
107 changes: 107 additions & 0 deletions llvm/test/MC/SystemZ/insn-good-zEC12.s
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,48 @@
# For zEC12 and above.
# RUN: llvm-mc -triple s390x-linux-gnu -mcpu=zEC12 -show-encoding %s | FileCheck %s

#CHECK: etnd %r0 # encoding: [0xb2,0xec,0x00,0x00]
#CHECK: etnd %r15 # encoding: [0xb2,0xec,0x00,0xf0]
#CHECK: etnd %r7 # encoding: [0xb2,0xec,0x00,0x70]

etnd %r0
etnd %r15
etnd %r7

#CHECK: ntstg %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x25]
#CHECK: ntstg %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x25]
#CHECK: ntstg %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x25]
#CHECK: ntstg %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x25]
#CHECK: ntstg %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x25]
#CHECK: ntstg %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x25]
#CHECK: ntstg %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x25]
#CHECK: ntstg %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x25]
#CHECK: ntstg %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x25]
#CHECK: ntstg %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x25]

ntstg %r0, -524288
ntstg %r0, -1
ntstg %r0, 0
ntstg %r0, 1
ntstg %r0, 524287
ntstg %r0, 0(%r1)
ntstg %r0, 0(%r15)
ntstg %r0, 524287(%r1,%r15)
ntstg %r0, 524287(%r15,%r1)
ntstg %r15, 0

#CHECK: ppa %r0, %r0, 0 # encoding: [0xb2,0xe8,0x00,0x00]
#CHECK: ppa %r0, %r0, 15 # encoding: [0xb2,0xe8,0xf0,0x00]
#CHECK: ppa %r0, %r15, 0 # encoding: [0xb2,0xe8,0x00,0x0f]
#CHECK: ppa %r4, %r6, 7 # encoding: [0xb2,0xe8,0x70,0x46]
#CHECK: ppa %r15, %r0, 0 # encoding: [0xb2,0xe8,0x00,0xf0]

ppa %r0, %r0, 0
ppa %r0, %r0, 15
ppa %r0, %r15, 0
ppa %r4, %r6, 7
ppa %r15, %r0, 0

#CHECK: risbgn %r0, %r0, 0, 0, 0 # encoding: [0xec,0x00,0x00,0x00,0x00,0x59]
#CHECK: risbgn %r0, %r0, 0, 0, 63 # encoding: [0xec,0x00,0x00,0x00,0x3f,0x59]
#CHECK: risbgn %r0, %r0, 0, 255, 0 # encoding: [0xec,0x00,0x00,0xff,0x00,0x59]
Expand All @@ -17,3 +59,68 @@
risbgn %r15,%r0,0,0,0
risbgn %r4,%r5,6,7,8

#CHECK: tabort 0 # encoding: [0xb2,0xfc,0x00,0x00]
#CHECK: tabort 0(%r1) # encoding: [0xb2,0xfc,0x10,0x00]
#CHECK: tabort 0(%r15) # encoding: [0xb2,0xfc,0xf0,0x00]
#CHECK: tabort 4095 # encoding: [0xb2,0xfc,0x0f,0xff]
#CHECK: tabort 4095(%r1) # encoding: [0xb2,0xfc,0x1f,0xff]
#CHECK: tabort 4095(%r15) # encoding: [0xb2,0xfc,0xff,0xff]

tabort 0
tabort 0(%r1)
tabort 0(%r15)
tabort 4095
tabort 4095(%r1)
tabort 4095(%r15)

#CHECK: tbegin 0, 0 # encoding: [0xe5,0x60,0x00,0x00,0x00,0x00]
#CHECK: tbegin 4095, 0 # encoding: [0xe5,0x60,0x0f,0xff,0x00,0x00]
#CHECK: tbegin 0, 0 # encoding: [0xe5,0x60,0x00,0x00,0x00,0x00]
#CHECK: tbegin 0, 1 # encoding: [0xe5,0x60,0x00,0x00,0x00,0x01]
#CHECK: tbegin 0, 32767 # encoding: [0xe5,0x60,0x00,0x00,0x7f,0xff]
#CHECK: tbegin 0, 32768 # encoding: [0xe5,0x60,0x00,0x00,0x80,0x00]
#CHECK: tbegin 0, 65535 # encoding: [0xe5,0x60,0x00,0x00,0xff,0xff]
#CHECK: tbegin 0(%r1), 42 # encoding: [0xe5,0x60,0x10,0x00,0x00,0x2a]
#CHECK: tbegin 0(%r15), 42 # encoding: [0xe5,0x60,0xf0,0x00,0x00,0x2a]
#CHECK: tbegin 4095(%r1), 42 # encoding: [0xe5,0x60,0x1f,0xff,0x00,0x2a]
#CHECK: tbegin 4095(%r15), 42 # encoding: [0xe5,0x60,0xff,0xff,0x00,0x2a]

tbegin 0, 0
tbegin 4095, 0
tbegin 0, 0
tbegin 0, 1
tbegin 0, 32767
tbegin 0, 32768
tbegin 0, 65535
tbegin 0(%r1), 42
tbegin 0(%r15), 42
tbegin 4095(%r1), 42
tbegin 4095(%r15), 42

#CHECK: tbeginc 0, 0 # encoding: [0xe5,0x61,0x00,0x00,0x00,0x00]
#CHECK: tbeginc 4095, 0 # encoding: [0xe5,0x61,0x0f,0xff,0x00,0x00]
#CHECK: tbeginc 0, 0 # encoding: [0xe5,0x61,0x00,0x00,0x00,0x00]
#CHECK: tbeginc 0, 1 # encoding: [0xe5,0x61,0x00,0x00,0x00,0x01]
#CHECK: tbeginc 0, 32767 # encoding: [0xe5,0x61,0x00,0x00,0x7f,0xff]
#CHECK: tbeginc 0, 32768 # encoding: [0xe5,0x61,0x00,0x00,0x80,0x00]
#CHECK: tbeginc 0, 65535 # encoding: [0xe5,0x61,0x00,0x00,0xff,0xff]
#CHECK: tbeginc 0(%r1), 42 # encoding: [0xe5,0x61,0x10,0x00,0x00,0x2a]
#CHECK: tbeginc 0(%r15), 42 # encoding: [0xe5,0x61,0xf0,0x00,0x00,0x2a]
#CHECK: tbeginc 4095(%r1), 42 # encoding: [0xe5,0x61,0x1f,0xff,0x00,0x2a]
#CHECK: tbeginc 4095(%r15), 42 # encoding: [0xe5,0x61,0xff,0xff,0x00,0x2a]

tbeginc 0, 0
tbeginc 4095, 0
tbeginc 0, 0
tbeginc 0, 1
tbeginc 0, 32767
tbeginc 0, 32768
tbeginc 0, 65535
tbeginc 0(%r1), 42
tbeginc 0(%r15), 42
tbeginc 4095(%r1), 42
tbeginc 4095(%r15), 42

#CHECK: tend # encoding: [0xb2,0xf8,0x00,0x00]

tend