7 changes: 5 additions & 2 deletions llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -298,6 +298,11 @@ bool PPCAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,

switch (ExtraCode[0]) {
default: return true; // Unknown modifier.
case 'L': // A memory reference to the upper word of a double word op.
O << getDataLayout().getPointerSize() << "(";
printOperand(MI, OpNo, O);
O << ")";
return false;
case 'y': // A memory reference for an X-form instruction
{
const char *RegName = "r0";
Expand All @@ -309,7 +314,6 @@ bool PPCAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
}
case 'U': // Print 'u' for update form.
case 'X': // Print 'x' for indexed form.
{
// FIXME: Currently for PowerPC memory operands are always loaded
// into a register, so we never get an update or indexed form.
// This is bad even for offset forms, since even if we know we
Expand All @@ -319,7 +323,6 @@ bool PPCAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
assert(MI->getOperand(OpNo).isReg());
return false;
}
}
}

assert(MI->getOperand(OpNo).isReg());
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -181,9 +181,9 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
adjustReg(MBB, MBBI, DL, FPReg, SPReg,
StackSize - RVFI->getVarArgsSaveSize(), MachineInstr::FrameSetup);

// Emit ".cfi_def_cfa $fp, 0"
// Emit ".cfi_def_cfa $fp, -RVFI->getVarArgsSaveSize()"
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfa(
nullptr, RI->getDwarfRegNum(FPReg, true), 0));
nullptr, RI->getDwarfRegNum(FPReg, true), -RVFI->getVarArgsSaveSize()));
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex);
}
Expand Down
34 changes: 34 additions & 0 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -197,6 +197,14 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setTruncStoreAction(MVT::f64, MVT::f16, Expand);
}

if (Subtarget.is64Bit() &&
!(Subtarget.hasStdExtD() || Subtarget.hasStdExtF())) {
setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
}

setOperationAction(ISD::GlobalAddress, XLenVT, Custom);
setOperationAction(ISD::BlockAddress, XLenVT, Custom);
setOperationAction(ISD::ConstantPool, XLenVT, Custom);
Expand Down Expand Up @@ -876,6 +884,32 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
switch (N->getOpcode()) {
default:
llvm_unreachable("Don't know how to custom type legalize this operation!");
case ISD::STRICT_FP_TO_SINT:
case ISD::STRICT_FP_TO_UINT:
case ISD::FP_TO_SINT:
case ISD::FP_TO_UINT: {
bool IsStrict = N->isStrictFPOpcode();
assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
"Unexpected custom legalisation");
SDValue Op0 = IsStrict ? N->getOperand(1) : N->getOperand(0);
RTLIB::Libcall LC;
if (N->getOpcode() == ISD::FP_TO_SINT ||
N->getOpcode() == ISD::STRICT_FP_TO_SINT)
LC = RTLIB::getFPTOSINT(Op0.getValueType(), N->getValueType(0));
else
LC = RTLIB::getFPTOUINT(Op0.getValueType(), N->getValueType(0));
MakeLibCallOptions CallOptions;
EVT OpVT = Op0.getValueType();
CallOptions.setTypeListBeforeSoften(OpVT, N->getValueType(0), true);
SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
SDValue Result;
std::tie(Result, Chain) =
makeLibCall(DAG, LC, N->getValueType(0), Op0, CallOptions, DL, Chain);
Results.push_back(Result);
if (IsStrict)
Results.push_back(Chain);
break;
}
case ISD::READCYCLECOUNTER: {
assert(!Subtarget.is64Bit() &&
"READCYCLECOUNTER only has custom type legalization on riscv32");
Expand Down
62 changes: 62 additions & 0 deletions llvm/test/CodeGen/AArch64/funclet-match-add-sub-stack.ll
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,62 @@
; RUN: llc -o - %s -mtriple=aarch64-windows | FileCheck %s
; Check that the stack bump around a funclet is computed correctly in both the
; prologue and epilogue in the case we have a MaxCallFrameSize > 0 and are doing alloca
target datalayout = "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-pc-windows-msvc19.25.28611"

; // requires passing arguments on the stack
; void test2(void*, int, int, int, int, int, int, int, int);
;
; // function with the funclet being checked
; void test1(size_t bytes)
; {
; // alloca forces a separate callee save bump and stack bump
; void *data = _alloca(bytes);
; try {
; test2(data, 0, 1, 2, 3, 4, 5, 6, 7);
; } catch (...) {
; // the funclet being checked
; }
; }

; CHECK-LABEL: ?catch$2@?0??test1@@YAX_K@Z@4HA
; CHECK: sub sp, sp, #16
; CHECK: add sp, sp, #16
; Function Attrs: uwtable
define dso_local void @"?test1@@YAX_K@Z"(i64 %0) #0 personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*) {
%2 = alloca i64, align 8
%3 = alloca i8*, align 8
store i64 %0, i64* %2, align 8
%4 = load i64, i64* %2, align 8
%5 = alloca i8, i64 %4, align 16
store i8* %5, i8** %3, align 8
%6 = load i8*, i8** %3, align 8
invoke void @"?test2@@YAXPEAXHHHHHHHH@Z"(i8* %6, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7)
to label %13 unwind label %7

7: ; preds = %1
%8 = catchswitch within none [label %9] unwind to caller

9: ; preds = %7
%10 = catchpad within %8 [i8* null, i32 64, i8* null]
catchret from %10 to label %11

11: ; preds = %9
br label %12

12: ; preds = %11, %13
ret void

13: ; preds = %1
br label %12
}

declare dso_local void @"?test2@@YAXPEAXHHHHHHHH@Z"(i8*, i32, i32, i32, i32, i32, i32, i32, i32) #1

declare dso_local i32 @__CxxFrameHandler3(...)

attributes #0 = { uwtable }

!llvm.module.flags = !{!0}

!0 = !{i32 1, !"wchar_size", i32 2}
24 changes: 12 additions & 12 deletions llvm/test/CodeGen/AArch64/seh-finally.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -37,7 +37,7 @@ entry:
; CHECK-LABEL: simple_seh
; CHECK: add x29, sp, #16
; CHECK: mov x0, #-2
; CHECK: stur x0, [x29, #-16]
; CHECK: stur x0, [x29, #16]
; CHECK: .set .Lsimple_seh$frame_escape_0, -8
; CHECK: ldur w0, [x29, #-8]
; CHECK: bl foo
Expand Down Expand Up @@ -87,13 +87,13 @@ define void @stack_realign() #0 personality i8* bitcast (i32 (...)* @__C_specifi
entry:
; CHECK-LABEL: stack_realign
; CHECK: mov x29, sp
; CHECK: sub x9, sp, #64
; CHECK: sub x9, sp, #16
; CHECK: and sp, x9, #0xffffffffffffffe0
; CHECK: mov x19, sp
; CHECK: mov x0, #-2
; CHECK: stur x0, [x19, #16]
; CHECK: .set .Lstack_realign$frame_escape_0, 32
; CHECK: ldr w0, [x19, #32]
; CHECK: stur x0, [x29, #32]
; CHECK: .set .Lstack_realign$frame_escape_0, 0
; CHECK: ldr w0, [x19]
; CHECK: bl foo

%o = alloca %struct.S, align 32
Expand Down Expand Up @@ -142,7 +142,7 @@ entry:
; CHECK-LABEL: vla_present
; CHECK: add x29, sp, #32
; CHECK: mov x1, #-2
; CHECK: stur x1, [x29, #-32]
; CHECK: stur x1, [x29, #16]
; CHECK: .set .Lvla_present$frame_escape_0, -4
; CHECK: stur w0, [x29, #-4]
; CHECK: ldur w8, [x29, #-4]
Expand Down Expand Up @@ -206,17 +206,17 @@ define void @vla_and_realign(i32 %n) #0 personality i8* bitcast (i32 (...)* @__C
entry:
; CHECK-LABEL: vla_and_realign
; CHECK: mov x29, sp
; CHECK: sub x9, sp, #64
; CHECK: sub x9, sp, #48
; CHECK: and sp, x9, #0xffffffffffffffe0
; CHECK: mov x19, sp
; CHECK: mov x1, #-2
; CHECK: stur x1, [x19]
; CHECK: stur x1, [x29, #32]
; CHECK: .set .Lvla_and_realign$frame_escape_0, 32
; CHECK: str w0, [x29, #28]
; CHECK: ldr w8, [x29, #28]
; CHECK: str w0, [x29, #44]
; CHECK: ldr w8, [x29, #44]
; CHECK: mov x9, sp
; CHECK: str x9, [x19, #24]
; CHECK: str x8, [x19, #16]
; CHECK: str x9, [x29, #24]
; CHECK: str x8, [x19, #24]
; CHECK: ldr w0, [x19, #32]
; CHECK: bl foo

Expand Down
7 changes: 3 additions & 4 deletions llvm/test/CodeGen/AArch64/wineh-try-catch-cbz.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,11 +4,10 @@
; but the original issue only reproduced if the cbz was immediately
; after the frame setup.)

; CHECK: sub sp, sp, #32
; CHECK-NEXT: stp x29, x30, [sp, #16]
; CHECK-NEXT: add x29, sp, #16
; CHECK: stp x29, x30, [sp, #-32]!
; CHECK-NEXT: mov x29, sp
; CHECK-NEXT: mov x1, #-2
; CHECK-NEXT: stur x1, [x29, #-16]
; CHECK-NEXT: stur x1, [x29, #16]
; CHECK-NEXT: cbz w0, .LBB0_2

target datalayout = "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128"
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AArch64/wineh-try-catch-realign.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@
; CHECK: stp x29, x30, [sp, #-32]!
; CHECK-NEXT: str x28, [sp, #16]
; CHECK-NEXT: str x19, [sp, #24]
; CHECK-NEXT: add x0, x19, #64
; CHECK-NEXT: add x0, x19, #0
; CHECK-NEXT: mov w1, wzr
; CHECK-NEXT: bl "?bb@@YAXPEAHH@Z"
; CHECK-NEXT: adrp x0, .LBB0_1
Expand Down
14 changes: 7 additions & 7 deletions llvm/test/CodeGen/AArch64/wineh-try-catch.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11,19 +11,19 @@
; and the parent function.

; The following checks that the unwind help object has -2 stored into it at
; fp - 400 - 256 = fp - 656, which is on-entry sp - 48 + 32 - 656 =
; on-entry sp - 672. We check this offset in the table later on.
; fp + 16, which is on-entry sp - 16.
; We check this offset in the table later on.

; CHECK-LABEL: "?func@@YAHXZ":
; CHECK: stp x29, x30, [sp, #-48]!
; CHECK: stp x29, x30, [sp, #-64]!
; CHECK: str x28, [sp, #16]
; CHECK: str x21, [sp, #24]
; CHECK: stp x19, x20, [sp, #32]
; CHECK: mov x29, sp
; CHECK: sub sp, sp, #624
; CHECK: mov x19, sp
; CHECK: mov x0, #-2
; CHECK: stur x0, [x19]
; CHECK: stur x0, [x29, #48]

; Now check that x is stored at fp - 20. We check that this is the same
; location accessed from the funclet to retrieve x.
Expand Down Expand Up @@ -72,7 +72,7 @@

; Now check that the offset of the unwind help object from the stack pointer on
; entry to func is encoded in cppxdata that is passed to __CxxFrameHandler3. As
; computed above, this comes to -672.
; computed above, this comes to -16.
; CHECK-LABEL: "$cppxdata$?func@@YAHXZ":
; CHECK-NEXT: .word 429065506 ; MagicNumber
; CHECK-NEXT: .word 2 ; MaxState
Expand All @@ -81,7 +81,7 @@
; CHECK-NEXT: .word ("$tryMap$?func@@YAHXZ")@IMGREL ; TryBlockMap
; CHECK-NEXT: .word 4 ; IPMapEntries
; CHECK-NEXT: .word ("$ip2state$?func@@YAHXZ")@IMGREL ; IPToStateXData
; CHECK-NEXT: .word -672 ; UnwindHelp
; CHECK-NEXT: .word -16 ; UnwindHelp

; UNWIND: Function: ?func@@YAHXZ (0x0)
; UNWIND: Prologue [
Expand All @@ -91,7 +91,7 @@
; UNWIND-NEXT: ; stp x19, x20, [sp, #32]
; UNWIND-NEXT: ; str x21, [sp, #24]
; UNWIND-NEXT: ; str x28, [sp, #16]
; UNWIND-NEXT: ; stp x29, x30, [sp, #-48]!
; UNWIND-NEXT: ; stp x29, x30, [sp, #-64]!
; UNWIND-NEXT: ; end
; UNWIND: Function: ?catch$2@?0??func@@YAHXZ@4HA
; UNWIND: Prologue [
Expand Down
69 changes: 69 additions & 0 deletions llvm/test/CodeGen/AArch64/wineh-unwindhelp-via-fp.ll
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,69 @@
; RUN: llc -o - %s -mtriple=aarch64-windows | FileCheck %s
; Check that we allocate the unwind help stack object in a fixed location from fp
; so that the runtime can find it when handling an exception
target datalayout = "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-pc-windows-msvc19.25.28611"

; Check that the store to the unwind help object for func2 is via FP
; CHECK-LABEL: ?func2@@YAXXZ
; CHECK: mov x[[#SCRATCH_REG:]], #-2
; CHECK: stur x[[#SCRATCH_REG:]], [x29, #[[#]]]
;
; // struct that requires greater than stack alignment
; struct alignas(32) A
; {
; // data that would be invalid for unwind help (> 0)
; int _x[4]{42, 42, 42, 42};
; ~A() {}
; };
;
; // cause us to run the funclet in func2
; void func3()
; {
; throw 1;
; }
;
; // the funclet that ensures we have the unwind help correct
; void func2()
; {
; A a;
; func3();
; }
;
; // function to ensure we are misaligned in func2
; void func1()
; {
; func2();
; }
;
; // set things up and ensure alignment for func1
; void test()
; {
; try {
; A a;
; func1();
; } catch(...) {}
; }

%struct.A = type { [4 x i32], [16 x i8] }
declare dso_local %struct.A* @"??0A@@QEAA@XZ"(%struct.A* returned %0)
declare dso_local void @"??1A@@QEAA@XZ"(%struct.A* %0)
declare dso_local i32 @__CxxFrameHandler3(...)
declare dso_local void @"?func3@@YAXXZ"()

; Function Attrs: noinline optnone uwtable
define dso_local void @"?func2@@YAXXZ"() #0 personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*) {
%1 = alloca %struct.A, align 32
%2 = call %struct.A* @"??0A@@QEAA@XZ"(%struct.A* %1) #3
invoke void @"?func3@@YAXXZ"()
to label %3 unwind label %4

3: ; preds = %0
call void @"??1A@@QEAA@XZ"(%struct.A* %1) #3
ret void

4: ; preds = %0
%5 = cleanuppad within none []
call void @"??1A@@QEAA@XZ"(%struct.A* %1) #3 [ "funclet"(token %5) ]
cleanupret from %5 unwind to caller
}
13 changes: 12 additions & 1 deletion llvm/test/CodeGen/PowerPC/inlineasm-output-template.ll
View file
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
; RUN: llc -mtriple=ppc32-- < %s | FileCheck %s
; RUN: llc -mtriple=ppc32 < %s | FileCheck %s
; RUN: llc -mtriple=ppc64 < %s | FileCheck %s --check-prefix=PPC64

; Test that %c works with immediates
; CHECK-LABEL: test_inlineasm_c_output_template0
Expand All @@ -24,3 +25,13 @@ define dso_local i32 @test_inlineasm_c_output_template2() {
tail call void asm sideeffect "#TEST ${0:n}", "i"(i32 42)
ret i32 42
}

; Test that the machine specific %L works with memory operands.
; CHECK-LABEL: test_inlineasm_L_output_template
; CHECK: # 4(5)
; PPC64-LABEL: test_inlineasm_L_output_template
; PPC64: # 8(4)
define dso_local void @test_inlineasm_L_output_template(i64 %0, i64* %1) {
tail call void asm sideeffect "# ${0:L}", "*m"(i64* %1)
ret void
}
10 changes: 10 additions & 0 deletions llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1628,6 +1628,7 @@ define void @cmpxchg_i32_monotonic_monotonic(i32* %ptr, i32 %cmp, i32 %val) noun
;
; RV64IA-LABEL: cmpxchg_i32_monotonic_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: sext.w a1, a1
; RV64IA-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB20_3
Expand Down Expand Up @@ -1680,6 +1681,7 @@ define void @cmpxchg_i32_acquire_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwi
;
; RV64IA-LABEL: cmpxchg_i32_acquire_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: sext.w a1, a1
; RV64IA-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB21_3
Expand Down Expand Up @@ -1732,6 +1734,7 @@ define void @cmpxchg_i32_acquire_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind
;
; RV64IA-LABEL: cmpxchg_i32_acquire_acquire:
; RV64IA: # %bb.0:
; RV64IA-NEXT: sext.w a1, a1
; RV64IA-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB22_3
Expand Down Expand Up @@ -1784,6 +1787,7 @@ define void @cmpxchg_i32_release_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwi
;
; RV64IA-LABEL: cmpxchg_i32_release_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: sext.w a1, a1
; RV64IA-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB23_3
Expand Down Expand Up @@ -1836,6 +1840,7 @@ define void @cmpxchg_i32_release_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind
;
; RV64IA-LABEL: cmpxchg_i32_release_acquire:
; RV64IA: # %bb.0:
; RV64IA-NEXT: sext.w a1, a1
; RV64IA-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB24_3
Expand Down Expand Up @@ -1888,6 +1893,7 @@ define void @cmpxchg_i32_acq_rel_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwi
;
; RV64IA-LABEL: cmpxchg_i32_acq_rel_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: sext.w a1, a1
; RV64IA-NEXT: .LBB25_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB25_3
Expand Down Expand Up @@ -1940,6 +1946,7 @@ define void @cmpxchg_i32_acq_rel_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind
;
; RV64IA-LABEL: cmpxchg_i32_acq_rel_acquire:
; RV64IA: # %bb.0:
; RV64IA-NEXT: sext.w a1, a1
; RV64IA-NEXT: .LBB26_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB26_3
Expand Down Expand Up @@ -1992,6 +1999,7 @@ define void @cmpxchg_i32_seq_cst_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwi
;
; RV64IA-LABEL: cmpxchg_i32_seq_cst_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: sext.w a1, a1
; RV64IA-NEXT: .LBB27_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB27_3
Expand Down Expand Up @@ -2044,6 +2052,7 @@ define void @cmpxchg_i32_seq_cst_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind
;
; RV64IA-LABEL: cmpxchg_i32_seq_cst_acquire:
; RV64IA: # %bb.0:
; RV64IA-NEXT: sext.w a1, a1
; RV64IA-NEXT: .LBB28_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB28_3
Expand Down Expand Up @@ -2096,6 +2105,7 @@ define void @cmpxchg_i32_seq_cst_seq_cst(i32* %ptr, i32 %cmp, i32 %val) nounwind
;
; RV64IA-LABEL: cmpxchg_i32_seq_cst_seq_cst:
; RV64IA: # %bb.0:
; RV64IA-NEXT: sext.w a1, a1
; RV64IA-NEXT: .LBB29_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB29_3
Expand Down
124 changes: 122 additions & 2 deletions llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -174,7 +174,7 @@ define i32 @fcvt_w_s(float %a) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: call __fixsfdi
; RV64I-NEXT: call __fixsfsi
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
Expand All @@ -187,7 +187,7 @@ define i32 @fcvt_wu_s(float %a) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: call __fixunssfdi
; RV64I-NEXT: call __fixunssfsi
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
Expand Down Expand Up @@ -710,3 +710,123 @@ define float @fp_trunc(double %a) nounwind {
%conv = fptrunc double %a to float
ret float %conv
}

define i32 @fp32_to_ui32(float %a) nounwind {
; RV64I-LABEL: fp32_to_ui32:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: call __fixunssfsi
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
entry:
%conv = fptoui float %a to i32
ret i32 %conv
}

define i32 @fp32_to_si32(float %a) nounwind {
; RV64I-LABEL: fp32_to_si32:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: call __fixsfsi
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
entry:
%conv = fptosi float %a to i32
ret i32 %conv
}

define i32 @fp64_to_ui32(double %a) nounwind {
; RV64I-LABEL: fp64_to_ui32:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: call __fixunsdfsi
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
entry:
%conv = fptoui double %a to i32
ret i32 %conv
}

define i32 @fp64_to_si32(double %a) nounwind {
; RV64I-LABEL: fp64_to_si32:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: call __fixdfsi
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
entry:
%conv = fptosi double %a to i32
ret i32 %conv
}



declare i32 @llvm.experimental.constrained.fptoui.i32.f32(float, metadata)
declare i32 @llvm.experimental.constrained.fptosi.i32.f32(float, metadata)
declare i32 @llvm.experimental.constrained.fptosi.i32.f64(double, metadata)
declare i32 @llvm.experimental.constrained.fptoui.i32.f64(double, metadata)

define i32 @strict_fp32_to_ui32(float %a) nounwind strictfp {
; RV64I-LABEL: strict_fp32_to_ui32:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: call __fixunssfsi
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
entry:
%conv = tail call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %a, metadata !"fpexcept.strict")
ret i32 %conv
}

define i32 @strict_fp32_to_si32(float %a) nounwind strictfp {
; RV64I-LABEL: strict_fp32_to_si32:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: call __fixsfsi
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
entry:
%conv = tail call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %a, metadata !"fpexcept.strict")
ret i32 %conv
}

define i32 @strict_fp64_to_ui32(double %a) nounwind strictfp {
; RV64I-LABEL: strict_fp64_to_ui32:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: call __fixunsdfsi
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
entry:
%conv = tail call i32 @llvm.experimental.constrained.fptoui.i32.f64(double %a, metadata !"fpexcept.strict")
ret i32 %conv
}

define i32 @struct_fp64_to_si32(double %a) nounwind strictfp {
; RV64I-LABEL: struct_fp64_to_si32:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: call __fixdfsi
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
entry:
%conv = tail call i32 @llvm.experimental.constrained.fptosi.i32.f64(double %a, metadata !"fpexcept.strict")
ret i32 %conv
}

8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/vararg.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -64,7 +64,7 @@ define i32 @va1(i8* %fmt, ...) {
; ILP32-ILP32F-WITHFP-NEXT: .cfi_offset ra, -36
; ILP32-ILP32F-WITHFP-NEXT: .cfi_offset s0, -40
; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16
; ILP32-ILP32F-WITHFP-NEXT: .cfi_def_cfa s0, 0
; ILP32-ILP32F-WITHFP-NEXT: .cfi_def_cfa s0, 32
; ILP32-ILP32F-WITHFP-NEXT: mv a0, a1
; ILP32-ILP32F-WITHFP-NEXT: sw a7, 28(s0)
; ILP32-ILP32F-WITHFP-NEXT: sw a6, 24(s0)
Expand Down Expand Up @@ -124,7 +124,7 @@ define i32 @va1(i8* %fmt, ...) {
; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_offset ra, -72
; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_offset s0, -80
; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 32
; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_def_cfa s0, 0
; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_def_cfa s0, 64
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, 8(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 56(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 48(s0)
Expand Down Expand Up @@ -1809,7 +1809,7 @@ define i32 @va_large_stack(i8* %fmt, ...) {
; ILP32-ILP32F-WITHFP-NEXT: .cfi_offset ra, -36
; ILP32-ILP32F-WITHFP-NEXT: .cfi_offset s0, -40
; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 2000
; ILP32-ILP32F-WITHFP-NEXT: .cfi_def_cfa s0, 0
; ILP32-ILP32F-WITHFP-NEXT: .cfi_def_cfa s0, 32
; ILP32-ILP32F-WITHFP-NEXT: lui a0, 24414
; ILP32-ILP32F-WITHFP-NEXT: addi a0, a0, -1728
; ILP32-ILP32F-WITHFP-NEXT: sub sp, sp, a0
Expand Down Expand Up @@ -1937,7 +1937,7 @@ define i32 @va_large_stack(i8* %fmt, ...) {
; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_offset ra, -72
; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_offset s0, -80
; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 1968
; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_def_cfa s0, 0
; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_def_cfa s0, 64
; LP64-LP64F-LP64D-WITHFP-NEXT: lui a0, 24414
; LP64-LP64F-LP64D-WITHFP-NEXT: addiw a0, a0, -1680
; LP64-LP64F-LP64D-WITHFP-NEXT: sub sp, sp, a0
Expand Down