313 changes: 313 additions & 0 deletions llvm/test/MC/AArch64/SME2/fmax.s
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST


fmax {z0.d, z1.d}, {z0.d, z1.d}, z0.d // 11000001-11100000-10100001-00000000
// CHECK-INST: fmax { z0.d, z1.d }, { z0.d, z1.d }, z0.d
// CHECK-ENCODING: [0x00,0xa1,0xe0,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e0a100 <unknown>

fmax {z20.d, z21.d}, {z20.d, z21.d}, z5.d // 11000001-11100101-10100001-00010100
// CHECK-INST: fmax { z20.d, z21.d }, { z20.d, z21.d }, z5.d
// CHECK-ENCODING: [0x14,0xa1,0xe5,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e5a114 <unknown>

fmax {z22.d, z23.d}, {z22.d, z23.d}, z8.d // 11000001-11101000-10100001-00010110
// CHECK-INST: fmax { z22.d, z23.d }, { z22.d, z23.d }, z8.d
// CHECK-ENCODING: [0x16,0xa1,0xe8,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e8a116 <unknown>

fmax {z30.d, z31.d}, {z30.d, z31.d}, z15.d // 11000001-11101111-10100001-00011110
// CHECK-INST: fmax { z30.d, z31.d }, { z30.d, z31.d }, z15.d
// CHECK-ENCODING: [0x1e,0xa1,0xef,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1efa11e <unknown>


fmax {z0.d, z1.d}, {z0.d, z1.d}, {z0.d, z1.d} // 11000001-11100000-10110001-00000000
// CHECK-INST: fmax { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }
// CHECK-ENCODING: [0x00,0xb1,0xe0,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e0b100 <unknown>

fmax {z20.d, z21.d}, {z20.d, z21.d}, {z20.d, z21.d} // 11000001-11110100-10110001-00010100
// CHECK-INST: fmax { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }
// CHECK-ENCODING: [0x14,0xb1,0xf4,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1f4b114 <unknown>

fmax {z22.d, z23.d}, {z22.d, z23.d}, {z8.d, z9.d} // 11000001-11101000-10110001-00010110
// CHECK-INST: fmax { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }
// CHECK-ENCODING: [0x16,0xb1,0xe8,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e8b116 <unknown>

fmax {z30.d, z31.d}, {z30.d, z31.d}, {z30.d, z31.d} // 11000001-11111110-10110001-00011110
// CHECK-INST: fmax { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }
// CHECK-ENCODING: [0x1e,0xb1,0xfe,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1feb11e <unknown>


fmax {z0.h, z1.h}, {z0.h, z1.h}, z0.h // 11000001-01100000-10100001-00000000
// CHECK-INST: fmax { z0.h, z1.h }, { z0.h, z1.h }, z0.h
// CHECK-ENCODING: [0x00,0xa1,0x60,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c160a100 <unknown>

fmax {z20.h, z21.h}, {z20.h, z21.h}, z5.h // 11000001-01100101-10100001-00010100
// CHECK-INST: fmax { z20.h, z21.h }, { z20.h, z21.h }, z5.h
// CHECK-ENCODING: [0x14,0xa1,0x65,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c165a114 <unknown>

fmax {z22.h, z23.h}, {z22.h, z23.h}, z8.h // 11000001-01101000-10100001-00010110
// CHECK-INST: fmax { z22.h, z23.h }, { z22.h, z23.h }, z8.h
// CHECK-ENCODING: [0x16,0xa1,0x68,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c168a116 <unknown>

fmax {z30.h, z31.h}, {z30.h, z31.h}, z15.h // 11000001-01101111-10100001-00011110
// CHECK-INST: fmax { z30.h, z31.h }, { z30.h, z31.h }, z15.h
// CHECK-ENCODING: [0x1e,0xa1,0x6f,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c16fa11e <unknown>


fmax {z0.h, z1.h}, {z0.h, z1.h}, {z0.h, z1.h} // 11000001-01100000-10110001-00000000
// CHECK-INST: fmax { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }
// CHECK-ENCODING: [0x00,0xb1,0x60,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c160b100 <unknown>

fmax {z20.h, z21.h}, {z20.h, z21.h}, {z20.h, z21.h} // 11000001-01110100-10110001-00010100
// CHECK-INST: fmax { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }
// CHECK-ENCODING: [0x14,0xb1,0x74,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c174b114 <unknown>

fmax {z22.h, z23.h}, {z22.h, z23.h}, {z8.h, z9.h} // 11000001-01101000-10110001-00010110
// CHECK-INST: fmax { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }
// CHECK-ENCODING: [0x16,0xb1,0x68,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c168b116 <unknown>

fmax {z30.h, z31.h}, {z30.h, z31.h}, {z30.h, z31.h} // 11000001-01111110-10110001-00011110
// CHECK-INST: fmax { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }
// CHECK-ENCODING: [0x1e,0xb1,0x7e,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c17eb11e <unknown>


fmax {z0.s, z1.s}, {z0.s, z1.s}, z0.s // 11000001-10100000-10100001-00000000
// CHECK-INST: fmax { z0.s, z1.s }, { z0.s, z1.s }, z0.s
// CHECK-ENCODING: [0x00,0xa1,0xa0,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a0a100 <unknown>

fmax {z20.s, z21.s}, {z20.s, z21.s}, z5.s // 11000001-10100101-10100001-00010100
// CHECK-INST: fmax { z20.s, z21.s }, { z20.s, z21.s }, z5.s
// CHECK-ENCODING: [0x14,0xa1,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a5a114 <unknown>

fmax {z22.s, z23.s}, {z22.s, z23.s}, z8.s // 11000001-10101000-10100001-00010110
// CHECK-INST: fmax { z22.s, z23.s }, { z22.s, z23.s }, z8.s
// CHECK-ENCODING: [0x16,0xa1,0xa8,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a8a116 <unknown>

fmax {z30.s, z31.s}, {z30.s, z31.s}, z15.s // 11000001-10101111-10100001-00011110
// CHECK-INST: fmax { z30.s, z31.s }, { z30.s, z31.s }, z15.s
// CHECK-ENCODING: [0x1e,0xa1,0xaf,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1afa11e <unknown>


fmax {z0.s, z1.s}, {z0.s, z1.s}, {z0.s, z1.s} // 11000001-10100000-10110001-00000000
// CHECK-INST: fmax { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }
// CHECK-ENCODING: [0x00,0xb1,0xa0,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a0b100 <unknown>

fmax {z20.s, z21.s}, {z20.s, z21.s}, {z20.s, z21.s} // 11000001-10110100-10110001-00010100
// CHECK-INST: fmax { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }
// CHECK-ENCODING: [0x14,0xb1,0xb4,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1b4b114 <unknown>

fmax {z22.s, z23.s}, {z22.s, z23.s}, {z8.s, z9.s} // 11000001-10101000-10110001-00010110
// CHECK-INST: fmax { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }
// CHECK-ENCODING: [0x16,0xb1,0xa8,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a8b116 <unknown>

fmax {z30.s, z31.s}, {z30.s, z31.s}, {z30.s, z31.s} // 11000001-10111110-10110001-00011110
// CHECK-INST: fmax { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }
// CHECK-ENCODING: [0x1e,0xb1,0xbe,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1beb11e <unknown>


fmax {z0.d - z3.d}, {z0.d - z3.d}, z0.d // 11000001-11100000-10101001-00000000
// CHECK-INST: fmax { z0.d - z3.d }, { z0.d - z3.d }, z0.d
// CHECK-ENCODING: [0x00,0xa9,0xe0,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e0a900 <unknown>

fmax {z20.d - z23.d}, {z20.d - z23.d}, z5.d // 11000001-11100101-10101001-00010100
// CHECK-INST: fmax { z20.d - z23.d }, { z20.d - z23.d }, z5.d
// CHECK-ENCODING: [0x14,0xa9,0xe5,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e5a914 <unknown>

fmax {z20.d - z23.d}, {z20.d - z23.d}, z8.d // 11000001-11101000-10101001-00010100
// CHECK-INST: fmax { z20.d - z23.d }, { z20.d - z23.d }, z8.d
// CHECK-ENCODING: [0x14,0xa9,0xe8,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e8a914 <unknown>

fmax {z28.d - z31.d}, {z28.d - z31.d}, z15.d // 11000001-11101111-10101001-00011100
// CHECK-INST: fmax { z28.d - z31.d }, { z28.d - z31.d }, z15.d
// CHECK-ENCODING: [0x1c,0xa9,0xef,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1efa91c <unknown>


fmax {z0.d - z3.d}, {z0.d - z3.d}, {z0.d - z3.d} // 11000001-11100000-10111001-00000000
// CHECK-INST: fmax { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }
// CHECK-ENCODING: [0x00,0xb9,0xe0,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e0b900 <unknown>

fmax {z20.d - z23.d}, {z20.d - z23.d}, {z20.d - z23.d} // 11000001-11110100-10111001-00010100
// CHECK-INST: fmax { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }
// CHECK-ENCODING: [0x14,0xb9,0xf4,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1f4b914 <unknown>

fmax {z20.d - z23.d}, {z20.d - z23.d}, {z8.d - z11.d} // 11000001-11101000-10111001-00010100
// CHECK-INST: fmax { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }
// CHECK-ENCODING: [0x14,0xb9,0xe8,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e8b914 <unknown>

fmax {z28.d - z31.d}, {z28.d - z31.d}, {z28.d - z31.d} // 11000001-11111100-10111001-00011100
// CHECK-INST: fmax { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }
// CHECK-ENCODING: [0x1c,0xb9,0xfc,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1fcb91c <unknown>


fmax {z0.h - z3.h}, {z0.h - z3.h}, z0.h // 11000001-01100000-10101001-00000000
// CHECK-INST: fmax { z0.h - z3.h }, { z0.h - z3.h }, z0.h
// CHECK-ENCODING: [0x00,0xa9,0x60,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c160a900 <unknown>

fmax {z20.h - z23.h}, {z20.h - z23.h}, z5.h // 11000001-01100101-10101001-00010100
// CHECK-INST: fmax { z20.h - z23.h }, { z20.h - z23.h }, z5.h
// CHECK-ENCODING: [0x14,0xa9,0x65,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c165a914 <unknown>

fmax {z20.h - z23.h}, {z20.h - z23.h}, z8.h // 11000001-01101000-10101001-00010100
// CHECK-INST: fmax { z20.h - z23.h }, { z20.h - z23.h }, z8.h
// CHECK-ENCODING: [0x14,0xa9,0x68,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c168a914 <unknown>

fmax {z28.h - z31.h}, {z28.h - z31.h}, z15.h // 11000001-01101111-10101001-00011100
// CHECK-INST: fmax { z28.h - z31.h }, { z28.h - z31.h }, z15.h
// CHECK-ENCODING: [0x1c,0xa9,0x6f,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c16fa91c <unknown>


fmax {z0.h - z3.h}, {z0.h - z3.h}, {z0.h - z3.h} // 11000001-01100000-10111001-00000000
// CHECK-INST: fmax { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }
// CHECK-ENCODING: [0x00,0xb9,0x60,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c160b900 <unknown>

fmax {z20.h - z23.h}, {z20.h - z23.h}, {z20.h - z23.h} // 11000001-01110100-10111001-00010100
// CHECK-INST: fmax { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }
// CHECK-ENCODING: [0x14,0xb9,0x74,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c174b914 <unknown>

fmax {z20.h - z23.h}, {z20.h - z23.h}, {z8.h - z11.h} // 11000001-01101000-10111001-00010100
// CHECK-INST: fmax { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }
// CHECK-ENCODING: [0x14,0xb9,0x68,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c168b914 <unknown>

fmax {z28.h - z31.h}, {z28.h - z31.h}, {z28.h - z31.h} // 11000001-01111100-10111001-00011100
// CHECK-INST: fmax { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }
// CHECK-ENCODING: [0x1c,0xb9,0x7c,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c17cb91c <unknown>


fmax {z0.s - z3.s}, {z0.s - z3.s}, z0.s // 11000001-10100000-10101001-00000000
// CHECK-INST: fmax { z0.s - z3.s }, { z0.s - z3.s }, z0.s
// CHECK-ENCODING: [0x00,0xa9,0xa0,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a0a900 <unknown>

fmax {z20.s - z23.s}, {z20.s - z23.s}, z5.s // 11000001-10100101-10101001-00010100
// CHECK-INST: fmax { z20.s - z23.s }, { z20.s - z23.s }, z5.s
// CHECK-ENCODING: [0x14,0xa9,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a5a914 <unknown>

fmax {z20.s - z23.s}, {z20.s - z23.s}, z8.s // 11000001-10101000-10101001-00010100
// CHECK-INST: fmax { z20.s - z23.s }, { z20.s - z23.s }, z8.s
// CHECK-ENCODING: [0x14,0xa9,0xa8,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a8a914 <unknown>

fmax {z28.s - z31.s}, {z28.s - z31.s}, z15.s // 11000001-10101111-10101001-00011100
// CHECK-INST: fmax { z28.s - z31.s }, { z28.s - z31.s }, z15.s
// CHECK-ENCODING: [0x1c,0xa9,0xaf,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1afa91c <unknown>


fmax {z0.s - z3.s}, {z0.s - z3.s}, {z0.s - z3.s} // 11000001-10100000-10111001-00000000
// CHECK-INST: fmax { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }
// CHECK-ENCODING: [0x00,0xb9,0xa0,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a0b900 <unknown>

fmax {z20.s - z23.s}, {z20.s - z23.s}, {z20.s - z23.s} // 11000001-10110100-10111001-00010100
// CHECK-INST: fmax { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }
// CHECK-ENCODING: [0x14,0xb9,0xb4,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1b4b914 <unknown>

fmax {z20.s - z23.s}, {z20.s - z23.s}, {z8.s - z11.s} // 11000001-10101000-10111001-00010100
// CHECK-INST: fmax { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }
// CHECK-ENCODING: [0x14,0xb9,0xa8,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a8b914 <unknown>

fmax {z28.s - z31.s}, {z28.s - z31.s}, {z28.s - z31.s} // 11000001-10111100-10111001-00011100
// CHECK-INST: fmax { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }
// CHECK-ENCODING: [0x1c,0xb9,0xbc,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1bcb91c <unknown>

30 changes: 30 additions & 0 deletions llvm/test/MC/AArch64/SME2/fmaxnm-diagnostics.s
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s

// --------------------------------------------------------------------------//
// Invalid vector list

fmaxnm {z0.d, z1.d}, {z0.d-z2.d}, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fmaxnm {z0.d, z1.d}, {z0.d-z2.d}, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

fmaxnm {z1.s-z2.s}, {z0.s, z1.s}, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element type
// CHECK-NEXT: fmaxnm {z1.s-z2.s}, {z0.s, z1.s}, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid single register

fmaxnm {z0.h, z1.h}, {z2.h-z3.h}, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
// CHECK-NEXT: fmaxnm {z0.h, z1.h}, {z2.h-z3.h}, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid Register Suffix

fmaxnm {z0.h, z1.h}, {z2.h-z3.h}, z14.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
// CHECK-NEXT: fmaxnm {z0.h, z1.h}, {z2.h-z3.h}, z14.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
313 changes: 313 additions & 0 deletions llvm/test/MC/AArch64/SME2/fmaxnm.s
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST


fmaxnm {z0.d, z1.d}, {z0.d, z1.d}, z0.d // 11000001-11100000-10100001-00100000
// CHECK-INST: fmaxnm { z0.d, z1.d }, { z0.d, z1.d }, z0.d
// CHECK-ENCODING: [0x20,0xa1,0xe0,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e0a120 <unknown>

fmaxnm {z20.d, z21.d}, {z20.d, z21.d}, z5.d // 11000001-11100101-10100001-00110100
// CHECK-INST: fmaxnm { z20.d, z21.d }, { z20.d, z21.d }, z5.d
// CHECK-ENCODING: [0x34,0xa1,0xe5,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e5a134 <unknown>

fmaxnm {z22.d, z23.d}, {z22.d, z23.d}, z8.d // 11000001-11101000-10100001-00110110
// CHECK-INST: fmaxnm { z22.d, z23.d }, { z22.d, z23.d }, z8.d
// CHECK-ENCODING: [0x36,0xa1,0xe8,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e8a136 <unknown>

fmaxnm {z30.d, z31.d}, {z30.d, z31.d}, z15.d // 11000001-11101111-10100001-00111110
// CHECK-INST: fmaxnm { z30.d, z31.d }, { z30.d, z31.d }, z15.d
// CHECK-ENCODING: [0x3e,0xa1,0xef,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1efa13e <unknown>


fmaxnm {z0.d, z1.d}, {z0.d, z1.d}, {z0.d, z1.d} // 11000001-11100000-10110001-00100000
// CHECK-INST: fmaxnm { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }
// CHECK-ENCODING: [0x20,0xb1,0xe0,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e0b120 <unknown>

fmaxnm {z20.d, z21.d}, {z20.d, z21.d}, {z20.d, z21.d} // 11000001-11110100-10110001-00110100
// CHECK-INST: fmaxnm { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }
// CHECK-ENCODING: [0x34,0xb1,0xf4,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1f4b134 <unknown>

fmaxnm {z22.d, z23.d}, {z22.d, z23.d}, {z8.d, z9.d} // 11000001-11101000-10110001-00110110
// CHECK-INST: fmaxnm { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }
// CHECK-ENCODING: [0x36,0xb1,0xe8,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e8b136 <unknown>

fmaxnm {z30.d, z31.d}, {z30.d, z31.d}, {z30.d, z31.d} // 11000001-11111110-10110001-00111110
// CHECK-INST: fmaxnm { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }
// CHECK-ENCODING: [0x3e,0xb1,0xfe,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1feb13e <unknown>


fmaxnm {z0.h, z1.h}, {z0.h, z1.h}, z0.h // 11000001-01100000-10100001-00100000
// CHECK-INST: fmaxnm { z0.h, z1.h }, { z0.h, z1.h }, z0.h
// CHECK-ENCODING: [0x20,0xa1,0x60,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c160a120 <unknown>

fmaxnm {z20.h, z21.h}, {z20.h, z21.h}, z5.h // 11000001-01100101-10100001-00110100
// CHECK-INST: fmaxnm { z20.h, z21.h }, { z20.h, z21.h }, z5.h
// CHECK-ENCODING: [0x34,0xa1,0x65,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c165a134 <unknown>

fmaxnm {z22.h, z23.h}, {z22.h, z23.h}, z8.h // 11000001-01101000-10100001-00110110
// CHECK-INST: fmaxnm { z22.h, z23.h }, { z22.h, z23.h }, z8.h
// CHECK-ENCODING: [0x36,0xa1,0x68,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c168a136 <unknown>

fmaxnm {z30.h, z31.h}, {z30.h, z31.h}, z15.h // 11000001-01101111-10100001-00111110
// CHECK-INST: fmaxnm { z30.h, z31.h }, { z30.h, z31.h }, z15.h
// CHECK-ENCODING: [0x3e,0xa1,0x6f,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c16fa13e <unknown>


fmaxnm {z0.h, z1.h}, {z0.h, z1.h}, {z0.h, z1.h} // 11000001-01100000-10110001-00100000
// CHECK-INST: fmaxnm { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }
// CHECK-ENCODING: [0x20,0xb1,0x60,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c160b120 <unknown>

fmaxnm {z20.h, z21.h}, {z20.h, z21.h}, {z20.h, z21.h} // 11000001-01110100-10110001-00110100
// CHECK-INST: fmaxnm { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }
// CHECK-ENCODING: [0x34,0xb1,0x74,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c174b134 <unknown>

fmaxnm {z22.h, z23.h}, {z22.h, z23.h}, {z8.h, z9.h} // 11000001-01101000-10110001-00110110
// CHECK-INST: fmaxnm { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }
// CHECK-ENCODING: [0x36,0xb1,0x68,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c168b136 <unknown>

fmaxnm {z30.h, z31.h}, {z30.h, z31.h}, {z30.h, z31.h} // 11000001-01111110-10110001-00111110
// CHECK-INST: fmaxnm { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }
// CHECK-ENCODING: [0x3e,0xb1,0x7e,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c17eb13e <unknown>


fmaxnm {z0.s, z1.s}, {z0.s, z1.s}, z0.s // 11000001-10100000-10100001-00100000
// CHECK-INST: fmaxnm { z0.s, z1.s }, { z0.s, z1.s }, z0.s
// CHECK-ENCODING: [0x20,0xa1,0xa0,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a0a120 <unknown>

fmaxnm {z20.s, z21.s}, {z20.s, z21.s}, z5.s // 11000001-10100101-10100001-00110100
// CHECK-INST: fmaxnm { z20.s, z21.s }, { z20.s, z21.s }, z5.s
// CHECK-ENCODING: [0x34,0xa1,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a5a134 <unknown>

fmaxnm {z22.s, z23.s}, {z22.s, z23.s}, z8.s // 11000001-10101000-10100001-00110110
// CHECK-INST: fmaxnm { z22.s, z23.s }, { z22.s, z23.s }, z8.s
// CHECK-ENCODING: [0x36,0xa1,0xa8,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a8a136 <unknown>

fmaxnm {z30.s, z31.s}, {z30.s, z31.s}, z15.s // 11000001-10101111-10100001-00111110
// CHECK-INST: fmaxnm { z30.s, z31.s }, { z30.s, z31.s }, z15.s
// CHECK-ENCODING: [0x3e,0xa1,0xaf,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1afa13e <unknown>


fmaxnm {z0.s, z1.s}, {z0.s, z1.s}, {z0.s, z1.s} // 11000001-10100000-10110001-00100000
// CHECK-INST: fmaxnm { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }
// CHECK-ENCODING: [0x20,0xb1,0xa0,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a0b120 <unknown>

fmaxnm {z20.s, z21.s}, {z20.s, z21.s}, {z20.s, z21.s} // 11000001-10110100-10110001-00110100
// CHECK-INST: fmaxnm { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }
// CHECK-ENCODING: [0x34,0xb1,0xb4,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1b4b134 <unknown>

fmaxnm {z22.s, z23.s}, {z22.s, z23.s}, {z8.s, z9.s} // 11000001-10101000-10110001-00110110
// CHECK-INST: fmaxnm { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }
// CHECK-ENCODING: [0x36,0xb1,0xa8,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a8b136 <unknown>

fmaxnm {z30.s, z31.s}, {z30.s, z31.s}, {z30.s, z31.s} // 11000001-10111110-10110001-00111110
// CHECK-INST: fmaxnm { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }
// CHECK-ENCODING: [0x3e,0xb1,0xbe,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1beb13e <unknown>


fmaxnm {z0.d - z3.d}, {z0.d - z3.d}, z0.d // 11000001-11100000-10101001-00100000
// CHECK-INST: fmaxnm { z0.d - z3.d }, { z0.d - z3.d }, z0.d
// CHECK-ENCODING: [0x20,0xa9,0xe0,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e0a920 <unknown>

fmaxnm {z20.d - z23.d}, {z20.d - z23.d}, z5.d // 11000001-11100101-10101001-00110100
// CHECK-INST: fmaxnm { z20.d - z23.d }, { z20.d - z23.d }, z5.d
// CHECK-ENCODING: [0x34,0xa9,0xe5,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e5a934 <unknown>

fmaxnm {z20.d - z23.d}, {z20.d - z23.d}, z8.d // 11000001-11101000-10101001-00110100
// CHECK-INST: fmaxnm { z20.d - z23.d }, { z20.d - z23.d }, z8.d
// CHECK-ENCODING: [0x34,0xa9,0xe8,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e8a934 <unknown>

fmaxnm {z28.d - z31.d}, {z28.d - z31.d}, z15.d // 11000001-11101111-10101001-00111100
// CHECK-INST: fmaxnm { z28.d - z31.d }, { z28.d - z31.d }, z15.d
// CHECK-ENCODING: [0x3c,0xa9,0xef,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1efa93c <unknown>


fmaxnm {z0.d - z3.d}, {z0.d - z3.d}, {z0.d - z3.d} // 11000001-11100000-10111001-00100000
// CHECK-INST: fmaxnm { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }
// CHECK-ENCODING: [0x20,0xb9,0xe0,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e0b920 <unknown>

fmaxnm {z20.d - z23.d}, {z20.d - z23.d}, {z20.d - z23.d} // 11000001-11110100-10111001-00110100
// CHECK-INST: fmaxnm { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }
// CHECK-ENCODING: [0x34,0xb9,0xf4,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1f4b934 <unknown>

fmaxnm {z20.d - z23.d}, {z20.d - z23.d}, {z8.d - z11.d} // 11000001-11101000-10111001-00110100
// CHECK-INST: fmaxnm { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }
// CHECK-ENCODING: [0x34,0xb9,0xe8,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e8b934 <unknown>

fmaxnm {z28.d - z31.d}, {z28.d - z31.d}, {z28.d - z31.d} // 11000001-11111100-10111001-00111100
// CHECK-INST: fmaxnm { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }
// CHECK-ENCODING: [0x3c,0xb9,0xfc,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1fcb93c <unknown>


fmaxnm {z0.h - z3.h}, {z0.h - z3.h}, z0.h // 11000001-01100000-10101001-00100000
// CHECK-INST: fmaxnm { z0.h - z3.h }, { z0.h - z3.h }, z0.h
// CHECK-ENCODING: [0x20,0xa9,0x60,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c160a920 <unknown>

fmaxnm {z20.h - z23.h}, {z20.h - z23.h}, z5.h // 11000001-01100101-10101001-00110100
// CHECK-INST: fmaxnm { z20.h - z23.h }, { z20.h - z23.h }, z5.h
// CHECK-ENCODING: [0x34,0xa9,0x65,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c165a934 <unknown>

fmaxnm {z20.h - z23.h}, {z20.h - z23.h}, z8.h // 11000001-01101000-10101001-00110100
// CHECK-INST: fmaxnm { z20.h - z23.h }, { z20.h - z23.h }, z8.h
// CHECK-ENCODING: [0x34,0xa9,0x68,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c168a934 <unknown>

fmaxnm {z28.h - z31.h}, {z28.h - z31.h}, z15.h // 11000001-01101111-10101001-00111100
// CHECK-INST: fmaxnm { z28.h - z31.h }, { z28.h - z31.h }, z15.h
// CHECK-ENCODING: [0x3c,0xa9,0x6f,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c16fa93c <unknown>


fmaxnm {z0.h - z3.h}, {z0.h - z3.h}, {z0.h - z3.h} // 11000001-01100000-10111001-00100000
// CHECK-INST: fmaxnm { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }
// CHECK-ENCODING: [0x20,0xb9,0x60,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c160b920 <unknown>

fmaxnm {z20.h - z23.h}, {z20.h - z23.h}, {z20.h - z23.h} // 11000001-01110100-10111001-00110100
// CHECK-INST: fmaxnm { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }
// CHECK-ENCODING: [0x34,0xb9,0x74,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c174b934 <unknown>

fmaxnm {z20.h - z23.h}, {z20.h - z23.h}, {z8.h - z11.h} // 11000001-01101000-10111001-00110100
// CHECK-INST: fmaxnm { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }
// CHECK-ENCODING: [0x34,0xb9,0x68,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c168b934 <unknown>

fmaxnm {z28.h - z31.h}, {z28.h - z31.h}, {z28.h - z31.h} // 11000001-01111100-10111001-00111100
// CHECK-INST: fmaxnm { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }
// CHECK-ENCODING: [0x3c,0xb9,0x7c,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c17cb93c <unknown>


fmaxnm {z0.s - z3.s}, {z0.s - z3.s}, z0.s // 11000001-10100000-10101001-00100000
// CHECK-INST: fmaxnm { z0.s - z3.s }, { z0.s - z3.s }, z0.s
// CHECK-ENCODING: [0x20,0xa9,0xa0,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a0a920 <unknown>

fmaxnm {z20.s - z23.s}, {z20.s - z23.s}, z5.s // 11000001-10100101-10101001-00110100
// CHECK-INST: fmaxnm { z20.s - z23.s }, { z20.s - z23.s }, z5.s
// CHECK-ENCODING: [0x34,0xa9,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a5a934 <unknown>

fmaxnm {z20.s - z23.s}, {z20.s - z23.s}, z8.s // 11000001-10101000-10101001-00110100
// CHECK-INST: fmaxnm { z20.s - z23.s }, { z20.s - z23.s }, z8.s
// CHECK-ENCODING: [0x34,0xa9,0xa8,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a8a934 <unknown>

fmaxnm {z28.s - z31.s}, {z28.s - z31.s}, z15.s // 11000001-10101111-10101001-00111100
// CHECK-INST: fmaxnm { z28.s - z31.s }, { z28.s - z31.s }, z15.s
// CHECK-ENCODING: [0x3c,0xa9,0xaf,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1afa93c <unknown>


fmaxnm {z0.s - z3.s}, {z0.s - z3.s}, {z0.s - z3.s} // 11000001-10100000-10111001-00100000
// CHECK-INST: fmaxnm { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }
// CHECK-ENCODING: [0x20,0xb9,0xa0,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a0b920 <unknown>

fmaxnm {z20.s - z23.s}, {z20.s - z23.s}, {z20.s - z23.s} // 11000001-10110100-10111001-00110100
// CHECK-INST: fmaxnm { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }
// CHECK-ENCODING: [0x34,0xb9,0xb4,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1b4b934 <unknown>

fmaxnm {z20.s - z23.s}, {z20.s - z23.s}, {z8.s - z11.s} // 11000001-10101000-10111001-00110100
// CHECK-INST: fmaxnm { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }
// CHECK-ENCODING: [0x34,0xb9,0xa8,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a8b934 <unknown>

fmaxnm {z28.s - z31.s}, {z28.s - z31.s}, {z28.s - z31.s} // 11000001-10111100-10111001-00111100
// CHECK-INST: fmaxnm { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }
// CHECK-ENCODING: [0x3c,0xb9,0xbc,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1bcb93c <unknown>

30 changes: 30 additions & 0 deletions llvm/test/MC/AArch64/SME2/fmin-diagnostics.s
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Original file line number Diff line number Diff line change
@@ -0,0 +1,30 @@
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s

// --------------------------------------------------------------------------//
// Invalid vector list

fmin {z0.d, z1.d}, {z0.d-z2.d}, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fmin {z0.d, z1.d}, {z0.d-z2.d}, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

fmin {z1.s-z2.s}, {z0.s, z1.s}, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element type
// CHECK-NEXT: fmin {z1.s-z2.s}, {z0.s, z1.s}, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid single register

fmin {z0.h, z1.h}, {z2.h-z3.h}, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
// CHECK-NEXT: fmin {z0.h, z1.h}, {z2.h-z3.h}, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid Register Suffix

fmin {z0.h, z1.h}, {z2.h-z3.h}, z14.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
// CHECK-NEXT: fmin {z0.h, z1.h}, {z2.h-z3.h}, z14.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
313 changes: 313 additions & 0 deletions llvm/test/MC/AArch64/SME2/fmin.s
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Original file line number Diff line number Diff line change
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST


fmin {z0.d, z1.d}, {z0.d, z1.d}, z0.d // 11000001-11100000-10100001-00000001
// CHECK-INST: fmin { z0.d, z1.d }, { z0.d, z1.d }, z0.d
// CHECK-ENCODING: [0x01,0xa1,0xe0,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e0a101 <unknown>

fmin {z20.d, z21.d}, {z20.d, z21.d}, z5.d // 11000001-11100101-10100001-00010101
// CHECK-INST: fmin { z20.d, z21.d }, { z20.d, z21.d }, z5.d
// CHECK-ENCODING: [0x15,0xa1,0xe5,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e5a115 <unknown>

fmin {z22.d, z23.d}, {z22.d, z23.d}, z8.d // 11000001-11101000-10100001-00010111
// CHECK-INST: fmin { z22.d, z23.d }, { z22.d, z23.d }, z8.d
// CHECK-ENCODING: [0x17,0xa1,0xe8,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e8a117 <unknown>

fmin {z30.d, z31.d}, {z30.d, z31.d}, z15.d // 11000001-11101111-10100001-00011111
// CHECK-INST: fmin { z30.d, z31.d }, { z30.d, z31.d }, z15.d
// CHECK-ENCODING: [0x1f,0xa1,0xef,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1efa11f <unknown>


fmin {z0.d, z1.d}, {z0.d, z1.d}, {z0.d, z1.d} // 11000001-11100000-10110001-00000001
// CHECK-INST: fmin { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }
// CHECK-ENCODING: [0x01,0xb1,0xe0,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e0b101 <unknown>

fmin {z20.d, z21.d}, {z20.d, z21.d}, {z20.d, z21.d} // 11000001-11110100-10110001-00010101
// CHECK-INST: fmin { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }
// CHECK-ENCODING: [0x15,0xb1,0xf4,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1f4b115 <unknown>

fmin {z22.d, z23.d}, {z22.d, z23.d}, {z8.d, z9.d} // 11000001-11101000-10110001-00010111
// CHECK-INST: fmin { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }
// CHECK-ENCODING: [0x17,0xb1,0xe8,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e8b117 <unknown>

fmin {z30.d, z31.d}, {z30.d, z31.d}, {z30.d, z31.d} // 11000001-11111110-10110001-00011111
// CHECK-INST: fmin { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }
// CHECK-ENCODING: [0x1f,0xb1,0xfe,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1feb11f <unknown>


fmin {z0.h, z1.h}, {z0.h, z1.h}, z0.h // 11000001-01100000-10100001-00000001
// CHECK-INST: fmin { z0.h, z1.h }, { z0.h, z1.h }, z0.h
// CHECK-ENCODING: [0x01,0xa1,0x60,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c160a101 <unknown>

fmin {z20.h, z21.h}, {z20.h, z21.h}, z5.h // 11000001-01100101-10100001-00010101
// CHECK-INST: fmin { z20.h, z21.h }, { z20.h, z21.h }, z5.h
// CHECK-ENCODING: [0x15,0xa1,0x65,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c165a115 <unknown>

fmin {z22.h, z23.h}, {z22.h, z23.h}, z8.h // 11000001-01101000-10100001-00010111
// CHECK-INST: fmin { z22.h, z23.h }, { z22.h, z23.h }, z8.h
// CHECK-ENCODING: [0x17,0xa1,0x68,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c168a117 <unknown>

fmin {z30.h, z31.h}, {z30.h, z31.h}, z15.h // 11000001-01101111-10100001-00011111
// CHECK-INST: fmin { z30.h, z31.h }, { z30.h, z31.h }, z15.h
// CHECK-ENCODING: [0x1f,0xa1,0x6f,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c16fa11f <unknown>


fmin {z0.h, z1.h}, {z0.h, z1.h}, {z0.h, z1.h} // 11000001-01100000-10110001-00000001
// CHECK-INST: fmin { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }
// CHECK-ENCODING: [0x01,0xb1,0x60,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c160b101 <unknown>

fmin {z20.h, z21.h}, {z20.h, z21.h}, {z20.h, z21.h} // 11000001-01110100-10110001-00010101
// CHECK-INST: fmin { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }
// CHECK-ENCODING: [0x15,0xb1,0x74,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c174b115 <unknown>

fmin {z22.h, z23.h}, {z22.h, z23.h}, {z8.h, z9.h} // 11000001-01101000-10110001-00010111
// CHECK-INST: fmin { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }
// CHECK-ENCODING: [0x17,0xb1,0x68,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c168b117 <unknown>

fmin {z30.h, z31.h}, {z30.h, z31.h}, {z30.h, z31.h} // 11000001-01111110-10110001-00011111
// CHECK-INST: fmin { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }
// CHECK-ENCODING: [0x1f,0xb1,0x7e,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c17eb11f <unknown>


fmin {z0.s, z1.s}, {z0.s, z1.s}, z0.s // 11000001-10100000-10100001-00000001
// CHECK-INST: fmin { z0.s, z1.s }, { z0.s, z1.s }, z0.s
// CHECK-ENCODING: [0x01,0xa1,0xa0,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a0a101 <unknown>

fmin {z20.s, z21.s}, {z20.s, z21.s}, z5.s // 11000001-10100101-10100001-00010101
// CHECK-INST: fmin { z20.s, z21.s }, { z20.s, z21.s }, z5.s
// CHECK-ENCODING: [0x15,0xa1,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a5a115 <unknown>

fmin {z22.s, z23.s}, {z22.s, z23.s}, z8.s // 11000001-10101000-10100001-00010111
// CHECK-INST: fmin { z22.s, z23.s }, { z22.s, z23.s }, z8.s
// CHECK-ENCODING: [0x17,0xa1,0xa8,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a8a117 <unknown>

fmin {z30.s, z31.s}, {z30.s, z31.s}, z15.s // 11000001-10101111-10100001-00011111
// CHECK-INST: fmin { z30.s, z31.s }, { z30.s, z31.s }, z15.s
// CHECK-ENCODING: [0x1f,0xa1,0xaf,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1afa11f <unknown>


fmin {z0.s, z1.s}, {z0.s, z1.s}, {z0.s, z1.s} // 11000001-10100000-10110001-00000001
// CHECK-INST: fmin { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }
// CHECK-ENCODING: [0x01,0xb1,0xa0,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a0b101 <unknown>

fmin {z20.s, z21.s}, {z20.s, z21.s}, {z20.s, z21.s} // 11000001-10110100-10110001-00010101
// CHECK-INST: fmin { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }
// CHECK-ENCODING: [0x15,0xb1,0xb4,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1b4b115 <unknown>

fmin {z22.s, z23.s}, {z22.s, z23.s}, {z8.s, z9.s} // 11000001-10101000-10110001-00010111
// CHECK-INST: fmin { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }
// CHECK-ENCODING: [0x17,0xb1,0xa8,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a8b117 <unknown>

fmin {z30.s, z31.s}, {z30.s, z31.s}, {z30.s, z31.s} // 11000001-10111110-10110001-00011111
// CHECK-INST: fmin { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }
// CHECK-ENCODING: [0x1f,0xb1,0xbe,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1beb11f <unknown>


fmin {z0.d - z3.d}, {z0.d - z3.d}, z0.d // 11000001-11100000-10101001-00000001
// CHECK-INST: fmin { z0.d - z3.d }, { z0.d - z3.d }, z0.d
// CHECK-ENCODING: [0x01,0xa9,0xe0,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e0a901 <unknown>

fmin {z20.d - z23.d}, {z20.d - z23.d}, z5.d // 11000001-11100101-10101001-00010101
// CHECK-INST: fmin { z20.d - z23.d }, { z20.d - z23.d }, z5.d
// CHECK-ENCODING: [0x15,0xa9,0xe5,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e5a915 <unknown>

fmin {z20.d - z23.d}, {z20.d - z23.d}, z8.d // 11000001-11101000-10101001-00010101
// CHECK-INST: fmin { z20.d - z23.d }, { z20.d - z23.d }, z8.d
// CHECK-ENCODING: [0x15,0xa9,0xe8,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e8a915 <unknown>

fmin {z28.d - z31.d}, {z28.d - z31.d}, z15.d // 11000001-11101111-10101001-00011101
// CHECK-INST: fmin { z28.d - z31.d }, { z28.d - z31.d }, z15.d
// CHECK-ENCODING: [0x1d,0xa9,0xef,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1efa91d <unknown>


fmin {z0.d - z3.d}, {z0.d - z3.d}, {z0.d - z3.d} // 11000001-11100000-10111001-00000001
// CHECK-INST: fmin { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }
// CHECK-ENCODING: [0x01,0xb9,0xe0,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e0b901 <unknown>

fmin {z20.d - z23.d}, {z20.d - z23.d}, {z20.d - z23.d} // 11000001-11110100-10111001-00010101
// CHECK-INST: fmin { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }
// CHECK-ENCODING: [0x15,0xb9,0xf4,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1f4b915 <unknown>

fmin {z20.d - z23.d}, {z20.d - z23.d}, {z8.d - z11.d} // 11000001-11101000-10111001-00010101
// CHECK-INST: fmin { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }
// CHECK-ENCODING: [0x15,0xb9,0xe8,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e8b915 <unknown>

fmin {z28.d - z31.d}, {z28.d - z31.d}, {z28.d - z31.d} // 11000001-11111100-10111001-00011101
// CHECK-INST: fmin { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }
// CHECK-ENCODING: [0x1d,0xb9,0xfc,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1fcb91d <unknown>


fmin {z0.h - z3.h}, {z0.h - z3.h}, z0.h // 11000001-01100000-10101001-00000001
// CHECK-INST: fmin { z0.h - z3.h }, { z0.h - z3.h }, z0.h
// CHECK-ENCODING: [0x01,0xa9,0x60,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c160a901 <unknown>

fmin {z20.h - z23.h}, {z20.h - z23.h}, z5.h // 11000001-01100101-10101001-00010101
// CHECK-INST: fmin { z20.h - z23.h }, { z20.h - z23.h }, z5.h
// CHECK-ENCODING: [0x15,0xa9,0x65,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c165a915 <unknown>

fmin {z20.h - z23.h}, {z20.h - z23.h}, z8.h // 11000001-01101000-10101001-00010101
// CHECK-INST: fmin { z20.h - z23.h }, { z20.h - z23.h }, z8.h
// CHECK-ENCODING: [0x15,0xa9,0x68,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c168a915 <unknown>

fmin {z28.h - z31.h}, {z28.h - z31.h}, z15.h // 11000001-01101111-10101001-00011101
// CHECK-INST: fmin { z28.h - z31.h }, { z28.h - z31.h }, z15.h
// CHECK-ENCODING: [0x1d,0xa9,0x6f,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c16fa91d <unknown>


fmin {z0.h - z3.h}, {z0.h - z3.h}, {z0.h - z3.h} // 11000001-01100000-10111001-00000001
// CHECK-INST: fmin { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }
// CHECK-ENCODING: [0x01,0xb9,0x60,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c160b901 <unknown>

fmin {z20.h - z23.h}, {z20.h - z23.h}, {z20.h - z23.h} // 11000001-01110100-10111001-00010101
// CHECK-INST: fmin { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }
// CHECK-ENCODING: [0x15,0xb9,0x74,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c174b915 <unknown>

fmin {z20.h - z23.h}, {z20.h - z23.h}, {z8.h - z11.h} // 11000001-01101000-10111001-00010101
// CHECK-INST: fmin { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }
// CHECK-ENCODING: [0x15,0xb9,0x68,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c168b915 <unknown>

fmin {z28.h - z31.h}, {z28.h - z31.h}, {z28.h - z31.h} // 11000001-01111100-10111001-00011101
// CHECK-INST: fmin { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }
// CHECK-ENCODING: [0x1d,0xb9,0x7c,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c17cb91d <unknown>


fmin {z0.s - z3.s}, {z0.s - z3.s}, z0.s // 11000001-10100000-10101001-00000001
// CHECK-INST: fmin { z0.s - z3.s }, { z0.s - z3.s }, z0.s
// CHECK-ENCODING: [0x01,0xa9,0xa0,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a0a901 <unknown>

fmin {z20.s - z23.s}, {z20.s - z23.s}, z5.s // 11000001-10100101-10101001-00010101
// CHECK-INST: fmin { z20.s - z23.s }, { z20.s - z23.s }, z5.s
// CHECK-ENCODING: [0x15,0xa9,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a5a915 <unknown>

fmin {z20.s - z23.s}, {z20.s - z23.s}, z8.s // 11000001-10101000-10101001-00010101
// CHECK-INST: fmin { z20.s - z23.s }, { z20.s - z23.s }, z8.s
// CHECK-ENCODING: [0x15,0xa9,0xa8,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a8a915 <unknown>

fmin {z28.s - z31.s}, {z28.s - z31.s}, z15.s // 11000001-10101111-10101001-00011101
// CHECK-INST: fmin { z28.s - z31.s }, { z28.s - z31.s }, z15.s
// CHECK-ENCODING: [0x1d,0xa9,0xaf,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1afa91d <unknown>


fmin {z0.s - z3.s}, {z0.s - z3.s}, {z0.s - z3.s} // 11000001-10100000-10111001-00000001
// CHECK-INST: fmin { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }
// CHECK-ENCODING: [0x01,0xb9,0xa0,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a0b901 <unknown>

fmin {z20.s - z23.s}, {z20.s - z23.s}, {z20.s - z23.s} // 11000001-10110100-10111001-00010101
// CHECK-INST: fmin { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }
// CHECK-ENCODING: [0x15,0xb9,0xb4,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1b4b915 <unknown>

fmin {z20.s - z23.s}, {z20.s - z23.s}, {z8.s - z11.s} // 11000001-10101000-10111001-00010101
// CHECK-INST: fmin { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }
// CHECK-ENCODING: [0x15,0xb9,0xa8,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a8b915 <unknown>

fmin {z28.s - z31.s}, {z28.s - z31.s}, {z28.s - z31.s} // 11000001-10111100-10111001-00011101
// CHECK-INST: fmin { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }
// CHECK-ENCODING: [0x1d,0xb9,0xbc,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1bcb91d <unknown>

30 changes: 30 additions & 0 deletions llvm/test/MC/AArch64/SME2/fminnm-diagnostics.s
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,30 @@
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s

// --------------------------------------------------------------------------//
// Invalid vector list

fminnm {z0.d, z1.d}, {z0.d-z2.d}, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fminnm {z0.d, z1.d}, {z0.d-z2.d}, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

fminnm {z1.s-z2.s}, {z0.s, z1.s}, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element type
// CHECK-NEXT: fminnm {z1.s-z2.s}, {z0.s, z1.s}, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid single register

fminnm {z0.h, z1.h}, {z2.h-z3.h}, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
// CHECK-NEXT: fminnm {z0.h, z1.h}, {z2.h-z3.h}, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid Register Suffix

fminnm {z0.h, z1.h}, {z2.h-z3.h}, z14.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
// CHECK-NEXT: fminnm {z0.h, z1.h}, {z2.h-z3.h}, z14.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
313 changes: 313 additions & 0 deletions llvm/test/MC/AArch64/SME2/fminnm.s
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Original file line number Diff line number Diff line change
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST


fminnm {z0.d, z1.d}, {z0.d, z1.d}, z0.d // 11000001-11100000-10100001-00100001
// CHECK-INST: fminnm { z0.d, z1.d }, { z0.d, z1.d }, z0.d
// CHECK-ENCODING: [0x21,0xa1,0xe0,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e0a121 <unknown>

fminnm {z20.d, z21.d}, {z20.d, z21.d}, z5.d // 11000001-11100101-10100001-00110101
// CHECK-INST: fminnm { z20.d, z21.d }, { z20.d, z21.d }, z5.d
// CHECK-ENCODING: [0x35,0xa1,0xe5,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e5a135 <unknown>

fminnm {z22.d, z23.d}, {z22.d, z23.d}, z8.d // 11000001-11101000-10100001-00110111
// CHECK-INST: fminnm { z22.d, z23.d }, { z22.d, z23.d }, z8.d
// CHECK-ENCODING: [0x37,0xa1,0xe8,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e8a137 <unknown>

fminnm {z30.d, z31.d}, {z30.d, z31.d}, z15.d // 11000001-11101111-10100001-00111111
// CHECK-INST: fminnm { z30.d, z31.d }, { z30.d, z31.d }, z15.d
// CHECK-ENCODING: [0x3f,0xa1,0xef,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1efa13f <unknown>


fminnm {z0.d, z1.d}, {z0.d, z1.d}, {z0.d, z1.d} // 11000001-11100000-10110001-00100001
// CHECK-INST: fminnm { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }
// CHECK-ENCODING: [0x21,0xb1,0xe0,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e0b121 <unknown>

fminnm {z20.d, z21.d}, {z20.d, z21.d}, {z20.d, z21.d} // 11000001-11110100-10110001-00110101
// CHECK-INST: fminnm { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }
// CHECK-ENCODING: [0x35,0xb1,0xf4,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1f4b135 <unknown>

fminnm {z22.d, z23.d}, {z22.d, z23.d}, {z8.d, z9.d} // 11000001-11101000-10110001-00110111
// CHECK-INST: fminnm { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }
// CHECK-ENCODING: [0x37,0xb1,0xe8,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e8b137 <unknown>

fminnm {z30.d, z31.d}, {z30.d, z31.d}, {z30.d, z31.d} // 11000001-11111110-10110001-00111111
// CHECK-INST: fminnm { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }
// CHECK-ENCODING: [0x3f,0xb1,0xfe,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1feb13f <unknown>


fminnm {z0.h, z1.h}, {z0.h, z1.h}, z0.h // 11000001-01100000-10100001-00100001
// CHECK-INST: fminnm { z0.h, z1.h }, { z0.h, z1.h }, z0.h
// CHECK-ENCODING: [0x21,0xa1,0x60,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c160a121 <unknown>

fminnm {z20.h, z21.h}, {z20.h, z21.h}, z5.h // 11000001-01100101-10100001-00110101
// CHECK-INST: fminnm { z20.h, z21.h }, { z20.h, z21.h }, z5.h
// CHECK-ENCODING: [0x35,0xa1,0x65,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c165a135 <unknown>

fminnm {z22.h, z23.h}, {z22.h, z23.h}, z8.h // 11000001-01101000-10100001-00110111
// CHECK-INST: fminnm { z22.h, z23.h }, { z22.h, z23.h }, z8.h
// CHECK-ENCODING: [0x37,0xa1,0x68,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c168a137 <unknown>

fminnm {z30.h, z31.h}, {z30.h, z31.h}, z15.h // 11000001-01101111-10100001-00111111
// CHECK-INST: fminnm { z30.h, z31.h }, { z30.h, z31.h }, z15.h
// CHECK-ENCODING: [0x3f,0xa1,0x6f,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c16fa13f <unknown>


fminnm {z0.h, z1.h}, {z0.h, z1.h}, {z0.h, z1.h} // 11000001-01100000-10110001-00100001
// CHECK-INST: fminnm { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }
// CHECK-ENCODING: [0x21,0xb1,0x60,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c160b121 <unknown>

fminnm {z20.h, z21.h}, {z20.h, z21.h}, {z20.h, z21.h} // 11000001-01110100-10110001-00110101
// CHECK-INST: fminnm { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }
// CHECK-ENCODING: [0x35,0xb1,0x74,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c174b135 <unknown>

fminnm {z22.h, z23.h}, {z22.h, z23.h}, {z8.h, z9.h} // 11000001-01101000-10110001-00110111
// CHECK-INST: fminnm { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }
// CHECK-ENCODING: [0x37,0xb1,0x68,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c168b137 <unknown>

fminnm {z30.h, z31.h}, {z30.h, z31.h}, {z30.h, z31.h} // 11000001-01111110-10110001-00111111
// CHECK-INST: fminnm { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }
// CHECK-ENCODING: [0x3f,0xb1,0x7e,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c17eb13f <unknown>


fminnm {z0.s, z1.s}, {z0.s, z1.s}, z0.s // 11000001-10100000-10100001-00100001
// CHECK-INST: fminnm { z0.s, z1.s }, { z0.s, z1.s }, z0.s
// CHECK-ENCODING: [0x21,0xa1,0xa0,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a0a121 <unknown>

fminnm {z20.s, z21.s}, {z20.s, z21.s}, z5.s // 11000001-10100101-10100001-00110101
// CHECK-INST: fminnm { z20.s, z21.s }, { z20.s, z21.s }, z5.s
// CHECK-ENCODING: [0x35,0xa1,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a5a135 <unknown>

fminnm {z22.s, z23.s}, {z22.s, z23.s}, z8.s // 11000001-10101000-10100001-00110111
// CHECK-INST: fminnm { z22.s, z23.s }, { z22.s, z23.s }, z8.s
// CHECK-ENCODING: [0x37,0xa1,0xa8,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a8a137 <unknown>

fminnm {z30.s, z31.s}, {z30.s, z31.s}, z15.s // 11000001-10101111-10100001-00111111
// CHECK-INST: fminnm { z30.s, z31.s }, { z30.s, z31.s }, z15.s
// CHECK-ENCODING: [0x3f,0xa1,0xaf,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1afa13f <unknown>


fminnm {z0.s, z1.s}, {z0.s, z1.s}, {z0.s, z1.s} // 11000001-10100000-10110001-00100001
// CHECK-INST: fminnm { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }
// CHECK-ENCODING: [0x21,0xb1,0xa0,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a0b121 <unknown>

fminnm {z20.s, z21.s}, {z20.s, z21.s}, {z20.s, z21.s} // 11000001-10110100-10110001-00110101
// CHECK-INST: fminnm { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }
// CHECK-ENCODING: [0x35,0xb1,0xb4,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1b4b135 <unknown>

fminnm {z22.s, z23.s}, {z22.s, z23.s}, {z8.s, z9.s} // 11000001-10101000-10110001-00110111
// CHECK-INST: fminnm { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }
// CHECK-ENCODING: [0x37,0xb1,0xa8,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a8b137 <unknown>

fminnm {z30.s, z31.s}, {z30.s, z31.s}, {z30.s, z31.s} // 11000001-10111110-10110001-00111111
// CHECK-INST: fminnm { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }
// CHECK-ENCODING: [0x3f,0xb1,0xbe,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1beb13f <unknown>


fminnm {z0.d - z3.d}, {z0.d - z3.d}, z0.d // 11000001-11100000-10101001-00100001
// CHECK-INST: fminnm { z0.d - z3.d }, { z0.d - z3.d }, z0.d
// CHECK-ENCODING: [0x21,0xa9,0xe0,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e0a921 <unknown>

fminnm {z20.d - z23.d}, {z20.d - z23.d}, z5.d // 11000001-11100101-10101001-00110101
// CHECK-INST: fminnm { z20.d - z23.d }, { z20.d - z23.d }, z5.d
// CHECK-ENCODING: [0x35,0xa9,0xe5,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e5a935 <unknown>

fminnm {z20.d - z23.d}, {z20.d - z23.d}, z8.d // 11000001-11101000-10101001-00110101
// CHECK-INST: fminnm { z20.d - z23.d }, { z20.d - z23.d }, z8.d
// CHECK-ENCODING: [0x35,0xa9,0xe8,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e8a935 <unknown>

fminnm {z28.d - z31.d}, {z28.d - z31.d}, z15.d // 11000001-11101111-10101001-00111101
// CHECK-INST: fminnm { z28.d - z31.d }, { z28.d - z31.d }, z15.d
// CHECK-ENCODING: [0x3d,0xa9,0xef,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1efa93d <unknown>


fminnm {z0.d - z3.d}, {z0.d - z3.d}, {z0.d - z3.d} // 11000001-11100000-10111001-00100001
// CHECK-INST: fminnm { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }
// CHECK-ENCODING: [0x21,0xb9,0xe0,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e0b921 <unknown>

fminnm {z20.d - z23.d}, {z20.d - z23.d}, {z20.d - z23.d} // 11000001-11110100-10111001-00110101
// CHECK-INST: fminnm { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }
// CHECK-ENCODING: [0x35,0xb9,0xf4,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1f4b935 <unknown>

fminnm {z20.d - z23.d}, {z20.d - z23.d}, {z8.d - z11.d} // 11000001-11101000-10111001-00110101
// CHECK-INST: fminnm { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }
// CHECK-ENCODING: [0x35,0xb9,0xe8,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e8b935 <unknown>

fminnm {z28.d - z31.d}, {z28.d - z31.d}, {z28.d - z31.d} // 11000001-11111100-10111001-00111101
// CHECK-INST: fminnm { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }
// CHECK-ENCODING: [0x3d,0xb9,0xfc,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1fcb93d <unknown>


fminnm {z0.h - z3.h}, {z0.h - z3.h}, z0.h // 11000001-01100000-10101001-00100001
// CHECK-INST: fminnm { z0.h - z3.h }, { z0.h - z3.h }, z0.h
// CHECK-ENCODING: [0x21,0xa9,0x60,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c160a921 <unknown>

fminnm {z20.h - z23.h}, {z20.h - z23.h}, z5.h // 11000001-01100101-10101001-00110101
// CHECK-INST: fminnm { z20.h - z23.h }, { z20.h - z23.h }, z5.h
// CHECK-ENCODING: [0x35,0xa9,0x65,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c165a935 <unknown>

fminnm {z20.h - z23.h}, {z20.h - z23.h}, z8.h // 11000001-01101000-10101001-00110101
// CHECK-INST: fminnm { z20.h - z23.h }, { z20.h - z23.h }, z8.h
// CHECK-ENCODING: [0x35,0xa9,0x68,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c168a935 <unknown>

fminnm {z28.h - z31.h}, {z28.h - z31.h}, z15.h // 11000001-01101111-10101001-00111101
// CHECK-INST: fminnm { z28.h - z31.h }, { z28.h - z31.h }, z15.h
// CHECK-ENCODING: [0x3d,0xa9,0x6f,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c16fa93d <unknown>


fminnm {z0.h - z3.h}, {z0.h - z3.h}, {z0.h - z3.h} // 11000001-01100000-10111001-00100001
// CHECK-INST: fminnm { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }
// CHECK-ENCODING: [0x21,0xb9,0x60,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c160b921 <unknown>

fminnm {z20.h - z23.h}, {z20.h - z23.h}, {z20.h - z23.h} // 11000001-01110100-10111001-00110101
// CHECK-INST: fminnm { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }
// CHECK-ENCODING: [0x35,0xb9,0x74,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c174b935 <unknown>

fminnm {z20.h - z23.h}, {z20.h - z23.h}, {z8.h - z11.h} // 11000001-01101000-10111001-00110101
// CHECK-INST: fminnm { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }
// CHECK-ENCODING: [0x35,0xb9,0x68,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c168b935 <unknown>

fminnm {z28.h - z31.h}, {z28.h - z31.h}, {z28.h - z31.h} // 11000001-01111100-10111001-00111101
// CHECK-INST: fminnm { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }
// CHECK-ENCODING: [0x3d,0xb9,0x7c,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c17cb93d <unknown>


fminnm {z0.s - z3.s}, {z0.s - z3.s}, z0.s // 11000001-10100000-10101001-00100001
// CHECK-INST: fminnm { z0.s - z3.s }, { z0.s - z3.s }, z0.s
// CHECK-ENCODING: [0x21,0xa9,0xa0,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a0a921 <unknown>

fminnm {z20.s - z23.s}, {z20.s - z23.s}, z5.s // 11000001-10100101-10101001-00110101
// CHECK-INST: fminnm { z20.s - z23.s }, { z20.s - z23.s }, z5.s
// CHECK-ENCODING: [0x35,0xa9,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a5a935 <unknown>

fminnm {z20.s - z23.s}, {z20.s - z23.s}, z8.s // 11000001-10101000-10101001-00110101
// CHECK-INST: fminnm { z20.s - z23.s }, { z20.s - z23.s }, z8.s
// CHECK-ENCODING: [0x35,0xa9,0xa8,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a8a935 <unknown>

fminnm {z28.s - z31.s}, {z28.s - z31.s}, z15.s // 11000001-10101111-10101001-00111101
// CHECK-INST: fminnm { z28.s - z31.s }, { z28.s - z31.s }, z15.s
// CHECK-ENCODING: [0x3d,0xa9,0xaf,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1afa93d <unknown>


fminnm {z0.s - z3.s}, {z0.s - z3.s}, {z0.s - z3.s} // 11000001-10100000-10111001-00100001
// CHECK-INST: fminnm { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }
// CHECK-ENCODING: [0x21,0xb9,0xa0,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a0b921 <unknown>

fminnm {z20.s - z23.s}, {z20.s - z23.s}, {z20.s - z23.s} // 11000001-10110100-10111001-00110101
// CHECK-INST: fminnm { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }
// CHECK-ENCODING: [0x35,0xb9,0xb4,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1b4b935 <unknown>

fminnm {z20.s - z23.s}, {z20.s - z23.s}, {z8.s - z11.s} // 11000001-10101000-10111001-00110101
// CHECK-INST: fminnm { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }
// CHECK-ENCODING: [0x35,0xb9,0xa8,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a8b935 <unknown>

fminnm {z28.s - z31.s}, {z28.s - z31.s}, {z28.s - z31.s} // 11000001-10111100-10111001-00111101
// CHECK-INST: fminnm { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }
// CHECK-ENCODING: [0x3d,0xb9,0xbc,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1bcb93d <unknown>

30 changes: 30 additions & 0 deletions llvm/test/MC/AArch64/SME2/smax-diagnostics.s
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Original file line number Diff line number Diff line change
@@ -0,0 +1,30 @@
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s

// --------------------------------------------------------------------------//
// Invalid vector list

smax {z0.h, z1.h}, {z0.h-z2.h}, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: smax {z0.h, z1.h}, {z0.h-z2.h}, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

smax {z1.d-z2.d}, {z0.d, z1.d}, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element type
// CHECK-NEXT: smax {z1.d-z2.d}, {z0.d, z1.d}, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid single register

smax {z0.b, z1.b}, {z2.b-z3.b}, z31.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b
// CHECK-NEXT: smax {z0.b, z1.b}, {z2.b-z3.b}, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid Register Suffix

smax {z0.b, z1.b}, {z2.b-z3.b}, z14.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b
// CHECK-NEXT: smax {z0.b, z1.b}, {z2.b-z3.b}, z14.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
413 changes: 413 additions & 0 deletions llvm/test/MC/AArch64/SME2/smax.s
View file

Large diffs are not rendered by default.

30 changes: 30 additions & 0 deletions llvm/test/MC/AArch64/SME2/smin-diagnostics.s
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Original file line number Diff line number Diff line change
@@ -0,0 +1,30 @@
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s

// --------------------------------------------------------------------------//
// Invalid vector list

smin {z0.h, z1.h}, {z0.h-z2.h}, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: smin {z0.h, z1.h}, {z0.h-z2.h}, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

smin {z1.d-z2.d}, {z0.d, z1.d}, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element type
// CHECK-NEXT: smin {z1.d-z2.d}, {z0.d, z1.d}, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid single register

smin {z0.b, z1.b}, {z2.b-z3.b}, z31.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b
// CHECK-NEXT: smin {z0.b, z1.b}, {z2.b-z3.b}, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid Register Suffix

smin {z0.b, z1.b}, {z2.b-z3.b}, z14.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b
// CHECK-NEXT: smin {z0.b, z1.b}, {z2.b-z3.b}, z14.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
413 changes: 413 additions & 0 deletions llvm/test/MC/AArch64/SME2/smin.s
View file

Large diffs are not rendered by default.

50 changes: 50 additions & 0 deletions llvm/test/MC/AArch64/SME2/srshl-diagnostics.s
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Original file line number Diff line number Diff line change
@@ -0,0 +1,50 @@
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s

// --------------------------------------------------------------------------//
// Invalid vector list

srshl {z0.h-z2.h}, {z0.h-z1.h}, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: srshl {z0.h-z2.h}, {z0.h-z1.h}, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

srshl {z0.s-z1.s}, {z2.s-z4.s}, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: srshl {z0.s-z1.s}, {z2.s-z4.s}, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

srshl {z20.d-z23.d}, {z20.d-z23.d}, {z8.d-z12.d}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
// CHECK-NEXT: srshl {z20.d-z23.d}, {z20.d-z23.d}, {z8.d-z12.d}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

srshl {z29.b-z30.b}, {z30.b-z31.b}, z15.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
// CHECK-NEXT: srshl {z29.b-z30.b}, {z30.b-z31.b}, z15.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

srshl {z20.h-z23.h}, {z21.h-z24.h}, {z8.h-z11.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
// CHECK-NEXT: srshl {z20.h-z23.h}, {z21.h-z24.h}, {z8.h-z11.h}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

srshl {z28.b-z31.b}, {z28.b-z31.b}, {z27.b-z30.b}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
// CHECK-NEXT: srshl {z28.b-z31.b}, {z28.b-z31.b}, {z27.b-z30.b}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid Single Register

srshl {z20.h-z21.h}, {z20.h-z21.h}, z16.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
// CHECK-NEXT: srshl {z20.h-z21.h}, {z20.h-z21.h}, z16.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid Register Suffix

srshl {z0.d-z3.d}, {z0.d-z3.d}, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.d..z15.d
// CHECK-NEXT: srshl {z0.d-z3.d}, {z0.d-z3.d}, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
413 changes: 413 additions & 0 deletions llvm/test/MC/AArch64/SME2/srshl.s
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30 changes: 30 additions & 0 deletions llvm/test/MC/AArch64/SME2/umax-diagnostics.s
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Original file line number Diff line number Diff line change
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s

// --------------------------------------------------------------------------//
// Invalid vector list

umax {z0.h, z1.h}, {z0.h-z2.h}, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: umax {z0.h, z1.h}, {z0.h-z2.h}, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

umax {z1.d-z2.d}, {z0.d, z1.d}, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element type
// CHECK-NEXT: umax {z1.d-z2.d}, {z0.d, z1.d}, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid single register

umax {z0.b, z1.b}, {z2.b-z3.b}, z31.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b
// CHECK-NEXT: umax {z0.b, z1.b}, {z2.b-z3.b}, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid Register Suffix

umax {z0.b, z1.b}, {z2.b-z3.b}, z14.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b
// CHECK-NEXT: umax {z0.b, z1.b}, {z2.b-z3.b}, z14.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
413 changes: 413 additions & 0 deletions llvm/test/MC/AArch64/SME2/umax.s
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30 changes: 30 additions & 0 deletions llvm/test/MC/AArch64/SME2/umin-diagnostics.s
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Original file line number Diff line number Diff line change
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s

// --------------------------------------------------------------------------//
// Invalid vector list

umin {z0.h, z1.h}, {z0.h-z2.h}, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: umin {z0.h, z1.h}, {z0.h-z2.h}, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

umin {z1.d-z2.d}, {z0.d, z1.d}, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element type
// CHECK-NEXT: umin {z1.d-z2.d}, {z0.d, z1.d}, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid single register

umin {z0.b, z1.b}, {z2.b-z3.b}, z31.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b
// CHECK-NEXT: umin {z0.b, z1.b}, {z2.b-z3.b}, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid Register Suffix

umin {z0.b, z1.b}, {z2.b-z3.b}, z14.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b
// CHECK-NEXT: umin {z0.b, z1.b}, {z2.b-z3.b}, z14.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
413 changes: 413 additions & 0 deletions llvm/test/MC/AArch64/SME2/umin.s
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50 changes: 50 additions & 0 deletions llvm/test/MC/AArch64/SME2/urshl-diagnostics.s
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s

// --------------------------------------------------------------------------//
// Invalid vector list

urshl {z0.h-z2.h}, {z0.h-z1.h}, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: urshl {z0.h-z2.h}, {z0.h-z1.h}, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

urshl {z0.s-z1.s}, {z2.s-z4.s}, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: urshl {z0.s-z1.s}, {z2.s-z4.s}, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

urshl {z20.d-z23.d}, {z20.d-z23.d}, {z8.d-z12.d}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
// CHECK-NEXT: urshl {z20.d-z23.d}, {z20.d-z23.d}, {z8.d-z12.d}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

urshl {z29.b-z30.b}, {z30.b-z31.b}, z15.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
// CHECK-NEXT: urshl {z29.b-z30.b}, {z30.b-z31.b}, z15.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

urshl {z20.h-z23.h}, {z21.h-z24.h}, {z8.h-z11.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
// CHECK-NEXT: urshl {z20.h-z23.h}, {z21.h-z24.h}, {z8.h-z11.h}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

urshl {z28.b-z31.b}, {z28.b-z31.b}, {z27.b-z30.b}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
// CHECK-NEXT: urshl {z28.b-z31.b}, {z28.b-z31.b}, {z27.b-z30.b}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid Single Register

urshl {z20.h-z21.h}, {z20.h-z21.h}, z16.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
// CHECK-NEXT: urshl {z20.h-z21.h}, {z20.h-z21.h}, z16.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid Register Suffix

urshl {z0.d-z3.d}, {z0.d-z3.d}, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.d..z15.d
// CHECK-NEXT: urshl {z0.d-z3.d}, {z0.d-z3.d}, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
414 changes: 414 additions & 0 deletions llvm/test/MC/AArch64/SME2/urshl.s
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