4 changes: 2 additions & 2 deletions llvm/test/CodeGen/Mips/llvm-ir/select-flt.ll
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Expand Up @@ -46,8 +46,8 @@ entry:
; M3: mov.s $f0, $f13

; CMOV-32: mtc1 $6, $f0
; CMOV-32: mtc1 $5, $f1
; CMOV-32: andi $[[T0:[0-9]+]], $4, 1
; CMOV-32: mtc1 $5, $f1
; CMOV-32: movn.s $f0, $f1, $[[T0]]

; SEL-32: mtc1 $5, $[[F0:f[0-9]+]]
Expand All @@ -63,8 +63,8 @@ entry:
; SEL-64: sel.s $f0, $f14, $f13

; MM32R3: mtc1 $6, $[[F0:f[0-9]+]]
; MM32R3: mtc1 $5, $[[F1:f[0-9]+]]
; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1
; MM32R3: mtc1 $5, $[[F1:f[0-9]+]]
; MM32R3: movn.s $f0, $[[F1]], $[[T0]]

%r = select i1 %s, float %x, float %y
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20 changes: 10 additions & 10 deletions llvm/test/CodeGen/Mips/llvm-ir/select-int.ll
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Expand Up @@ -163,14 +163,14 @@ entry:
; CMOV-32: movn $3, $7, $[[T0]]

; SEL-32: andi $[[T0:[0-9]+]], $4, 1
; SEL-32: selnez $[[T1:[0-9]+]], $6, $[[T0]]
; SEL-32: lw $[[T2:[0-9]+]], 16($sp)
; SEL-32: seleqz $[[T3:[0-9]+]], $[[T2]], $[[T0]]
; SEL-32: or $2, $[[T1]], $[[T3]]
; SEL-32: selnez $[[T4:[0-9]+]], $7, $[[T0]]
; SEL-32: lw $[[T5:[0-9]+]], 20($sp)
; SEL-32: seleqz $[[T6:[0-9]+]], $[[T5]], $[[T0]]
; SEL-32: or $3, $[[T4]], $[[T6]]
; SEL-32: lw $[[T1:[0-9]+]], 16($sp)
; SEL-32: seleqz $[[T2:[0-9]+]], $[[T1]], $[[T0]]
; SEL-32: selnez $[[T3:[0-9]+]], $6, $[[T0]]
; SEL-32: or $2, $[[T3]], $[[T2]]
; SEL-32: lw $[[T4:[0-9]+]], 20($sp)
; SEL-32: seleqz $[[T5:[0-9]+]], $[[T4]], $[[T0]]
; SEL-32: selnez $[[T6:[0-9]+]], $7, $[[T0]]
; SEL-32: or $3, $[[T6]], $[[T5]]

; M3: andi $[[T0:[0-9]+]], $4, 1
; M3: bnez $[[T0]], [[BB0:\.LBB[0-9_]+]]
Expand Down Expand Up @@ -198,13 +198,13 @@ entry:
; MM32R3: movn $3, $7, $[[T0]]

; MM32R6: andi16 $[[T0:[0-9]+]], $4, 1
; MM32R6: selnez $[[T1:[0-9]+]], $6, $[[T0]]
; MM32R6: lw $[[T2:[0-9]+]], 16($sp)
; MM32R6: seleqz $[[T3:[0-9]+]], $[[T2]], $[[T0]]
; MM32R6: selnez $[[T1:[0-9]+]], $6, $[[T0]]
; MM32R6: or $2, $[[T1]], $[[T3]]
; MM32R6: selnez $[[T6:[0-9]+]], $7, $[[T0]]
; MM32R6: lw $[[T4:[0-9]+]], 20($sp)
; MM32R6: seleqz $[[T5:[0-9]+]], $[[T4]], $[[T0]]
; MM32R6: selnez $[[T6:[0-9]+]], $7, $[[T0]]
; MM32R6: or $3, $[[T6]], $[[T5]]

%r = select i1 %s, i64 %x, i64 %y
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16 changes: 8 additions & 8 deletions llvm/test/CodeGen/Mips/llvm-ir/sub.ll
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Expand Up @@ -134,16 +134,16 @@ entry:
; GP32-MM: sltu $[[T1:[0-9]+]], $[[T2:[0-9]+]], $[[T0]]
; GP32-MM: lw $[[T3:[0-9]+]], 16($sp)
; GP32-MM: addu $[[T3]], $[[T1]], $[[T3]]
; GP32-MM: lw $[[T5:[0-9]+]], 24($sp)
; GP32-MM: lw $[[T4:[0-9]+]], 28($sp)
; GP32-MM: subu $[[T1]], $7, $[[T4]]
; GP32-MM: subu $[[T3]], $4, $[[T3]]
; GP32-MM: sltu $[[T6:[0-9]+]], $6, $[[T5]]
; GP32-MM: lw $[[T4:[0-9]+]], 24($sp)
; GP32-MM: lw $[[T5:[0-9]+]], 28($sp)
; GP32-MM: subu $[[T1]], $7, $[[T5]]
; GP32-MM: subu $[[T3]], $[[T6:[0-9]+]], $[[T3]]
; GP32-MM: sltu $[[T6]], $6, $[[T4]]
; GP32-MM: addu $[[T0]], $[[T6]], $[[T0]]
; GP32-MM: subu $[[T0]], $5, $[[T0]]
; GP32-MM: sltu $[[T7:[0-9]+]], $7, $[[T4]]
; GP32-MM: addu $[[T8:[0-8]+]], $[[T7]], $[[T5]]
; GP32-MM: subu $[[T9:[0-9]+]], $6, $[[T8]]
; GP32-MM: sltu $[[T6]], $7, $[[T5]]
; GP32-MM: addu $[[T6]], $[[T6]], $[[T4]]
; GP32-MM: subu $[[T6]], $6, $[[T6]]
; GP32-MM: move $[[T2]], $[[T1]]

; GP64: dsubu $3, $5, $7
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10 changes: 5 additions & 5 deletions llvm/test/CodeGen/Mips/llvm-ir/xor.ll
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Expand Up @@ -117,25 +117,25 @@ define signext i128 @xor_i128(i128 signext %a, i128 signext %b) {
entry:
; ALL-LABEL: xor_i128:

; GP32: lw $[[T0:[0-9]+]], 24($sp)
; GP32: lw $[[T1:[0-9]+]], 20($sp)
; GP32: lw $[[T2:[0-9]+]], 16($sp)
; GP32: xor $2, $4, $[[T2]]
; GP32: xor $3, $5, $[[T1]]
; GP32: lw $[[T0:[0-9]+]], 24($sp)
; GP32: xor $4, $6, $[[T0]]
; GP32: lw $[[T3:[0-9]+]], 28($sp)
; GP32: xor $5, $7, $[[T3]]

; GP64: xor $2, $4, $6
; GP64: xor $3, $5, $7

; MM32: lw $[[T0:[0-9]+]], 32($sp)
; MM32: lw $[[T1:[0-9]+]], 28($sp)
; MM32: lw $[[T2:[0-9]+]], 24($sp)
; MM32: lw $[[T1:[0-9]+]], 20($sp)
; MM32: lw $[[T2:[0-9]+]], 16($sp)
; MM32: xor16 $[[T2]], $4
; MM32: xor16 $[[T1]], $5
; MM32: lw $[[T0:[0-9]+]], 24($sp)
; MM32: xor16 $[[T0]], $6
; MM32: lw $[[T3:[0-9]+]], 36($sp)
; MM32: lw $[[T3:[0-9]+]], 28($sp)
; MM32: xor16 $[[T3]], $7

; MM64: xor $2, $4, $6
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Mips/longbranch.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -102,8 +102,8 @@ end:

; N64: [[BB0]]:
; N64: daddiu $[[GP:[0-9]+]], $[[R1]], %lo(%neg(%gp_rel(test1)))
; N64: ld $[[R2:[0-9]+]], %got_disp(x)($[[GP]])
; N64: addiu $[[R3:[0-9]+]], $zero, 1
; N64: ld $[[R2:[0-9]+]], %got_disp(x)($[[GP]])
; N64: sw $[[R3]], 0($[[R2]])
; N64: [[BB2]]:
; N64: jr $ra
Expand Down
17 changes: 10 additions & 7 deletions llvm/test/CodeGen/Mips/no-odd-spreg.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -19,6 +19,9 @@ entry:
;
; On the other hand, if odd single precision registers are not permitted, it
; will be forced to spill/reload either %a or %0.
;
; This is affected by scheduling as the new machine scheduler schedules the
; two adds together, avoiding the spill+reload.

%0 = fadd float %a, 1.0
call void asm "# Clobber", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
Expand All @@ -27,15 +30,15 @@ entry:
}

; ALL-LABEL: two_floats:
; ODDSPREG: add.s $f13, $f12, ${{f[0-9]+}}
; ODDSPREG: add.s $f[[RES:[0-9]]], $f12, ${{f[0-9]+}}
; ODDSPREG: add.s ${{f[0-9]+}}, $f12, $f[[RES]]
; ODDSPREG-NOT: swc1
; ODDSPREG-NOT: lwc1
; ODDSPREG: add.s $f0, $f12, $f13

; NOODDSPREG: add.s $[[T0:f[0-9]*[02468]]], $f12, ${{f[0-9]+}}
; NOODDSPREG: swc1 $[[T0]],
; NOODDSPREG: lwc1 $[[T1:f[0-9]*[02468]]],
; NOODDSPREG: add.s $f0, $f12, $[[T1]]
; NOODDSPREG-NOT: swc1 $[[T0]],
; NOODDSPREG-NOT: lwc1 $[[T1:f[0-9]*[02468]]],
; NOODDSPREG: add.s ${{f[0-9]+}}, $f12, $[[T0]]

define double @two_doubles(double %a) {
entry:
Expand All @@ -51,8 +54,8 @@ entry:
}

; ALL-LABEL: two_doubles:
; ALL: add.d $[[T0:f[0-9]+]], $f12, ${{f[0-9]+}}
; ALL: add.d $f0, $f12, $[[T0]]
; ALL-DAG: add.d $[[T0:f[0-9]+]], $f12, ${{f[0-9]+}}
; ALL-DAG: add.d $f0, $f12, $[[T0]]


; INVALID: -mattr=+nooddspreg is not currently permitted for a 32-bit FPU register file (FR=0 mode).
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/Mips/prevent-hoisting.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -13,17 +13,17 @@
; The check for first "addiu" instruction is added so that we can match the correct "b" instruction.
; CHECK: andi
; CHECK: b $[[BB0:BB[0-9_]+]]
; CHECK-NEXT: sll
; CHECK: sll

; Check that at the start of a fallthrough block there is a instruction that writes to $1.
; CHECK-NEXT: {{BB[0-9_#]+}}:
; CHECK-NEXT: lw $[[R1:[0-9]+]], %got(assignSE2partition)($[[R2:[0-9]+]])
; CHECK-NEXT: sll $1, $[[R0:[0-9]+]], 4
; CHECK: {{BB[0-9_#]+}}:
; CHECK: sll $1, $[[R0:[0-9]+]], 4
; CHECK: lw $[[R1:[0-9]+]], %got(assignSE2partition)($[[R2:[0-9]+]])

; Check that identical instructions are at the start of a target block.
; CHECK: [[BB0]]:
; CHECK-NEXT: lw $[[R1]], %got(assignSE2partition)($[[R2]])
; CHECK-NEXT: sll $1, $[[R0]], 4
; CHECK: sll $1, $[[R0]], 4
; CHECK: lw $[[R1]], %got(assignSE2partition)($[[R2]])


%struct.img_par = type { i32, i32, i32, i32, i32*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [16 x [16 x i16]], [6 x [32 x i32]], [16 x [16 x i32]], [4 x [12 x [4 x [4 x i32]]]], [16 x i32], i8**, i32*, i32***, i32**, i32, i32, i32, i32, %struct.Slice*, %struct.macroblock*, i32, i32, i32, i32, i32, i32, %struct.DecRefPicMarking_s*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [3 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32***, i32***, i32****, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [3 x [2 x i32]], [3 x [2 x i32]], i32, i32, i32, i32, %struct.timeb, %struct.timeb, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
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4 changes: 2 additions & 2 deletions llvm/test/DebugInfo/Mips/dsr-fixed-objects.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -29,7 +29,7 @@ declare void @foo(i32*)
;
; x -> DW_OP_reg1(51)
; F0: [[LOC]]: Beginning address offset: 0x0000000000000028
; F0: Ending address offset: 0x0000000000000030
; F0: Ending address offset: 0x000000000000002c
; F0: Location description: 51

define i32 @f0(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d, i32 signext %e) !dbg !4 {
Expand Down Expand Up @@ -65,7 +65,7 @@ entry:

; x -> DW_OP_reg1(51)
; F1: [[LOC]]: Beginning address offset: 0x0000000000000080
; F1: Ending address offset: 0x0000000000000088
; F1: Ending address offset: 0x0000000000000084
; F1: Location description: 51

define i32 @f1(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d, i32 signext %e) !dbg !15 {
Expand Down