128 changes: 26 additions & 102 deletions llvm/test/CodeGen/RISCV/rvv/vrol-sdnode.ll
View file
Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64
; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB,CHECK-ZVBB32
; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB,CHECK-ZVBB64
; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-ZVBB
; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-ZVBB

declare <vscale x 1 x i8> @llvm.fshl.nxv1i8(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>)

Expand Down Expand Up @@ -942,21 +942,15 @@ define <vscale x 1 x i64> @vrol_vv_nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x
define <vscale x 1 x i64> @vrol_vx_nxv1i64(<vscale x 1 x i64> %a, i64 %b) {
; CHECK-RV32-LABEL: vrol_vx_nxv1i64:
; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: addi sp, sp, -16
; CHECK-RV32-NEXT: .cfi_def_cfa_offset 16
; CHECK-RV32-NEXT: sw a1, 12(sp)
; CHECK-RV32-NEXT: sw a0, 8(sp)
; CHECK-RV32-NEXT: addi a0, sp, 8
; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; CHECK-RV32-NEXT: vlse64.v v9, (a0), zero
; CHECK-RV32-NEXT: vmv.v.x v9, a0
; CHECK-RV32-NEXT: li a0, 63
; CHECK-RV32-NEXT: vand.vx v10, v9, a0
; CHECK-RV32-NEXT: vsll.vv v10, v8, v10
; CHECK-RV32-NEXT: vrsub.vi v9, v9, 0
; CHECK-RV32-NEXT: vand.vx v9, v9, a0
; CHECK-RV32-NEXT: vsrl.vv v8, v8, v9
; CHECK-RV32-NEXT: vor.vv v8, v10, v8
; CHECK-RV32-NEXT: addi sp, sp, 16
; CHECK-RV32-NEXT: ret
;
; CHECK-RV64-LABEL: vrol_vx_nxv1i64:
Expand All @@ -970,24 +964,11 @@ define <vscale x 1 x i64> @vrol_vx_nxv1i64(<vscale x 1 x i64> %a, i64 %b) {
; CHECK-RV64-NEXT: vor.vv v8, v9, v8
; CHECK-RV64-NEXT: ret
;
; CHECK-ZVBB32-LABEL: vrol_vx_nxv1i64:
; CHECK-ZVBB32: # %bb.0:
; CHECK-ZVBB32-NEXT: addi sp, sp, -16
; CHECK-ZVBB32-NEXT: .cfi_def_cfa_offset 16
; CHECK-ZVBB32-NEXT: sw a1, 12(sp)
; CHECK-ZVBB32-NEXT: sw a0, 8(sp)
; CHECK-ZVBB32-NEXT: addi a0, sp, 8
; CHECK-ZVBB32-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; CHECK-ZVBB32-NEXT: vlse64.v v9, (a0), zero
; CHECK-ZVBB32-NEXT: vrol.vv v8, v8, v9
; CHECK-ZVBB32-NEXT: addi sp, sp, 16
; CHECK-ZVBB32-NEXT: ret
;
; CHECK-ZVBB64-LABEL: vrol_vx_nxv1i64:
; CHECK-ZVBB64: # %bb.0:
; CHECK-ZVBB64-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; CHECK-ZVBB64-NEXT: vrol.vx v8, v8, a0
; CHECK-ZVBB64-NEXT: ret
; CHECK-ZVBB-LABEL: vrol_vx_nxv1i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0
; CHECK-ZVBB-NEXT: ret
%b.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
%b.splat = shufflevector <vscale x 1 x i64> %b.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
%x = call <vscale x 1 x i64> @llvm.fshl.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %a, <vscale x 1 x i64> %b.splat)
Expand Down Expand Up @@ -1021,21 +1002,15 @@ define <vscale x 2 x i64> @vrol_vv_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x
define <vscale x 2 x i64> @vrol_vx_nxv2i64(<vscale x 2 x i64> %a, i64 %b) {
; CHECK-RV32-LABEL: vrol_vx_nxv2i64:
; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: addi sp, sp, -16
; CHECK-RV32-NEXT: .cfi_def_cfa_offset 16
; CHECK-RV32-NEXT: sw a1, 12(sp)
; CHECK-RV32-NEXT: sw a0, 8(sp)
; CHECK-RV32-NEXT: addi a0, sp, 8
; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma
; CHECK-RV32-NEXT: vlse64.v v10, (a0), zero
; CHECK-RV32-NEXT: vmv.v.x v10, a0
; CHECK-RV32-NEXT: li a0, 63
; CHECK-RV32-NEXT: vand.vx v12, v10, a0
; CHECK-RV32-NEXT: vsll.vv v12, v8, v12
; CHECK-RV32-NEXT: vrsub.vi v10, v10, 0
; CHECK-RV32-NEXT: vand.vx v10, v10, a0
; CHECK-RV32-NEXT: vsrl.vv v8, v8, v10
; CHECK-RV32-NEXT: vor.vv v8, v12, v8
; CHECK-RV32-NEXT: addi sp, sp, 16
; CHECK-RV32-NEXT: ret
;
; CHECK-RV64-LABEL: vrol_vx_nxv2i64:
Expand All @@ -1049,24 +1024,11 @@ define <vscale x 2 x i64> @vrol_vx_nxv2i64(<vscale x 2 x i64> %a, i64 %b) {
; CHECK-RV64-NEXT: vor.vv v8, v10, v8
; CHECK-RV64-NEXT: ret
;
; CHECK-ZVBB32-LABEL: vrol_vx_nxv2i64:
; CHECK-ZVBB32: # %bb.0:
; CHECK-ZVBB32-NEXT: addi sp, sp, -16
; CHECK-ZVBB32-NEXT: .cfi_def_cfa_offset 16
; CHECK-ZVBB32-NEXT: sw a1, 12(sp)
; CHECK-ZVBB32-NEXT: sw a0, 8(sp)
; CHECK-ZVBB32-NEXT: addi a0, sp, 8
; CHECK-ZVBB32-NEXT: vsetvli a1, zero, e64, m2, ta, ma
; CHECK-ZVBB32-NEXT: vlse64.v v10, (a0), zero
; CHECK-ZVBB32-NEXT: vrol.vv v8, v8, v10
; CHECK-ZVBB32-NEXT: addi sp, sp, 16
; CHECK-ZVBB32-NEXT: ret
;
; CHECK-ZVBB64-LABEL: vrol_vx_nxv2i64:
; CHECK-ZVBB64: # %bb.0:
; CHECK-ZVBB64-NEXT: vsetvli a1, zero, e64, m2, ta, ma
; CHECK-ZVBB64-NEXT: vrol.vx v8, v8, a0
; CHECK-ZVBB64-NEXT: ret
; CHECK-ZVBB-LABEL: vrol_vx_nxv2i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a1, zero, e64, m2, ta, ma
; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0
; CHECK-ZVBB-NEXT: ret
%b.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
%b.splat = shufflevector <vscale x 2 x i64> %b.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
%x = call <vscale x 2 x i64> @llvm.fshl.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b.splat)
Expand Down Expand Up @@ -1100,21 +1062,15 @@ define <vscale x 4 x i64> @vrol_vv_nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x
define <vscale x 4 x i64> @vrol_vx_nxv4i64(<vscale x 4 x i64> %a, i64 %b) {
; CHECK-RV32-LABEL: vrol_vx_nxv4i64:
; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: addi sp, sp, -16
; CHECK-RV32-NEXT: .cfi_def_cfa_offset 16
; CHECK-RV32-NEXT: sw a1, 12(sp)
; CHECK-RV32-NEXT: sw a0, 8(sp)
; CHECK-RV32-NEXT: addi a0, sp, 8
; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma
; CHECK-RV32-NEXT: vlse64.v v12, (a0), zero
; CHECK-RV32-NEXT: vmv.v.x v12, a0
; CHECK-RV32-NEXT: li a0, 63
; CHECK-RV32-NEXT: vand.vx v16, v12, a0
; CHECK-RV32-NEXT: vsll.vv v16, v8, v16
; CHECK-RV32-NEXT: vrsub.vi v12, v12, 0
; CHECK-RV32-NEXT: vand.vx v12, v12, a0
; CHECK-RV32-NEXT: vsrl.vv v8, v8, v12
; CHECK-RV32-NEXT: vor.vv v8, v16, v8
; CHECK-RV32-NEXT: addi sp, sp, 16
; CHECK-RV32-NEXT: ret
;
; CHECK-RV64-LABEL: vrol_vx_nxv4i64:
Expand All @@ -1128,24 +1084,11 @@ define <vscale x 4 x i64> @vrol_vx_nxv4i64(<vscale x 4 x i64> %a, i64 %b) {
; CHECK-RV64-NEXT: vor.vv v8, v12, v8
; CHECK-RV64-NEXT: ret
;
; CHECK-ZVBB32-LABEL: vrol_vx_nxv4i64:
; CHECK-ZVBB32: # %bb.0:
; CHECK-ZVBB32-NEXT: addi sp, sp, -16
; CHECK-ZVBB32-NEXT: .cfi_def_cfa_offset 16
; CHECK-ZVBB32-NEXT: sw a1, 12(sp)
; CHECK-ZVBB32-NEXT: sw a0, 8(sp)
; CHECK-ZVBB32-NEXT: addi a0, sp, 8
; CHECK-ZVBB32-NEXT: vsetvli a1, zero, e64, m4, ta, ma
; CHECK-ZVBB32-NEXT: vlse64.v v12, (a0), zero
; CHECK-ZVBB32-NEXT: vrol.vv v8, v8, v12
; CHECK-ZVBB32-NEXT: addi sp, sp, 16
; CHECK-ZVBB32-NEXT: ret
;
; CHECK-ZVBB64-LABEL: vrol_vx_nxv4i64:
; CHECK-ZVBB64: # %bb.0:
; CHECK-ZVBB64-NEXT: vsetvli a1, zero, e64, m4, ta, ma
; CHECK-ZVBB64-NEXT: vrol.vx v8, v8, a0
; CHECK-ZVBB64-NEXT: ret
; CHECK-ZVBB-LABEL: vrol_vx_nxv4i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a1, zero, e64, m4, ta, ma
; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0
; CHECK-ZVBB-NEXT: ret
%b.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
%b.splat = shufflevector <vscale x 4 x i64> %b.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
%x = call <vscale x 4 x i64> @llvm.fshl.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %a, <vscale x 4 x i64> %b.splat)
Expand Down Expand Up @@ -1179,21 +1122,15 @@ define <vscale x 8 x i64> @vrol_vv_nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x
define <vscale x 8 x i64> @vrol_vx_nxv8i64(<vscale x 8 x i64> %a, i64 %b) {
; CHECK-RV32-LABEL: vrol_vx_nxv8i64:
; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: addi sp, sp, -16
; CHECK-RV32-NEXT: .cfi_def_cfa_offset 16
; CHECK-RV32-NEXT: sw a1, 12(sp)
; CHECK-RV32-NEXT: sw a0, 8(sp)
; CHECK-RV32-NEXT: addi a0, sp, 8
; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; CHECK-RV32-NEXT: vlse64.v v16, (a0), zero
; CHECK-RV32-NEXT: vmv.v.x v16, a0
; CHECK-RV32-NEXT: li a0, 63
; CHECK-RV32-NEXT: vand.vx v24, v16, a0
; CHECK-RV32-NEXT: vsll.vv v24, v8, v24
; CHECK-RV32-NEXT: vrsub.vi v16, v16, 0
; CHECK-RV32-NEXT: vand.vx v16, v16, a0
; CHECK-RV32-NEXT: vsrl.vv v8, v8, v16
; CHECK-RV32-NEXT: vor.vv v8, v24, v8
; CHECK-RV32-NEXT: addi sp, sp, 16
; CHECK-RV32-NEXT: ret
;
; CHECK-RV64-LABEL: vrol_vx_nxv8i64:
Expand All @@ -1207,24 +1144,11 @@ define <vscale x 8 x i64> @vrol_vx_nxv8i64(<vscale x 8 x i64> %a, i64 %b) {
; CHECK-RV64-NEXT: vor.vv v8, v16, v8
; CHECK-RV64-NEXT: ret
;
; CHECK-ZVBB32-LABEL: vrol_vx_nxv8i64:
; CHECK-ZVBB32: # %bb.0:
; CHECK-ZVBB32-NEXT: addi sp, sp, -16
; CHECK-ZVBB32-NEXT: .cfi_def_cfa_offset 16
; CHECK-ZVBB32-NEXT: sw a1, 12(sp)
; CHECK-ZVBB32-NEXT: sw a0, 8(sp)
; CHECK-ZVBB32-NEXT: addi a0, sp, 8
; CHECK-ZVBB32-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; CHECK-ZVBB32-NEXT: vlse64.v v16, (a0), zero
; CHECK-ZVBB32-NEXT: vrol.vv v8, v8, v16
; CHECK-ZVBB32-NEXT: addi sp, sp, 16
; CHECK-ZVBB32-NEXT: ret
;
; CHECK-ZVBB64-LABEL: vrol_vx_nxv8i64:
; CHECK-ZVBB64: # %bb.0:
; CHECK-ZVBB64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; CHECK-ZVBB64-NEXT: vrol.vx v8, v8, a0
; CHECK-ZVBB64-NEXT: ret
; CHECK-ZVBB-LABEL: vrol_vx_nxv8i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0
; CHECK-ZVBB-NEXT: ret
%b.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%b.splat = shufflevector <vscale x 8 x i64> %b.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%x = call <vscale x 8 x i64> @llvm.fshl.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %a, <vscale x 8 x i64> %b.splat)
Expand Down
368 changes: 90 additions & 278 deletions llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll
View file

Large diffs are not rendered by default.

17 changes: 6 additions & 11 deletions llvm/test/CodeGen/WebAssembly/pr59626.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,16 +16,13 @@ define i8 @f(ptr %0, ptr %1) {
; CHECK-32-NEXT: i32.const 0
; CHECK-32-NEXT: i32.store8 2
; CHECK-32-NEXT: local.get 1
; CHECK-32-NEXT: local.get 0
; CHECK-32-NEXT: i8x16.splat
; CHECK-32-NEXT: v128.store16_lane 0, 0
; CHECK-32-NEXT: v128.const 0, 0
; CHECK-32-NEXT: i32x4.extract_lane 0
; CHECK-32-NEXT: i32.const 0
; CHECK-32-NEXT: i32.store16 0
; CHECK-32-NEXT: i32.const 0
; CHECK-32-NEXT: # fallthrough-return
;
; CHECK-64-LABEL: f:
; CHECK-64: .functype f (i64, i64) -> (i32)
; CHECK-64-NEXT: .local i32
; CHECK-64-NEXT: # %bb.0: # %BB
; CHECK-64-NEXT: local.get 0
; CHECK-64-NEXT: i32.const 0
Expand All @@ -34,11 +31,9 @@ define i8 @f(ptr %0, ptr %1) {
; CHECK-64-NEXT: i32.const 0
; CHECK-64-NEXT: i32.store16 0
; CHECK-64-NEXT: local.get 1
; CHECK-64-NEXT: local.get 2
; CHECK-64-NEXT: i8x16.splat
; CHECK-64-NEXT: v128.store16_lane 0, 0
; CHECK-64-NEXT: v128.const 0, 0
; CHECK-64-NEXT: i32x4.extract_lane 0
; CHECK-64-NEXT: i32.const 0
; CHECK-64-NEXT: i32.store16 0
; CHECK-64-NEXT: i32.const 0
; CHECK-64-NEXT: # fallthrough-return
BB:
store <3 x i8> zeroinitializer, ptr %0
Expand Down