60 changes: 60 additions & 0 deletions llvm/include/llvm/CodeGen/Register.h
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Original file line number Diff line number Diff line change
@@ -0,0 +1,60 @@
//===-- llvm/CodeGen/Register.h ---------------------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//

#ifndef LLVM_CODEGEN_REGISTER_H
#define LLVM_CODEGEN_REGISTER_H

#include <cassert>

namespace llvm {

/// Wrapper class representing virtual and physical registers. Should be passed
/// by value.
class Register {
unsigned Reg;

public:
Register(unsigned Val = 0): Reg(Val) {}

/// Return true if the specified register number is in the virtual register
/// namespace.
bool isVirtual() const {
return int(Reg) < 0;
}

/// Return true if the specified register number is in the physical register
/// namespace.
bool isPhysical() const {
return int(Reg) > 0;
}

/// Convert a virtual register number to a 0-based index. The first virtual
/// register in a function will get the index 0.
unsigned virtRegIndex() const {
assert(isVirtual() && "Not a virtual register");
return Reg & ~(1u << 31);
}

/// Convert a 0-based index to a virtual register number.
/// This is the inverse operation of VirtReg2IndexFunctor below.
static Register index2VirtReg(unsigned Index) {
return Register(Index | (1u << 31));
}

operator unsigned() const {
return Reg;
}

bool isValid() const {
return Reg != 0;
}
};

}

#endif
9 changes: 5 additions & 4 deletions llvm/include/llvm/CodeGen/SwiftErrorValueTracking.h
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Original file line number Diff line number Diff line change
Expand Up @@ -17,6 +17,7 @@

#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/Register.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/DebugLoc.h"
#include <functional>
Expand All @@ -41,18 +42,18 @@ class SwiftErrorValueTracking {

/// A map from swifterror value in a basic block to the virtual register it is
/// currently represented by.
DenseMap<std::pair<const MachineBasicBlock *, const Value *>, unsigned>
DenseMap<std::pair<const MachineBasicBlock *, const Value *>, Register>
VRegDefMap;

/// A list of upward exposed vreg uses that need to be satisfied by either a
/// copy def or a phi node at the beginning of the basic block representing
/// the predecessor(s) swifterror value.
DenseMap<std::pair<const MachineBasicBlock *, const Value *>, unsigned>
DenseMap<std::pair<const MachineBasicBlock *, const Value *>, Register>
VRegUpwardsUse;

/// A map from instructions that define/use a swifterror value to the virtual
/// register that represents that def/use.
llvm::DenseMap<PointerIntPair<const Instruction *, 1, bool>, unsigned>
llvm::DenseMap<PointerIntPair<const Instruction *, 1, bool>, Register>
VRegDefUses;

/// The swifterror argument of the current function.
Expand Down Expand Up @@ -80,7 +81,7 @@ class SwiftErrorValueTracking {

/// Set the swifterror virtual register in the VRegDefMap for this
/// basic block.
void setCurrentVReg(const MachineBasicBlock *MBB, const Value *, unsigned);
void setCurrentVReg(const MachineBasicBlock *MBB, const Value *, Register);

/// Get or create the swifterror value virtual register for a def of a
/// swifterror by an instruction.
Expand Down
2 changes: 1 addition & 1 deletion llvm/include/llvm/CodeGen/TargetRegisterInfo.h
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Original file line number Diff line number Diff line change
Expand Up @@ -990,7 +990,7 @@ class TargetRegisterInfo : public MCRegisterInfo {

/// getFrameRegister - This method should return the register used as a base
/// for values allocated in the current stack frame.
virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0;
virtual Register getFrameRegister(const MachineFunction &MF) const = 0;

/// Mark a register and all its aliases as reserved in the given set.
void markSuperRegs(BitVector &RegisterSet, unsigned Reg) const;
Expand Down
4 changes: 2 additions & 2 deletions llvm/include/llvm/CodeGen/VirtRegMap.h
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Original file line number Diff line number Diff line change
Expand Up @@ -97,8 +97,8 @@ class TargetInstrInfo;

/// returns the physical register mapped to the specified
/// virtual register
unsigned getPhys(unsigned virtReg) const {
assert(TargetRegisterInfo::isVirtualRegister(virtReg));
Register getPhys(Register virtReg) const {
assert(virtReg.isVirtual());
return Virt2PhysMap[virtReg];
}

Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -38,12 +38,12 @@ using EntryIndex = DbgValueHistoryMap::EntryIndex;
// If @MI is a DBG_VALUE with debug value described by a
// defined register, returns the number of this register.
// In the other case, returns 0.
static unsigned isDescribedByReg(const MachineInstr &MI) {
static Register isDescribedByReg(const MachineInstr &MI) {
assert(MI.isDebugValue());
assert(MI.getNumOperands() == 4);
// If location of variable is described using a register (directly or
// indirectly), this register is always a first operand.
return MI.getOperand(0).isReg() ? MI.getOperand(0).getReg() : 0;
return MI.getOperand(0).isReg() ? MI.getOperand(0).getReg() : Register();
}

bool DbgValueHistoryMap::startDbgValue(InlinedEntity Var,
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -27,8 +27,8 @@ using namespace llvm;
void CallLowering::anchor() {}

bool CallLowering::lowerCall(MachineIRBuilder &MIRBuilder, ImmutableCallSite CS,
unsigned ResReg, ArrayRef<unsigned> ArgRegs,
unsigned SwiftErrorVReg,
Register ResReg, ArrayRef<Register> ArgRegs,
Register SwiftErrorVReg,
std::function<unsigned()> GetCalleeReg) const {
auto &DL = CS.getParent()->getParent()->getParent()->getDataLayout();

Expand Down Expand Up @@ -131,7 +131,7 @@ bool CallLowering::handleAssignments(MachineIRBuilder &MIRBuilder,
if (Handler.assignArg(i, CurVT, CurVT, CCValAssign::Full, Args[i], CCInfo)) {
// Try to use the register type if we couldn't assign the VT.
if (!Handler.isArgumentHandler() || !CurVT.isValid())
return false;
return false;
CurVT = TLI->getRegisterTypeForCallingConv(
F.getContext(), F.getCallingConv(), EVT(CurVT));
if (Handler.assignArg(i, CurVT, CurVT, CCValAssign::Full, Args[i], CCInfo))
Expand Down
56 changes: 28 additions & 28 deletions llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -169,7 +169,7 @@ IRTranslator::allocateVRegs(const Value &Val) {
return *Regs;
}

ArrayRef<unsigned> IRTranslator::getOrCreateVRegs(const Value &Val) {
ArrayRef<Register> IRTranslator::getOrCreateVRegs(const Value &Val) {
auto VRegsIt = VMap.findVRegs(Val);
if (VRegsIt != VMap.vregs_end())
return *VRegsIt->second;
Expand Down Expand Up @@ -363,11 +363,11 @@ bool IRTranslator::translateRet(const User &U, MachineIRBuilder &MIRBuilder) {
if (Ret && DL->getTypeStoreSize(Ret->getType()) == 0)
Ret = nullptr;

ArrayRef<unsigned> VRegs;
ArrayRef<Register> VRegs;
if (Ret)
VRegs = getOrCreateVRegs(*Ret);

unsigned SwiftErrorVReg = 0;
Register SwiftErrorVReg = 0;
if (CLI->supportSwiftError() && SwiftError.getFunctionArg()) {
SwiftErrorVReg = SwiftError.getOrCreateVRegUseAt(
&RI, &MIRBuilder.getMBB(), SwiftError.getFunctionArg());
Expand Down Expand Up @@ -858,7 +858,7 @@ bool IRTranslator::translateLoad(const User &U, MachineIRBuilder &MIRBuilder) {
if (DL->getTypeStoreSize(LI.getType()) == 0)
return true;

ArrayRef<unsigned> Regs = getOrCreateVRegs(LI);
ArrayRef<Register> Regs = getOrCreateVRegs(LI);
ArrayRef<uint64_t> Offsets = *VMap.getOffsets(LI);
unsigned Base = getOrCreateVReg(*LI.getPointerOperand());

Expand All @@ -875,7 +875,7 @@ bool IRTranslator::translateLoad(const User &U, MachineIRBuilder &MIRBuilder) {


for (unsigned i = 0; i < Regs.size(); ++i) {
unsigned Addr = 0;
Register Addr;
MIRBuilder.materializeGEP(Addr, Base, OffsetTy, Offsets[i] / 8);

MachinePointerInfo Ptr(LI.getPointerOperand(), Offsets[i] / 8);
Expand All @@ -899,7 +899,7 @@ bool IRTranslator::translateStore(const User &U, MachineIRBuilder &MIRBuilder) {
if (DL->getTypeStoreSize(SI.getValueOperand()->getType()) == 0)
return true;

ArrayRef<unsigned> Vals = getOrCreateVRegs(*SI.getValueOperand());
ArrayRef<Register> Vals = getOrCreateVRegs(*SI.getValueOperand());
ArrayRef<uint64_t> Offsets = *VMap.getOffsets(*SI.getValueOperand());
unsigned Base = getOrCreateVReg(*SI.getPointerOperand());

Expand All @@ -916,7 +916,7 @@ bool IRTranslator::translateStore(const User &U, MachineIRBuilder &MIRBuilder) {
}

for (unsigned i = 0; i < Vals.size(); ++i) {
unsigned Addr = 0;
Register Addr;
MIRBuilder.materializeGEP(Addr, Base, OffsetTy, Offsets[i] / 8);

MachinePointerInfo Ptr(SI.getPointerOperand(), Offsets[i] / 8);
Expand Down Expand Up @@ -958,7 +958,7 @@ bool IRTranslator::translateExtractValue(const User &U,
MachineIRBuilder &MIRBuilder) {
const Value *Src = U.getOperand(0);
uint64_t Offset = getOffsetFromIndices(U, *DL);
ArrayRef<unsigned> SrcRegs = getOrCreateVRegs(*Src);
ArrayRef<Register> SrcRegs = getOrCreateVRegs(*Src);
ArrayRef<uint64_t> Offsets = *VMap.getOffsets(*Src);
unsigned Idx = llvm::lower_bound(Offsets, Offset) - Offsets.begin();
auto &DstRegs = allocateVRegs(U);
Expand All @@ -975,8 +975,8 @@ bool IRTranslator::translateInsertValue(const User &U,
uint64_t Offset = getOffsetFromIndices(U, *DL);
auto &DstRegs = allocateVRegs(U);
ArrayRef<uint64_t> DstOffsets = *VMap.getOffsets(U);
ArrayRef<unsigned> SrcRegs = getOrCreateVRegs(*Src);
ArrayRef<unsigned> InsertedRegs = getOrCreateVRegs(*U.getOperand(1));
ArrayRef<Register> SrcRegs = getOrCreateVRegs(*Src);
ArrayRef<Register> InsertedRegs = getOrCreateVRegs(*U.getOperand(1));
auto InsertedIt = InsertedRegs.begin();

for (unsigned i = 0; i < DstRegs.size(); ++i) {
Expand All @@ -992,9 +992,9 @@ bool IRTranslator::translateInsertValue(const User &U,
bool IRTranslator::translateSelect(const User &U,
MachineIRBuilder &MIRBuilder) {
unsigned Tst = getOrCreateVReg(*U.getOperand(0));
ArrayRef<unsigned> ResRegs = getOrCreateVRegs(U);
ArrayRef<unsigned> Op0Regs = getOrCreateVRegs(*U.getOperand(1));
ArrayRef<unsigned> Op1Regs = getOrCreateVRegs(*U.getOperand(2));
ArrayRef<Register> ResRegs = getOrCreateVRegs(U);
ArrayRef<Register> Op0Regs = getOrCreateVRegs(*U.getOperand(1));
ArrayRef<Register> Op1Regs = getOrCreateVRegs(*U.getOperand(2));

const SelectInst &SI = cast<SelectInst>(U);
uint16_t Flags = 0;
Expand Down Expand Up @@ -1186,7 +1186,7 @@ void IRTranslator::getStackGuard(unsigned DstReg,

bool IRTranslator::translateOverflowIntrinsic(const CallInst &CI, unsigned Op,
MachineIRBuilder &MIRBuilder) {
ArrayRef<unsigned> ResRegs = getOrCreateVRegs(CI);
ArrayRef<Register> ResRegs = getOrCreateVRegs(CI);
MIRBuilder.buildInstr(Op)
.addDef(ResRegs[0])
.addDef(ResRegs[1])
Expand Down Expand Up @@ -1539,7 +1539,7 @@ bool IRTranslator::translateInlineAsm(const CallInst &CI,

unsigned IRTranslator::packRegs(const Value &V,
MachineIRBuilder &MIRBuilder) {
ArrayRef<unsigned> Regs = getOrCreateVRegs(V);
ArrayRef<Register> Regs = getOrCreateVRegs(V);
ArrayRef<uint64_t> Offsets = *VMap.getOffsets(V);
LLT BigTy = getLLTForType(*V.getType(), *DL);

Expand All @@ -1558,7 +1558,7 @@ unsigned IRTranslator::packRegs(const Value &V,

void IRTranslator::unpackRegs(const Value &V, unsigned Src,
MachineIRBuilder &MIRBuilder) {
ArrayRef<unsigned> Regs = getOrCreateVRegs(V);
ArrayRef<Register> Regs = getOrCreateVRegs(V);
ArrayRef<uint64_t> Offsets = *VMap.getOffsets(V);

for (unsigned i = 0; i < Regs.size(); ++i)
Expand Down Expand Up @@ -1586,12 +1586,12 @@ bool IRTranslator::translateCall(const User &U, MachineIRBuilder &MIRBuilder) {

if (!F || !F->isIntrinsic() || ID == Intrinsic::not_intrinsic) {
bool IsSplitType = valueIsSplit(CI);
unsigned Res = IsSplitType ? MRI->createGenericVirtualRegister(
Register Res = IsSplitType ? MRI->createGenericVirtualRegister(
getLLTForType(*CI.getType(), *DL))
: getOrCreateVReg(CI);

SmallVector<unsigned, 8> Args;
unsigned SwiftErrorVReg = 0;
SmallVector<Register, 8> Args;
Register SwiftErrorVReg;
for (auto &Arg: CI.arg_operands()) {
if (CLI->supportSwiftError() && isSwiftError(Arg)) {
LLT Ty = getLLTForType(*Arg->getType(), *DL);
Expand Down Expand Up @@ -1622,7 +1622,7 @@ bool IRTranslator::translateCall(const User &U, MachineIRBuilder &MIRBuilder) {
if (translateKnownIntrinsic(CI, ID, MIRBuilder))
return true;

ArrayRef<unsigned> ResultRegs;
ArrayRef<Register> ResultRegs;
if (!CI.getType()->isVoidTy())
ResultRegs = getOrCreateVRegs(CI);

Expand Down Expand Up @@ -1690,8 +1690,8 @@ bool IRTranslator::translateInvoke(const User &U,
unsigned Res = 0;
if (!I.getType()->isVoidTy())
Res = MRI->createGenericVirtualRegister(getLLTForType(*I.getType(), *DL));
SmallVector<unsigned, 8> Args;
unsigned SwiftErrorVReg = 0;
SmallVector<Register, 8> Args;
Register SwiftErrorVReg;
for (auto &Arg : I.arg_operands()) {
if (CLI->supportSwiftError() && isSwiftError(Arg)) {
LLT Ty = getLLTForType(*Arg->getType(), *DL);
Expand Down Expand Up @@ -1776,7 +1776,7 @@ bool IRTranslator::translateLandingPad(const User &U,
return false;

MBB.addLiveIn(ExceptionReg);
ArrayRef<unsigned> ResRegs = getOrCreateVRegs(LP);
ArrayRef<Register> ResRegs = getOrCreateVRegs(LP);
MIRBuilder.buildCopy(ResRegs[0], ExceptionReg);

unsigned SelectorReg = TLI.getExceptionSelectorRegister(PersonalityFn);
Expand Down Expand Up @@ -2069,7 +2069,7 @@ void IRTranslator::finishPendingPhis() {
SmallSet<const MachineBasicBlock *, 16> SeenPreds;
for (unsigned i = 0; i < PI->getNumIncomingValues(); ++i) {
auto IRPred = PI->getIncomingBlock(i);
ArrayRef<unsigned> ValRegs = getOrCreateVRegs(*PI->getIncomingValue(i));
ArrayRef<Register> ValRegs = getOrCreateVRegs(*PI->getIncomingValue(i));
for (auto Pred : getMachinePredBBs({IRPred, PI->getParent()})) {
if (SeenPreds.count(Pred))
continue;
Expand Down Expand Up @@ -2136,7 +2136,7 @@ bool IRTranslator::translate(const Constant &C, unsigned Reg) {
// Return the scalar if it is a <1 x Ty> vector.
if (CAZ->getNumElements() == 1)
return translate(*CAZ->getElementValue(0u), Reg);
SmallVector<unsigned, 4> Ops;
SmallVector<Register, 4> Ops;
for (unsigned i = 0; i < CAZ->getNumElements(); ++i) {
Constant &Elt = *CAZ->getElementValue(i);
Ops.push_back(getOrCreateVReg(Elt));
Expand All @@ -2146,7 +2146,7 @@ bool IRTranslator::translate(const Constant &C, unsigned Reg) {
// Return the scalar if it is a <1 x Ty> vector.
if (CV->getNumElements() == 1)
return translate(*CV->getElementAsConstant(0), Reg);
SmallVector<unsigned, 4> Ops;
SmallVector<Register, 4> Ops;
for (unsigned i = 0; i < CV->getNumElements(); ++i) {
Constant &Elt = *CV->getElementAsConstant(i);
Ops.push_back(getOrCreateVReg(Elt));
Expand All @@ -2164,7 +2164,7 @@ bool IRTranslator::translate(const Constant &C, unsigned Reg) {
} else if (auto CV = dyn_cast<ConstantVector>(&C)) {
if (CV->getNumOperands() == 1)
return translate(*CV->getOperand(0), Reg);
SmallVector<unsigned, 4> Ops;
SmallVector<Register, 4> Ops;
for (unsigned i = 0; i < CV->getNumOperands(); ++i) {
Ops.push_back(getOrCreateVReg(*CV->getOperand(i)));
}
Expand Down Expand Up @@ -2274,7 +2274,7 @@ bool IRTranslator::runOnMachineFunction(MachineFunction &CurMF) {
EntryBB->addSuccessor(&getMBB(F.front()));

// Lower the actual args into this basic block.
SmallVector<unsigned, 8> VRegArgs;
SmallVector<Register, 8> VRegArgs;
for (const Argument &Arg: F.args()) {
if (DL->getTypeStoreSize(Arg.getType()) == 0)
continue; // Don't handle zero sized types.
Expand Down
122 changes: 61 additions & 61 deletions llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
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Large diffs are not rendered by default.

26 changes: 13 additions & 13 deletions llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -210,7 +210,7 @@ MachineInstrBuilder MachineIRBuilder::buildGEP(unsigned Res, unsigned Op0,
}

Optional<MachineInstrBuilder>
MachineIRBuilder::materializeGEP(unsigned &Res, unsigned Op0,
MachineIRBuilder::materializeGEP(Register &Res, Register Op0,
const LLT &ValueTy, uint64_t Value) {
assert(Res == 0 && "Res is a result argument");
assert(ValueTy.isScalar() && "invalid offset type");
Expand Down Expand Up @@ -506,7 +506,7 @@ MachineInstrBuilder MachineIRBuilder::buildExtract(const DstOp &Dst,
return Extract;
}

void MachineIRBuilder::buildSequence(unsigned Res, ArrayRef<unsigned> Ops,
void MachineIRBuilder::buildSequence(Register Res, ArrayRef<Register> Ops,
ArrayRef<uint64_t> Indices) {
#ifndef NDEBUG
assert(Ops.size() == Indices.size() && "incompatible args");
Expand Down Expand Up @@ -535,11 +535,11 @@ void MachineIRBuilder::buildSequence(unsigned Res, ArrayRef<unsigned> Ops,
return;
}

unsigned ResIn = getMRI()->createGenericVirtualRegister(ResTy);
Register ResIn = getMRI()->createGenericVirtualRegister(ResTy);
buildUndef(ResIn);

for (unsigned i = 0; i < Ops.size(); ++i) {
unsigned ResOut = i + 1 == Ops.size()
Register ResOut = i + 1 == Ops.size()
? Res
: getMRI()->createGenericVirtualRegister(ResTy);
buildInsert(ResOut, ResIn, Ops[i], Indices[i]);
Expand All @@ -552,7 +552,7 @@ MachineInstrBuilder MachineIRBuilder::buildUndef(const DstOp &Res) {
}

MachineInstrBuilder MachineIRBuilder::buildMerge(const DstOp &Res,
ArrayRef<unsigned> Ops) {
ArrayRef<Register> Ops) {
// Unfortunately to convert from ArrayRef<LLT> to ArrayRef<SrcOp>,
// we need some temporary storage for the DstOp objects. Here we use a
// sufficiently large SmallVector to not go through the heap.
Expand All @@ -572,13 +572,13 @@ MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<LLT> Res,
MachineInstrBuilder MachineIRBuilder::buildUnmerge(LLT Res,
const SrcOp &Op) {
unsigned NumReg = Op.getLLTTy(*getMRI()).getSizeInBits() / Res.getSizeInBits();
SmallVector<unsigned, 8> TmpVec;
SmallVector<Register, 8> TmpVec;
for (unsigned I = 0; I != NumReg; ++I)
TmpVec.push_back(getMRI()->createGenericVirtualRegister(Res));
return buildUnmerge(TmpVec, Op);
}

MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<unsigned> Res,
MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<Register> Res,
const SrcOp &Op) {
// Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<DstOp>,
// we need some temporary storage for the DstOp objects. Here we use a
Expand All @@ -588,7 +588,7 @@ MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<unsigned> Res,
}

MachineInstrBuilder MachineIRBuilder::buildBuildVector(const DstOp &Res,
ArrayRef<unsigned> Ops) {
ArrayRef<Register> Ops) {
// Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<SrcOp>,
// we need some temporary storage for the DstOp objects. Here we use a
// sufficiently large SmallVector to not go through the heap.
Expand All @@ -604,7 +604,7 @@ MachineInstrBuilder MachineIRBuilder::buildSplatVector(const DstOp &Res,

MachineInstrBuilder
MachineIRBuilder::buildBuildVectorTrunc(const DstOp &Res,
ArrayRef<unsigned> Ops) {
ArrayRef<Register> Ops) {
// Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<SrcOp>,
// we need some temporary storage for the DstOp objects. Here we use a
// sufficiently large SmallVector to not go through the heap.
Expand All @@ -613,16 +613,16 @@ MachineIRBuilder::buildBuildVectorTrunc(const DstOp &Res,
}

MachineInstrBuilder
MachineIRBuilder::buildConcatVectors(const DstOp &Res, ArrayRef<unsigned> Ops) {
MachineIRBuilder::buildConcatVectors(const DstOp &Res, ArrayRef<Register> Ops) {
// Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<SrcOp>,
// we need some temporary storage for the DstOp objects. Here we use a
// sufficiently large SmallVector to not go through the heap.
SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
return buildInstr(TargetOpcode::G_CONCAT_VECTORS, Res, TmpVec);
}

MachineInstrBuilder MachineIRBuilder::buildInsert(unsigned Res, unsigned Src,
unsigned Op, unsigned Index) {
MachineInstrBuilder MachineIRBuilder::buildInsert(Register Res, Register Src,
Register Op, unsigned Index) {
assert(Index + getMRI()->getType(Op).getSizeInBits() <=
getMRI()->getType(Res).getSizeInBits() &&
"insertion past the end of a register");
Expand All @@ -640,7 +640,7 @@ MachineInstrBuilder MachineIRBuilder::buildInsert(unsigned Res, unsigned Src,
}

MachineInstrBuilder MachineIRBuilder::buildIntrinsic(Intrinsic::ID ID,
ArrayRef<unsigned> ResultRegs,
ArrayRef<Register> ResultRegs,
bool HasSideEffects) {
auto MIB =
buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/CodeGen/LiveDebugValues.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -70,12 +70,12 @@ STATISTIC(NumInserted, "Number of DBG_VALUE instructions inserted");

// If @MI is a DBG_VALUE with debug value described by a defined
// register, returns the number of this register. In the other case, returns 0.
static unsigned isDbgValueDescribedByReg(const MachineInstr &MI) {
static Register isDbgValueDescribedByReg(const MachineInstr &MI) {
assert(MI.isDebugValue() && "expected a DBG_VALUE");
assert(MI.getNumOperands() == 4 && "malformed DBG_VALUE");
// If location of variable is described using a register (directly
// or indirectly), this register is always a first operand.
return MI.getOperand(0).isReg() ? MI.getOperand(0).getReg() : 0;
return MI.getOperand(0).isReg() ? MI.getOperand(0).getReg() : Register();
}

namespace {
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/MachineOperand.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -342,7 +342,7 @@ hash_code llvm::hash_value(const MachineOperand &MO) {
switch (MO.getType()) {
case MachineOperand::MO_Register:
// Register operands don't have target flags.
return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
return hash_combine(MO.getType(), (unsigned)MO.getReg(), MO.getSubReg(), MO.isDef());
case MachineOperand::MO_Immediate:
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
case MachineOperand::MO_CImmediate:
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/CodeGen/MachineRegisterInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -154,7 +154,7 @@ unsigned MachineRegisterInfo::createIncompleteVirtualRegister(StringRef Name) {
/// createVirtualRegister - Create and return a new virtual register in the
/// function with the specified register class.
///
unsigned
Register
MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass,
StringRef Name) {
assert(RegClass && "Cannot create register without RegClass!");
Expand All @@ -169,7 +169,7 @@ MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass,
return Reg;
}

unsigned MachineRegisterInfo::cloneVirtualRegister(unsigned VReg,
Register MachineRegisterInfo::cloneVirtualRegister(Register VReg,
StringRef Name) {
unsigned Reg = createIncompleteVirtualRegister(Name);
VRegInfo[Reg].first = VRegInfo[VReg].first;
Expand All @@ -184,7 +184,7 @@ void MachineRegisterInfo::setType(unsigned VReg, LLT Ty) {
VRegToType[VReg] = Ty;
}

unsigned
Register
MachineRegisterInfo::createGenericVirtualRegister(LLT Ty, StringRef Name) {
// New virtual register number.
unsigned Reg = createIncompleteVirtualRegister(Name);
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/CodeGen/RegAllocGreedy.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2874,14 +2874,14 @@ void RAGreedy::collectHintInfo(unsigned Reg, HintsInfo &Out) {
if (!Instr.isFullCopy())
continue;
// Look for the other end of the copy.
unsigned OtherReg = Instr.getOperand(0).getReg();
Register OtherReg = Instr.getOperand(0).getReg();
if (OtherReg == Reg) {
OtherReg = Instr.getOperand(1).getReg();
if (OtherReg == Reg)
continue;
}
// Get the current assignment.
unsigned OtherPhysReg = TargetRegisterInfo::isPhysicalRegister(OtherReg)
Register OtherPhysReg = TargetRegisterInfo::isPhysicalRegister(OtherReg)
? OtherReg
: VRM->getPhys(OtherReg);
// Push the collected information.
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7879,7 +7879,7 @@ static void GetRegistersForValue(SelectionDAG &DAG, const SDLoc &DL,

for (; NumRegs; --NumRegs, ++I) {
assert(I != RC->end() && "Ran out of registers to allocate!");
auto R = (AssignedReg) ? *I : RegInfo.createVirtualRegister(RC);
Register R = AssignedReg ? Register(*I) : RegInfo.createVirtualRegister(RC);
Regs.push_back(R);
}

Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -570,7 +570,7 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
bool hasFI = MI->getOperand(0).isFI();
unsigned Reg =
Register Reg =
hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg();
if (TargetRegisterInfo::isPhysicalRegister(Reg))
EntryMBB->insert(EntryMBB->begin(), MI);
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/CodeGen/SwiftErrorValueTracking.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -42,7 +42,7 @@ unsigned SwiftErrorValueTracking::getOrCreateVReg(const MachineBasicBlock *MBB,
}

void SwiftErrorValueTracking::setCurrentVReg(const MachineBasicBlock *MBB,
const Value *Val, unsigned VReg) {
const Value *Val, Register VReg) {
VRegDefMap[std::make_pair(MBB, Val)] = VReg;
}

Expand Down Expand Up @@ -161,7 +161,7 @@ void SwiftErrorValueTracking::propagateVRegs() {
auto UUseIt = VRegUpwardsUse.find(Key);
auto VRegDefIt = VRegDefMap.find(Key);
bool UpwardsUse = UUseIt != VRegUpwardsUse.end();
unsigned UUseVReg = UpwardsUse ? UUseIt->second : 0;
Register UUseVReg = UpwardsUse ? UUseIt->second : Register();
bool DownwardDef = VRegDefIt != VRegDefMap.end();
assert(!(UpwardsUse && !DownwardDef) &&
"We can't have an upwards use but no downwards def");
Expand Down Expand Up @@ -238,7 +238,7 @@ void SwiftErrorValueTracking::propagateVRegs() {
// destination virtual register number otherwise we generate a new one.
auto &DL = MF->getDataLayout();
auto const *RC = TLI->getRegClassFor(TLI->getPointerTy(DL));
unsigned PHIVReg =
Register PHIVReg =
UpwardsUse ? UUseVReg : MF->getRegInfo().createVirtualRegister(RC);
MachineInstrBuilder PHI =
BuildMI(*MBB, MBB->getFirstNonPHI(), DLoc,
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/CodeGen/TargetInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -163,9 +163,9 @@ MachineInstr *TargetInstrInfo::commuteInstructionImpl(MachineInstr &MI,
assert(MI.getOperand(Idx1).isReg() && MI.getOperand(Idx2).isReg() &&
"This only knows how to commute register operands so far");

unsigned Reg0 = HasDef ? MI.getOperand(0).getReg() : 0;
unsigned Reg1 = MI.getOperand(Idx1).getReg();
unsigned Reg2 = MI.getOperand(Idx2).getReg();
Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register();
Register Reg1 = MI.getOperand(Idx1).getReg();
Register Reg2 = MI.getOperand(Idx2).getReg();
unsigned SubReg0 = HasDef ? MI.getOperand(0).getSubReg() : 0;
unsigned SubReg1 = MI.getOperand(Idx1).getSubReg();
unsigned SubReg2 = MI.getOperand(Idx2).getSubReg();
Expand Down
10 changes: 5 additions & 5 deletions llvm/lib/Target/AArch64/AArch64CallLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -232,8 +232,8 @@ void AArch64CallLowering::splitToValueTypes(

bool AArch64CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
const Value *Val,
ArrayRef<unsigned> VRegs,
unsigned SwiftErrorVReg) const {
ArrayRef<Register> VRegs,
Register SwiftErrorVReg) const {
auto MIB = MIRBuilder.buildInstrNoInsert(AArch64::RET_ReallyLR);
assert(((Val && !VRegs.empty()) || (!Val && VRegs.empty())) &&
"Return value without a vreg");
Expand Down Expand Up @@ -352,7 +352,7 @@ bool AArch64CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,

bool AArch64CallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
const Function &F,
ArrayRef<unsigned> VRegs) const {
ArrayRef<Register> VRegs) const {
MachineFunction &MF = MIRBuilder.getMF();
MachineBasicBlock &MBB = MIRBuilder.getMBB();
MachineRegisterInfo &MRI = MF.getRegInfo();
Expand Down Expand Up @@ -427,7 +427,7 @@ bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
const MachineOperand &Callee,
const ArgInfo &OrigRet,
ArrayRef<ArgInfo> OrigArgs,
unsigned SwiftErrorVReg) const {
Register SwiftErrorVReg) const {
MachineFunction &MF = MIRBuilder.getMF();
const Function &F = MF.getFunction();
MachineRegisterInfo &MRI = MF.getRegInfo();
Expand Down Expand Up @@ -495,7 +495,7 @@ bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
SplitArgs.clear();

SmallVector<uint64_t, 8> RegOffsets;
SmallVector<unsigned, 8> SplitRegs;
SmallVector<Register, 8> SplitRegs;
splitToValueTypes(OrigRet, SplitArgs, DL, MRI, F.getCallingConv(),
[&](unsigned Reg, uint64_t Offset) {
RegOffsets.push_back(Offset);
Expand Down
8 changes: 4 additions & 4 deletions llvm/lib/Target/AArch64/AArch64CallLowering.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -34,16 +34,16 @@ class AArch64CallLowering: public CallLowering {
AArch64CallLowering(const AArch64TargetLowering &TLI);

bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val,
ArrayRef<unsigned> VRegs,
unsigned SwiftErrorVReg) const override;
ArrayRef<Register> VRegs,
Register SwiftErrorVReg) const override;

bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F,
ArrayRef<unsigned> VRegs) const override;
ArrayRef<Register> VRegs) const override;

bool lowerCall(MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv,
const MachineOperand &Callee, const ArgInfo &OrigRet,
ArrayRef<ArgInfo> OrigArgs,
unsigned SwiftErrorVReg) const override;
Register SwiftErrorVReg) const override;

bool lowerCall(MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv,
const MachineOperand &Callee, const ArgInfo &OrigRet,
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -212,8 +212,8 @@ class FalkorHWPFFix : public MachineFunctionPass {
struct LoadInfo {
LoadInfo() = default;

unsigned DestReg = 0;
unsigned BaseReg = 0;
Register DestReg;
Register BaseReg;
int BaseRegIdx = -1;
const MachineOperand *OffsetOpnd = nullptr;
bool IsPrePost = false;
Expand Down Expand Up @@ -647,7 +647,7 @@ static Optional<LoadInfo> getLoadInfo(const MachineInstr &MI) {
return None;

LoadInfo LI;
LI.DestReg = DestRegIdx == -1 ? 0 : MI.getOperand(DestRegIdx).getReg();
LI.DestReg = DestRegIdx == -1 ? Register() : MI.getOperand(DestRegIdx).getReg();
LI.BaseReg = BaseReg;
LI.BaseRegIdx = BaseRegIdx;
LI.OffsetOpnd = OffsetIdx == -1 ? nullptr : &MI.getOperand(OffsetIdx);
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1018,9 +1018,9 @@ void AArch64InstructionSelector::materializeLargeCMVal(
MovZ->addOperand(MF, MachineOperand::CreateImm(0));
constrainSelectedInstRegOperands(*MovZ, TII, TRI, RBI);

auto BuildMovK = [&](unsigned SrcReg, unsigned char Flags, unsigned Offset,
unsigned ForceDstReg) {
unsigned DstReg = ForceDstReg
auto BuildMovK = [&](Register SrcReg, unsigned char Flags, unsigned Offset,
Register ForceDstReg) {
Register DstReg = ForceDstReg
? ForceDstReg
: MRI.createVirtualRegister(&AArch64::GPR64RegClass);
auto MovI = MIB.buildInstr(AArch64::MOVKXi).addDef(DstReg).addUse(SrcReg);
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -379,8 +379,8 @@ bool AArch64RedundantCopyElimination::optimizeBlock(MachineBasicBlock *MBB) {
bool IsCopy = MI->isCopy();
bool IsMoveImm = MI->isMoveImmediate();
if (IsCopy || IsMoveImm) {
MCPhysReg DefReg = MI->getOperand(0).getReg();
MCPhysReg SrcReg = IsCopy ? MI->getOperand(1).getReg() : 0;
Register DefReg = MI->getOperand(0).getReg();
Register SrcReg = IsCopy ? MI->getOperand(1).getReg() : Register();
int64_t SrcImm = IsMoveImm ? MI->getOperand(1).getImm() : 0;
if (!MRI->isReserved(DefReg) &&
((IsCopy && (SrcReg == AArch64::XZR || SrcReg == AArch64::WZR)) ||
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -279,7 +279,7 @@ bool AArch64RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
return false;
}

unsigned
Register
AArch64RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
const AArch64FrameLowering *TFI = getFrameLowering(MF);
return TFI->hasFP(MF) ? AArch64::FP : AArch64::SP;
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64RegisterInfo.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -113,7 +113,7 @@ class AArch64RegisterInfo final : public AArch64GenRegisterInfo {
unsigned getBaseRegister() const;

// Debug information queries.
unsigned getFrameRegister(const MachineFunction &MF) const override;
Register getFrameRegister(const MachineFunction &MF) const override;

unsigned getRegPressureLimit(const TargetRegisterClass *RC,
MachineFunction &MF) const override;
Expand Down
10 changes: 5 additions & 5 deletions llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -69,7 +69,7 @@ AMDGPUCallLowering::AMDGPUCallLowering(const AMDGPUTargetLowering &TLI)

bool AMDGPUCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
const Value *Val,
ArrayRef<unsigned> VRegs) const {
ArrayRef<Register> VRegs) const {

MachineFunction &MF = MIRBuilder.getMF();
MachineRegisterInfo &MRI = MF.getRegInfo();
Expand All @@ -81,7 +81,7 @@ bool AMDGPUCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
return true;
}

unsigned VReg = VRegs[0];
Register VReg = VRegs[0];

const Function &F = MF.getFunction();
auto &DL = F.getParent()->getDataLayout();
Expand Down Expand Up @@ -138,14 +138,14 @@ unsigned AMDGPUCallLowering::lowerParameterPtr(MachineIRBuilder &MIRBuilder,
void AMDGPUCallLowering::lowerParameter(MachineIRBuilder &MIRBuilder,
Type *ParamTy, uint64_t Offset,
unsigned Align,
unsigned DstReg) const {
Register DstReg) const {
MachineFunction &MF = MIRBuilder.getMF();
const Function &F = MF.getFunction();
const DataLayout &DL = F.getParent()->getDataLayout();
PointerType *PtrTy = PointerType::get(ParamTy, AMDGPUAS::CONSTANT_ADDRESS);
MachinePointerInfo PtrInfo(UndefValue::get(PtrTy));
unsigned TypeSize = DL.getTypeStoreSize(ParamTy);
unsigned PtrReg = lowerParameterPtr(MIRBuilder, ParamTy, Offset);
Register PtrReg = lowerParameterPtr(MIRBuilder, ParamTy, Offset);

MachineMemOperand *MMO =
MF.getMachineMemOperand(PtrInfo, MachineMemOperand::MOLoad |
Expand Down Expand Up @@ -195,7 +195,7 @@ static void allocateSystemSGPRs(CCState &CCInfo,

bool AMDGPUCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
const Function &F,
ArrayRef<unsigned> VRegs) const {
ArrayRef<Register> VRegs) const {
// AMDGPU_GS and AMDGP_HS are not supported yet.
if (F.getCallingConv() == CallingConv::AMDGPU_GS ||
F.getCallingConv() == CallingConv::AMDGPU_HS)
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/AMDGPU/AMDGPUCallLowering.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -27,15 +27,15 @@ class AMDGPUCallLowering: public CallLowering {

void lowerParameter(MachineIRBuilder &MIRBuilder, Type *ParamTy,
uint64_t Offset, unsigned Align,
unsigned DstReg) const;
Register DstReg) const;

public:
AMDGPUCallLowering(const AMDGPUTargetLowering &TLI);

bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val,
ArrayRef<unsigned> VRegs) const override;
ArrayRef<Register> VRegs) const override;
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F,
ArrayRef<unsigned> VRegs) const override;
ArrayRef<Register> VRegs) const override;
static CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg);
static CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg);
};
Expand Down
8 changes: 4 additions & 4 deletions llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -791,8 +791,8 @@ unsigned AMDGPULegalizerInfo::getSegmentAperture(
4,
MinAlign(64, StructOffset));

unsigned LoadResult = MRI.createGenericVirtualRegister(S32);
unsigned LoadAddr = AMDGPU::NoRegister;
Register LoadResult = MRI.createGenericVirtualRegister(S32);
Register LoadAddr;

MIRBuilder.materializeGEP(LoadAddr, QueuePtr, LLT::scalar(64), StructOffset);
MIRBuilder.buildLoad(LoadResult, LoadAddr, *MMO);
Expand All @@ -806,8 +806,8 @@ bool AMDGPULegalizerInfo::legalizeAddrSpaceCast(

MIRBuilder.setInstr(MI);

unsigned Dst = MI.getOperand(0).getReg();
unsigned Src = MI.getOperand(1).getReg();
Register Dst = MI.getOperand(0).getReg();
Register Src = MI.getOperand(1).getReg();

LLT DstTy = MRI.getType(Dst);
LLT SrcTy = MRI.getType(Src);
Expand Down
28 changes: 14 additions & 14 deletions llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -375,7 +375,7 @@ AMDGPURegisterBankInfo::getInstrAlternativeMappings(

void AMDGPURegisterBankInfo::split64BitValueForMapping(
MachineIRBuilder &B,
SmallVector<unsigned, 2> &Regs,
SmallVector<Register, 2> &Regs,
LLT HalfTy,
unsigned Reg) const {
assert(HalfTy.getSizeInBits() == 32);
Expand All @@ -396,7 +396,7 @@ void AMDGPURegisterBankInfo::split64BitValueForMapping(
}

/// Replace the current type each register in \p Regs has with \p NewTy
static void setRegsToType(MachineRegisterInfo &MRI, ArrayRef<unsigned> Regs,
static void setRegsToType(MachineRegisterInfo &MRI, ArrayRef<Register> Regs,
LLT NewTy) {
for (unsigned Reg : Regs) {
assert(MRI.getType(Reg).getSizeInBits() == NewTy.getSizeInBits());
Expand Down Expand Up @@ -445,7 +445,7 @@ void AMDGPURegisterBankInfo::executeInWaterfallLoop(

// Use a set to avoid extra readfirstlanes in the case where multiple operands
// are the same register.
SmallSet<unsigned, 4> SGPROperandRegs;
SmallSet<Register, 4> SGPROperandRegs;
for (unsigned Op : OpIndices) {
assert(MI.getOperand(Op).isUse());
unsigned Reg = MI.getOperand(Op).getReg();
Expand All @@ -459,9 +459,9 @@ void AMDGPURegisterBankInfo::executeInWaterfallLoop(
return;

MachineIRBuilder B(MI);
SmallVector<unsigned, 4> ResultRegs;
SmallVector<unsigned, 4> InitResultRegs;
SmallVector<unsigned, 4> PhiRegs;
SmallVector<Register, 4> ResultRegs;
SmallVector<Register, 4> InitResultRegs;
SmallVector<Register, 4> PhiRegs;
for (MachineOperand &Def : MI.defs()) {
LLT ResTy = MRI.getType(Def.getReg());
const RegisterBank *DefBank = getRegBank(Def.getReg(), MRI, *TRI);
Expand Down Expand Up @@ -575,7 +575,7 @@ void AMDGPURegisterBankInfo::executeInWaterfallLoop(
}
} else {
LLT S32 = LLT::scalar(32);
SmallVector<unsigned, 8> ReadlanePieces;
SmallVector<Register, 8> ReadlanePieces;

// The compares can be done as 64-bit, but the extract needs to be done
// in 32-bit pieces.
Expand Down Expand Up @@ -732,10 +732,10 @@ void AMDGPURegisterBankInfo::applyMappingImpl(

LLT HalfTy = getHalfSizedType(DstTy);

SmallVector<unsigned, 2> DefRegs(OpdMapper.getVRegs(0));
SmallVector<unsigned, 1> Src0Regs(OpdMapper.getVRegs(1));
SmallVector<unsigned, 2> Src1Regs(OpdMapper.getVRegs(2));
SmallVector<unsigned, 2> Src2Regs(OpdMapper.getVRegs(3));
SmallVector<Register, 2> DefRegs(OpdMapper.getVRegs(0));
SmallVector<Register, 1> Src0Regs(OpdMapper.getVRegs(1));
SmallVector<Register, 2> Src1Regs(OpdMapper.getVRegs(2));
SmallVector<Register, 2> Src2Regs(OpdMapper.getVRegs(3));

// All inputs are SGPRs, nothing special to do.
if (DefRegs.empty()) {
Expand Down Expand Up @@ -781,9 +781,9 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
break;

LLT HalfTy = getHalfSizedType(DstTy);
SmallVector<unsigned, 2> DefRegs(OpdMapper.getVRegs(0));
SmallVector<unsigned, 2> Src0Regs(OpdMapper.getVRegs(1));
SmallVector<unsigned, 2> Src1Regs(OpdMapper.getVRegs(2));
SmallVector<Register, 2> DefRegs(OpdMapper.getVRegs(0));
SmallVector<Register, 2> Src0Regs(OpdMapper.getVRegs(1));
SmallVector<Register, 2> Src1Regs(OpdMapper.getVRegs(2));

// All inputs are SGPRs, nothing special to do.
if (DefRegs.empty()) {
Expand Down
3 changes: 2 additions & 1 deletion llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,7 @@
#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H
#define LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H

#include "llvm/CodeGen/Register.h"
#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"

#define GET_REGBANK_DECLARATIONS
Expand Down Expand Up @@ -54,7 +55,7 @@ class AMDGPURegisterBankInfo : public AMDGPUGenRegisterBankInfo {
/// Split 64-bit value \p Reg into two 32-bit halves and populate them into \p
/// Regs. This appropriately sets the regbank of the new registers.
void split64BitValueForMapping(MachineIRBuilder &B,
SmallVector<unsigned, 2> &Regs,
SmallVector<Register, 2> &Regs,
LLT HalfTy,
unsigned Reg) const;

Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -82,7 +82,7 @@ const uint32_t *SIRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
}
}

unsigned SIRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
Register SIRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
const SIFrameLowering *TFI =
MF.getSubtarget<GCNSubtarget>().getFrameLowering();
const SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/R600Packetizer.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -186,8 +186,8 @@ class R600PacketizerList : public VLIWPacketizerList {
// Does MII and MIJ share the same pred_sel ?
int OpI = TII->getOperandIdx(MII->getOpcode(), R600::OpName::pred_sel),
OpJ = TII->getOperandIdx(MIJ->getOpcode(), R600::OpName::pred_sel);
unsigned PredI = (OpI > -1)?MII->getOperand(OpI).getReg():0,
PredJ = (OpJ > -1)?MIJ->getOperand(OpJ).getReg():0;
Register PredI = (OpI > -1)?MII->getOperand(OpI).getReg() : Register(),
PredJ = (OpJ > -1)?MIJ->getOperand(OpJ).getReg() : Register();
if (PredI != PredJ)
return false;
if (SUJ->isSucc(SUI)) {
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/R600RegisterInfo.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -67,7 +67,7 @@ const MCPhysReg *R600RegisterInfo::getCalleeSavedRegs(
return &CalleeSavedReg;
}

unsigned R600RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
Register R600RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
return R600::NoRegister;
}

Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/R600RegisterInfo.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -26,7 +26,7 @@ struct R600RegisterInfo final : public R600GenRegisterInfo {

BitVector getReservedRegs(const MachineFunction &MF) const override;
const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
unsigned getFrameRegister(const MachineFunction &MF) const override;
Register getFrameRegister(const MachineFunction &MF) const override;

/// get the HW encoding for a register's channel.
unsigned getHWRegChan(unsigned reg) const;
Expand Down
10 changes: 5 additions & 5 deletions llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -185,7 +185,7 @@ void SILowerControlFlow::emitIf(MachineInstr &MI) {
assert(SaveExec.getSubReg() == AMDGPU::NoSubRegister &&
Cond.getSubReg() == AMDGPU::NoSubRegister);

unsigned SaveExecReg = SaveExec.getReg();
Register SaveExecReg = SaveExec.getReg();

MachineOperand &ImpDefSCC = MI.getOperand(4);
assert(ImpDefSCC.getReg() == AMDGPU::SCC && ImpDefSCC.isDef());
Expand All @@ -197,7 +197,7 @@ void SILowerControlFlow::emitIf(MachineInstr &MI) {

// Add an implicit def of exec to discourage scheduling VALU after this which
// will interfere with trying to form s_and_saveexec_b64 later.
unsigned CopyReg = SimpleIf ? SaveExecReg
Register CopyReg = SimpleIf ? SaveExecReg
: MRI->createVirtualRegister(BoolRC);
MachineInstr *CopyExec =
BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), CopyReg)
Expand Down Expand Up @@ -266,7 +266,7 @@ void SILowerControlFlow::emitElse(MachineInstr &MI) {
MachineBasicBlock &MBB = *MI.getParent();
const DebugLoc &DL = MI.getDebugLoc();

unsigned DstReg = MI.getOperand(0).getReg();
Register DstReg = MI.getOperand(0).getReg();
assert(MI.getOperand(0).getSubReg() == AMDGPU::NoSubRegister);

bool ExecModified = MI.getOperand(3).getImm() != 0;
Expand All @@ -275,14 +275,14 @@ void SILowerControlFlow::emitElse(MachineInstr &MI) {
// We are running before TwoAddressInstructions, and si_else's operands are
// tied. In order to correctly tie the registers, split this into a copy of
// the src like it does.
unsigned CopyReg = MRI->createVirtualRegister(BoolRC);
Register CopyReg = MRI->createVirtualRegister(BoolRC);
MachineInstr *CopyExec =
BuildMI(MBB, Start, DL, TII->get(AMDGPU::COPY), CopyReg)
.add(MI.getOperand(1)); // Saved EXEC

// This must be inserted before phis and any spill code inserted before the
// else.
unsigned SaveReg = ExecModified ?
Register SaveReg = ExecModified ?
MRI->createVirtualRegister(BoolRC) : DstReg;
MachineInstr *OrSaveExec =
BuildMI(MBB, Start, DL, TII->get(OrSaveExecOpc), SaveReg)
Expand Down
8 changes: 4 additions & 4 deletions llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -721,7 +721,7 @@ bool SIRegisterInfo::spillSGPR(MachineBasicBlock::iterator MI,
if (SpillToSMEM && OnlyToVGPR)
return false;

unsigned FrameReg = getFrameRegister(*MF);
Register FrameReg = getFrameRegister(*MF);

assert(SpillToVGPR || (SuperReg != MFI->getStackPtrOffsetReg() &&
SuperReg != MFI->getFrameOffsetReg() &&
Expand Down Expand Up @@ -914,7 +914,7 @@ bool SIRegisterInfo::restoreSGPR(MachineBasicBlock::iterator MI,
unsigned EltSize = 4;
unsigned ScalarLoadOp;

unsigned FrameReg = getFrameRegister(*MF);
Register FrameReg = getFrameRegister(*MF);

const TargetRegisterClass *RC = getPhysRegClass(SuperReg);
if (SpillToSMEM && isSGPRClass(RC)) {
Expand Down Expand Up @@ -1063,7 +1063,7 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
MachineOperand &FIOp = MI->getOperand(FIOperandNum);
int Index = MI->getOperand(FIOperandNum).getIndex();

unsigned FrameReg = getFrameRegister(*MF);
Register FrameReg = getFrameRegister(*MF);

switch (MI->getOpcode()) {
// SGPR register spill
Expand Down Expand Up @@ -1154,7 +1154,7 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
= MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);

bool IsCopy = MI->getOpcode() == AMDGPU::V_MOV_B32_e32;
unsigned ResultReg = IsCopy ?
Register ResultReg = IsCopy ?
MI->getOperand(0).getReg() :
MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);

Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/SIRegisterInfo.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -70,7 +70,7 @@ class SIRegisterInfo final : public AMDGPURegisterInfo {
return 100;
}

unsigned getFrameRegister(const MachineFunction &MF) const override;
Register getFrameRegister(const MachineFunction &MF) const override;

bool canRealignStack(const MachineFunction &MF) const override;
bool requiresRegisterScavenging(const MachineFunction &Fn) const override;
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/ARC/ARCOptAddrMode.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -424,7 +424,7 @@ bool ARCOptAddrMode::canSinkLoadStoreTo(MachineInstr *Ldst, MachineInstr *To) {
bool IsStore = Ldst->mayStore();
bool IsLoad = Ldst->mayLoad();

unsigned ValReg = IsLoad ? Ldst->getOperand(0).getReg() : 0;
Register ValReg = IsLoad ? Ldst->getOperand(0).getReg() : Register();
for (; MI != ME && MI != End; ++MI) {
if (MI->isDebugValue())
continue;
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/ARC/ARCRegisterInfo.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -186,7 +186,7 @@ void ARCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,

// Special handling of DBG_VALUE instructions.
if (MI.isDebugValue()) {
unsigned FrameReg = getFrameRegister(MF);
Register FrameReg = getFrameRegister(MF);
MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
return;
Expand Down Expand Up @@ -219,7 +219,7 @@ void ARCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
ObjSize, RS, SPAdj);
}

unsigned ARCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
Register ARCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
const ARCFrameLowering *TFI = getFrameLowering(MF);
return TFI->hasFP(MF) ? ARC::FP : ARC::SP;
}
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/ARC/ARCRegisterInfo.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -46,7 +46,7 @@ struct ARCRegisterInfo : public ARCGenRegisterInfo {
CallingConv::ID CC) const override;

// Debug information queries.
unsigned getFrameRegister(const MachineFunction &MF) const override;
Register getFrameRegister(const MachineFunction &MF) const override;

//! Return whether to emit frame moves
static bool needsFrameMoves(const MachineFunction &MF);
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -426,7 +426,7 @@ cannotEliminateFrame(const MachineFunction &MF) const {
|| needsStackRealignment(MF);
}

unsigned
Register
ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
const ARMFrameLowering *TFI = getFrameLowering(MF);
Expand Down Expand Up @@ -786,7 +786,7 @@ ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
int PIdx = MI.findFirstPredOperandIdx();
ARMCC::CondCodes Pred = (PIdx == -1)
? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
Register PredReg = (PIdx == -1) ? Register() : MI.getOperand(PIdx+1).getReg();
if (Offset == 0)
// Must be addrmode4/6.
MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, false);
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -173,7 +173,7 @@ class ARMBaseRegisterInfo : public ARMGenRegisterInfo {
bool cannotEliminateFrame(const MachineFunction &MF) const;

// Debug information queries.
unsigned getFrameRegister(const MachineFunction &MF) const override;
Register getFrameRegister(const MachineFunction &MF) const override;
unsigned getBaseRegister() const { return BasePtr; }

bool isLowRegister(unsigned Reg) const;
Expand Down
24 changes: 12 additions & 12 deletions llvm/lib/Target/ARM/ARMCallLowering.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -151,7 +151,7 @@ struct OutgoingValueHandler : public CallLowering::ValueHandler {
assert(VA.isRegLoc() && "Value should be in reg");
assert(NextVA.isRegLoc() && "Value should be in reg");

unsigned NewRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)),
Register NewRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)),
MRI.createGenericVirtualRegister(LLT::scalar(32))};
MIRBuilder.buildUnmerge(NewRegs, Arg.Reg);

Expand Down Expand Up @@ -232,7 +232,7 @@ void ARMCallLowering::splitToValueTypes(
/// Lower the return value for the already existing \p Ret. This assumes that
/// \p MIRBuilder's insertion point is correct.
bool ARMCallLowering::lowerReturnVal(MachineIRBuilder &MIRBuilder,
const Value *Val, ArrayRef<unsigned> VRegs,
const Value *Val, ArrayRef<Register> VRegs,
MachineInstrBuilder &Ret) const {
if (!Val)
// Nothing to do here.
Expand All @@ -257,9 +257,9 @@ bool ARMCallLowering::lowerReturnVal(MachineIRBuilder &MIRBuilder,
ArgInfo CurArgInfo(VRegs[i], SplitEVTs[i].getTypeForEVT(Ctx));
setArgFlags(CurArgInfo, AttributeList::ReturnIndex, DL, F);

SmallVector<unsigned, 4> Regs;
SmallVector<Register, 4> Regs;
splitToValueTypes(CurArgInfo, SplitVTs, MF,
[&](unsigned Reg) { Regs.push_back(Reg); });
[&](Register Reg) { Regs.push_back(Reg); });
if (Regs.size() > 1)
MIRBuilder.buildUnmerge(Regs, VRegs[i]);
}
Expand All @@ -273,7 +273,7 @@ bool ARMCallLowering::lowerReturnVal(MachineIRBuilder &MIRBuilder,

bool ARMCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
const Value *Val,
ArrayRef<unsigned> VRegs) const {
ArrayRef<Register> VRegs) const {
assert(!Val == VRegs.empty() && "Return value without a vreg");

auto const &ST = MIRBuilder.getMF().getSubtarget<ARMSubtarget>();
Expand Down Expand Up @@ -386,7 +386,7 @@ struct IncomingValueHandler : public CallLowering::ValueHandler {
assert(VA.isRegLoc() && "Value should be in reg");
assert(NextVA.isRegLoc() && "Value should be in reg");

unsigned NewRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)),
Register NewRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)),
MRI.createGenericVirtualRegister(LLT::scalar(32))};

assignValueToReg(NewRegs[0], VA.getLocReg(), VA);
Expand Down Expand Up @@ -421,7 +421,7 @@ struct FormalArgHandler : public IncomingValueHandler {

bool ARMCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
const Function &F,
ArrayRef<unsigned> VRegs) const {
ArrayRef<Register> VRegs) const {
auto &TLI = *getTLI<ARMTargetLowering>();
auto Subtarget = TLI.getSubtarget();

Expand Down Expand Up @@ -453,7 +453,7 @@ bool ARMCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
AssignFn);

SmallVector<ArgInfo, 8> ArgInfos;
SmallVector<unsigned, 4> SplitRegs;
SmallVector<Register, 4> SplitRegs;
unsigned Idx = 0;
for (auto &Arg : F.args()) {
ArgInfo AInfo(VRegs[Idx], Arg.getType());
Expand All @@ -462,7 +462,7 @@ bool ARMCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
SplitRegs.clear();

splitToValueTypes(AInfo, ArgInfos, MF,
[&](unsigned Reg) { SplitRegs.push_back(Reg); });
[&](Register Reg) { SplitRegs.push_back(Reg); });

if (!SplitRegs.empty())
MIRBuilder.buildMerge(VRegs[Idx], SplitRegs);
Expand Down Expand Up @@ -568,7 +568,7 @@ bool ARMCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
if (Arg.Flags.isByVal())
return false;

SmallVector<unsigned, 8> Regs;
SmallVector<Register, 8> Regs;
splitToValueTypes(Arg, ArgInfos, MF,
[&](unsigned Reg) { Regs.push_back(Reg); });

Expand All @@ -589,9 +589,9 @@ bool ARMCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
return false;

ArgInfos.clear();
SmallVector<unsigned, 8> SplitRegs;
SmallVector<Register, 8> SplitRegs;
splitToValueTypes(OrigRet, ArgInfos, MF,
[&](unsigned Reg) { SplitRegs.push_back(Reg); });
[&](Register Reg) { SplitRegs.push_back(Reg); });

auto RetAssignFn = TLI.CCAssignFnForReturn(CallConv, IsVarArg);
CallReturnHandler RetHandler(MIRBuilder, MRI, MIB, RetAssignFn);
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/ARM/ARMCallLowering.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -33,18 +33,18 @@ class ARMCallLowering : public CallLowering {
ARMCallLowering(const ARMTargetLowering &TLI);

bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val,
ArrayRef<unsigned> VRegs) const override;
ArrayRef<Register> VRegs) const override;

bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F,
ArrayRef<unsigned> VRegs) const override;
ArrayRef<Register> VRegs) const override;

bool lowerCall(MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv,
const MachineOperand &Callee, const ArgInfo &OrigRet,
ArrayRef<ArgInfo> OrigArgs) const override;

private:
bool lowerReturnVal(MachineIRBuilder &MIRBuilder, const Value *Val,
ArrayRef<unsigned> VRegs,
ArrayRef<Register> VRegs,
MachineInstrBuilder &Ret) const;

using SplitArgTy = std::function<void(unsigned Reg)>;
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/BPF/BPFRegisterInfo.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -121,6 +121,6 @@ void BPFRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
}
}

unsigned BPFRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
Register BPFRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
return BPF::R10;
}
2 changes: 1 addition & 1 deletion llvm/lib/Target/BPF/BPFRegisterInfo.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -32,7 +32,7 @@ struct BPFRegisterInfo : public BPFGenRegisterInfo {
unsigned FIOperandNum,
RegScavenger *RS = nullptr) const override;

unsigned getFrameRegister(const MachineFunction &MF) const override;
Register getFrameRegister(const MachineFunction &MF) const override;
};
}

Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -254,8 +254,8 @@ static bool isUnsafeToMoveAcross(MachineInstr &MI, unsigned UseReg,
MI.isMetaInstruction();
}

static unsigned UseReg(const MachineOperand& MO) {
return MO.isReg() ? MO.getReg() : 0;
static Register UseReg(const MachineOperand& MO) {
return MO.isReg() ? MO.getReg() : Register();
}

/// isSafeToMoveTogether - Returns true if it is safe to move I1 next to I2 such
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/Hexagon/HexagonGenMux.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -303,8 +303,8 @@ bool HexagonGenMux::genMuxInBlock(MachineBasicBlock &B) {
std::advance(It2, MaxX);
MachineInstr &Def1 = *It1, &Def2 = *It2;
MachineOperand *Src1 = &Def1.getOperand(2), *Src2 = &Def2.getOperand(2);
unsigned SR1 = Src1->isReg() ? Src1->getReg() : 0;
unsigned SR2 = Src2->isReg() ? Src2->getReg() : 0;
Register SR1 = Src1->isReg() ? Src1->getReg() : Register();
Register SR2 = Src2->isReg() ? Src2->getReg() : Register();
bool Failure = false, CanUp = true, CanDown = true;
for (unsigned X = MinX+1; X < MaxX; X++) {
const DefUseInfo &DU = DUM.lookup(X);
Expand Down
1 change: 1 addition & 0 deletions llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -51,6 +51,7 @@ namespace {

RegisterSubReg(unsigned r = 0, unsigned s = 0) : R(r), S(s) {}
RegisterSubReg(const MachineOperand &MO) : R(MO.getReg()), S(MO.getSubReg()) {}
RegisterSubReg(const Register &Reg) : R(Reg), S(0) {}

bool operator== (const RegisterSubReg &Reg) const {
return R == Reg.R && S == Reg.S;
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -286,7 +286,7 @@ unsigned HexagonRegisterInfo::getRARegister() const {
}


unsigned HexagonRegisterInfo::getFrameRegister(const MachineFunction
Register HexagonRegisterInfo::getFrameRegister(const MachineFunction
&MF) const {
const HexagonFrameLowering *TFI = getFrameLowering(MF);
if (TFI->hasFP(MF))
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/Hexagon/HexagonRegisterInfo.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -66,7 +66,7 @@ class HexagonRegisterInfo : public HexagonGenRegisterInfo {

// Debug information queries.
unsigned getRARegister() const;
unsigned getFrameRegister(const MachineFunction &MF) const override;
Register getFrameRegister(const MachineFunction &MF) const override;
unsigned getFrameRegister() const;
unsigned getStackRegister() const;

Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/Lanai/LanaiRegisterInfo.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -258,12 +258,12 @@ bool LanaiRegisterInfo::hasBasePointer(const MachineFunction &MF) const {

unsigned LanaiRegisterInfo::getRARegister() const { return Lanai::RCA; }

unsigned
Register
LanaiRegisterInfo::getFrameRegister(const MachineFunction & /*MF*/) const {
return Lanai::FP;
}

unsigned LanaiRegisterInfo::getBaseRegister() const { return Lanai::R14; }
Register LanaiRegisterInfo::getBaseRegister() const { return Lanai::R14; }

const uint32_t *
LanaiRegisterInfo::getCallPreservedMask(const MachineFunction & /*MF*/,
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/Lanai/LanaiRegisterInfo.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -42,8 +42,8 @@ struct LanaiRegisterInfo : public LanaiGenRegisterInfo {

// Debug information queries.
unsigned getRARegister() const;
unsigned getFrameRegister(const MachineFunction &MF) const override;
unsigned getBaseRegister() const;
Register getFrameRegister(const MachineFunction &MF) const override;
Register getBaseRegister() const;
bool hasBasePointer(const MachineFunction &MF) const;

int getDwarfRegNum(unsigned RegNum, bool IsEH) const;
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/MSP430/MSP430RegisterInfo.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -154,7 +154,7 @@ MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
}

unsigned MSP430RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
Register MSP430RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
const MSP430FrameLowering *TFI = getFrameLowering(MF);
return TFI->hasFP(MF) ? MSP430::FP : MSP430::SP;
}
2 changes: 1 addition & 1 deletion llvm/lib/Target/MSP430/MSP430RegisterInfo.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -37,7 +37,7 @@ struct MSP430RegisterInfo : public MSP430GenRegisterInfo {
RegScavenger *RS = nullptr) const override;

// Debug information queries.
unsigned getFrameRegister(const MachineFunction &MF) const override;
Register getFrameRegister(const MachineFunction &MF) const override;
};

} // end namespace llvm
Expand Down
66 changes: 33 additions & 33 deletions llvm/lib/Target/Mips/MipsCallLowering.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,7 @@ using namespace llvm;
MipsCallLowering::MipsCallLowering(const MipsTargetLowering &TLI)
: CallLowering(&TLI) {}

bool MipsCallLowering::MipsHandler::assign(unsigned VReg, const CCValAssign &VA,
bool MipsCallLowering::MipsHandler::assign(Register VReg, const CCValAssign &VA,
const EVT &VT) {
if (VA.isRegLoc()) {
assignValueToReg(VReg, VA, VT);
Expand All @@ -36,7 +36,7 @@ bool MipsCallLowering::MipsHandler::assign(unsigned VReg, const CCValAssign &VA,
return true;
}

bool MipsCallLowering::MipsHandler::assignVRegs(ArrayRef<unsigned> VRegs,
bool MipsCallLowering::MipsHandler::assignVRegs(ArrayRef<Register> VRegs,
ArrayRef<CCValAssign> ArgLocs,
unsigned ArgLocsStartIndex,
const EVT &VT) {
Expand All @@ -47,14 +47,14 @@ bool MipsCallLowering::MipsHandler::assignVRegs(ArrayRef<unsigned> VRegs,
}

void MipsCallLowering::MipsHandler::setLeastSignificantFirst(
SmallVectorImpl<unsigned> &VRegs) {
SmallVectorImpl<Register> &VRegs) {
if (!MIRBuilder.getMF().getDataLayout().isLittleEndian())
std::reverse(VRegs.begin(), VRegs.end());
}

bool MipsCallLowering::MipsHandler::handle(
ArrayRef<CCValAssign> ArgLocs, ArrayRef<CallLowering::ArgInfo> Args) {
SmallVector<unsigned, 4> VRegs;
SmallVector<Register, 4> VRegs;
unsigned SplitLength;
const Function &F = MIRBuilder.getMF().getFunction();
const DataLayout &DL = F.getParent()->getDataLayout();
Expand Down Expand Up @@ -90,17 +90,17 @@ class IncomingValueHandler : public MipsCallLowering::MipsHandler {
: MipsHandler(MIRBuilder, MRI) {}

private:
void assignValueToReg(unsigned ValVReg, const CCValAssign &VA,
void assignValueToReg(Register ValVReg, const CCValAssign &VA,
const EVT &VT) override;

unsigned getStackAddress(const CCValAssign &VA,
MachineMemOperand *&MMO) override;

void assignValueToAddress(unsigned ValVReg, const CCValAssign &VA) override;
void assignValueToAddress(Register ValVReg, const CCValAssign &VA) override;

bool handleSplit(SmallVectorImpl<unsigned> &VRegs,
bool handleSplit(SmallVectorImpl<Register> &VRegs,
ArrayRef<CCValAssign> ArgLocs, unsigned ArgLocsStartIndex,
unsigned ArgsReg, const EVT &VT) override;
Register ArgsReg, const EVT &VT) override;

virtual void markPhysRegUsed(unsigned PhysReg) {
MIRBuilder.getMBB().addLiveIn(PhysReg);
Expand Down Expand Up @@ -129,7 +129,7 @@ class CallReturnHandler : public IncomingValueHandler {

} // end anonymous namespace

void IncomingValueHandler::assignValueToReg(unsigned ValVReg,
void IncomingValueHandler::assignValueToReg(Register ValVReg,
const CCValAssign &VA,
const EVT &VT) {
const MipsSubtarget &STI =
Expand Down Expand Up @@ -194,22 +194,22 @@ unsigned IncomingValueHandler::getStackAddress(const CCValAssign &VA,
return AddrReg;
}

void IncomingValueHandler::assignValueToAddress(unsigned ValVReg,
void IncomingValueHandler::assignValueToAddress(Register ValVReg,
const CCValAssign &VA) {
if (VA.getLocInfo() == CCValAssign::SExt ||
VA.getLocInfo() == CCValAssign::ZExt ||
VA.getLocInfo() == CCValAssign::AExt) {
unsigned LoadReg = MRI.createGenericVirtualRegister(LLT::scalar(32));
Register LoadReg = MRI.createGenericVirtualRegister(LLT::scalar(32));
buildLoad(LoadReg, VA);
MIRBuilder.buildTrunc(ValVReg, LoadReg);
} else
buildLoad(ValVReg, VA);
}

bool IncomingValueHandler::handleSplit(SmallVectorImpl<unsigned> &VRegs,
bool IncomingValueHandler::handleSplit(SmallVectorImpl<Register> &VRegs,
ArrayRef<CCValAssign> ArgLocs,
unsigned ArgLocsStartIndex,
unsigned ArgsReg, const EVT &VT) {
Register ArgsReg, const EVT &VT) {
if (!assignVRegs(VRegs, ArgLocs, ArgLocsStartIndex, VT))
return false;
setLeastSignificantFirst(VRegs);
Expand All @@ -225,28 +225,28 @@ class OutgoingValueHandler : public MipsCallLowering::MipsHandler {
: MipsHandler(MIRBuilder, MRI), MIB(MIB) {}

private:
void assignValueToReg(unsigned ValVReg, const CCValAssign &VA,
void assignValueToReg(Register ValVReg, const CCValAssign &VA,
const EVT &VT) override;

unsigned getStackAddress(const CCValAssign &VA,
MachineMemOperand *&MMO) override;

void assignValueToAddress(unsigned ValVReg, const CCValAssign &VA) override;
void assignValueToAddress(Register ValVReg, const CCValAssign &VA) override;

bool handleSplit(SmallVectorImpl<unsigned> &VRegs,
bool handleSplit(SmallVectorImpl<Register> &VRegs,
ArrayRef<CCValAssign> ArgLocs, unsigned ArgLocsStartIndex,
unsigned ArgsReg, const EVT &VT) override;
Register ArgsReg, const EVT &VT) override;

unsigned extendRegister(unsigned ValReg, const CCValAssign &VA);
unsigned extendRegister(Register ValReg, const CCValAssign &VA);

MachineInstrBuilder &MIB;
};
} // end anonymous namespace

void OutgoingValueHandler::assignValueToReg(unsigned ValVReg,
void OutgoingValueHandler::assignValueToReg(Register ValVReg,
const CCValAssign &VA,
const EVT &VT) {
unsigned PhysReg = VA.getLocReg();
Register PhysReg = VA.getLocReg();
const MipsSubtarget &STI =
static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget());

Expand Down Expand Up @@ -287,14 +287,14 @@ unsigned OutgoingValueHandler::getStackAddress(const CCValAssign &VA,

LLT p0 = LLT::pointer(0, 32);
LLT s32 = LLT::scalar(32);
unsigned SPReg = MRI.createGenericVirtualRegister(p0);
Register SPReg = MRI.createGenericVirtualRegister(p0);
MIRBuilder.buildCopy(SPReg, Mips::SP);

unsigned OffsetReg = MRI.createGenericVirtualRegister(s32);
Register OffsetReg = MRI.createGenericVirtualRegister(s32);
unsigned Offset = VA.getLocMemOffset();
MIRBuilder.buildConstant(OffsetReg, Offset);

unsigned AddrReg = MRI.createGenericVirtualRegister(p0);
Register AddrReg = MRI.createGenericVirtualRegister(p0);
MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg);

MachinePointerInfo MPO =
Expand All @@ -306,30 +306,30 @@ unsigned OutgoingValueHandler::getStackAddress(const CCValAssign &VA,
return AddrReg;
}

void OutgoingValueHandler::assignValueToAddress(unsigned ValVReg,
void OutgoingValueHandler::assignValueToAddress(Register ValVReg,
const CCValAssign &VA) {
MachineMemOperand *MMO;
unsigned Addr = getStackAddress(VA, MMO);
Register Addr = getStackAddress(VA, MMO);
unsigned ExtReg = extendRegister(ValVReg, VA);
MIRBuilder.buildStore(ExtReg, Addr, *MMO);
}

unsigned OutgoingValueHandler::extendRegister(unsigned ValReg,
unsigned OutgoingValueHandler::extendRegister(Register ValReg,
const CCValAssign &VA) {
LLT LocTy{VA.getLocVT()};
switch (VA.getLocInfo()) {
case CCValAssign::SExt: {
unsigned ExtReg = MRI.createGenericVirtualRegister(LocTy);
Register ExtReg = MRI.createGenericVirtualRegister(LocTy);
MIRBuilder.buildSExt(ExtReg, ValReg);
return ExtReg;
}
case CCValAssign::ZExt: {
unsigned ExtReg = MRI.createGenericVirtualRegister(LocTy);
Register ExtReg = MRI.createGenericVirtualRegister(LocTy);
MIRBuilder.buildZExt(ExtReg, ValReg);
return ExtReg;
}
case CCValAssign::AExt: {
unsigned ExtReg = MRI.createGenericVirtualRegister(LocTy);
Register ExtReg = MRI.createGenericVirtualRegister(LocTy);
MIRBuilder.buildAnyExt(ExtReg, ValReg);
return ExtReg;
}
Expand All @@ -342,10 +342,10 @@ unsigned OutgoingValueHandler::extendRegister(unsigned ValReg,
llvm_unreachable("unable to extend register");
}

bool OutgoingValueHandler::handleSplit(SmallVectorImpl<unsigned> &VRegs,
bool OutgoingValueHandler::handleSplit(SmallVectorImpl<Register> &VRegs,
ArrayRef<CCValAssign> ArgLocs,
unsigned ArgLocsStartIndex,
unsigned ArgsReg, const EVT &VT) {
Register ArgsReg, const EVT &VT) {
MIRBuilder.buildUnmerge(VRegs, ArgsReg);
setLeastSignificantFirst(VRegs);
if (!assignVRegs(VRegs, ArgLocs, ArgLocsStartIndex, VT))
Expand Down Expand Up @@ -396,7 +396,7 @@ static void setLocInfo(SmallVectorImpl<CCValAssign> &ArgLocs,

bool MipsCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
const Value *Val,
ArrayRef<unsigned> VRegs) const {
ArrayRef<Register> VRegs) const {

MachineInstrBuilder Ret = MIRBuilder.buildInstrNoInsert(Mips::RetRA);

Expand Down Expand Up @@ -444,7 +444,7 @@ bool MipsCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,

bool MipsCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
const Function &F,
ArrayRef<unsigned> VRegs) const {
ArrayRef<Register> VRegs) const {

// Quick exit if there aren't any args.
if (F.arg_empty())
Expand Down
18 changes: 9 additions & 9 deletions llvm/lib/Target/Mips/MipsCallLowering.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -34,39 +34,39 @@ class MipsCallLowering : public CallLowering {
ArrayRef<CallLowering::ArgInfo> Args);

protected:
bool assignVRegs(ArrayRef<unsigned> VRegs, ArrayRef<CCValAssign> ArgLocs,
bool assignVRegs(ArrayRef<Register> VRegs, ArrayRef<CCValAssign> ArgLocs,
unsigned ArgLocsStartIndex, const EVT &VT);

void setLeastSignificantFirst(SmallVectorImpl<unsigned> &VRegs);
void setLeastSignificantFirst(SmallVectorImpl<Register> &VRegs);

MachineIRBuilder &MIRBuilder;
MachineRegisterInfo &MRI;

private:
bool assign(unsigned VReg, const CCValAssign &VA, const EVT &VT);
bool assign(Register VReg, const CCValAssign &VA, const EVT &VT);

virtual unsigned getStackAddress(const CCValAssign &VA,
MachineMemOperand *&MMO) = 0;

virtual void assignValueToReg(unsigned ValVReg, const CCValAssign &VA,
virtual void assignValueToReg(Register ValVReg, const CCValAssign &VA,
const EVT &VT) = 0;

virtual void assignValueToAddress(unsigned ValVReg,
virtual void assignValueToAddress(Register ValVReg,
const CCValAssign &VA) = 0;

virtual bool handleSplit(SmallVectorImpl<unsigned> &VRegs,
virtual bool handleSplit(SmallVectorImpl<Register> &VRegs,
ArrayRef<CCValAssign> ArgLocs,
unsigned ArgLocsStartIndex, unsigned ArgsReg,
unsigned ArgLocsStartIndex, Register ArgsReg,
const EVT &VT) = 0;
};

MipsCallLowering(const MipsTargetLowering &TLI);

bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val,
ArrayRef<unsigned> VRegs) const override;
ArrayRef<Register> VRegs) const override;

bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F,
ArrayRef<unsigned> VRegs) const override;
ArrayRef<Register> VRegs) const override;

bool lowerCall(MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv,
const MachineOperand &Callee, const ArgInfo &OrigRet,
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/Mips/MipsRegisterInfo.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -277,7 +277,7 @@ eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset);
}

unsigned MipsRegisterInfo::
Register MipsRegisterInfo::
getFrameRegister(const MachineFunction &MF) const {
const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/Mips/MipsRegisterInfo.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -69,7 +69,7 @@ class MipsRegisterInfo : public MipsGenRegisterInfo {
bool canRealignStack(const MachineFunction &MF) const override;

/// Debug information queries.
unsigned getFrameRegister(const MachineFunction &MF) const override;
Register getFrameRegister(const MachineFunction &MF) const override;

/// Return GPR register class.
virtual const TargetRegisterClass *intRegClass(unsigned Size) const = 0;
Expand Down
16 changes: 8 additions & 8 deletions llvm/lib/Target/Mips/MipsSEISelLowering.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3763,19 +3763,19 @@ MipsSETargetLowering::emitFPEXTEND_PSEUDO(MachineInstr &MI,

const TargetInstrInfo *TII = Subtarget.getInstrInfo();
DebugLoc DL = MI.getDebugLoc();
unsigned Fd = MI.getOperand(0).getReg();
unsigned Ws = MI.getOperand(1).getReg();
Register Fd = MI.getOperand(0).getReg();
Register Ws = MI.getOperand(1).getReg();

MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
const TargetRegisterClass *GPRRC =
IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
unsigned MTC1Opc = IsFGR64onMips64
? Mips::DMTC1
: (IsFGR64onMips32 ? Mips::MTC1_D64 : Mips::MTC1);
unsigned COPYOpc = IsFGR64onMips64 ? Mips::COPY_S_D : Mips::COPY_S_W;
Register COPYOpc = IsFGR64onMips64 ? Mips::COPY_S_D : Mips::COPY_S_W;

unsigned Wtemp = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
unsigned WPHI = Wtemp;
Register Wtemp = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
Register WPHI = Wtemp;

BuildMI(*BB, MI, DL, TII->get(Mips::FEXUPR_W), Wtemp).addReg(Ws);
if (IsFGR64) {
Expand All @@ -3784,15 +3784,15 @@ MipsSETargetLowering::emitFPEXTEND_PSEUDO(MachineInstr &MI,
}

// Perform the safety regclass copy mentioned above.
unsigned Rtemp = RegInfo.createVirtualRegister(GPRRC);
unsigned FPRPHI = IsFGR64onMips32
Register Rtemp = RegInfo.createVirtualRegister(GPRRC);
Register FPRPHI = IsFGR64onMips32
? RegInfo.createVirtualRegister(&Mips::FGR64RegClass)
: Fd;
BuildMI(*BB, MI, DL, TII->get(COPYOpc), Rtemp).addReg(WPHI).addImm(0);
BuildMI(*BB, MI, DL, TII->get(MTC1Opc), FPRPHI).addReg(Rtemp);

if (IsFGR64onMips32) {
unsigned Rtemp2 = RegInfo.createVirtualRegister(GPRRC);
Register Rtemp2 = RegInfo.createVirtualRegister(GPRRC);
BuildMI(*BB, MI, DL, TII->get(Mips::COPY_S_W), Rtemp2)
.addReg(WPHI)
.addImm(1);
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/NVPTX/NVPTXRegisterInfo.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -126,6 +126,6 @@ void NVPTXRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
}

unsigned NVPTXRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
Register NVPTXRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
return NVPTX::VRFrame;
}
2 changes: 1 addition & 1 deletion llvm/lib/Target/NVPTX/NVPTXRegisterInfo.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -42,7 +42,7 @@ class NVPTXRegisterInfo : public NVPTXGenRegisterInfo {
unsigned FIOperandNum,
RegScavenger *RS = nullptr) const override;

unsigned getFrameRegister(const MachineFunction &MF) const override;
Register getFrameRegister(const MachineFunction &MF) const override;

ManagedStringPool *getStrPool() const {
return const_cast<ManagedStringPool *>(&ManagedStrPool);
Expand Down
104 changes: 52 additions & 52 deletions llvm/lib/Target/PowerPC/PPCISelLowering.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2448,7 +2448,7 @@ bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
/// Returns true if we should use a direct load into vector instruction
/// (such as lxsd or lfd), instead of a load into gpr + direct move sequence.
static bool usePartialVectorLoads(SDNode *N, const PPCSubtarget& ST) {

// If there are any other uses other than scalar to vector, then we should
// keep it as a scalar load -> direct move pattern to prevent multiple
// loads.
Expand Down Expand Up @@ -5109,7 +5109,7 @@ PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag, SDValue &Chain,
// We cannot add R2/X2 as an operand here for PATCHPOINT, because there is
// no way to mark dependencies as implicit here.
// We will add the R2/X2 dependency in EmitInstrWithCustomInserter.
if (!isPatchPoint)
if (!isPatchPoint)
Ops.push_back(DAG.getRegister(isPPC64 ? PPC::X2
: PPC::R2, PtrVT));
}
Expand Down Expand Up @@ -7087,7 +7087,7 @@ SDValue PPCTargetLowering::LowerTRUNCATEVector(SDValue Op,
// undefined):
// < MSB1|LSB1, MSB2|LSB2, uu, uu, uu, uu, uu, uu> to
// < LSB1, LSB2, u, u, u, u, u, u, u, u, u, u, u, u, u, u>
//
//
// The same operation in little-endian ordering will be:
// <uu, uu, uu, uu, uu, uu, LSB2|MSB2, LSB1|MSB1> to
// <u, u, u, u, u, u, u, u, u, u, u, u, u, u, LSB2, LSB1>
Expand Down Expand Up @@ -9839,7 +9839,7 @@ SDValue PPCTargetLowering::LowerABS(SDValue Op, SelectionDAG &DAG) const {
BifID = Intrinsic::ppc_altivec_vmaxsh;
else if (VT == MVT::v16i8)
BifID = Intrinsic::ppc_altivec_vmaxsb;

return BuildIntrinsicOp(BifID, X, Y, DAG, dl, VT);
}

Expand Down Expand Up @@ -10119,10 +10119,10 @@ PPCTargetLowering::EmitAtomicBinary(MachineInstr &MI, MachineBasicBlock *BB,
MachineFunction *F = BB->getParent();
MachineFunction::iterator It = ++BB->getIterator();

unsigned dest = MI.getOperand(0).getReg();
unsigned ptrA = MI.getOperand(1).getReg();
unsigned ptrB = MI.getOperand(2).getReg();
unsigned incr = MI.getOperand(3).getReg();
Register dest = MI.getOperand(0).getReg();
Register ptrA = MI.getOperand(1).getReg();
Register ptrB = MI.getOperand(2).getReg();
Register incr = MI.getOperand(3).getReg();
DebugLoc dl = MI.getDebugLoc();

MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
Expand All @@ -10138,7 +10138,7 @@ PPCTargetLowering::EmitAtomicBinary(MachineInstr &MI, MachineBasicBlock *BB,
exitMBB->transferSuccessorsAndUpdatePHIs(BB);

MachineRegisterInfo &RegInfo = F->getRegInfo();
unsigned TmpReg = (!BinOpcode) ? incr :
Register TmpReg = (!BinOpcode) ? incr :
RegInfo.createVirtualRegister( AtomicSize == 8 ? &PPC::G8RCRegClass
: &PPC::GPRCRegClass);

Expand Down Expand Up @@ -10246,20 +10246,20 @@ MachineBasicBlock *PPCTargetLowering::EmitPartwordAtomicBinary(
is64bit ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;

unsigned PtrReg = RegInfo.createVirtualRegister(RC);
unsigned Shift1Reg = RegInfo.createVirtualRegister(GPRC);
unsigned ShiftReg =
Register PtrReg = RegInfo.createVirtualRegister(RC);
Register Shift1Reg = RegInfo.createVirtualRegister(GPRC);
Register ShiftReg =
isLittleEndian ? Shift1Reg : RegInfo.createVirtualRegister(GPRC);
unsigned Incr2Reg = RegInfo.createVirtualRegister(GPRC);
unsigned MaskReg = RegInfo.createVirtualRegister(GPRC);
unsigned Mask2Reg = RegInfo.createVirtualRegister(GPRC);
unsigned Mask3Reg = RegInfo.createVirtualRegister(GPRC);
unsigned Tmp2Reg = RegInfo.createVirtualRegister(GPRC);
unsigned Tmp3Reg = RegInfo.createVirtualRegister(GPRC);
unsigned Tmp4Reg = RegInfo.createVirtualRegister(GPRC);
unsigned TmpDestReg = RegInfo.createVirtualRegister(GPRC);
unsigned Ptr1Reg;
unsigned TmpReg =
Register Incr2Reg = RegInfo.createVirtualRegister(GPRC);
Register MaskReg = RegInfo.createVirtualRegister(GPRC);
Register Mask2Reg = RegInfo.createVirtualRegister(GPRC);
Register Mask3Reg = RegInfo.createVirtualRegister(GPRC);
Register Tmp2Reg = RegInfo.createVirtualRegister(GPRC);
Register Tmp3Reg = RegInfo.createVirtualRegister(GPRC);
Register Tmp4Reg = RegInfo.createVirtualRegister(GPRC);
Register TmpDestReg = RegInfo.createVirtualRegister(GPRC);
Register Ptr1Reg;
Register TmpReg =
(!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(GPRC);

// thisMBB:
Expand Down Expand Up @@ -11061,23 +11061,23 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
is64bit ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;

unsigned PtrReg = RegInfo.createVirtualRegister(RC);
unsigned Shift1Reg = RegInfo.createVirtualRegister(GPRC);
unsigned ShiftReg =
Register PtrReg = RegInfo.createVirtualRegister(RC);
Register Shift1Reg = RegInfo.createVirtualRegister(GPRC);
Register ShiftReg =
isLittleEndian ? Shift1Reg : RegInfo.createVirtualRegister(GPRC);
unsigned NewVal2Reg = RegInfo.createVirtualRegister(GPRC);
unsigned NewVal3Reg = RegInfo.createVirtualRegister(GPRC);
unsigned OldVal2Reg = RegInfo.createVirtualRegister(GPRC);
unsigned OldVal3Reg = RegInfo.createVirtualRegister(GPRC);
unsigned MaskReg = RegInfo.createVirtualRegister(GPRC);
unsigned Mask2Reg = RegInfo.createVirtualRegister(GPRC);
unsigned Mask3Reg = RegInfo.createVirtualRegister(GPRC);
unsigned Tmp2Reg = RegInfo.createVirtualRegister(GPRC);
unsigned Tmp4Reg = RegInfo.createVirtualRegister(GPRC);
unsigned TmpDestReg = RegInfo.createVirtualRegister(GPRC);
unsigned Ptr1Reg;
unsigned TmpReg = RegInfo.createVirtualRegister(GPRC);
unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
Register NewVal2Reg = RegInfo.createVirtualRegister(GPRC);
Register NewVal3Reg = RegInfo.createVirtualRegister(GPRC);
Register OldVal2Reg = RegInfo.createVirtualRegister(GPRC);
Register OldVal3Reg = RegInfo.createVirtualRegister(GPRC);
Register MaskReg = RegInfo.createVirtualRegister(GPRC);
Register Mask2Reg = RegInfo.createVirtualRegister(GPRC);
Register Mask3Reg = RegInfo.createVirtualRegister(GPRC);
Register Tmp2Reg = RegInfo.createVirtualRegister(GPRC);
Register Tmp4Reg = RegInfo.createVirtualRegister(GPRC);
Register TmpDestReg = RegInfo.createVirtualRegister(GPRC);
Register Ptr1Reg;
Register TmpReg = RegInfo.createVirtualRegister(GPRC);
Register ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
// thisMBB:
// ...
// fallthrough --> loopMBB
Expand Down Expand Up @@ -11273,7 +11273,7 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
// Save FPSCR value.
BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), OldFPSCRReg);

// The floating point rounding mode is in the bits 62:63 of FPCSR, and has
// The floating point rounding mode is in the bits 62:63 of FPCSR, and has
// the following settings:
// 00 Round to nearest
// 01 Round to 0
Expand All @@ -11293,7 +11293,7 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,

// Copy register from F8RCRegClass::SrcReg to G8RCRegClass::DestReg
// or copy register from G8RCRegClass::SrcReg to F8RCRegClass::DestReg.
// If the target doesn't have DirectMove, we should use stack to do the
// If the target doesn't have DirectMove, we should use stack to do the
// conversion, because the target doesn't have the instructions like mtvsrd
// or mfvsrd to do this conversion directly.
auto copyRegFromG8RCOrF8RC = [&] (unsigned DestReg, unsigned SrcReg) {
Expand Down Expand Up @@ -11339,8 +11339,8 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
MachineMemOperand::MOLoad, MFI.getObjectSize(FrameIdx),
MFI.getObjectAlignment(FrameIdx));

// Load from the stack where SrcReg is stored, and save to DestReg,
// so we have done the RegClass conversion from RegClass::SrcReg to
// Load from the stack where SrcReg is stored, and save to DestReg,
// so we have done the RegClass conversion from RegClass::SrcReg to
// RegClass::DestReg.
BuildMI(*BB, MI, dl, TII->get(LoadOp), DestReg)
.addImm(0)
Expand All @@ -11350,14 +11350,14 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
};

unsigned OldFPSCRReg = MI.getOperand(0).getReg();

// Save FPSCR value.
BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), OldFPSCRReg);

// When the operand is gprc register, use two least significant bits of the
// register and mtfsf instruction to set the bits 62:63 of FPSCR.
//
// copy OldFPSCRTmpReg, OldFPSCRReg
// register and mtfsf instruction to set the bits 62:63 of FPSCR.
//
// copy OldFPSCRTmpReg, OldFPSCRReg
// (INSERT_SUBREG ExtSrcReg, (IMPLICIT_DEF ImDefReg), SrcOp, 1)
// rldimi NewFPSCRTmpReg, ExtSrcReg, OldFPSCRReg, 0, 62
// copy NewFPSCRReg, NewFPSCRTmpReg
Expand All @@ -11367,7 +11367,7 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
unsigned OldFPSCRTmpReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);

copyRegFromG8RCOrF8RC(OldFPSCRTmpReg, OldFPSCRReg);

unsigned ImDefReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
unsigned ExtSrcReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);

Expand Down Expand Up @@ -13791,9 +13791,9 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
}
case ISD::BUILD_VECTOR:
return DAGCombineBuildVector(N, DCI);
case ISD::ABS:
case ISD::ABS:
return combineABS(N, DCI);
case ISD::VSELECT:
case ISD::VSELECT:
return combineVSelect(N, DCI);
}

Expand Down Expand Up @@ -13891,10 +13891,10 @@ unsigned PPCTargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {

if (!DisableInnermostLoopAlign32) {
// If the nested loop is an innermost loop, prefer to a 32-byte alignment,
// so that we can decrease cache misses and branch-prediction misses.
// so that we can decrease cache misses and branch-prediction misses.
// Actual alignment of the loop will depend on the hotness check and other
// logic in alignBlocks.
if (ML->getLoopDepth() > 1 && ML->getSubLoops().empty())
if (ML->getLoopDepth() > 1 && ML->getSubLoops().empty())
return 5;
}

Expand Down Expand Up @@ -14310,7 +14310,7 @@ bool PPCTargetLowering::isAccessedAsGotIndirect(SDValue GA) const {
if (CModel == CodeModel::Small || CModel == CodeModel::Large)
return true;

// JumpTable and BlockAddress are accessed as got-indirect.
// JumpTable and BlockAddress are accessed as got-indirect.
if (isa<JumpTableSDNode>(GA) || isa<BlockAddressSDNode>(GA))
return true;

Expand Down
16 changes: 8 additions & 8 deletions llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -391,9 +391,9 @@ MachineInstr *PPCInstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
// Swap op1/op2
assert(((OpIdx1 == 1 && OpIdx2 == 2) || (OpIdx1 == 2 && OpIdx2 == 1)) &&
"Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMIo.");
unsigned Reg0 = MI.getOperand(0).getReg();
unsigned Reg1 = MI.getOperand(1).getReg();
unsigned Reg2 = MI.getOperand(2).getReg();
Register Reg0 = MI.getOperand(0).getReg();
Register Reg1 = MI.getOperand(1).getReg();
Register Reg2 = MI.getOperand(2).getReg();
unsigned SubReg1 = MI.getOperand(1).getSubReg();
unsigned SubReg2 = MI.getOperand(2).getSubReg();
bool Reg1IsKill = MI.getOperand(1).isKill();
Expand Down Expand Up @@ -421,7 +421,7 @@ MachineInstr *PPCInstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,

if (NewMI) {
// Create a new instruction.
unsigned Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg();
Register Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg();
bool Reg0IsDead = MI.getOperand(0).isDead();
return BuildMI(MF, MI.getDebugLoc(), MI.getDesc())
.addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
Expand Down Expand Up @@ -2400,7 +2400,7 @@ MachineInstr *PPCInstrInfo::getForwardingDefMI(
return &*It;
}
break;
} else if (It->readsRegister(Reg, &getRegisterInfo()))
} else if (It->readsRegister(Reg, &getRegisterInfo()))
// If we see another use of this reg between the def and the MI,
// we want to flat it so the def isn't deleted.
SeenIntermediateUse = true;
Expand Down Expand Up @@ -3218,7 +3218,7 @@ static void swapMIOperands(MachineInstr &MI, unsigned Op1, unsigned Op2) {
}
}

// Check if the 'MI' that has the index OpNoForForwarding
// Check if the 'MI' that has the index OpNoForForwarding
// meets the requirement described in the ImmInstrInfo.
bool PPCInstrInfo::isUseMIElgibleForForwarding(MachineInstr &MI,
const ImmInstrInfo &III,
Expand Down Expand Up @@ -3264,7 +3264,7 @@ bool PPCInstrInfo::isDefMIElgibleForForwarding(MachineInstr &DefMI,
MachineOperand *&RegMO) const {
unsigned Opc = DefMI.getOpcode();
if (Opc != PPC::ADDItocL && Opc != PPC::ADDI && Opc != PPC::ADDI8)
return false;
return false;

assert(DefMI.getNumOperands() >= 3 &&
"Add inst must have at least three operands");
Expand Down Expand Up @@ -3436,7 +3436,7 @@ bool PPCInstrInfo::transformToImmFormFedByAdd(
// Otherwise, it is Constant Pool Index(CPI) or Global,
// which is relocation in fact. We need to replace the special zero
// register with ImmMO.
// Before that, we need to fixup the target flags for imm.
// Before that, we need to fixup the target flags for imm.
// For some reason, we miss to set the flag for the ImmMO if it is CPI.
if (DefMI.getOpcode() == PPC::ADDItocL)
ImmMO->setTargetFlags(PPCII::MO_TOC_LO);
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1114,7 +1114,7 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true);
}

unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
Register PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
const PPCFrameLowering *TFI = getFrameLowering(MF);

if (!TM.isPPC64())
Expand All @@ -1123,7 +1123,7 @@ unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
return TFI->hasFP(MF) ? PPC::X31 : PPC::X1;
}

unsigned PPCRegisterInfo::getBaseRegister(const MachineFunction &MF) const {
Register PPCRegisterInfo::getBaseRegister(const MachineFunction &MF) const {
const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
if (!hasBasePointer(MF))
return getFrameRegister(MF);
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/PowerPC/PPCRegisterInfo.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -132,10 +132,10 @@ class PPCRegisterInfo : public PPCGenRegisterInfo {
int64_t Offset) const override;

// Debug information queries.
unsigned getFrameRegister(const MachineFunction &MF) const override;
Register getFrameRegister(const MachineFunction &MF) const override;

// Base pointer (stack realignment) support.
unsigned getBaseRegister(const MachineFunction &MF) const;
Register getBaseRegister(const MachineFunction &MF) const;
bool hasBasePointer(const MachineFunction &MF) const;

/// stripRegisterPrefix - This method strips the character prefix from a
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -124,7 +124,7 @@ void RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
}

unsigned RISCVRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
Register RISCVRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
const TargetFrameLowering *TFI = getFrameLowering(MF);
return TFI->hasFP(MF) ? RISCV::X8 : RISCV::X2;
}
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/RISCVRegisterInfo.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -39,7 +39,7 @@ struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
unsigned FIOperandNum,
RegScavenger *RS = nullptr) const override;

unsigned getFrameRegister(const MachineFunction &MF) const override;
Register getFrameRegister(const MachineFunction &MF) const override;

bool requiresRegisterScavenging(const MachineFunction &MF) const override {
return true;
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/Sparc/SparcRegisterInfo.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -212,7 +212,7 @@ SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,

}

unsigned SparcRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
Register SparcRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
return SP::I6;
}

Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/Sparc/SparcRegisterInfo.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -38,7 +38,7 @@ struct SparcRegisterInfo : public SparcGenRegisterInfo {
int SPAdj, unsigned FIOperandNum,
RegScavenger *RS = nullptr) const override;

unsigned getFrameRegister(const MachineFunction &MF) const override;
Register getFrameRegister(const MachineFunction &MF) const override;

bool canRealignStack(const MachineFunction &MF) const override;

Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/SystemZ/SystemZElimCompare.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -525,9 +525,9 @@ bool SystemZElimCompare::fuseCompareOperations(
// SrcReg2 is the register if the source operand is a register,
// 0 if the source operand is immediate, and the base register
// if the source operand is memory (index is not supported).
unsigned SrcReg = Compare.getOperand(0).getReg();
unsigned SrcReg2 =
Compare.getOperand(1).isReg() ? Compare.getOperand(1).getReg() : 0;
Register SrcReg = Compare.getOperand(0).getReg();
Register SrcReg2 =
Compare.getOperand(1).isReg() ? Compare.getOperand(1).getReg() : Register();
MachineBasicBlock::iterator MBBI = Compare, MBBE = Branch;
for (++MBBI; MBBI != MBBE; ++MBBI)
if (MBBI->modifiesRegister(SrcReg, TRI) ||
Expand Down
54 changes: 27 additions & 27 deletions llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6249,7 +6249,7 @@ static MachineBasicBlock *splitBlockBefore(MachineBasicBlock::iterator MI,
}

// Force base value Base into a register before MI. Return the register.
static unsigned forceReg(MachineInstr &MI, MachineOperand &Base,
static Register forceReg(MachineInstr &MI, MachineOperand &Base,
const SystemZInstrInfo *TII) {
if (Base.isReg())
return Base.getReg();
Expand All @@ -6258,7 +6258,7 @@ static unsigned forceReg(MachineInstr &MI, MachineOperand &Base,
MachineFunction &MF = *MBB->getParent();
MachineRegisterInfo &MRI = MF.getRegInfo();

unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
Register Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
BuildMI(*MBB, MI, MI.getDebugLoc(), TII->get(SystemZ::LA), Reg)
.add(Base)
.addImm(0)
Expand Down Expand Up @@ -6542,8 +6542,8 @@ MachineBasicBlock *SystemZTargetLowering::emitAtomicLoadBinary(
MachineOperand Base = earlyUseOperand(MI.getOperand(1));
int64_t Disp = MI.getOperand(2).getImm();
MachineOperand Src2 = earlyUseOperand(MI.getOperand(3));
unsigned BitShift = (IsSubWord ? MI.getOperand(4).getReg() : 0);
unsigned NegBitShift = (IsSubWord ? MI.getOperand(5).getReg() : 0);
Register BitShift = IsSubWord ? MI.getOperand(4).getReg() : Register();
Register NegBitShift = IsSubWord ? MI.getOperand(5).getReg() : Register();
DebugLoc DL = MI.getDebugLoc();
if (IsSubWord)
BitSize = MI.getOperand(6).getImm();
Expand All @@ -6561,12 +6561,12 @@ MachineBasicBlock *SystemZTargetLowering::emitAtomicLoadBinary(
assert(LOpcode && CSOpcode && "Displacement out of range");

// Create virtual registers for temporary results.
unsigned OrigVal = MRI.createVirtualRegister(RC);
unsigned OldVal = MRI.createVirtualRegister(RC);
unsigned NewVal = (BinOpcode || IsSubWord ?
Register OrigVal = MRI.createVirtualRegister(RC);
Register OldVal = MRI.createVirtualRegister(RC);
Register NewVal = (BinOpcode || IsSubWord ?
MRI.createVirtualRegister(RC) : Src2.getReg());
unsigned RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
unsigned RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
Register RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
Register RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);

// Insert a basic block for the main loop.
MachineBasicBlock *StartMBB = MBB;
Expand Down Expand Up @@ -6659,9 +6659,9 @@ MachineBasicBlock *SystemZTargetLowering::emitAtomicLoadMinMax(
unsigned Dest = MI.getOperand(0).getReg();
MachineOperand Base = earlyUseOperand(MI.getOperand(1));
int64_t Disp = MI.getOperand(2).getImm();
unsigned Src2 = MI.getOperand(3).getReg();
unsigned BitShift = (IsSubWord ? MI.getOperand(4).getReg() : 0);
unsigned NegBitShift = (IsSubWord ? MI.getOperand(5).getReg() : 0);
Register Src2 = MI.getOperand(3).getReg();
Register BitShift = (IsSubWord ? MI.getOperand(4).getReg() : Register());
Register NegBitShift = (IsSubWord ? MI.getOperand(5).getReg() : Register());
DebugLoc DL = MI.getDebugLoc();
if (IsSubWord)
BitSize = MI.getOperand(6).getImm();
Expand All @@ -6679,12 +6679,12 @@ MachineBasicBlock *SystemZTargetLowering::emitAtomicLoadMinMax(
assert(LOpcode && CSOpcode && "Displacement out of range");

// Create virtual registers for temporary results.
unsigned OrigVal = MRI.createVirtualRegister(RC);
unsigned OldVal = MRI.createVirtualRegister(RC);
unsigned NewVal = MRI.createVirtualRegister(RC);
unsigned RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
unsigned RotatedAltVal = (IsSubWord ? MRI.createVirtualRegister(RC) : Src2);
unsigned RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
Register OrigVal = MRI.createVirtualRegister(RC);
Register OldVal = MRI.createVirtualRegister(RC);
Register NewVal = MRI.createVirtualRegister(RC);
Register RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
Register RotatedAltVal = (IsSubWord ? MRI.createVirtualRegister(RC) : Src2);
Register RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);

// Insert 3 basic blocks for the loop.
MachineBasicBlock *StartMBB = MBB;
Expand Down Expand Up @@ -6967,22 +6967,22 @@ MachineBasicBlock *SystemZTargetLowering::emitMemMemWrapper(
if (MI.getNumExplicitOperands() > 5) {
bool HaveSingleBase = DestBase.isIdenticalTo(SrcBase);

uint64_t StartCountReg = MI.getOperand(5).getReg();
uint64_t StartSrcReg = forceReg(MI, SrcBase, TII);
uint64_t StartDestReg = (HaveSingleBase ? StartSrcReg :
Register StartCountReg = MI.getOperand(5).getReg();
Register StartSrcReg = forceReg(MI, SrcBase, TII);
Register StartDestReg = (HaveSingleBase ? StartSrcReg :
forceReg(MI, DestBase, TII));

const TargetRegisterClass *RC = &SystemZ::ADDR64BitRegClass;
uint64_t ThisSrcReg = MRI.createVirtualRegister(RC);
uint64_t ThisDestReg = (HaveSingleBase ? ThisSrcReg :
Register ThisSrcReg = MRI.createVirtualRegister(RC);
Register ThisDestReg = (HaveSingleBase ? ThisSrcReg :
MRI.createVirtualRegister(RC));
uint64_t NextSrcReg = MRI.createVirtualRegister(RC);
uint64_t NextDestReg = (HaveSingleBase ? NextSrcReg :
Register NextSrcReg = MRI.createVirtualRegister(RC);
Register NextDestReg = (HaveSingleBase ? NextSrcReg :
MRI.createVirtualRegister(RC));

RC = &SystemZ::GR64BitRegClass;
uint64_t ThisCountReg = MRI.createVirtualRegister(RC);
uint64_t NextCountReg = MRI.createVirtualRegister(RC);
Register ThisCountReg = MRI.createVirtualRegister(RC);
Register NextCountReg = MRI.createVirtualRegister(RC);

MachineBasicBlock *StartMBB = MBB;
MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
Expand Down
8 changes: 4 additions & 4 deletions llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1179,13 +1179,13 @@ MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl(
MemOpcode = -1;
else {
assert(NumOps == 3 && "Expected two source registers.");
unsigned DstReg = MI.getOperand(0).getReg();
unsigned DstPhys =
Register DstReg = MI.getOperand(0).getReg();
Register DstPhys =
(TRI->isVirtualRegister(DstReg) ? VRM->getPhys(DstReg) : DstReg);
unsigned SrcReg = (OpNum == 2 ? MI.getOperand(1).getReg()
Register SrcReg = (OpNum == 2 ? MI.getOperand(1).getReg()
: ((OpNum == 1 && MI.isCommutable())
? MI.getOperand(2).getReg()
: 0));
: Register()));
if (DstPhys && !SystemZ::GRH32BitRegClass.contains(DstPhys) && SrcReg &&
TRI->isVirtualRegister(SrcReg) && DstPhys == VRM->getPhys(SrcReg))
NeedsCommute = (OpNum == 1);
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -164,8 +164,8 @@ SystemZRegisterInfo::getRegAllocationHints(unsigned VirtReg,
continue;

auto tryAddHint = [&](const MachineOperand *MO) -> void {
unsigned Reg = MO->getReg();
unsigned PhysReg = isPhysicalRegister(Reg) ? Reg : VRM->getPhys(Reg);
Register Reg = MO->getReg();
Register PhysReg = isPhysicalRegister(Reg) ? Reg : VRM->getPhys(Reg);
if (PhysReg) {
if (MO->getSubReg())
PhysReg = getSubReg(PhysReg, MO->getSubReg());
Expand Down Expand Up @@ -399,7 +399,7 @@ bool SystemZRegisterInfo::shouldCoalesce(MachineInstr *MI,
return true;
}

unsigned
Register
SystemZRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
const SystemZFrameLowering *TFI = getFrameLowering(MF);
return TFI->hasFP(MF) ? SystemZ::R11D : SystemZ::R15D;
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/SystemZ/SystemZRegisterInfo.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -83,7 +83,7 @@ struct SystemZRegisterInfo : public SystemZGenRegisterInfo {
const TargetRegisterClass *NewRC,
LiveIntervals &LIS) const override;

unsigned getFrameRegister(const MachineFunction &MF) const override;
Register getFrameRegister(const MachineFunction &MF) const override;
};

} // end namespace llvm
Expand Down
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