18 changes: 0 additions & 18 deletions llvm/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -12,8 +12,6 @@
entry:
ret void
}
@var = global i8 0
define i8* @test_global() { ret i8* undef }
...

---
Expand Down Expand Up @@ -84,19 +82,3 @@ body: |
%3:_(s32) = G_ANYEXT %2
$w0 = COPY %3
...

---
name: test_global
registers:
- { id: 0, class: _ }
body: |
bb.0:
; CHECK-LABEL: name: test_global
; CHECK: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var
; CHECK: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[GV]](p0)
; CHECK: $x0 = COPY [[PTRTOINT]](s64)
%0(p0) = G_GLOBAL_VALUE @var
%1:_(s64) = G_PTRTOINT %0
$x0 = COPY %1
...
38 changes: 38 additions & 0 deletions llvm/test/CodeGen/AArch64/GlobalISel/legalize-global.mir
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Original file line number Diff line number Diff line change
@@ -0,0 +1,38 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -run-pass=legalizer %s -o - | FileCheck %s
# RUN: llc -O0 -run-pass=legalizer --relocation-model=pic %s -o - | FileCheck %s --check-prefix=PIC
# RUN: llc -O0 -run-pass=legalizer --code-model=large %s -o - | FileCheck %s --check-prefix=CMLARGE

--- |
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "aarch64--"
@var = external global i8
define i8* @test_global() { ret i8* undef }
...
---
name: test_global
registers:
- { id: 0, class: _ }
body: |
bb.0:
; We don't want to lower to G_ADD_LOW when we need a GOT access, or when the code
; model isn't 'Small'.
; CHECK-LABEL: name: test_global
; CHECK: [[ADRP:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @var
; CHECK: [[ADD_LOW:%[0-9]+]]:_(p0) = G_ADD_LOW [[ADRP]](p0), target-flags(aarch64-pageoff, aarch64-nc) @var
; CHECK: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[ADD_LOW]](p0)
; CHECK: $x0 = COPY [[PTRTOINT]](s64)
; PIC-LABEL: name: test_global
; PIC: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var
; PIC: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[GV]](p0)
; PIC: $x0 = COPY [[PTRTOINT]](s64)
; CMLARGE-LABEL: name: test_global
; CMLARGE: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var
; CMLARGE: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[GV]](p0)
; CMLARGE: $x0 = COPY [[PTRTOINT]](s64)
%0(p0) = G_GLOBAL_VALUE @var
%1:_(s64) = G_PTRTOINT %0
$x0 = COPY %1
...
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -73,8 +73,8 @@
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
#
# DEBUG-NEXT: G_GLOBAL_VALUE (opcode {{[0-9]+}}): 1 type index, 0 imm indices
# DEBUG-NEXT: .. the first uncovered type index: 1, OK
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
#
# DEBUG-NEXT: G_EXTRACT (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
Expand Down
88 changes: 88 additions & 0 deletions llvm/test/CodeGen/AArch64/GlobalISel/localizer.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -34,6 +34,22 @@
store i32 3, i32* @var1, align 4
br label %if.end

if.end:
ret i32 0
}
define i32 @adrp_add() {
entry:
%0 = load i32, i32* @var1, align 4
%cmp = icmp eq i32 %0, 1
br i1 %cmp, label %if.then, label %if.end

if.then:
store i32 2, i32* @var2, align 4
store i32 3, i32* @var1, align 4
store i32 2, i32* @var3, align 4
store i32 3, i32* @var1, align 4
br label %if.end

if.end:
ret i32 0
}
Expand Down Expand Up @@ -390,6 +406,78 @@ body: |
$w0 = COPY %8(s32)
RET_ReallyLR implicit $w0
...
---
name: adrp_add
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: adrp_add
; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK: [[ADRP:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @var1
; CHECK: %addlow1:gpr(p0) = G_ADD_LOW [[ADRP]](p0), target-flags(aarch64-pageoff, aarch64-nc) @var1
; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 2
; CHECK: [[ADRP1:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @var2
; CHECK: %addlow2:gpr(p0) = G_ADD_LOW [[ADRP1]](p0), target-flags(aarch64-pageoff, aarch64-nc) @var2
; CHECK: [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 3
; CHECK: [[ADRP2:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @var3
; CHECK: %addlow3:gpr(p0) = G_ADD_LOW [[ADRP2]](p0), target-flags(aarch64-pageoff, aarch64-nc) @var3
; CHECK: [[C2:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0
; CHECK: [[LOAD:%[0-9]+]]:gpr(s32) = G_LOAD [[ADRP]](p0) :: (load 4 from @var1)
; CHECK: [[C3:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
; CHECK: [[ICMP:%[0-9]+]]:gpr(s32) = G_ICMP intpred(eq), [[LOAD]](s32), [[C3]]
; CHECK: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: G_BRCOND [[TRUNC]](s1), %bb.1
; CHECK: G_BR %bb.2
; CHECK: bb.1.if.then:
; CHECK: successors: %bb.2(0x80000000)
; CHECK: [[ADRP3:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @var2
; CHECK: [[ADD_LOW:%[0-9]+]]:gpr(p0) = G_ADD_LOW [[ADRP3]](p0), target-flags(aarch64-pageoff, aarch64-nc) @var2
; CHECK: [[C4:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 2
; CHECK: G_STORE [[C4]](s32), [[ADD_LOW]](p0) :: (store 4 into @var2)
; CHECK: [[C5:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 3
; CHECK: [[ADRP4:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @var1
; CHECK: [[ADD_LOW1:%[0-9]+]]:gpr(p0) = G_ADD_LOW [[ADRP4]](p0), target-flags(aarch64-pageoff, aarch64-nc) @var1
; CHECK: G_STORE [[C5]](s32), [[ADD_LOW1]](p0) :: (store 4 into @var1)
; CHECK: [[ADRP5:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @var3
; CHECK: [[ADD_LOW2:%[0-9]+]]:gpr(p0) = G_ADD_LOW [[ADRP5]](p0), target-flags(aarch64-pageoff, aarch64-nc) @var3
; CHECK: G_STORE [[C4]](s32), [[ADD_LOW2]](p0) :: (store 4 into @var3)
; CHECK: G_STORE [[C5]](s32), [[ADD_LOW1]](p0) :: (store 4 into @var1)
; CHECK: bb.2.if.end:
; CHECK: [[C6:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0
; CHECK: $w0 = COPY [[C6]](s32)
; CHECK: RET_ReallyLR implicit $w0
; Some of these instructions are dead.
bb.1.entry:
%1:gpr64(p0) = ADRP target-flags(aarch64-page) @var1
%addlow1:gpr(p0) = G_ADD_LOW %1(p0), target-flags(aarch64-pageoff, aarch64-nc) @var1
%2:gpr(s32) = G_CONSTANT i32 1
%4:gpr(s32) = G_CONSTANT i32 2
%5:gpr64(p0) = ADRP target-flags(aarch64-page) @var2
%addlow2:gpr(p0) = G_ADD_LOW %5(p0), target-flags(aarch64-pageoff, aarch64-nc) @var2
%6:gpr(s32) = G_CONSTANT i32 3
%7:gpr64(p0) = ADRP target-flags(aarch64-page) @var3
%addlow3:gpr(p0) = G_ADD_LOW %7(p0), target-flags(aarch64-pageoff, aarch64-nc) @var3
%8:gpr(s32) = G_CONSTANT i32 0
%0:gpr(s32) = G_LOAD %1(p0) :: (load 4 from @var1)
%9:gpr(s32) = G_ICMP intpred(eq), %0(s32), %2
%3:gpr(s1) = G_TRUNC %9(s32)
G_BRCOND %3(s1), %bb.2
G_BR %bb.3
bb.2.if.then:
G_STORE %4(s32), %addlow2(p0) :: (store 4 into @var2)
G_STORE %6(s32), %addlow1(p0) :: (store 4 into @var1)
G_STORE %4(s32), %addlow3(p0) :: (store 4 into @var3)
G_STORE %6(s32), %addlow1(p0) :: (store 4 into @var1)
bb.3.if.end:
$w0 = COPY %8(s32)
RET_ReallyLR implicit $w0
...
---
name: test_inttoptr
Expand Down
13 changes: 12 additions & 1 deletion llvm/test/CodeGen/AArch64/arm64-custom-call-saved-reg.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -52,7 +52,7 @@
; RUN: -mattr=+call-saved-x18 \
; RUN: -global-isel \
; RUN: -o - %s | FileCheck %s \
; RUN: --check-prefix=CHECK-SAVED-ALL
; RUN: --check-prefix=CHECK-SAVED-ALL-GISEL

; Used to exhaust the supply of GPRs.
@var = global [30 x i64] zeroinitializer
Expand Down Expand Up @@ -124,6 +124,17 @@ define void @caller() {
; CHECK-SAVED-ALL-DAG: ldr x15
; CHECK-SAVED-ALL-DAG: ldr x18

; CHECK-SAVED-ALL-GISEL: adrp x16, var
; CHECK-SAVED-ALL-GISEL-DAG: ldr x8
; CHECK-SAVED-ALL-GISEL-DAG: ldr x9
; CHECK-SAVED-ALL-GISEL-DAG: ldr x10
; CHECK-SAVED-ALL-GISEL-DAG: ldr x11
; CHECK-SAVED-ALL-GISEL-DAG: ldr x12
; CHECK-SAVED-ALL-GISEL-DAG: ldr x13
; CHECK-SAVED-ALL-GISEL-DAG: ldr x14
; CHECK-SAVED-ALL-GISEL-DAG: ldr x15
; CHECK-SAVED-ALL-GISEL-DAG: ldr x18

call void @callee()
; CHECK: bl callee

Expand Down
20 changes: 8 additions & 12 deletions llvm/test/CodeGen/AArch64/arm64-ldxr-stxr.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -41,12 +41,10 @@ define void @test_load_i8(i8* %addr) {
; CHECK-NOT: and
; CHECK: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]

; FIXME: GlobalISel doesn't fold ands/adds into load/store addressing modes
; right now/ So, we won't get the :lo12:var.
; GISEL-LABEL: test_load_i8:
; GISEL: ldxrb w[[LOADVAL:[0-9]+]], [x0]
; GISEL-NOT: uxtb
; GISEL: str x[[LOADVAL]], [{{x[0-9]+}}]
; GISEL: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
%val = call i64 @llvm.aarch64.ldxr.p0i8(i8* %addr)
%shortval = trunc i64 %val to i8
%extval = zext i8 %shortval to i64
Expand All @@ -65,7 +63,7 @@ define void @test_load_i16(i16* %addr) {
; GISEL-LABEL: test_load_i16:
; GISEL: ldxrh w[[LOADVAL:[0-9]+]], [x0]
; GISEL-NOT: uxtb
; GISEL: str x[[LOADVAL]], [{{x[0-9]+}}]
; GISEL: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
%val = call i64 @llvm.aarch64.ldxr.p0i16(i16* %addr)
%shortval = trunc i64 %val to i16
%extval = zext i16 %shortval to i64
Expand All @@ -84,7 +82,7 @@ define void @test_load_i32(i32* %addr) {
; GISEL-LABEL: test_load_i32:
; GISEL: ldxr w[[LOADVAL:[0-9]+]], [x0]
; GISEL-NOT: uxtb
; GISEL: str x[[LOADVAL]], [{{x[0-9]+}}]
; GISEL: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
%val = call i64 @llvm.aarch64.ldxr.p0i32(i32* %addr)
%shortval = trunc i64 %val to i32
%extval = zext i32 %shortval to i64
Expand All @@ -101,7 +99,7 @@ define void @test_load_i64(i64* %addr) {
; GISEL-LABEL: test_load_i64:
; GISEL: ldxr x[[LOADVAL:[0-9]+]], [x0]
; GISEL-NOT: uxtb
; GISEL: str x[[LOADVAL]], [{{x[0-9]+}}]
; GISEL: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
%val = call i64 @llvm.aarch64.ldxr.p0i64(i64* %addr)
store i64 %val, i64* @var, align 8
ret void
Expand Down Expand Up @@ -218,11 +216,9 @@ define void @test_load_acquire_i8(i8* %addr) {
; CHECK-NOT: and
; CHECK: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]

; FIXME: GlobalISel doesn't fold ands/adds into load/store addressing modes
; right now/ So, we won't get the :lo12:var.
; GISEL-LABEL: test_load_acquire_i8:
; GISEL: ldaxrb w[[LOADVAL:[0-9]+]], [x0]
; GISEL-DAG: str x[[LOADVAL]], [{{x[0-9]+}}]
; GISEL-DAG: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
%val = call i64 @llvm.aarch64.ldaxr.p0i8(i8* %addr)
%shortval = trunc i64 %val to i8
%extval = zext i8 %shortval to i64
Expand All @@ -240,7 +236,7 @@ define void @test_load_acquire_i16(i16* %addr) {

; GISEL-LABEL: test_load_acquire_i16:
; GISEL: ldaxrh w[[LOADVAL:[0-9]+]], [x0]
; GISEL: str x[[LOADVAL]], [{{x[0-9]+}}]
; GISEL: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
%val = call i64 @llvm.aarch64.ldaxr.p0i16(i16* %addr)
%shortval = trunc i64 %val to i16
%extval = zext i16 %shortval to i64
Expand All @@ -258,7 +254,7 @@ define void @test_load_acquire_i32(i32* %addr) {

; GISEL-LABEL: test_load_acquire_i32:
; GISEL: ldaxr w[[LOADVAL:[0-9]+]], [x0]
; GISEL: str x[[LOADVAL]], [{{x[0-9]+}}]
; GISEL: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
%val = call i64 @llvm.aarch64.ldaxr.p0i32(i32* %addr)
%shortval = trunc i64 %val to i32
%extval = zext i32 %shortval to i64
Expand All @@ -274,7 +270,7 @@ define void @test_load_acquire_i64(i64* %addr) {

; GISEL-LABEL: test_load_acquire_i64:
; GISEL: ldaxr x[[LOADVAL:[0-9]+]], [x0]
; GISEL: str x[[LOADVAL]], [{{x[0-9]+}}]
; GISEL: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
%val = call i64 @llvm.aarch64.ldaxr.p0i64(i64* %addr)
store i64 %val, i64* @var, align 8
ret void
Expand Down
3 changes: 1 addition & 2 deletions llvm/test/CodeGen/AArch64/dllimport.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -28,8 +28,7 @@ define i32 @get_ext() {
; DAG-ISEL: ldr w0, [x8, ext]
; FAST-ISEL: add x8, x8, ext
; FAST-ISEL: ldr w0, [x8]
; GLOBAL-ISEL-FALLBACK: add x8, x8, ext
; GLOBAL-ISEL-FALLBACK: ldr w0, [x8]
; GLOBAL-ISEL-FALLBACK: ldr w0, [x8, ext]
; CHECK: ret

define i32* @get_var_pointer() {
Expand Down
56 changes: 56 additions & 0 deletions llvm/test/CodeGen/AArch64/loh-use-between-adrp-add.mir
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Original file line number Diff line number Diff line change
@@ -0,0 +1,56 @@
# RUN: llc -o - %s -mtriple=aarch64-apple-ios -run-pass=aarch64-collect-loh -debug-only=aarch64-collect-loh 2>&1 | FileCheck %s
# REQUIRES: asserts
--- |
@rrdpb = local_unnamed_addr global i32 zeroinitializer, align 8

define internal void @test_use_between() {
ret void
}
define internal void @test_no_use_between() {
ret void
}

...
# CHECK-LABEL: ********** AArch64 Collect LOH **********
# CHECK-LABEL: Looking in function test_use_between
# Check that we don't have an AdrpAdd LOH because there's a use of the ADD defreg
# in between the two.
# CHECK-NOT: MCLOH_AdrpAdd

# CHECK-LABEL: Looking in function test_no_use_between
# CHECK: MCLOH_AdrpAdd
---
name: test_use_between
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$x11', virtual-reg: '' }
- { reg: '$x12', virtual-reg: '' }
body: |
bb.0:
liveins: $x11, $x12
renamable $x15 = ADRP target-flags(aarch64-page) @rrdpb
STRXui renamable $x12, killed renamable $x11, 1 :: (store 8)
renamable $x11 = ADDXri killed renamable $x15, target-flags(aarch64-pageoff, aarch64-nc) @rrdpb, 0
STRXui renamable $x11, killed renamable $x11, 0
RET undef $lr
...

---
name: test_no_use_between
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$x11', virtual-reg: '' }
- { reg: '$x12', virtual-reg: '' }
body: |
bb.0:
liveins: $x11, $x12
STRXui renamable $x12, killed renamable $x11, 1 :: (store 8)
renamable $x15 = ADRP target-flags(aarch64-page) @rrdpb
renamable $x11 = ADDXri killed renamable $x15, target-flags(aarch64-pageoff, aarch64-nc) @rrdpb, 0
STRXui renamable $x11, killed renamable $x11, 0
RET undef $lr
...