| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,31 @@ | ||
| // RUN: %check_clang_tidy %s bugprone-return-const-ref-from-parameter %t | ||
|
|
||
| using T = int; | ||
| using TConst = int const; | ||
| using TConstRef = int const&; | ||
|
|
||
| namespace invalid { | ||
|
|
||
| int const &f1(int const &a) { return a; } | ||
| // CHECK-MESSAGES: :[[@LINE-1]]:38: warning: returning a constant reference parameter | ||
|
|
||
| int const &f2(T const &a) { return a; } | ||
| // CHECK-MESSAGES: :[[@LINE-1]]:36: warning: returning a constant reference parameter | ||
|
|
||
| int const &f3(TConstRef a) { return a; } | ||
| // CHECK-MESSAGES: :[[@LINE-1]]:37: warning: returning a constant reference parameter | ||
|
|
||
| int const &f4(TConst &a) { return a; } | ||
| // CHECK-MESSAGES: :[[@LINE-1]]:35: warning: returning a constant reference parameter | ||
|
|
||
| } // namespace invalid | ||
|
|
||
| namespace valid { | ||
|
|
||
| int const &f1(int &a) { return a; } | ||
|
|
||
| int const &f2(int &&a) { return a; } | ||
|
|
||
| int f1(int const &a) { return a; } | ||
|
|
||
| } // namespace valid |
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,132 @@ | ||
| // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 | ||
| // REQUIRES: riscv-registered-target | ||
| // RUN: %clang_cc1 -triple riscv64 -target-feature +v \ | ||
| // RUN: -target-feature +experimental-zvfbfmin \ | ||
| // RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ | ||
| // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ | ||
| // RUN: FileCheck --check-prefix=CHECK-RV64 %s | ||
|
|
||
| #include <riscv_vector.h> | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vle16_v_bf16mf4( | ||
| // CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vle.nxv1bf16.i64(<vscale x 1 x bfloat> poison, ptr [[RS1]], i64 [[VL]]) | ||
| // CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]] | ||
| // | ||
| vbfloat16mf4_t test_vle16_v_bf16mf4(const __bf16 *rs1, size_t vl) { | ||
| return __riscv_vle16_v_bf16mf4(rs1, vl); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vle16_v_bf16mf2( | ||
| // CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vle.nxv2bf16.i64(<vscale x 2 x bfloat> poison, ptr [[RS1]], i64 [[VL]]) | ||
| // CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]] | ||
| // | ||
| vbfloat16mf2_t test_vle16_v_bf16mf2(const __bf16 *rs1, size_t vl) { | ||
| return __riscv_vle16_v_bf16mf2(rs1, vl); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vle16_v_bf16m1( | ||
| // CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vle.nxv4bf16.i64(<vscale x 4 x bfloat> poison, ptr [[RS1]], i64 [[VL]]) | ||
| // CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]] | ||
| // | ||
| vbfloat16m1_t test_vle16_v_bf16m1(const __bf16 *rs1, size_t vl) { | ||
| return __riscv_vle16_v_bf16m1(rs1, vl); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vle16_v_bf16m2( | ||
| // CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vle.nxv8bf16.i64(<vscale x 8 x bfloat> poison, ptr [[RS1]], i64 [[VL]]) | ||
| // CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]] | ||
| // | ||
| vbfloat16m2_t test_vle16_v_bf16m2(const __bf16 *rs1, size_t vl) { | ||
| return __riscv_vle16_v_bf16m2(rs1, vl); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vle16_v_bf16m4( | ||
| // CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vle.nxv16bf16.i64(<vscale x 16 x bfloat> poison, ptr [[RS1]], i64 [[VL]]) | ||
| // CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]] | ||
| // | ||
| vbfloat16m4_t test_vle16_v_bf16m4(const __bf16 *rs1, size_t vl) { | ||
| return __riscv_vle16_v_bf16m4(rs1, vl); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 32 x bfloat> @test_vle16_v_bf16m8( | ||
| // CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.riscv.vle.nxv32bf16.i64(<vscale x 32 x bfloat> poison, ptr [[RS1]], i64 [[VL]]) | ||
| // CHECK-RV64-NEXT: ret <vscale x 32 x bfloat> [[TMP0]] | ||
| // | ||
| vbfloat16m8_t test_vle16_v_bf16m8(const __bf16 *rs1, size_t vl) { | ||
| return __riscv_vle16_v_bf16m8(rs1, vl); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vle16_v_bf16mf4_m( | ||
| // CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vle.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, ptr [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3) | ||
| // CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]] | ||
| // | ||
| vbfloat16mf4_t test_vle16_v_bf16mf4_m(vbool64_t vm, const __bf16 *rs1, | ||
| size_t vl) { | ||
| return __riscv_vle16_v_bf16mf4_m(vm, rs1, vl); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vle16_v_bf16mf2_m( | ||
| // CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vle.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, ptr [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3) | ||
| // CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]] | ||
| // | ||
| vbfloat16mf2_t test_vle16_v_bf16mf2_m(vbool32_t vm, const __bf16 *rs1, | ||
| size_t vl) { | ||
| return __riscv_vle16_v_bf16mf2_m(vm, rs1, vl); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vle16_v_bf16m1_m( | ||
| // CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vle.mask.nxv4bf16.i64(<vscale x 4 x bfloat> poison, ptr [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3) | ||
| // CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]] | ||
| // | ||
| vbfloat16m1_t test_vle16_v_bf16m1_m(vbool16_t vm, const __bf16 *rs1, | ||
| size_t vl) { | ||
| return __riscv_vle16_v_bf16m1_m(vm, rs1, vl); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vle16_v_bf16m2_m( | ||
| // CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vle.mask.nxv8bf16.i64(<vscale x 8 x bfloat> poison, ptr [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3) | ||
| // CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]] | ||
| // | ||
| vbfloat16m2_t test_vle16_v_bf16m2_m(vbool8_t vm, const __bf16 *rs1, size_t vl) { | ||
| return __riscv_vle16_v_bf16m2_m(vm, rs1, vl); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vle16_v_bf16m4_m( | ||
| // CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vle.mask.nxv16bf16.i64(<vscale x 16 x bfloat> poison, ptr [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3) | ||
| // CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]] | ||
| // | ||
| vbfloat16m4_t test_vle16_v_bf16m4_m(vbool4_t vm, const __bf16 *rs1, size_t vl) { | ||
| return __riscv_vle16_v_bf16m4_m(vm, rs1, vl); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 32 x bfloat> @test_vle16_v_bf16m8_m( | ||
| // CHECK-RV64-SAME: <vscale x 32 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.riscv.vle.mask.nxv32bf16.i64(<vscale x 32 x bfloat> poison, ptr [[RS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 3) | ||
| // CHECK-RV64-NEXT: ret <vscale x 32 x bfloat> [[TMP0]] | ||
| // | ||
| vbfloat16m8_t test_vle16_v_bf16m8_m(vbool2_t vm, const __bf16 *rs1, size_t vl) { | ||
| return __riscv_vle16_v_bf16m8_m(vm, rs1, vl); | ||
| } |
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,177 @@ | ||
| // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 | ||
| // REQUIRES: riscv-registered-target | ||
| // RUN: %clang_cc1 -triple riscv64 -target-feature +v \ | ||
| // RUN: -target-feature +experimental-zvfbfmin \ | ||
| // RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ | ||
| // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ | ||
| // RUN: FileCheck --check-prefix=CHECK-RV64 %s | ||
|
|
||
| #include <riscv_vector.h> | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vle16ff_v_bf16mf4( | ||
| // CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.nxv1bf16.i64(<vscale x 1 x bfloat> poison, ptr [[RS1]], i64 [[VL]]) | ||
| // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x bfloat>, i64 } [[TMP0]], 0 | ||
| // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x bfloat>, i64 } [[TMP0]], 1 | ||
| // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 | ||
| // CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP1]] | ||
| // | ||
| vbfloat16mf4_t test_vle16ff_v_bf16mf4(const __bf16 *rs1, size_t *new_vl, | ||
| size_t vl) { | ||
| return __riscv_vle16ff_v_bf16mf4(rs1, new_vl, vl); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vle16ff_v_bf16mf2( | ||
| // CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.nxv2bf16.i64(<vscale x 2 x bfloat> poison, ptr [[RS1]], i64 [[VL]]) | ||
| // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 2 x bfloat>, i64 } [[TMP0]], 0 | ||
| // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x bfloat>, i64 } [[TMP0]], 1 | ||
| // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 | ||
| // CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP1]] | ||
| // | ||
| vbfloat16mf2_t test_vle16ff_v_bf16mf2(const __bf16 *rs1, size_t *new_vl, | ||
| size_t vl) { | ||
| return __riscv_vle16ff_v_bf16mf2(rs1, new_vl, vl); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vle16ff_v_bf16m1( | ||
| // CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.nxv4bf16.i64(<vscale x 4 x bfloat> poison, ptr [[RS1]], i64 [[VL]]) | ||
| // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 4 x bfloat>, i64 } [[TMP0]], 0 | ||
| // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x bfloat>, i64 } [[TMP0]], 1 | ||
| // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 | ||
| // CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP1]] | ||
| // | ||
| vbfloat16m1_t test_vle16ff_v_bf16m1(const __bf16 *rs1, size_t *new_vl, | ||
| size_t vl) { | ||
| return __riscv_vle16ff_v_bf16m1(rs1, new_vl, vl); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vle16ff_v_bf16m2( | ||
| // CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 8 x bfloat>, i64 } @llvm.riscv.vleff.nxv8bf16.i64(<vscale x 8 x bfloat> poison, ptr [[RS1]], i64 [[VL]]) | ||
| // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 8 x bfloat>, i64 } [[TMP0]], 0 | ||
| // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x bfloat>, i64 } [[TMP0]], 1 | ||
| // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 | ||
| // CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP1]] | ||
| // | ||
| vbfloat16m2_t test_vle16ff_v_bf16m2(const __bf16 *rs1, size_t *new_vl, | ||
| size_t vl) { | ||
| return __riscv_vle16ff_v_bf16m2(rs1, new_vl, vl); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vle16ff_v_bf16m4( | ||
| // CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 16 x bfloat>, i64 } @llvm.riscv.vleff.nxv16bf16.i64(<vscale x 16 x bfloat> poison, ptr [[RS1]], i64 [[VL]]) | ||
| // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 16 x bfloat>, i64 } [[TMP0]], 0 | ||
| // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 16 x bfloat>, i64 } [[TMP0]], 1 | ||
| // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 | ||
| // CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP1]] | ||
| // | ||
| vbfloat16m4_t test_vle16ff_v_bf16m4(const __bf16 *rs1, size_t *new_vl, | ||
| size_t vl) { | ||
| return __riscv_vle16ff_v_bf16m4(rs1, new_vl, vl); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 32 x bfloat> @test_vle16ff_v_bf16m8( | ||
| // CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 32 x bfloat>, i64 } @llvm.riscv.vleff.nxv32bf16.i64(<vscale x 32 x bfloat> poison, ptr [[RS1]], i64 [[VL]]) | ||
| // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 32 x bfloat>, i64 } [[TMP0]], 0 | ||
| // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 32 x bfloat>, i64 } [[TMP0]], 1 | ||
| // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 | ||
| // CHECK-RV64-NEXT: ret <vscale x 32 x bfloat> [[TMP1]] | ||
| // | ||
| vbfloat16m8_t test_vle16ff_v_bf16m8(const __bf16 *rs1, size_t *new_vl, | ||
| size_t vl) { | ||
| return __riscv_vle16ff_v_bf16m8(rs1, new_vl, vl); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vle16ff_v_bf16mf4_m( | ||
| // CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, ptr [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3) | ||
| // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x bfloat>, i64 } [[TMP0]], 0 | ||
| // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x bfloat>, i64 } [[TMP0]], 1 | ||
| // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 | ||
| // CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP1]] | ||
| // | ||
| vbfloat16mf4_t test_vle16ff_v_bf16mf4_m(vbool64_t vm, const __bf16 *rs1, | ||
| size_t *new_vl, size_t vl) { | ||
| return __riscv_vle16ff_v_bf16mf4_m(vm, rs1, new_vl, vl); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vle16ff_v_bf16mf2_m( | ||
| // CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, ptr [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3) | ||
| // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 2 x bfloat>, i64 } [[TMP0]], 0 | ||
| // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x bfloat>, i64 } [[TMP0]], 1 | ||
| // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 | ||
| // CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP1]] | ||
| // | ||
| vbfloat16mf2_t test_vle16ff_v_bf16mf2_m(vbool32_t vm, const __bf16 *rs1, | ||
| size_t *new_vl, size_t vl) { | ||
| return __riscv_vle16ff_v_bf16mf2_m(vm, rs1, new_vl, vl); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vle16ff_v_bf16m1_m( | ||
| // CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv4bf16.i64(<vscale x 4 x bfloat> poison, ptr [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3) | ||
| // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 4 x bfloat>, i64 } [[TMP0]], 0 | ||
| // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x bfloat>, i64 } [[TMP0]], 1 | ||
| // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 | ||
| // CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP1]] | ||
| // | ||
| vbfloat16m1_t test_vle16ff_v_bf16m1_m(vbool16_t vm, const __bf16 *rs1, | ||
| size_t *new_vl, size_t vl) { | ||
| return __riscv_vle16ff_v_bf16m1_m(vm, rs1, new_vl, vl); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vle16ff_v_bf16m2_m( | ||
| // CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 8 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv8bf16.i64(<vscale x 8 x bfloat> poison, ptr [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3) | ||
| // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 8 x bfloat>, i64 } [[TMP0]], 0 | ||
| // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x bfloat>, i64 } [[TMP0]], 1 | ||
| // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 | ||
| // CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP1]] | ||
| // | ||
| vbfloat16m2_t test_vle16ff_v_bf16m2_m(vbool8_t vm, const __bf16 *rs1, | ||
| size_t *new_vl, size_t vl) { | ||
| return __riscv_vle16ff_v_bf16m2_m(vm, rs1, new_vl, vl); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vle16ff_v_bf16m4_m( | ||
| // CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 16 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv16bf16.i64(<vscale x 16 x bfloat> poison, ptr [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3) | ||
| // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 16 x bfloat>, i64 } [[TMP0]], 0 | ||
| // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 16 x bfloat>, i64 } [[TMP0]], 1 | ||
| // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 | ||
| // CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP1]] | ||
| // | ||
| vbfloat16m4_t test_vle16ff_v_bf16m4_m(vbool4_t vm, const __bf16 *rs1, | ||
| size_t *new_vl, size_t vl) { | ||
| return __riscv_vle16ff_v_bf16m4_m(vm, rs1, new_vl, vl); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 32 x bfloat> @test_vle16ff_v_bf16m8_m( | ||
| // CHECK-RV64-SAME: <vscale x 32 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 32 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv32bf16.i64(<vscale x 32 x bfloat> poison, ptr [[RS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 3) | ||
| // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 32 x bfloat>, i64 } [[TMP0]], 0 | ||
| // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 32 x bfloat>, i64 } [[TMP0]], 1 | ||
| // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 | ||
| // CHECK-RV64-NEXT: ret <vscale x 32 x bfloat> [[TMP1]] | ||
| // | ||
| vbfloat16m8_t test_vle16ff_v_bf16m8_m(vbool2_t vm, const __bf16 *rs1, | ||
| size_t *new_vl, size_t vl) { | ||
| return __riscv_vle16ff_v_bf16m8_m(vm, rs1, new_vl, vl); | ||
| } |
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,159 @@ | ||
| // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 | ||
| // REQUIRES: riscv-registered-target | ||
| // RUN: %clang_cc1 -triple riscv64 -target-feature +v \ | ||
| // RUN: -target-feature +experimental-zvfbfmin \ | ||
| // RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ | ||
| // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ | ||
| // RUN: FileCheck --check-prefix=CHECK-RV64 %s | ||
|
|
||
| #include <riscv_vector.h> | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16mf2( | ||
| // CHECK-RV64-SAME: <vscale x 1 x bfloat> [[VALUE:%.*]]) #[[ATTR0:[0-9]+]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.vector.insert.nxv2bf16.nxv1bf16(<vscale x 2 x bfloat> poison, <vscale x 1 x bfloat> [[VALUE]], i64 0) | ||
| // CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]] | ||
| // | ||
| vbfloat16mf2_t test_vlmul_ext_v_bf16mf4_bf16mf2(vbfloat16mf4_t value) { | ||
| return __riscv_vlmul_ext_v_bf16mf4_bf16mf2(value); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m1( | ||
| // CHECK-RV64-SAME: <vscale x 1 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv1bf16(<vscale x 4 x bfloat> poison, <vscale x 1 x bfloat> [[VALUE]], i64 0) | ||
| // CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]] | ||
| // | ||
| vbfloat16m1_t test_vlmul_ext_v_bf16mf4_bf16m1(vbfloat16mf4_t value) { | ||
| return __riscv_vlmul_ext_v_bf16mf4_bf16m1(value); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m2( | ||
| // CHECK-RV64-SAME: <vscale x 1 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv1bf16(<vscale x 8 x bfloat> poison, <vscale x 1 x bfloat> [[VALUE]], i64 0) | ||
| // CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]] | ||
| // | ||
| vbfloat16m2_t test_vlmul_ext_v_bf16mf4_bf16m2(vbfloat16mf4_t value) { | ||
| return __riscv_vlmul_ext_v_bf16mf4_bf16m2(value); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m4( | ||
| // CHECK-RV64-SAME: <vscale x 1 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv1bf16(<vscale x 16 x bfloat> poison, <vscale x 1 x bfloat> [[VALUE]], i64 0) | ||
| // CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]] | ||
| // | ||
| vbfloat16m4_t test_vlmul_ext_v_bf16mf4_bf16m4(vbfloat16mf4_t value) { | ||
| return __riscv_vlmul_ext_v_bf16mf4_bf16m4(value); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m8( | ||
| // CHECK-RV64-SAME: <vscale x 1 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv1bf16(<vscale x 32 x bfloat> poison, <vscale x 1 x bfloat> [[VALUE]], i64 0) | ||
| // CHECK-RV64-NEXT: ret <vscale x 32 x bfloat> [[TMP0]] | ||
| // | ||
| vbfloat16m8_t test_vlmul_ext_v_bf16mf4_bf16m8(vbfloat16mf4_t value) { | ||
| return __riscv_vlmul_ext_v_bf16mf4_bf16m8(value); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m1( | ||
| // CHECK-RV64-SAME: <vscale x 2 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv2bf16(<vscale x 4 x bfloat> poison, <vscale x 2 x bfloat> [[VALUE]], i64 0) | ||
| // CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]] | ||
| // | ||
| vbfloat16m1_t test_vlmul_ext_v_bf16mf2_bf16m1(vbfloat16mf2_t value) { | ||
| return __riscv_vlmul_ext_v_bf16mf2_bf16m1(value); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m2( | ||
| // CHECK-RV64-SAME: <vscale x 2 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv2bf16(<vscale x 8 x bfloat> poison, <vscale x 2 x bfloat> [[VALUE]], i64 0) | ||
| // CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]] | ||
| // | ||
| vbfloat16m2_t test_vlmul_ext_v_bf16mf2_bf16m2(vbfloat16mf2_t value) { | ||
| return __riscv_vlmul_ext_v_bf16mf2_bf16m2(value); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m4( | ||
| // CHECK-RV64-SAME: <vscale x 2 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv2bf16(<vscale x 16 x bfloat> poison, <vscale x 2 x bfloat> [[VALUE]], i64 0) | ||
| // CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]] | ||
| // | ||
| vbfloat16m4_t test_vlmul_ext_v_bf16mf2_bf16m4(vbfloat16mf2_t value) { | ||
| return __riscv_vlmul_ext_v_bf16mf2_bf16m4(value); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m8( | ||
| // CHECK-RV64-SAME: <vscale x 2 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv2bf16(<vscale x 32 x bfloat> poison, <vscale x 2 x bfloat> [[VALUE]], i64 0) | ||
| // CHECK-RV64-NEXT: ret <vscale x 32 x bfloat> [[TMP0]] | ||
| // | ||
| vbfloat16m8_t test_vlmul_ext_v_bf16mf2_bf16m8(vbfloat16mf2_t value) { | ||
| return __riscv_vlmul_ext_v_bf16mf2_bf16m8(value); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vlmul_ext_v_bf16m1_bf16m2( | ||
| // CHECK-RV64-SAME: <vscale x 4 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat> poison, <vscale x 4 x bfloat> [[VALUE]], i64 0) | ||
| // CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]] | ||
| // | ||
| vbfloat16m2_t test_vlmul_ext_v_bf16m1_bf16m2(vbfloat16m1_t value) { | ||
| return __riscv_vlmul_ext_v_bf16m1_bf16m2(value); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16m1_bf16m4( | ||
| // CHECK-RV64-SAME: <vscale x 4 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat> poison, <vscale x 4 x bfloat> [[VALUE]], i64 0) | ||
| // CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]] | ||
| // | ||
| vbfloat16m4_t test_vlmul_ext_v_bf16m1_bf16m4(vbfloat16m1_t value) { | ||
| return __riscv_vlmul_ext_v_bf16m1_bf16m4(value); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16m1_bf16m8( | ||
| // CHECK-RV64-SAME: <vscale x 4 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> poison, <vscale x 4 x bfloat> [[VALUE]], i64 0) | ||
| // CHECK-RV64-NEXT: ret <vscale x 32 x bfloat> [[TMP0]] | ||
| // | ||
| vbfloat16m8_t test_vlmul_ext_v_bf16m1_bf16m8(vbfloat16m1_t value) { | ||
| return __riscv_vlmul_ext_v_bf16m1_bf16m8(value); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16m2_bf16m4( | ||
| // CHECK-RV64-SAME: <vscale x 8 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat> poison, <vscale x 8 x bfloat> [[VALUE]], i64 0) | ||
| // CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]] | ||
| // | ||
| vbfloat16m4_t test_vlmul_ext_v_bf16m2_bf16m4(vbfloat16m2_t value) { | ||
| return __riscv_vlmul_ext_v_bf16m2_bf16m4(value); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16m2_bf16m8( | ||
| // CHECK-RV64-SAME: <vscale x 8 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat> poison, <vscale x 8 x bfloat> [[VALUE]], i64 0) | ||
| // CHECK-RV64-NEXT: ret <vscale x 32 x bfloat> [[TMP0]] | ||
| // | ||
| vbfloat16m8_t test_vlmul_ext_v_bf16m2_bf16m8(vbfloat16m2_t value) { | ||
| return __riscv_vlmul_ext_v_bf16m2_bf16m8(value); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16m4_bf16m8( | ||
| // CHECK-RV64-SAME: <vscale x 16 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv16bf16(<vscale x 32 x bfloat> poison, <vscale x 16 x bfloat> [[VALUE]], i64 0) | ||
| // CHECK-RV64-NEXT: ret <vscale x 32 x bfloat> [[TMP0]] | ||
| // | ||
| vbfloat16m8_t test_vlmul_ext_v_bf16m4_bf16m8(vbfloat16m4_t value) { | ||
| return __riscv_vlmul_ext_v_bf16m4_bf16m8(value); | ||
| } |
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,159 @@ | ||
| // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 | ||
| // REQUIRES: riscv-registered-target | ||
| // RUN: %clang_cc1 -triple riscv64 -target-feature +v \ | ||
| // RUN: -target-feature +experimental-zvfbfmin \ | ||
| // RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ | ||
| // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ | ||
| // RUN: FileCheck --check-prefix=CHECK-RV64 %s | ||
|
|
||
| #include <riscv_vector.h> | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16mf2_bf16mf4( | ||
| // CHECK-RV64-SAME: <vscale x 2 x bfloat> [[VALUE:%.*]]) #[[ATTR0:[0-9]+]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv2bf16(<vscale x 2 x bfloat> [[VALUE]], i64 0) | ||
| // CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]] | ||
| // | ||
| vbfloat16mf4_t test_vlmul_trunc_v_bf16mf2_bf16mf4(vbfloat16mf2_t value) { | ||
| return __riscv_vlmul_trunc_v_bf16mf2_bf16mf4(value); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16m1_bf16mf4( | ||
| // CHECK-RV64-SAME: <vscale x 4 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv4bf16(<vscale x 4 x bfloat> [[VALUE]], i64 0) | ||
| // CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]] | ||
| // | ||
| vbfloat16mf4_t test_vlmul_trunc_v_bf16m1_bf16mf4(vbfloat16m1_t value) { | ||
| return __riscv_vlmul_trunc_v_bf16m1_bf16mf4(value); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vlmul_trunc_v_bf16m1_bf16mf2( | ||
| // CHECK-RV64-SAME: <vscale x 4 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv4bf16(<vscale x 4 x bfloat> [[VALUE]], i64 0) | ||
| // CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]] | ||
| // | ||
| vbfloat16mf2_t test_vlmul_trunc_v_bf16m1_bf16mf2(vbfloat16m1_t value) { | ||
| return __riscv_vlmul_trunc_v_bf16m1_bf16mf2(value); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16m2_bf16mf4( | ||
| // CHECK-RV64-SAME: <vscale x 8 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv8bf16(<vscale x 8 x bfloat> [[VALUE]], i64 0) | ||
| // CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]] | ||
| // | ||
| vbfloat16mf4_t test_vlmul_trunc_v_bf16m2_bf16mf4(vbfloat16m2_t value) { | ||
| return __riscv_vlmul_trunc_v_bf16m2_bf16mf4(value); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vlmul_trunc_v_bf16m2_bf16mf2( | ||
| // CHECK-RV64-SAME: <vscale x 8 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv8bf16(<vscale x 8 x bfloat> [[VALUE]], i64 0) | ||
| // CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]] | ||
| // | ||
| vbfloat16mf2_t test_vlmul_trunc_v_bf16m2_bf16mf2(vbfloat16m2_t value) { | ||
| return __riscv_vlmul_trunc_v_bf16m2_bf16mf2(value); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vlmul_trunc_v_bf16m2_bf16m1( | ||
| // CHECK-RV64-SAME: <vscale x 8 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat> [[VALUE]], i64 0) | ||
| // CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]] | ||
| // | ||
| vbfloat16m1_t test_vlmul_trunc_v_bf16m2_bf16m1(vbfloat16m2_t value) { | ||
| return __riscv_vlmul_trunc_v_bf16m2_bf16m1(value); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16m4_bf16mf4( | ||
| // CHECK-RV64-SAME: <vscale x 16 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv16bf16(<vscale x 16 x bfloat> [[VALUE]], i64 0) | ||
| // CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]] | ||
| // | ||
| vbfloat16mf4_t test_vlmul_trunc_v_bf16m4_bf16mf4(vbfloat16m4_t value) { | ||
| return __riscv_vlmul_trunc_v_bf16m4_bf16mf4(value); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vlmul_trunc_v_bf16m4_bf16mf2( | ||
| // CHECK-RV64-SAME: <vscale x 16 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv16bf16(<vscale x 16 x bfloat> [[VALUE]], i64 0) | ||
| // CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]] | ||
| // | ||
| vbfloat16mf2_t test_vlmul_trunc_v_bf16m4_bf16mf2(vbfloat16m4_t value) { | ||
| return __riscv_vlmul_trunc_v_bf16m4_bf16mf2(value); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vlmul_trunc_v_bf16m4_bf16m1( | ||
| // CHECK-RV64-SAME: <vscale x 16 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat> [[VALUE]], i64 0) | ||
| // CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]] | ||
| // | ||
| vbfloat16m1_t test_vlmul_trunc_v_bf16m4_bf16m1(vbfloat16m4_t value) { | ||
| return __riscv_vlmul_trunc_v_bf16m4_bf16m1(value); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vlmul_trunc_v_bf16m4_bf16m2( | ||
| // CHECK-RV64-SAME: <vscale x 16 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv16bf16(<vscale x 16 x bfloat> [[VALUE]], i64 0) | ||
| // CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]] | ||
| // | ||
| vbfloat16m2_t test_vlmul_trunc_v_bf16m4_bf16m2(vbfloat16m4_t value) { | ||
| return __riscv_vlmul_trunc_v_bf16m4_bf16m2(value); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16mf4( | ||
| // CHECK-RV64-SAME: <vscale x 32 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv32bf16(<vscale x 32 x bfloat> [[VALUE]], i64 0) | ||
| // CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]] | ||
| // | ||
| vbfloat16mf4_t test_vlmul_trunc_v_bf16m8_bf16mf4(vbfloat16m8_t value) { | ||
| return __riscv_vlmul_trunc_v_bf16m8_bf16mf4(value); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16mf2( | ||
| // CHECK-RV64-SAME: <vscale x 32 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv32bf16(<vscale x 32 x bfloat> [[VALUE]], i64 0) | ||
| // CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]] | ||
| // | ||
| vbfloat16mf2_t test_vlmul_trunc_v_bf16m8_bf16mf2(vbfloat16m8_t value) { | ||
| return __riscv_vlmul_trunc_v_bf16m8_bf16mf2(value); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16m1( | ||
| // CHECK-RV64-SAME: <vscale x 32 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv32bf16(<vscale x 32 x bfloat> [[VALUE]], i64 0) | ||
| // CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]] | ||
| // | ||
| vbfloat16m1_t test_vlmul_trunc_v_bf16m8_bf16m1(vbfloat16m8_t value) { | ||
| return __riscv_vlmul_trunc_v_bf16m8_bf16m1(value); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16m2( | ||
| // CHECK-RV64-SAME: <vscale x 32 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv32bf16(<vscale x 32 x bfloat> [[VALUE]], i64 0) | ||
| // CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]] | ||
| // | ||
| vbfloat16m2_t test_vlmul_trunc_v_bf16m8_bf16m2(vbfloat16m8_t value) { | ||
| return __riscv_vlmul_trunc_v_bf16m8_bf16m2(value); | ||
| } | ||
|
|
||
| // CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16m4( | ||
| // CHECK-RV64-SAME: <vscale x 32 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { | ||
| // CHECK-RV64-NEXT: entry: | ||
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.vector.extract.nxv16bf16.nxv32bf16(<vscale x 32 x bfloat> [[VALUE]], i64 0) | ||
| // CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]] | ||
| // | ||
| vbfloat16m4_t test_vlmul_trunc_v_bf16m8_bf16m4(vbfloat16m8_t value) { | ||
| return __riscv_vlmul_trunc_v_bf16m8_bf16m4(value); | ||
| } |