73 changes: 62 additions & 11 deletions llvm/test/CodeGen/SPARC/branches-relax.ll
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=sparc64 -sparc-bpcc-offset-bits=4 | FileCheck --check-prefix=SPARC64 %s
; RUN: llc < %s -mtriple=sparc64 -sparc-bpcc-offset-bits=4 -sparc-bpr-offset-bits=4 | FileCheck --check-prefix=SPARC64 %s

define i32 @branch_relax_int(i32 %in) {
; SPARC64-LABEL: branch_relax_int:
Expand Down Expand Up @@ -53,6 +53,57 @@ false:
ret i32 0
}

define i64 @branch_relax_reg(i64 %in) {
; SPARC64-LABEL: branch_relax_reg:
; SPARC64: .cfi_startproc
; SPARC64-NEXT: ! %bb.0:
; SPARC64-NEXT: save %sp, -128, %sp
; SPARC64-NEXT: .cfi_def_cfa_register %fp
; SPARC64-NEXT: .cfi_window_save
; SPARC64-NEXT: .cfi_register %o7, %i7
; SPARC64-NEXT: brnz %i0, .LBB1_1
; SPARC64-NEXT: nop
; SPARC64-NEXT: ba .LBB1_2
; SPARC64-NEXT: nop
; SPARC64-NEXT: .LBB1_1: ! %false
; SPARC64-NEXT: !APP
; SPARC64-NEXT: nop
; SPARC64-NEXT: nop
; SPARC64-NEXT: nop
; SPARC64-NEXT: nop
; SPARC64-NEXT: nop
; SPARC64-NEXT: nop
; SPARC64-NEXT: nop
; SPARC64-NEXT: nop
; SPARC64-NEXT: !NO_APP
; SPARC64-NEXT: ret
; SPARC64-NEXT: restore %g0, %g0, %o0
; SPARC64-NEXT: .LBB1_2: ! %true
; SPARC64-NEXT: mov 4, %i0
; SPARC64-NEXT: !APP
; SPARC64-NEXT: nop
; SPARC64-NEXT: nop
; SPARC64-NEXT: nop
; SPARC64-NEXT: nop
; SPARC64-NEXT: nop
; SPARC64-NEXT: nop
; SPARC64-NEXT: nop
; SPARC64-NEXT: nop
; SPARC64-NEXT: !NO_APP
; SPARC64-NEXT: ret
; SPARC64-NEXT: restore
%tst = icmp eq i64 %in, 0
br i1 %tst, label %true, label %false

true:
call void asm sideeffect "nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop", ""()
ret i64 4

false:
call void asm sideeffect "nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop", ""()
ret i64 0
}

define float @branch_relax_float(float %in) {
; SPARC64-LABEL: branch_relax_float:
; SPARC64: .cfi_startproc
Expand All @@ -61,20 +112,20 @@ define float @branch_relax_float(float %in) {
; SPARC64-NEXT: .cfi_def_cfa_register %fp
; SPARC64-NEXT: .cfi_window_save
; SPARC64-NEXT: .cfi_register %o7, %i7
; SPARC64-NEXT: sethi %h44(.LCPI1_0), %i0
; SPARC64-NEXT: add %i0, %m44(.LCPI1_0), %i0
; SPARC64-NEXT: sethi %h44(.LCPI2_0), %i0
; SPARC64-NEXT: add %i0, %m44(.LCPI2_0), %i0
; SPARC64-NEXT: sllx %i0, 12, %i0
; SPARC64-NEXT: ld [%i0+%l44(.LCPI1_0)], %f0
; SPARC64-NEXT: ld [%i0+%l44(.LCPI2_0)], %f0
; SPARC64-NEXT: fcmps %fcc0, %f1, %f0
; SPARC64-NEXT: fbe %fcc0, .LBB1_1
; SPARC64-NEXT: fbe %fcc0, .LBB2_1
; SPARC64-NEXT: nop
; SPARC64-NEXT: ba .LBB1_2
; SPARC64-NEXT: ba .LBB2_2
; SPARC64-NEXT: nop
; SPARC64-NEXT: .LBB1_1: ! %true
; SPARC64-NEXT: sethi %h44(.LCPI1_1), %i0
; SPARC64-NEXT: add %i0, %m44(.LCPI1_1), %i0
; SPARC64-NEXT: .LBB2_1: ! %true
; SPARC64-NEXT: sethi %h44(.LCPI2_1), %i0
; SPARC64-NEXT: add %i0, %m44(.LCPI2_1), %i0
; SPARC64-NEXT: sllx %i0, 12, %i0
; SPARC64-NEXT: ld [%i0+%l44(.LCPI1_1)], %f0
; SPARC64-NEXT: ld [%i0+%l44(.LCPI2_1)], %f0
; SPARC64-NEXT: !APP
; SPARC64-NEXT: nop
; SPARC64-NEXT: nop
Expand All @@ -87,7 +138,7 @@ define float @branch_relax_float(float %in) {
; SPARC64-NEXT: !NO_APP
; SPARC64-NEXT: ret
; SPARC64-NEXT: restore
; SPARC64-NEXT: .LBB1_2: ! %false
; SPARC64-NEXT: .LBB2_2: ! %false
; SPARC64-NEXT: !APP
; SPARC64-NEXT: nop
; SPARC64-NEXT: nop
Expand Down
66 changes: 55 additions & 11 deletions llvm/test/CodeGen/SPARC/branches-v9.ll
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Original file line number Diff line number Diff line change
@@ -1,13 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=sparcv9 -disable-sparc-leaf-proc | FileCheck %s

;; 1. When emitting code for v9, branches should always explicitly specify
;; 1. When emitting code for v9, CCR branches should always explicitly specify
;; %icc or %xcc.
;; 2. There should never be a `ba` that jumps into two instructions immediately
;; 2. Branches on the result of a 64-bit compare with constant zero should be
;; lowered into an instruction in the BPr class (§A.3 in V9 spec).
;; 3. There should never be a `ba` that jumps into two instructions immediately
;; following it.

define void @i(i32 signext %sel) {
; CHECK-LABEL: i:
define void @bricc(i32 signext %sel) {
; CHECK-LABEL: bricc:
; CHECK: .cfi_startproc
; CHECK-NEXT: ! %bb.0: ! %entry
; CHECK-NEXT: save %sp, -176, %sp
Expand Down Expand Up @@ -47,26 +49,68 @@ end:
ret void
}

define void @l(i64 %sel) {
; CHECK-LABEL: l:
define void @brxcc(i64 %sel) {
; CHECK-LABEL: brxcc:
; CHECK: .cfi_startproc
; CHECK-NEXT: ! %bb.0: ! %entry
; CHECK-NEXT: save %sp, -176, %sp
; CHECK-NEXT: .cfi_def_cfa_register %fp
; CHECK-NEXT: .cfi_window_save
; CHECK-NEXT: .cfi_register %o7, %i7
; CHECK-NEXT: cmp %i0, 0
; CHECK-NEXT: be %xcc, .LBB1_2
; CHECK-NEXT: cmp %i0, 1
; CHECK-NEXT: bne %xcc, .LBB1_2
; CHECK-NEXT: nop
; CHECK-NEXT: ! %bb.1: ! %tbb
; CHECK-NEXT: call f1
; CHECK-NEXT: nop
; CHECK-NEXT: ba .LBB1_3
; CHECK-NEXT: nop
; CHECK-NEXT: .LBB1_2: ! %fbb
; CHECK-NEXT: call f2
; CHECK-NEXT: nop
; CHECK-NEXT: .LBB1_3: ! %end
; CHECK-NEXT: call f3
; CHECK-NEXT: nop
; CHECK-NEXT: ret
; CHECK-NEXT: restore
entry:
;; Using 1 here because compares with zero
;; will be lowered into a `brz`, not `be`.
%cond = icmp eq i64 %sel, 1
br i1 %cond, label %tbb, label %fbb

fbb:
call void @f2()
br label %end

tbb:
call void @f1()
br label %end

end:
call void @f3()
ret void
}

define void @brreg(i64 %sel) {
; CHECK-LABEL: brreg:
; CHECK: .cfi_startproc
; CHECK-NEXT: ! %bb.0: ! %entry
; CHECK-NEXT: save %sp, -176, %sp
; CHECK-NEXT: .cfi_def_cfa_register %fp
; CHECK-NEXT: .cfi_window_save
; CHECK-NEXT: .cfi_register %o7, %i7
; CHECK-NEXT: brz %i0, .LBB2_2
; CHECK-NEXT: nop
; CHECK-NEXT: ! %bb.1: ! %fbb
; CHECK-NEXT: call f2
; CHECK-NEXT: nop
; CHECK-NEXT: ba .LBB1_3
; CHECK-NEXT: ba .LBB2_3
; CHECK-NEXT: nop
; CHECK-NEXT: .LBB1_2: ! %tbb
; CHECK-NEXT: .LBB2_2: ! %tbb
; CHECK-NEXT: call f1
; CHECK-NEXT: nop
; CHECK-NEXT: .LBB1_3: ! %end
; CHECK-NEXT: .LBB2_3: ! %end
; CHECK-NEXT: call f3
; CHECK-NEXT: nop
; CHECK-NEXT: ret
Expand Down
3 changes: 1 addition & 2 deletions llvm/test/CodeGen/SPARC/missinglabel.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -8,8 +8,7 @@ define void @f(i64 %a0) align 2 {
; CHECK-LABEL: f:
; CHECK: .cfi_startproc
; CHECK-NEXT: ! %bb.0: ! %entry
; CHECK-NEXT: cmp %o0, 0
; CHECK-NEXT: be %xcc, .LBB0_2
; CHECK-NEXT: brz %o0, .LBB0_2
; CHECK-NEXT: nop
; CHECK-NEXT: ! %bb.1: ! %cond.false
; CHECK-NEXT: .LBB0_2: ! %targetblock
Expand Down
31 changes: 31 additions & 0 deletions llvm/test/MC/Sparc/sparc64-bpr-offset.s
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Original file line number Diff line number Diff line change
@@ -0,0 +1,31 @@
! RUN: llvm-mc -arch=sparcv9 -filetype=obj %s | llvm-objdump -d - | FileCheck %s --check-prefix=BIN

!! SPARCv9/SPARC64 BPr branches have different offset encoding from the others,
!! make sure that our offset bits don't trample on other fields.
!! This is particularly important with backwards branches.

! BIN: 0: 02 c8 40 01 brz %g1, 1
! BIN: 4: 04 c8 40 01 brlez %g1, 1
! BIN: 8: 06 c8 40 01 brlz %g1, 1
! BIN: c: 0a c8 40 01 brnz %g1, 1
! BIN: 10: 0c c8 40 01 brgz %g1, 1
! BIN: 14: 0e c8 40 01 brgez %g1, 1
brz %g1, .+4
brlez %g1, .+4
brlz %g1, .+4
brnz %g1, .+4
brgz %g1, .+4
brgez %g1, .+4

! BIN: 18: 02 f8 7f ff brz %g1, 65535
! BIN: 1c: 04 f8 7f ff brlez %g1, 65535
! BIN: 20: 06 f8 7f ff brlz %g1, 65535
! BIN: 24: 0a f8 7f ff brnz %g1, 65535
! BIN: 28: 0c f8 7f ff brgz %g1, 65535
! BIN: 2c: 0e f8 7f ff brgez %g1, 65535
brz %g1, .-4
brlez %g1, .-4
brlz %g1, .-4
brnz %g1, .-4
brgz %g1, .-4
brgez %g1, .-4
55 changes: 22 additions & 33 deletions llvm/test/MC/Sparc/sparc64-ctrl-instructions.s
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Original file line number Diff line number Diff line change
Expand Up @@ -1150,24 +1150,18 @@
fbne,a,pn %fcc3, .BB0


! CHECK: brz %g1, .BB0 ! encoding: [0x02,0b11AA1000,0b01BBBBBB,B]
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br16_2
! CHECK-NEXT: ! fixup B - offset: 0, value: .BB0, kind: fixup_sparc_br16_14
! CHECK: brlez %g1, .BB0 ! encoding: [0x04,0b11AA1000,0b01BBBBBB,B]
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br16_2
! CHECK-NEXT: ! fixup B - offset: 0, value: .BB0, kind: fixup_sparc_br16_14
! CHECK: brlz %g1, .BB0 ! encoding: [0x06,0b11AA1000,0b01BBBBBB,B]
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br16_2
! CHECK-NEXT: ! fixup B - offset: 0, value: .BB0, kind: fixup_sparc_br16_14
! CHECK: brnz %g1, .BB0 ! encoding: [0x0a,0b11AA1000,0b01BBBBBB,B]
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br16_2
! CHECK-NEXT: ! fixup B - offset: 0, value: .BB0, kind: fixup_sparc_br16_14
! CHECK: brgz %g1, .BB0 ! encoding: [0x0c,0b11AA1000,0b01BBBBBB,B]
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br16_2
! CHECK-NEXT: ! fixup B - offset: 0, value: .BB0, kind: fixup_sparc_br16_14
! CHECK: brgez %g1, .BB0 ! encoding: [0x0e,0b11AA1000,0b01BBBBBB,B]
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br16_2
! CHECK-NEXT: ! fixup B - offset: 0, value: .BB0, kind: fixup_sparc_br16_14
! CHECK: brz %g1, .BB0 ! encoding: [0x02'A',0xc8'A',0x40'A',A]
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br16
! CHECK: brlez %g1, .BB0 ! encoding: [0x04'A',0xc8'A',0x40'A',A]
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br16
! CHECK: brlz %g1, .BB0 ! encoding: [0x06'A',0xc8'A',0x40'A',A]
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br16
! CHECK: brnz %g1, .BB0 ! encoding: [0x0a'A',0xc8'A',0x40'A',A]
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br16
! CHECK: brgz %g1, .BB0 ! encoding: [0x0c'A',0xc8'A',0x40'A',A]
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br16
! CHECK: brgez %g1, .BB0 ! encoding: [0x0e'A',0xc8'A',0x40'A',A]
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br16

brz %g1, .BB0
brlez %g1, .BB0
Expand All @@ -1176,29 +1170,24 @@
brgz %g1, .BB0
brgez %g1, .BB0

! CHECK: brz %g1, .BB0 ! encoding: [0x02,0b11AA1000,0b01BBBBBB,B]
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br16_2
! CHECK-NEXT: ! fixup B - offset: 0, value: .BB0, kind: fixup_sparc_br16_14
! CHECK: brz %g1, .BB0 ! encoding: [0x02'A',0xc8'A',0x40'A',A]
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br16
brz,pt %g1, .BB0

! CHECK: brz,a %g1, .BB0 ! encoding: [0x22,0b11AA1000,0b01BBBBBB,B]
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br16_2
! CHECK-NEXT: ! fixup B - offset: 0, value: .BB0, kind: fixup_sparc_br16_14
! CHECK: brz,a %g1, .BB0 ! encoding: [0x22'A',0xc8'A',0x40'A',A]
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br16
brz,a %g1, .BB0

! CHECK: brz,a %g1, .BB0 ! encoding: [0x22,0b11AA1000,0b01BBBBBB,B]
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br16_2
! CHECK-NEXT: ! fixup B - offset: 0, value: .BB0, kind: fixup_sparc_br16_14
! CHECK: brz,a %g1, .BB0 ! encoding: [0x22'A',0xc8'A',0x40'A',A]
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br16
brz,a,pt %g1, .BB0

! CHECK: brz,pn %g1, .BB0 ! encoding: [0x02,0b11AA0000,0b01BBBBBB,B]
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br16_2
! CHECK-NEXT: ! fixup B - offset: 0, value: .BB0, kind: fixup_sparc_br16_14
! CHECK: brz,pn %g1, .BB0 ! encoding: [0x02'A',0xc0'A',0x40'A',A]
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br16
brz,pn %g1, .BB0

! CHECK: brz,a,pn %g1, .BB0 ! encoding: [0x22,0b11AA0000,0b01BBBBBB,B]
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br16_2
! CHECK-NEXT: ! fixup B - offset: 0, value: .BB0, kind: fixup_sparc_br16_14
! CHECK: brz,a,pn %g1, .BB0 ! encoding: [0x22'A',0xc0'A',0x40'A',A]
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br16
brz,a,pn %g1, .BB0

! CHECK: movrz %g1, %g2, %g3 ! encoding: [0x87,0x78,0x44,0x02]
Expand Down