56 changes: 56 additions & 0 deletions llvm/test/CodeGen/AArch64/llround-conv.ll
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; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s

; CHECK-LABEL: testmsws:
; CHECK: bl llroundf
define i32 @testmsws(float %x) {
entry:
%0 = tail call i64 @llvm.llround.f32(float %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}

; CHECK-LABEL: testmsxs:
; CHECK: b llroundf
define i64 @testmsxs(float %x) {
entry:
%0 = tail call i64 @llvm.llround.f32(float %x)
ret i64 %0
}

; CHECK-LABEL: testmswd:
; CHECK: bl llround
define i32 @testmswd(double %x) {
entry:
%0 = tail call i64 @llvm.llround.f64(double %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}

; CHECK-LABEL: testmsxd:
; CHECK: b llround
define i64 @testmsxd(double %x) {
entry:
%0 = tail call i64 @llvm.llround.f64(double %x)
ret i64 %0
}

; CHECK-LABEL: testmswl:
; CHECK: bl llroundl
define i32 @testmswl(fp128 %x) {
entry:
%0 = tail call i64 @llvm.llround.f128(fp128 %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}

; CHECK-LABEL: testmsll:
; CHECK: b llroundl
define i64 @testmsll(fp128 %x) {
entry:
%0 = tail call i64 @llvm.llround.f128(fp128 %x)
ret i64 %0
}

declare i64 @llvm.llround.f32(float) nounwind readnone
declare i64 @llvm.llround.f64(double) nounwind readnone
declare i64 @llvm.llround.f128(fp128) nounwind readnone
56 changes: 56 additions & 0 deletions llvm/test/CodeGen/AArch64/lround-conv.ll
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; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s

; CHECK-LABEL: testmsws:
; CHECK: bl lroundf
define i32 @testmsws(float %x) {
entry:
%0 = tail call i64 @llvm.lround.i64.f32(float %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}

; CHECK-LABEL: testmsxs:
; CHECK: b lroundf
define i64 @testmsxs(float %x) {
entry:
%0 = tail call i64 @llvm.lround.i64.f32(float %x)
ret i64 %0
}

; CHECK-LABEL: testmswd:
; CHECK: bl lround
define i32 @testmswd(double %x) {
entry:
%0 = tail call i64 @llvm.lround.i64.f64(double %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}

; CHECK-LABEL: testmsxd:
; CHECK: b lround
define i64 @testmsxd(double %x) {
entry:
%0 = tail call i64 @llvm.lround.i64.f64(double %x)
ret i64 %0
}

; CHECK-LABEL: testmswl:
; CHECK: bl lroundl
define i32 @testmswl(fp128 %x) {
entry:
%0 = tail call i64 @llvm.lround.i64.f128(fp128 %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}

; CHECK-LABEL: testmsll:
; CHECK: b lroundl
define i64 @testmsll(fp128 %x) {
entry:
%0 = tail call i64 @llvm.lround.i64.f128(fp128 %x)
ret i64 %0
}

declare i64 @llvm.lround.i64.f32(float) nounwind readnone
declare i64 @llvm.lround.i64.f64(double) nounwind readnone
declare i64 @llvm.lround.i64.f128(fp128) nounwind readnone
25 changes: 25 additions & 0 deletions llvm/test/CodeGen/ARM/llround-conv.ll
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; RUN: llc < %s -mtriple=arm-eabi -float-abi=soft | FileCheck %s --check-prefix=SOFTFP
; RUN: llc < %s -mtriple=arm-eabi -float-abi=hard | FileCheck %s --check-prefix=HARDFP

; SOFTFP-LABEL: testmsxs_builtin:
; SOFTFP: bl llroundf
; HARDFP-LABEL: testmsxs_builtin:
; HARDFP: bl llroundf
define i64 @testmsxs_builtin(float %x) {
entry:
%0 = tail call i64 @llvm.llround.f32(float %x)
ret i64 %0
}

; SOFTFP-LABEL: testmsxd_builtin:
; SOFTFP: bl llround
; HARDFP-LABEL: testmsxd_builtin:
; HARDFP: bl llround
define i64 @testmsxd_builtin(double %x) {
entry:
%0 = tail call i64 @llvm.llround.f64(double %x)
ret i64 %0
}

declare i64 @llvm.llround.f32(float) nounwind readnone
declare i64 @llvm.llround.f64(double) nounwind readnone
25 changes: 25 additions & 0 deletions llvm/test/CodeGen/ARM/lround-conv.ll
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; RUN: llc < %s -mtriple=arm-eabi -float-abi=soft | FileCheck %s --check-prefix=SOFTFP
; RUN: llc < %s -mtriple=arm-eabi -float-abi=hard | FileCheck %s --check-prefix=HARDFP

; SOFTFP-LABEL: testmsws_builtin:
; SOFTFP: bl lroundf
; HARDFP-LABEL: testmsws_builtin:
; HARDFP: bl lroundf
define i32 @testmsws_builtin(float %x) {
entry:
%0 = tail call i32 @llvm.lround.i32.f32(float %x)
ret i32 %0
}

; SOFTFP-LABEL: testmswd_builtin:
; SOFTFP: bl lround
; HARDFP-LABEL: testmswd_builtin:
; HARDFP: bl lround
define i32 @testmswd_builtin(double %x) {
entry:
%0 = tail call i32 @llvm.lround.i32.f64(double %x)
ret i32 %0
}

declare i32 @llvm.lround.i32.f32(float) nounwind readnone
declare i32 @llvm.lround.i32.f64(double) nounwind readnone
56 changes: 56 additions & 0 deletions llvm/test/CodeGen/Mips/llround-conv.ll
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; RUN: llc < %s -mtriple=mips64el -mattr=+soft-float | FileCheck %s

define signext i32 @testmsws(float %x) {
; CHECK-LABEL: testmsws:
; CHECK: jal llroundf
entry:
%0 = tail call i64 @llvm.llround.f32(float %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}

define i64 @testmsxs(float %x) {
; CHECK-LABEL: testmsxs:
; CHECK: jal llroundf
entry:
%0 = tail call i64 @llvm.llround.f32(float %x)
ret i64 %0
}

define signext i32 @testmswd(double %x) {
; CHECK-LABEL: testmswd:
; CHECK: jal llround
entry:
%0 = tail call i64 @llvm.llround.f64(double %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}

define i64 @testmsxd(double %x) {
; CHECK-LABEL: testmsxd:
; CHECK: jal llround
entry:
%0 = tail call i64 @llvm.llround.f64(double %x)
ret i64 %0
}

define signext i32 @testmswl(fp128 %x) {
; CHECK-LABEL: testmswl:
; CHECK: jal llroundl
entry:
%0 = tail call i64 @llvm.llround.f128(fp128 %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}

define i64 @testmsll(fp128 %x) {
; CHECK-LABEL: testmsll:
; CHECK: jal llroundl
entry:
%0 = tail call i64 @llvm.llround.f128(fp128 %x)
ret i64 %0
}

declare i64 @llvm.llround.f32(float) nounwind readnone
declare i64 @llvm.llround.f64(double) nounwind readnone
declare i64 @llvm.llround.f128(fp128) nounwind readnone
56 changes: 56 additions & 0 deletions llvm/test/CodeGen/Mips/lround-conv.ll
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; RUN: llc < %s -mtriple=mips64el -mattr=+soft-float | FileCheck %s

define signext i32 @testmsws(float %x) {
; CHECK-LABEL: testmsws:
; CHECK: jal lroundf
entry:
%0 = tail call i64 @llvm.lround.i64.f32(float %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}

define i64 @testmsxs(float %x) {
; CHECK-LABEL: testmsxs:
; CHECK: jal lroundf
entry:
%0 = tail call i64 @llvm.lround.i64.f32(float %x)
ret i64 %0
}

define signext i32 @testmswd(double %x) {
; CHECK-LABEL: testmswd:
; CHECK: jal lround
entry:
%0 = tail call i64 @llvm.lround.i64.f64(double %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}

define i64 @testmsxd(double %x) {
; CHECK-LABEL: testmsxd:
; CHECK: jal lround
entry:
%0 = tail call i64 @llvm.lround.i64.f64(double %x)
ret i64 %0
}

define signext i32 @testmswl(fp128 %x) {
; CHECK-LABEL: testmswl:
; CHECK: jal lroundl
entry:
%0 = tail call i64 @llvm.lround.i64.f128(fp128 %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}

define signext i64 @testmsll(fp128 %x) {
; CHECK-LABEL: testmsll:
; CHECK: jal lroundl
entry:
%0 = tail call i64 @llvm.lround.i64.f128(fp128 %x)
ret i64 %0
}

declare i64 @llvm.lround.i64.f32(float) nounwind readnone
declare i64 @llvm.lround.i64.f64(double) nounwind readnone
declare i64 @llvm.lround.i64.f128(fp128) nounwind readnone
56 changes: 56 additions & 0 deletions llvm/test/CodeGen/PowerPC/llround-conv.ll
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; RUN: llc < %s -mtriple=powerpc64le | FileCheck %s

; CHECK-LABEL: testmsws:
; CHECK: bl llroundf
define signext i32 @testmsws(float %x) {
entry:
%0 = tail call i64 @llvm.llround.f32(float %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}

; CHECK-LABEL: testmsxs:
; CHECK: bl llroundf
define i64 @testmsxs(float %x) {
entry:
%0 = tail call i64 @llvm.llround.f32(float %x)
ret i64 %0
}

; CHECK-LABEL: testmswd:
; CHECK: bl llround
define signext i32 @testmswd(double %x) {
entry:
%0 = tail call i64 @llvm.llround.f64(double %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}

; CHECK-LABEL: testmsxd:
; CHECK: bl llround
define i64 @testmsxd(double %x) {
entry:
%0 = tail call i64 @llvm.llround.f64(double %x)
ret i64 %0
}

; CHECK-LABEL: testmswl:
; CHECK: bl llroundl
define signext i32 @testmswl(ppc_fp128 %x) {
entry:
%0 = tail call i64 @llvm.llround.ppcf128(ppc_fp128 %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}

; CHECK-LABEL: testmsll:
; CHECK: bl llroundl
define i64 @testmsll(ppc_fp128 %x) {
entry:
%0 = tail call i64 @llvm.llround.ppcf128(ppc_fp128 %x)
ret i64 %0
}

declare i64 @llvm.llround.f32(float) nounwind readnone
declare i64 @llvm.llround.f64(double) nounwind readnone
declare i64 @llvm.llround.ppcf128(ppc_fp128) nounwind readnone
56 changes: 56 additions & 0 deletions llvm/test/CodeGen/PowerPC/lround-conv.ll
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; RUN: llc < %s -mtriple=powerpc64le | FileCheck %s

; CHECK-LABEL: testmsws:
; CHECK: bl lroundf
define signext i32 @testmsws(float %x) {
entry:
%0 = tail call i64 @llvm.lround.i64.f32(float %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}

; CHECK-LABEL: testmsxs:
; CHECK: bl lroundf
define i64 @testmsxs(float %x) {
entry:
%0 = tail call i64 @llvm.lround.i64.f32(float %x)
ret i64 %0
}

; CHECK-LABEL: testmswd:
; CHECK: bl lround
define signext i32 @testmswd(double %x) {
entry:
%0 = tail call i64 @llvm.lround.i64.f64(double %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}

; CHECK-LABEL: testmsxd:
; CHECK: bl lround
define i64 @testmsxd(double %x) {
entry:
%0 = tail call i64 @llvm.lround.i64.f64(double %x)
ret i64 %0
}

; CHECK-LABEL: testmswl:
; CHECK: bl lroundl
define signext i32 @testmswl(ppc_fp128 %x) {
entry:
%0 = tail call i64 @llvm.lround.i64.ppcf128(ppc_fp128 %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}

; CHECK-LABEL: testmsll:
; CHECK: bl lroundl
define i64 @testmsll(ppc_fp128 %x) {
entry:
%0 = tail call i64 @llvm.lround.i64.ppcf128(ppc_fp128 %x)
ret i64 %0
}

declare i64 @llvm.lround.i64.f32(float) nounwind readnone
declare i64 @llvm.lround.i64.f64(double) nounwind readnone
declare i64 @llvm.lround.i64.ppcf128(ppc_fp128) nounwind readnone
60 changes: 60 additions & 0 deletions llvm/test/CodeGen/X86/llround-conv-i32.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown | FileCheck %s
; RUN: llc < %s -mtriple=i686-unknown -mattr=sse2 | FileCheck %s --check-prefix=SSE2

define i64 @testmsxs_builtin(float %x) {
; CHECK-LABEL: testmsxs_builtin:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushl %eax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: flds {{[0-9]+}}(%esp)
; CHECK-NEXT: fstps (%esp)
; CHECK-NEXT: calll llroundf
; CHECK-NEXT: popl %ecx
; CHECK-NEXT: .cfi_def_cfa_offset 4
; CHECK-NEXT: retl
;
; SSE2-LABEL: testmsxs_builtin:
; SSE2: # %bb.0: # %entry
; SSE2-NEXT: pushl %eax
; SSE2-NEXT: .cfi_def_cfa_offset 8
; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-NEXT: movss %xmm0, (%esp)
; SSE2-NEXT: calll llroundf
; SSE2-NEXT: popl %ecx
; SSE2-NEXT: .cfi_def_cfa_offset 4
; SSE2-NEXT: retl
entry:
%0 = tail call i64 @llvm.llround.f32(float %x)
ret i64 %0
}

define i64 @testmsxd_builtin(double %x) {
; CHECK-LABEL: testmsxd_builtin:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subl $8, %esp
; CHECK-NEXT: .cfi_def_cfa_offset 12
; CHECK-NEXT: fldl {{[0-9]+}}(%esp)
; CHECK-NEXT: fstpl (%esp)
; CHECK-NEXT: calll llround
; CHECK-NEXT: addl $8, %esp
; CHECK-NEXT: .cfi_def_cfa_offset 4
; CHECK-NEXT: retl
;
; SSE2-LABEL: testmsxd_builtin:
; SSE2: # %bb.0: # %entry
; SSE2-NEXT: subl $8, %esp
; SSE2-NEXT: .cfi_def_cfa_offset 12
; SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; SSE2-NEXT: movsd %xmm0, (%esp)
; SSE2-NEXT: calll llround
; SSE2-NEXT: addl $8, %esp
; SSE2-NEXT: .cfi_def_cfa_offset 4
; SSE2-NEXT: retl
entry:
%0 = tail call i64 @llvm.llround.f64(double %x)
ret i64 %0
}

declare i64 @llvm.llround.f32(float) nounwind readnone
declare i64 @llvm.llround.f64(double) nounwind readnone
83 changes: 83 additions & 0 deletions llvm/test/CodeGen/X86/llround-conv.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s

define i32 @testmsws(float %x) {
; CHECK-LABEL: testmsws:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq llroundf
; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
entry:
%0 = tail call i64 @llvm.llround.f32(float %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}

define i64 @testmsxs(float %x) {
; CHECK-LABEL: testmsxs:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: jmp llroundf # TAILCALL
entry:
%0 = tail call i64 @llvm.llround.f32(float %x)
ret i64 %0
}

define i32 @testmswd(double %x) {
; CHECK-LABEL: testmswd:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq llround
; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
entry:
%0 = tail call i64 @llvm.llround.f64(double %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}

define i64 @testmsxd(double %x) {
; CHECK-LABEL: testmsxd:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: jmp llround # TAILCALL
entry:
%0 = tail call i64 @llvm.llround.f64(double %x)
ret i64 %0
}

define i32 @testmswl(x86_fp80 %x) {
; CHECK-LABEL: testmswl:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: fldt {{[0-9]+}}(%rsp)
; CHECK-NEXT: fstpt (%rsp)
; CHECK-NEXT: callq llroundl
; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
entry:
%0 = tail call i64 @llvm.llround.f80(x86_fp80 %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}

define i64 @testmsll(x86_fp80 %x) {
; CHECK-LABEL: testmsll:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: jmp llroundl # TAILCALL
entry:
%0 = tail call i64 @llvm.llround.f80(x86_fp80 %x)
ret i64 %0
}

declare i64 @llvm.llround.f32(float) nounwind readnone
declare i64 @llvm.llround.f64(double) nounwind readnone
declare i64 @llvm.llround.f80(x86_fp80) nounwind readnone
32 changes: 32 additions & 0 deletions llvm/test/CodeGen/X86/lround-conv-i32.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown | FileCheck %s
; RUN: llc < %s -mtriple=i686-unknown -mattr=sse2 | FileCheck %s --check-prefix=SSE2

define i32 @testmsws_builtin(float %x) {
; CHECK-LABEL: testmsws_builtin:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: jmp lroundf # TAILCALL
;
; SSE2-LABEL: testmsws_builtin:
; SSE2: # %bb.0: # %entry
; SSE2-NEXT: jmp lroundf # TAILCALL
entry:
%0 = tail call i32 @llvm.lround.i32.f32(float %x)
ret i32 %0
}

define i32 @testmswd_builtin(double %x) {
; CHECK-LABEL: testmswd_builtin:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: jmp lround # TAILCALL
;
; SSE2-LABEL: testmswd_builtin:
; SSE2: # %bb.0: # %entry
; SSE2-NEXT: jmp lround # TAILCALL
entry:
%0 = tail call i32 @llvm.lround.i32.f64(double %x)
ret i32 %0
}

declare i32 @llvm.lround.i32.f32(float) nounwind readnone
declare i32 @llvm.lround.i32.f64(double) nounwind readnone
83 changes: 83 additions & 0 deletions llvm/test/CodeGen/X86/lround-conv.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s

define i32 @testmsws(float %x) {
; CHECK-LABEL: testmsws:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq lroundf
; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
entry:
%0 = tail call i64 @llvm.lround.i64.f32(float %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}

define i64 @testmsxs(float %x) {
; CHECK-LABEL: testmsxs:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: jmp lroundf # TAILCALL
entry:
%0 = tail call i64 @llvm.lround.i64.f32(float %x)
ret i64 %0
}

define i32 @testmswd(double %x) {
; CHECK-LABEL: testmswd:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq lround
; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
entry:
%0 = tail call i64 @llvm.lround.i64.f64(double %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}

define i64 @testmsxd(double %x) {
; CHECK-LABEL: testmsxd:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: jmp lround # TAILCALL
entry:
%0 = tail call i64 @llvm.lround.i64.f64(double %x)
ret i64 %0
}

define i32 @testmswl(x86_fp80 %x) {
; CHECK-LABEL: testmswl:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: fldt {{[0-9]+}}(%rsp)
; CHECK-NEXT: fstpt (%rsp)
; CHECK-NEXT: callq lroundl
; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
entry:
%0 = tail call i64 @llvm.lround.i64.f80(x86_fp80 %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}

define i64 @testmsll(x86_fp80 %x) {
; CHECK-LABEL: testmsll:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: jmp lroundl # TAILCALL
entry:
%0 = tail call i64 @llvm.lround.i64.f80(x86_fp80 %x)
ret i64 %0
}

declare i64 @llvm.lround.i64.f32(float) nounwind readnone
declare i64 @llvm.lround.i64.f64(double) nounwind readnone
declare i64 @llvm.lround.i64.f80(x86_fp80) nounwind readnone