1 change: 1 addition & 0 deletions llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3008,6 +3008,7 @@ void IRTranslator::finishPendingPhis() {

bool IRTranslator::translate(const Instruction &Inst) {
CurBuilder->setDebugLoc(Inst.getDebugLoc());
CurBuilder->setPCSections(Inst.getMetadata(LLVMContext::MD_pcsections));

auto &TLI = *MF->getSubtarget().getTargetLowering();
if (TLI.fallBackToDAGISel(Inst))
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -27,6 +27,7 @@ void MachineIRBuilder::setMF(MachineFunction &MF) {
State.MRI = &MF.getRegInfo();
State.TII = MF.getSubtarget().getInstrInfo();
State.DL = DebugLoc();
State.PCSections = nullptr;
State.II = MachineBasicBlock::iterator();
State.Observer = nullptr;
}
Expand All @@ -36,8 +37,7 @@ void MachineIRBuilder::setMF(MachineFunction &MF) {
//------------------------------------------------------------------------------

MachineInstrBuilder MachineIRBuilder::buildInstrNoInsert(unsigned Opcode) {
MachineInstrBuilder MIB = BuildMI(getMF(), getDL(), getTII().get(Opcode));
return MIB;
return BuildMI(getMF(), {getDL(), getPCSections()}, getTII().get(Opcode));
}

MachineInstrBuilder MachineIRBuilder::insertInstr(MachineInstrBuilder MIB) {
Expand Down
108 changes: 54 additions & 54 deletions llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
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22 changes: 22 additions & 0 deletions llvm/lib/MC/MCObjectFileInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1198,3 +1198,25 @@ MCObjectFileInfo::getPseudoProbeDescSection(StringRef FuncName) const {
}
return PseudoProbeDescSection;
}

MCSection *MCObjectFileInfo::getPCSection(StringRef Name,
const MCSection *TextSec) const {
if (Ctx->getObjectFileType() != MCContext::IsELF)
return nullptr;

// SHF_WRITE for relocations, and let user post-process data in-place.
unsigned Flags = ELF::SHF_WRITE | ELF::SHF_ALLOC | ELF::SHF_LINK_ORDER;

if (!TextSec)
TextSec = getTextSection();

StringRef GroupName;
const auto &ElfSec = static_cast<const MCSectionELF &>(*TextSec);
if (const MCSymbol *Group = ElfSec.getGroup()) {
GroupName = Group->getName();
Flags |= ELF::SHF_GROUP;
}
return Ctx->getELFSection(Name, ELF::SHT_PROGBITS, Flags, 0, GroupName, true,
ElfSec.getUniqueID(),
cast<MCSymbolELF>(TextSec->getBeginSymbol()));
}
38 changes: 19 additions & 19 deletions llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -186,7 +186,7 @@ bool AArch64ExpandPseudo::expandCMP_SWAP(
unsigned StlrOp, unsigned CmpOp, unsigned ExtendImm, unsigned ZeroReg,
MachineBasicBlock::iterator &NextMBBI) {
MachineInstr &MI = *MBBI;
DebugLoc DL = MI.getDebugLoc();
MIMetadata MIMD(MI);
const MachineOperand &Dest = MI.getOperand(0);
Register StatusReg = MI.getOperand(1).getReg();
bool StatusDead = MI.getOperand(1).isDead();
Expand All @@ -212,15 +212,15 @@ bool AArch64ExpandPseudo::expandCMP_SWAP(
// cmp xDest, xDesired
// b.ne .Ldone
if (!StatusDead)
BuildMI(LoadCmpBB, DL, TII->get(AArch64::MOVZWi), StatusReg)
BuildMI(LoadCmpBB, MIMD, TII->get(AArch64::MOVZWi), StatusReg)
.addImm(0).addImm(0);
BuildMI(LoadCmpBB, DL, TII->get(LdarOp), Dest.getReg())
BuildMI(LoadCmpBB, MIMD, TII->get(LdarOp), Dest.getReg())
.addReg(AddrReg);
BuildMI(LoadCmpBB, DL, TII->get(CmpOp), ZeroReg)
BuildMI(LoadCmpBB, MIMD, TII->get(CmpOp), ZeroReg)
.addReg(Dest.getReg(), getKillRegState(Dest.isDead()))
.addReg(DesiredReg)
.addImm(ExtendImm);
BuildMI(LoadCmpBB, DL, TII->get(AArch64::Bcc))
BuildMI(LoadCmpBB, MIMD, TII->get(AArch64::Bcc))
.addImm(AArch64CC::NE)
.addMBB(DoneBB)
.addReg(AArch64::NZCV, RegState::Implicit | RegState::Kill);
Expand All @@ -230,10 +230,10 @@ bool AArch64ExpandPseudo::expandCMP_SWAP(
// .Lstore:
// stlxr wStatus, xNew, [xAddr]
// cbnz wStatus, .Lloadcmp
BuildMI(StoreBB, DL, TII->get(StlrOp), StatusReg)
BuildMI(StoreBB, MIMD, TII->get(StlrOp), StatusReg)
.addReg(NewReg)
.addReg(AddrReg);
BuildMI(StoreBB, DL, TII->get(AArch64::CBNZW))
BuildMI(StoreBB, MIMD, TII->get(AArch64::CBNZW))
.addReg(StatusReg, getKillRegState(StatusDead))
.addMBB(LoadCmpBB);
StoreBB->addSuccessor(LoadCmpBB);
Expand Down Expand Up @@ -265,7 +265,7 @@ bool AArch64ExpandPseudo::expandCMP_SWAP_128(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
MachineBasicBlock::iterator &NextMBBI) {
MachineInstr &MI = *MBBI;
DebugLoc DL = MI.getDebugLoc();
MIMetadata MIMD(MI);
MachineOperand &DestLo = MI.getOperand(0);
MachineOperand &DestHi = MI.getOperand(1);
Register StatusReg = MI.getOperand(2).getReg();
Expand Down Expand Up @@ -318,27 +318,27 @@ bool AArch64ExpandPseudo::expandCMP_SWAP_128(
// cmp xDestLo, xDesiredLo
// sbcs xDestHi, xDesiredHi
// b.ne .Ldone
BuildMI(LoadCmpBB, DL, TII->get(LdxpOp))
BuildMI(LoadCmpBB, MIMD, TII->get(LdxpOp))
.addReg(DestLo.getReg(), RegState::Define)
.addReg(DestHi.getReg(), RegState::Define)
.addReg(AddrReg);
BuildMI(LoadCmpBB, DL, TII->get(AArch64::SUBSXrs), AArch64::XZR)
BuildMI(LoadCmpBB, MIMD, TII->get(AArch64::SUBSXrs), AArch64::XZR)
.addReg(DestLo.getReg(), getKillRegState(DestLo.isDead()))
.addReg(DesiredLoReg)
.addImm(0);
BuildMI(LoadCmpBB, DL, TII->get(AArch64::CSINCWr), StatusReg)
BuildMI(LoadCmpBB, MIMD, TII->get(AArch64::CSINCWr), StatusReg)
.addUse(AArch64::WZR)
.addUse(AArch64::WZR)
.addImm(AArch64CC::EQ);
BuildMI(LoadCmpBB, DL, TII->get(AArch64::SUBSXrs), AArch64::XZR)
BuildMI(LoadCmpBB, MIMD, TII->get(AArch64::SUBSXrs), AArch64::XZR)
.addReg(DestHi.getReg(), getKillRegState(DestHi.isDead()))
.addReg(DesiredHiReg)
.addImm(0);
BuildMI(LoadCmpBB, DL, TII->get(AArch64::CSINCWr), StatusReg)
BuildMI(LoadCmpBB, MIMD, TII->get(AArch64::CSINCWr), StatusReg)
.addUse(StatusReg, RegState::Kill)
.addUse(StatusReg, RegState::Kill)
.addImm(AArch64CC::EQ);
BuildMI(LoadCmpBB, DL, TII->get(AArch64::CBNZW))
BuildMI(LoadCmpBB, MIMD, TII->get(AArch64::CBNZW))
.addUse(StatusReg, getKillRegState(StatusDead))
.addMBB(FailBB);
LoadCmpBB->addSuccessor(FailBB);
Expand All @@ -347,25 +347,25 @@ bool AArch64ExpandPseudo::expandCMP_SWAP_128(
// .Lstore:
// stlxp wStatus, xNewLo, xNewHi, [xAddr]
// cbnz wStatus, .Lloadcmp
BuildMI(StoreBB, DL, TII->get(StxpOp), StatusReg)
BuildMI(StoreBB, MIMD, TII->get(StxpOp), StatusReg)
.addReg(NewLoReg)
.addReg(NewHiReg)
.addReg(AddrReg);
BuildMI(StoreBB, DL, TII->get(AArch64::CBNZW))
BuildMI(StoreBB, MIMD, TII->get(AArch64::CBNZW))
.addReg(StatusReg, getKillRegState(StatusDead))
.addMBB(LoadCmpBB);
BuildMI(StoreBB, DL, TII->get(AArch64::B)).addMBB(DoneBB);
BuildMI(StoreBB, MIMD, TII->get(AArch64::B)).addMBB(DoneBB);
StoreBB->addSuccessor(LoadCmpBB);
StoreBB->addSuccessor(DoneBB);

// .Lfail:
// stlxp wStatus, xDestLo, xDestHi, [xAddr]
// cbnz wStatus, .Lloadcmp
BuildMI(FailBB, DL, TII->get(StxpOp), StatusReg)
BuildMI(FailBB, MIMD, TII->get(StxpOp), StatusReg)
.addReg(DestLo.getReg())
.addReg(DestHi.getReg())
.addReg(AddrReg);
BuildMI(FailBB, DL, TII->get(AArch64::CBNZW))
BuildMI(FailBB, MIMD, TII->get(AArch64::CBNZW))
.addReg(StatusReg, getKillRegState(StatusDead))
.addMBB(LoadCmpBB);
FailBB->addSuccessor(LoadCmpBB);
Expand Down
142 changes: 71 additions & 71 deletions llvm/lib/Target/AArch64/AArch64FastISel.cpp
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142 changes: 71 additions & 71 deletions llvm/lib/Target/ARM/ARMFastISel.cpp
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24 changes: 12 additions & 12 deletions llvm/lib/Target/Mips/MipsFastISel.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -204,11 +204,11 @@ class MipsFastISel final : public FastISel {
unsigned materializeExternalCallSym(MCSymbol *Syn);

MachineInstrBuilder emitInst(unsigned Opc) {
return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc));
}

MachineInstrBuilder emitInst(unsigned Opc, unsigned DstReg) {
return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc),
DstReg);
}

Expand Down Expand Up @@ -338,7 +338,7 @@ unsigned MipsFastISel::fastMaterializeAlloca(const AllocaInst *AI) {

if (SI != FuncInfo.StaticAllocaMap.end()) {
Register ResultReg = createResultReg(&Mips::GPR32RegClass);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::LEA_ADDiu),
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Mips::LEA_ADDiu),
ResultReg)
.addFrameIndex(SI->second)
.addImm(0);
Expand Down Expand Up @@ -794,7 +794,7 @@ bool MipsFastISel::emitLoad(MVT VT, unsigned &ResultReg, Address &Addr) {
MachineMemOperand *MMO = MF->getMachineMemOperand(
MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad,
MFI.getObjectSize(FI), Align(4));
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), ResultReg)
.addFrameIndex(FI)
.addImm(Offset)
.addMemOperand(MMO);
Expand Down Expand Up @@ -843,7 +843,7 @@ bool MipsFastISel::emitStore(MVT VT, unsigned SrcReg, Address &Addr) {
MachineMemOperand *MMO = MF->getMachineMemOperand(
MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore,
MFI.getObjectSize(FI), Align(4));
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc))
.addReg(SrcReg)
.addFrameIndex(FI)
.addImm(Offset)
Expand Down Expand Up @@ -967,7 +967,7 @@ bool MipsFastISel::selectBranch(const Instruction *I) {
return false;
}

BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::BGTZ))
BuildMI(*BrBB, FuncInfo.InsertPt, MIMD, TII.get(Mips::BGTZ))
.addReg(ZExtCondReg)
.addMBB(TBB);
finishCondBranch(BI->getParent(), TBB, FBB);
Expand Down Expand Up @@ -1221,7 +1221,7 @@ bool MipsFastISel::processCallArgs(CallLoweringInfo &CLI,

// Now copy/store arg to correct locations.
if (VA.isRegLoc() && !VA.needsCustom()) {
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
CLI.OutRegs.push_back(VA.getLocReg());
} else if (VA.needsCustom()) {
Expand Down Expand Up @@ -1291,7 +1291,7 @@ bool MipsFastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT,
Register ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
if (!ResultReg)
return false;
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
TII.get(TargetOpcode::COPY),
ResultReg).addReg(RVLocs[0].getLocReg());
CLI.InRegs.push_back(RVLocs[0].getLocReg());
Expand Down Expand Up @@ -1461,7 +1461,7 @@ bool MipsFastISel::fastLowerArguments() {
// Without this, EmitLiveInCopies may eliminate the livein if its only
// use is a bitcast (which isn't turned into an instruction).
Register ResultReg = createResultReg(Allocation[ArgNo].RC);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
TII.get(TargetOpcode::COPY), ResultReg)
.addReg(DstReg, getKillRegState(true));
updateValueMap(&FormalArg, ResultReg);
Expand Down Expand Up @@ -1550,7 +1550,7 @@ bool MipsFastISel::fastLowerCall(CallLoweringInfo &CLI) {
DestAddress = materializeGV(Addr.getGlobalValue(), MVT::i32);
emitInst(TargetOpcode::COPY, Mips::T9).addReg(DestAddress);
MachineInstrBuilder MIB =
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::JALR),
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Mips::JALR),
Mips::RA).addReg(Mips::T9);

// Add implicit physical register uses to the call.
Expand Down Expand Up @@ -1756,7 +1756,7 @@ bool MipsFastISel::selectRet(const Instruction *I) {
}

// Make the copy.
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);

// Add register to return instruction.
Expand Down Expand Up @@ -2127,7 +2127,7 @@ unsigned MipsFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
const MCInstrDesc &II = TII.get(MachineInstOpcode);
Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II, ResultReg)
.addReg(Op0)
.addReg(Op1)
.addReg(Mips::HI0, RegState::ImplicitDefine | RegState::Dead)
Expand Down
110 changes: 55 additions & 55 deletions llvm/lib/Target/PowerPC/PPCFastISel.cpp
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50 changes: 25 additions & 25 deletions llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -388,7 +388,7 @@ void WebAssemblyFastISel::materializeLoadStoreOperands(Address &Addr) {
: &WebAssembly::I32RegClass);
unsigned Opc = Subtarget->hasAddr64() ? WebAssembly::CONST_I64
: WebAssembly::CONST_I32;
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), Reg)
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), Reg)
.addImm(0);
Addr.setReg(Reg);
}
Expand Down Expand Up @@ -460,12 +460,12 @@ unsigned WebAssemblyFastISel::zeroExtendToI32(unsigned Reg, const Value *V,
}

Register Imm = createResultReg(&WebAssembly::I32RegClass);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
TII.get(WebAssembly::CONST_I32), Imm)
.addImm(~(~uint64_t(0) << MVT(From).getSizeInBits()));

Register Result = createResultReg(&WebAssembly::I32RegClass);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
TII.get(WebAssembly::AND_I32), Result)
.addReg(Reg)
.addReg(Imm);
Expand All @@ -490,18 +490,18 @@ unsigned WebAssemblyFastISel::signExtendToI32(unsigned Reg, const Value *V,
}

Register Imm = createResultReg(&WebAssembly::I32RegClass);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
TII.get(WebAssembly::CONST_I32), Imm)
.addImm(32 - MVT(From).getSizeInBits());

Register Left = createResultReg(&WebAssembly::I32RegClass);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
TII.get(WebAssembly::SHL_I32), Left)
.addReg(Reg)
.addReg(Imm);

Register Right = createResultReg(&WebAssembly::I32RegClass);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
TII.get(WebAssembly::SHR_S_I32), Right)
.addReg(Left)
.addReg(Imm);
Expand All @@ -519,7 +519,7 @@ unsigned WebAssemblyFastISel::zeroExtend(unsigned Reg, const Value *V,
Reg = zeroExtendToI32(Reg, V, From);

Register Result = createResultReg(&WebAssembly::I64RegClass);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
TII.get(WebAssembly::I64_EXTEND_U_I32), Result)
.addReg(Reg);
return Result;
Expand All @@ -541,7 +541,7 @@ unsigned WebAssemblyFastISel::signExtend(unsigned Reg, const Value *V,
Reg = signExtendToI32(Reg, V, From);

Register Result = createResultReg(&WebAssembly::I64RegClass);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
TII.get(WebAssembly::I64_EXTEND_S_I32), Result)
.addReg(Reg);
return Result;
Expand Down Expand Up @@ -580,15 +580,15 @@ unsigned WebAssemblyFastISel::notValue(unsigned Reg) {
assert(MRI.getRegClass(Reg) == &WebAssembly::I32RegClass);

Register NotReg = createResultReg(&WebAssembly::I32RegClass);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
TII.get(WebAssembly::EQZ_I32), NotReg)
.addReg(Reg);
return NotReg;
}

unsigned WebAssemblyFastISel::copyValue(unsigned Reg) {
Register ResultReg = createResultReg(MRI.getRegClass(Reg));
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(WebAssembly::COPY),
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(WebAssembly::COPY),
ResultReg)
.addReg(Reg);
return ResultReg;
Expand All @@ -604,7 +604,7 @@ unsigned WebAssemblyFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
: &WebAssembly::I32RegClass);
unsigned Opc =
Subtarget->hasAddr64() ? WebAssembly::COPY_I64 : WebAssembly::COPY_I32;
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), ResultReg)
.addFrameIndex(SI->second);
return ResultReg;
}
Expand All @@ -623,7 +623,7 @@ unsigned WebAssemblyFastISel::fastMaterializeConstant(const Constant *C) {
: &WebAssembly::I32RegClass);
unsigned Opc = Subtarget->hasAddr64() ? WebAssembly::CONST_I64
: WebAssembly::CONST_I32;
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), ResultReg)
.addGlobalAddress(GV);
return ResultReg;
}
Expand Down Expand Up @@ -717,7 +717,7 @@ bool WebAssemblyFastISel::fastLowerArguments() {
return false;
}
Register ResultReg = createResultReg(RC);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), ResultReg)
.addImm(I);
updateValueMap(&Arg, ResultReg);

Expand Down Expand Up @@ -859,7 +859,7 @@ bool WebAssemblyFastISel::selectCall(const Instruction *I) {
return false;
}

auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc));

if (!IsVoid)
MIB.addReg(ResultReg, RegState::Define);
Expand All @@ -886,7 +886,7 @@ bool WebAssemblyFastISel::selectCall(const Instruction *I) {
// as 64-bit for uniformity with other pointer types.
// See also: WebAssemblyISelLowering.cpp: LowerCallResults
if (Subtarget->hasAddr64()) {
auto Wrap = BuildMI(*FuncInfo.MBB, std::prev(FuncInfo.InsertPt), DbgLoc,
auto Wrap = BuildMI(*FuncInfo.MBB, std::prev(FuncInfo.InsertPt), MIMD,
TII.get(WebAssembly::I32_WRAP_I64));
Register Reg32 = createResultReg(&WebAssembly::I32RegClass);
Wrap.addReg(Reg32, RegState::Define);
Expand Down Expand Up @@ -961,7 +961,7 @@ bool WebAssemblyFastISel::selectSelect(const Instruction *I) {
}

Register ResultReg = createResultReg(RC);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), ResultReg)
.addReg(TrueReg)
.addReg(FalseReg)
.addReg(CondReg);
Expand All @@ -979,7 +979,7 @@ bool WebAssemblyFastISel::selectTrunc(const Instruction *I) {

if (Trunc->getOperand(0)->getType()->isIntegerTy(64)) {
Register Result = createResultReg(&WebAssembly::I32RegClass);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
TII.get(WebAssembly::I32_WRAP_I64), Result)
.addReg(Reg);
Reg = Result;
Expand Down Expand Up @@ -1077,7 +1077,7 @@ bool WebAssemblyFastISel::selectICmp(const Instruction *I) {
return false;

Register ResultReg = createResultReg(&WebAssembly::I32RegClass);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), ResultReg)
.addReg(LHS)
.addReg(RHS);
updateValueMap(ICmp, ResultReg);
Expand Down Expand Up @@ -1138,7 +1138,7 @@ bool WebAssemblyFastISel::selectFCmp(const Instruction *I) {
}

Register ResultReg = createResultReg(&WebAssembly::I32RegClass);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), ResultReg)
.addReg(LHS)
.addReg(RHS);

Expand Down Expand Up @@ -1231,7 +1231,7 @@ bool WebAssemblyFastISel::selectLoad(const Instruction *I) {
materializeLoadStoreOperands(Addr);

Register ResultReg = createResultReg(RC);
auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc),
ResultReg);

addLoadStoreOperands(Addr, MIB, createMachineMemOperandFor(Load));
Expand Down Expand Up @@ -1291,7 +1291,7 @@ bool WebAssemblyFastISel::selectStore(const Instruction *I) {
if (VTIsi1)
ValueReg = maskI1Value(ValueReg, Store->getValueOperand());

auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc));

addLoadStoreOperands(Addr, MIB, createMachineMemOperandFor(Store));

Expand Down Expand Up @@ -1319,7 +1319,7 @@ bool WebAssemblyFastISel::selectBr(const Instruction *I) {
if (Not)
Opc = WebAssembly::BR_UNLESS;

BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc))
.addMBB(TBB)
.addReg(CondReg);

Expand All @@ -1334,7 +1334,7 @@ bool WebAssemblyFastISel::selectRet(const Instruction *I) {
const auto *Ret = cast<ReturnInst>(I);

if (Ret->getNumOperands() == 0) {
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
TII.get(WebAssembly::RETURN));
return true;
}
Expand Down Expand Up @@ -1379,14 +1379,14 @@ bool WebAssemblyFastISel::selectRet(const Instruction *I) {
if (Reg == 0)
return false;

BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
TII.get(WebAssembly::RETURN))
.addReg(Reg);
return true;
}

bool WebAssemblyFastISel::selectUnreachable(const Instruction *I) {
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
TII.get(WebAssembly::UNREACHABLE));
return true;
}
Expand Down
204 changes: 102 additions & 102 deletions llvm/lib/Target/X86/X86FastISel.cpp
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117 changes: 117 additions & 0 deletions llvm/test/CodeGen/AArch64/pcsections.ll
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Original file line number Diff line number Diff line change
@@ -0,0 +1,117 @@
; RUN: llc -O0 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-UNOPT,DEFCM
; RUN: llc -O1 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPT,DEFCM
; RUN: llc -O2 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPT,DEFCM
; RUN: llc -O3 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPT,DEFCM
; RUN: llc -O1 -code-model=large < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPT,LARGE

target triple = "aarch64-unknown-linux-gnu"

@foo = dso_local global i64 0, align 8
@bar = dso_local global i64 0, align 8

define i64 @multiple() !pcsections !0 {
; CHECK-LABEL: multiple:
; CHECK: .Lfunc_begin0:
; CHECK: // %bb.0: // %entry
; CHECK: .Lpcsection0:
; CHECK-NEXT: ldr
; CHECK-NEXT: ret
; CHECK: .section section_no_aux,"awo",@progbits,.text
; CHECK-NEXT: .Lpcsection_base0:
; DEFCM-NEXT: .word .Lfunc_begin0-.Lpcsection_base0
; LARGE-NEXT: .xword .Lfunc_begin0-.Lpcsection_base0
; CHECK-NEXT: .word .Lfunc_end0-.Lfunc_begin0
; CHECK-NEXT: .section section_aux_42,"awo",@progbits,.text
; CHECK-NEXT: .Lpcsection_base1:
; DEFCM-NEXT: .word .Lpcsection0-.Lpcsection_base1
; LARGE-NEXT: .xword .Lpcsection0-.Lpcsection_base1
; CHECK-NEXT: .word 42
; CHECK-NEXT: .section section_aux_21264,"awo",@progbits,.text
; CHECK-NEXT: .Lpcsection_base2:
; DEFCM-NEXT: .word .Lpcsection0-.Lpcsection_base2
; LARGE-NEXT: .xword .Lpcsection0-.Lpcsection_base2
; CHECK-NEXT: .word 21264
; CHECK-NEXT: .text
entry:
%0 = load i64, i64* @bar, align 8, !pcsections !1
ret i64 %0
}

define i64 @test_simple_atomic() {
; CHECK-LABEL: test_simple_atomic:
; CHECK: .Lpcsection1:
; CHECK-NEXT: ldr
; CHECK-NOT: .Lpcsection2
; CHECK: ldr
; CHECK: add
; CHECK-NEXT: ret
; CHECK: .section section_no_aux,"awo",@progbits,.text
; CHECK-NEXT: .Lpcsection_base3:
; DEFCM-NEXT: .word .Lpcsection1-.Lpcsection_base3
; LARGE-NEXT: .xword .Lpcsection1-.Lpcsection_base3
; CHECK-NEXT: .text
entry:
%0 = load atomic i64, i64* @foo monotonic, align 8, !pcsections !0
%1 = load i64, i64* @bar, align 8
%add = add nsw i64 %1, %0
ret i64 %add
}

define i64 @test_complex_atomic() {
; CHECK-LABEL: test_complex_atomic:
; ---
; CHECK-OPT: .Lpcsection2:
; CHECK-OPT-NEXT: ldxr
; CHECK-OPT: .Lpcsection3:
; CHECK-OPT-NEXT: add
; CHECK-OPT: .Lpcsection4:
; CHECK-OPT-NEXT: stxr
; CHECK-OPT: .Lpcsection5:
; CHECK-OPT-NEXT: cbnz
; ---
; CHECK-UNOPT: .Lpcsection2:
; CHECK-UNOPT-NEXT: ldr
; CHECK-UNOPT: .Lpcsection4:
; CHECK-UNOPT-NEXT: add
; CHECK-UNOPT: .Lpcsection5:
; CHECK-UNOPT-NEXT: ldaxr
; CHECK-UNOPT: .Lpcsection6:
; CHECK-UNOPT-NEXT: cmp
; CHECK-UNOPT: .Lpcsection8:
; CHECK-UNOPT-NEXT: stlxr
; CHECK-UNOPT: .Lpcsection9:
; CHECK-UNOPT-NEXT: cbnz
; CHECK-UNOPT: .Lpcsection12:
; CHECK-UNOPT-NEXT: b
; ---
; CHECK-NOT: .Lpcsection
; CHECK: ldr
; CHECK: ret
; CHECK: .section section_no_aux,"awo",@progbits,.text
; CHECK-NEXT: .Lpcsection_base4:
; DEFCM-NEXT: .word .Lpcsection2-.Lpcsection_base4
; LARGE-NEXT: .xword .Lpcsection2-.Lpcsection_base4
; CHECK-NEXT: .Lpcsection_base5:
; DEFCM-NEXT: .word .Lpcsection3-.Lpcsection_base5
; LARGE-NEXT: .xword .Lpcsection3-.Lpcsection_base5
; CHECK-NEXT: .Lpcsection_base6:
; DEFCM-NEXT: .word .Lpcsection4-.Lpcsection_base6
; LARGE-NEXT: .xword .Lpcsection4-.Lpcsection_base6
; CHECK-NEXT: .Lpcsection_base7:
; DEFCM-NEXT: .word .Lpcsection5-.Lpcsection_base7
; LARGE-NEXT: .xword .Lpcsection5-.Lpcsection_base7
; CHECK-UNOPT: .word .Lpcsection12-.Lpcsection_base14
; CHECK-NEXT: .text
entry:
%0 = atomicrmw add i64* @foo, i64 1 monotonic, align 8, !pcsections !0
%1 = load i64, i64* @bar, align 8
%inc = add nsw i64 %1, 1
store i64 %inc, i64* @bar, align 8
%add = add nsw i64 %1, %0
ret i64 %add
}

!0 = !{!"section_no_aux"}
!1 = !{!"section_aux_42", !2, !"section_aux_21264", !3}
!2 = !{i32 42}
!3 = !{i32 21264}
125 changes: 125 additions & 0 deletions llvm/test/CodeGen/X86/pcsections.ll
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Original file line number Diff line number Diff line change
@@ -0,0 +1,125 @@
; RUN: llc -O0 < %s | FileCheck %s --check-prefixes=CHECK,DEFCM
; RUN: llc -O1 < %s | FileCheck %s --check-prefixes=CHECK,DEFCM
; RUN: llc -O2 < %s | FileCheck %s --check-prefixes=CHECK,DEFCM
; RUN: llc -O3 < %s | FileCheck %s --check-prefixes=CHECK,DEFCM
; RUN: llc -O1 -code-model=large < %s | FileCheck %s --check-prefixes=CHECK,LARGE

target triple = "x86_64-unknown-linux-gnu"

@foo = dso_local global i64 0, align 8
@bar = dso_local global i64 0, align 8

define void @empty_no_aux() !pcsections !0 {
; CHECK-LABEL: empty_no_aux:
; CHECK-NEXT: .Lfunc_begin0
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: retq
; CHECK-NEXT: .Lfunc_end0:
; CHECK: .section section_no_aux,"awo",@progbits,.text
; CHECK-NEXT: .Lpcsection_base0:
; DEFCM-NEXT: .long .Lfunc_begin0-.Lpcsection_base0
; LARGE-NEXT: .quad .Lfunc_begin0-.Lpcsection_base0
; CHECK-NEXT: .long .Lfunc_end0-.Lfunc_begin0
; CHECK-NEXT: .text
entry:
ret void
}

define void @empty_aux() !pcsections !1 {
; CHECK-LABEL: empty_aux:
; CHECK-NEXT: .Lfunc_begin1
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: retq
; CHECK-NEXT: .Lfunc_end1:
; CHECK: .section section_aux,"awo",@progbits,.text
; CHECK-NEXT: .Lpcsection_base1:
; DEFCM-NEXT: .long .Lfunc_begin1-.Lpcsection_base1
; LARGE-NEXT: .quad .Lfunc_begin1-.Lpcsection_base1
; CHECK-NEXT: .long .Lfunc_end1-.Lfunc_begin1
; CHECK-NEXT: .long 10
; CHECK-NEXT: .long 20
; CHECK-NEXT: .long 30
; CHECK-NEXT: .text
entry:
ret void
}

define i64 @multiple() !pcsections !0 {
; CHECK-LABEL: multiple:
; CHECK-NEXT: .Lfunc_begin2
; CHECK: # %bb.0: # %entry
; CHECK: .Lpcsection0:
; CHECK-NEXT: movq
; CHECK-NEXT: retq
; CHECK-NEXT: .Lfunc_end2:
; CHECK: .section section_no_aux,"awo",@progbits,.text
; CHECK-NEXT: .Lpcsection_base2:
; DEFCM-NEXT: .long .Lfunc_begin2-.Lpcsection_base2
; LARGE-NEXT: .quad .Lfunc_begin2-.Lpcsection_base2
; CHECK-NEXT: .long .Lfunc_end2-.Lfunc_begin2
; CHECK-NEXT: .section section_aux_42,"awo",@progbits,.text
; CHECK-NEXT: .Lpcsection_base3:
; DEFCM-NEXT: .long .Lpcsection0-.Lpcsection_base3
; LARGE-NEXT: .quad .Lpcsection0-.Lpcsection_base3
; CHECK-NEXT: .long 42
; CHECK-NEXT: .section section_aux_21264,"awo",@progbits,.text
; CHECK-NEXT: .Lpcsection_base4:
; DEFCM-NEXT: .long .Lpcsection0-.Lpcsection_base4
; LARGE-NEXT: .quad .Lpcsection0-.Lpcsection_base4
; CHECK-NEXT: .long 21264
; CHECK-NEXT: .text
entry:
%0 = load i64, i64* @bar, align 8, !pcsections !2
ret i64 %0
}

define i64 @test_simple_atomic() {
; CHECK-LABEL: test_simple_atomic:
; CHECK: .Lpcsection1:
; CHECK-NEXT: movq
; CHECK-NOT: .Lpcsection
; CHECK: addq
; CHECK-NEXT: retq
; CHECK-NEXT: .Lfunc_end3:
; CHECK: .section section_no_aux,"awo",@progbits,.text
; CHECK-NEXT: .Lpcsection_base5:
; DEFCM-NEXT: .long .Lpcsection1-.Lpcsection_base5
; LARGE-NEXT: .quad .Lpcsection1-.Lpcsection_base5
; CHECK-NEXT: .text
entry:
%0 = load atomic i64, i64* @foo monotonic, align 8, !pcsections !0
%1 = load i64, i64* @bar, align 8
%add = add nsw i64 %1, %0
ret i64 %add
}

define i64 @test_complex_atomic() {
; CHECK-LABEL: test_complex_atomic:
; CHECK: movl $1
; CHECK-NEXT: .Lpcsection2:
; CHECK-NEXT: lock xaddq
; CHECK-NOT: .Lpcsection
; CHECK: movq
; CHECK: addq
; CHECK: retq
; CHECK-NEXT: .Lfunc_end4:
; CHECK: .section section_no_aux,"awo",@progbits,.text
; CHECK-NEXT: .Lpcsection_base6:
; DEFCM-NEXT: .long .Lpcsection2-.Lpcsection_base6
; LARGE-NEXT: .quad .Lpcsection2-.Lpcsection_base6
; CHECK-NEXT: .text
entry:
%0 = atomicrmw add i64* @foo, i64 1 monotonic, align 8, !pcsections !0
%1 = load i64, i64* @bar, align 8
%inc = add nsw i64 %1, 1
store i64 %inc, i64* @bar, align 8
%add = add nsw i64 %1, %0
ret i64 %add
}

!0 = !{!"section_no_aux"}
!1 = !{!"section_aux", !3}
!2 = !{!"section_aux_42", !4, !"section_aux_21264", !5}
!3 = !{i32 10, i32 20, i32 30}
!4 = !{i32 42}
!5 = !{i32 21264}
4,376 changes: 4,376 additions & 0 deletions llvm/test/Transforms/AtomicExpand/AArch64/pcsections.ll
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2 changes: 1 addition & 1 deletion llvm/utils/TableGen/FastISelEmitter.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -655,7 +655,7 @@ void FastISelMap::emitInstructionCode(raw_ostream &OS,

for (unsigned i = 0; i < Memo.PhysRegs.size(); ++i) {
if (Memo.PhysRegs[i] != "")
OS << " BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, "
OS << " BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, "
<< "TII.get(TargetOpcode::COPY), " << Memo.PhysRegs[i]
<< ").addReg(Op" << i << ");\n";
}
Expand Down