diff --git a/llvm/test/MC/RISCV/priv-rv64-valid.s b/llvm/test/MC/RISCV/priv-rv64-valid.s
@@ -0,0 +1,38 @@
+# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
+# RUN:     | llvm-objdump -M no-aliases -d - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST %s
+
+# RUN: not llvm-mc -triple riscv32 < %s 2>&1 \
+# RUN:     | FileCheck -check-prefix=CHECK-RV32 %s
+
+# CHECK-INST: hlv.wu a0, (a1)
+# CHECK: encoding: [0x73,0xc5,0x15,0x68]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
+hlv.wu   a0, (a1)
+
+# CHECK-INST: hlv.wu a0, (a1)
+# CHECK: encoding: [0x73,0xc5,0x15,0x68]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
+hlv.wu   a0, 0(a1)
+
+# CHECK-INST: hlv.d a0, (a1)
+# CHECK: encoding: [0x73,0xc5,0x05,0x6c]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
+hlv.d  a0, (a1)
+
+# CHECK-INST: hlv.d a0, (a1)
+# CHECK: encoding: [0x73,0xc5,0x05,0x6c]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
+hlv.d  a0, 0(a1)
+
+# CHECK-INST: hsv.d a0, (a1)
+# CHECK: encoding: [0x73,0xc0,0xa5,0x6e]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
+hsv.d   a0, (a1)
+
+# CHECK-INST: hsv.d a0, (a1)
+# CHECK: encoding: [0x73,0xc0,0xa5,0x6e]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
+hsv.d   a0, 0(a1)
diff --git a/llvm/test/MC/RISCV/priv-valid.s b/llvm/test/MC/RISCV/priv-valid.s
@@ -32,3 +32,91 @@ sfence.vma zero, zero
 # CHECK-INST: sfence.vma a0, a1
 # CHECK: encoding: [0x73,0x00,0xb5,0x12]
 sfence.vma a0, a1
+
+# CHECK-INST: sinval.vma zero, zero
+# CHECK: encoding: [0x73,0x00,0x00,0x16]
+sinval.vma zero, zero
+
+# CHECK-INST: sinval.vma a0, a1
+# CHECK: encoding: [0x73,0x00,0xb5,0x16]
+sinval.vma a0, a1
+
+# CHECK-INST: sfence.w.inval
+# CHECK: encoding: [0x73,0x00,0x00,0x18]
+sfence.w.inval
+
+# CHECK-INST: sfence.inval.ir
+# CHECK: encoding: [0x73,0x00,0x10,0x18]
+sfence.inval.ir
+
+# CHECK-INST: hfence.vvma zero, zero
+# CHECK: encoding: [0x73,0x00,0x00,0x22]
+hfence.vvma zero, zero
+
+# CHECK-INST: hfence.vvma a0, a1
+# CHECK: encoding: [0x73,0x00,0xb5,0x22]
+hfence.vvma a0, a1
+
+# CHECK-INST: hfence.gvma zero, zero
+# CHECK: encoding: [0x73,0x00,0x00,0x62]
+hfence.gvma zero, zero
+
+# CHECK-INST: hfence.gvma a0, a1
+# CHECK: encoding: [0x73,0x00,0xb5,0x62]
+hfence.gvma a0, a1
+
+# CHECK-INST: hinval.vvma zero, zero
+# CHECK: encoding: [0x73,0x00,0x00,0x26]
+hinval.vvma zero, zero
+
+# CHECK-INST: hinval.vvma a0, a1
+# CHECK: encoding: [0x73,0x00,0xb5,0x26]
+hinval.vvma a0, a1
+
+# CHECK-INST: hinval.gvma zero, zero
+# CHECK: encoding: [0x73,0x00,0x00,0x66]
+hinval.gvma zero, zero
+
+# CHECK-INST: hinval.gvma a0, a1
+# CHECK: encoding: [0x73,0x00,0xb5,0x66]
+hinval.gvma a0, a1
+
+# CHECK-INST: hlv.b a0, (a1)
+# CHECK: encoding: [0x73,0xc5,0x05,0x60]
+hlv.b   a0, (a1)
+
+# CHECK-INST: hlv.bu a0, (a1)
+# CHECK: encoding: [0x73,0xc5,0x15,0x60]
+hlv.bu  a0, (a1)
+
+# CHECK-INST: hlv.h a1, (a2)
+# CHECK: encoding: [0xf3,0x45,0x06,0x64]
+hlv.h   a1, (a2)
+
+# CHECK-INST: hlv.hu a1, (a1)
+# CHECK: encoding: [0xf3,0xc5,0x15,0x64]
+hlv.hu  a1, (a1)
+
+# CHECK-INST: hlvx.hu a1, (a2)
+# CHECK: encoding: [0xf3,0x45,0x36,0x64]
+hlvx.hu a1, (a2)
+
+# CHECK-INST: hlv.w a2, (a2)
+# CHECK: encoding: [0x73,0x46,0x06,0x68]
+hlv.w   a2, (a2)
+
+# CHECK-INST: hlvx.wu a2, (a3)
+# CHECK: encoding: [0x73,0xc6,0x36,0x68]
+hlvx.wu a2, (a3)
+
+# CHECK-INST: hsv.b a0, (a1)
+# CHECK: encoding: [0x73,0xc0,0xa5,0x62]
+hsv.b   a0, (a1)
+
+# CHECK-INST: hsv.h a0, (a1)
+# CHECK: encoding: [0x73,0xc0,0xa5,0x66]
+hsv.h   a0, (a1)
+
+# CHECK-INST: hsv.w a0, (a1)
+# CHECK: encoding: [0x73,0xc0,0xa5,0x6a]
+hsv.w   a0, (a1)
diff --git a/llvm/test/MC/RISCV/rvi-aliases-valid.s b/llvm/test/MC/RISCV/rvi-aliases-valid.s
@@ -256,6 +256,12 @@ sfence.vma
 # CHECK-S-OBJ-NOALIAS: sfence.vma a0, zero
 # CHECK-S-OBJ: sfence.vma a0
 sfence.vma a0
+# CHECK-S-OBJ-NOALIAS: hfence.gvma zero, zero
+# CHECK-S-OBJ: hfence.gvma
+hfence.gvma
+# CHECK-S-OBJ-NOALIAS: hfence.gvma a0, zero
+# CHECK-S-OBJ: hfence.gvma a0
+hfence.gvma a0
 
 # The following aliases are accepted as input but the canonical form
 # of the instruction will always be printed.