33 changes: 31 additions & 2 deletions clang/test/SemaCXX/warn-unused-variables.cpp
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Original file line number Diff line number Diff line change
@@ -1,5 +1,7 @@
// RUN: %clang_cc1 -fsyntax-only -Wunused-variable -Wunused-label -Wno-c++1y-extensions -verify %s
// RUN: %clang_cc1 -fsyntax-only -Wunused-variable -Wunused-label -Wno-c++1y-extensions -verify -std=gnu++11 %s
// RUN: %clang_cc1 -fsyntax-only -Wunused-variable -Wunused-label -Wno-c++1y-extensions -verify=expected,cxx98-14 -std=gnu++11 %s
// RUN: %clang_cc1 -fsyntax-only -Wunused-variable -Wunused-label -Wno-c++1y-extensions -verify=expected,cxx98-14 -std=gnu++14 %s
// RUN: %clang_cc1 -fsyntax-only -Wunused-variable -Wunused-label -Wno-c++1y-extensions -verify -std=gnu++17 %s
template<typename T> void f() {
T t;
t = 17;
Expand Down Expand Up @@ -183,7 +185,8 @@ void foo(int size) {
NonTriviallyDestructible array[2]; // no warning
NonTriviallyDestructible nestedArray[2][2]; // no warning

Foo fooScalar = 1; // expected-warning {{unused variable 'fooScalar'}}
// Copy initialzation gives warning before C++17
Foo fooScalar = 1; // cxx98-14-warning {{unused variable 'fooScalar'}}
Foo fooArray[] = {1,2}; // expected-warning {{unused variable 'fooArray'}}
Foo fooNested[2][2] = { {1,2}, {3,4} }; // expected-warning {{unused variable 'fooNested'}}
}
Expand Down Expand Up @@ -297,3 +300,29 @@ void RAIIWrapperTest() {
}

} // namespace gh54489

// Ensure that -Wunused-variable does not emit warning
// on copy constructors with side effects (C++17 and later)
#if __cplusplus >= 201703L
namespace gh79518 {

struct S {
S(int);
};

// With an initializer list
struct A {
int x;
A(int x) : x(x) {}
};

void foo() {
S s(0); // no warning
S s2 = 0; // no warning
S s3{0}; // no warning

A a = 1; // no warning
}

} // namespace gh79518
#endif
27 changes: 27 additions & 0 deletions clang/test/SemaHLSL/BuiltIns/round-errors.hlsl
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@@ -0,0 +1,27 @@

// RUN: %clang_cc1 -finclude-default-header -triple dxil-pc-shadermodel6.6-library %s -fnative-half-type -emit-llvm -disable-llvm-passes -verify -verify-ignore-unexpected

float test_too_few_arg() {
return __builtin_elementwise_round();
// expected-error@-1 {{too few arguments to function call, expected 1, have 0}}
}

float2 test_too_many_arg(float2 p0) {
return __builtin_elementwise_round(p0, p0);
// expected-error@-1 {{too many arguments to function call, expected 1, have 2}}
}

float builtin_bool_to_float_type_promotion(bool p1) {
return __builtin_elementwise_round(p1);
// expected-error@-1 {{1st argument must be a vector, integer or floating point type (was 'bool')}}
}

float builtin_round_int_to_float_promotion(int p1) {
return __builtin_elementwise_round(p1);
// expected-error@-1 {{1st argument must be a floating point type (was 'int')}}
}

float2 builtin_round_int2_to_float2_promotion(int2 p1) {
return __builtin_elementwise_round(p1);
// expected-error@-1 {{1st argument must be a floating point type (was 'int2' (aka 'vector<int, 2>'))}}
}
6 changes: 6 additions & 0 deletions flang/docs/Directives.md
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Expand Up @@ -30,3 +30,9 @@ A list of non-standard directives supported by Flang
end
end interface
```
* `!dir$ assume_aligned desginator:alignment`, where designator is a variable,
maybe with array indices, and alignment is what the compiler should assume the
alignment to be. E.g A:64 or B(1,1,1):128. The alignment should be a power of 2,
and is limited to 256.
[This directive is currently recognised by the parser, but not
handled by the other parts of the compiler].
1 change: 1 addition & 0 deletions flang/include/flang/Parser/dump-parse-tree.h
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Original file line number Diff line number Diff line change
Expand Up @@ -205,6 +205,7 @@ class ParseTreeDumper {
NODE(parser, CompilerDirective)
NODE(CompilerDirective, IgnoreTKR)
NODE(CompilerDirective, LoopCount)
NODE(CompilerDirective, AssumeAligned)
NODE(CompilerDirective, NameValue)
NODE(parser, ComplexLiteralConstant)
NODE(parser, ComplexPart)
Expand Down
8 changes: 7 additions & 1 deletion flang/include/flang/Parser/parse-tree.h
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Original file line number Diff line number Diff line change
Expand Up @@ -3309,12 +3309,18 @@ struct CompilerDirective {
struct LoopCount {
WRAPPER_CLASS_BOILERPLATE(LoopCount, std::list<std::uint64_t>);
};
struct AssumeAligned {
TUPLE_CLASS_BOILERPLATE(AssumeAligned);
std::tuple<common::Indirection<Designator>, uint64_t> t;
};
struct NameValue {
TUPLE_CLASS_BOILERPLATE(NameValue);
std::tuple<Name, std::optional<std::uint64_t>> t;
};
CharBlock source;
std::variant<std::list<IgnoreTKR>, LoopCount, std::list<NameValue>> u;
std::variant<std::list<IgnoreTKR>, LoopCount, std::list<AssumeAligned>,
std::list<NameValue>>
u;
};

// (CUDA) ATTRIBUTE(attribute) [::] name-list
Expand Down
30 changes: 29 additions & 1 deletion flang/lib/Optimizer/Builder/IntrinsicCall.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4195,39 +4195,45 @@ mlir::Value IntrinsicLibrary::genIeeeLogb(mlir::Type resultType,
builder.create<mlir::arith::BitcastOp>(loc, intType, realVal);
mlir::Type i1Ty = builder.getI1Type();

int exponentBias, significandSize;
int exponentBias, significandSize, nonSignificandSize;
switch (bitWidth) {
case 16:
if (realType.isF16()) {
// kind=2: 1 sign bit, 5 exponent bits, 10 significand bits
exponentBias = (1 << (5 - 1)) - 1; // 15
significandSize = 10;
nonSignificandSize = 6;
break;
}
assert(realType.isBF16() && "unknown 16-bit real type");
// kind=3: 1 sign bit, 8 exponent bits, 7 significand bits
exponentBias = (1 << (8 - 1)) - 1; // 127
significandSize = 7;
nonSignificandSize = 9;
break;
case 32:
// kind=4: 1 sign bit, 8 exponent bits, 23 significand bits
exponentBias = (1 << (8 - 1)) - 1; // 127
significandSize = 23;
nonSignificandSize = 9;
break;
case 64:
// kind=8: 1 sign bit, 11 exponent bits, 52 significand bits
exponentBias = (1 << (11 - 1)) - 1; // 1023
significandSize = 52;
nonSignificandSize = 12;
break;
case 80:
// kind=10: 1 sign bit, 15 exponent bits, 1+63 significand bits
exponentBias = (1 << (15 - 1)) - 1; // 16383
significandSize = 64;
nonSignificandSize = 16 + 1;
break;
case 128:
// kind=16: 1 sign bit, 15 exponent bits, 112 significand bits
exponentBias = (1 << (15 - 1)) - 1; // 16383
significandSize = 112;
nonSignificandSize = 16;
break;
default:
llvm_unreachable("unknown real type");
Expand Down Expand Up @@ -4259,6 +4265,11 @@ mlir::Value IntrinsicLibrary::genIeeeLogb(mlir::Type resultType,
/*withElseRegion=*/true);
// X is non-zero finite -- result is unbiased exponent of X
builder.setInsertionPointToStart(&innerIfOp.getThenRegion().front());
mlir::Value isNormal = genIsFPClass(i1Ty, args, normalTest);
auto normalIfOp = builder.create<fir::IfOp>(loc, resultType, isNormal,
/*withElseRegion=*/true);
// X is normal
builder.setInsertionPointToStart(&normalIfOp.getThenRegion().front());
mlir::Value biasedExponent = builder.create<mlir::arith::ShRUIOp>(
loc, shiftLeftOne,
builder.createIntegerConstant(loc, intType, significandSize + 1));
Expand All @@ -4268,6 +4279,23 @@ mlir::Value IntrinsicLibrary::genIeeeLogb(mlir::Type resultType,
result = builder.create<fir::ConvertOp>(loc, resultType, result);
builder.create<fir::ResultOp>(loc, result);

// X is denormal -- result is (-exponentBias - ctlz(significand))
builder.setInsertionPointToStart(&normalIfOp.getElseRegion().front());
mlir::Value significand = builder.create<mlir::arith::ShLIOp>(
loc, intVal,
builder.createIntegerConstant(loc, intType, nonSignificandSize));
mlir::Value ctlz =
builder.create<mlir::math::CountLeadingZerosOp>(loc, significand);
mlir::Type i32Ty = builder.getI32Type();
result = builder.create<mlir::arith::SubIOp>(
loc, builder.createIntegerConstant(loc, i32Ty, -exponentBias),
builder.create<fir::ConvertOp>(loc, i32Ty, ctlz));
result = builder.create<fir::ConvertOp>(loc, resultType, result);
builder.create<fir::ResultOp>(loc, result);

builder.setInsertionPointToEnd(&innerIfOp.getThenRegion().front());
builder.create<fir::ResultOp>(loc, normalIfOp.getResult(0));

// X is infinity or NaN -- result is +infinity or NaN
builder.setInsertionPointToStart(&innerIfOp.getElseRegion().front());
result = builder.create<mlir::arith::ShRUIOp>(loc, shiftLeftOne, one);
Expand Down
4 changes: 4 additions & 0 deletions flang/lib/Parser/Fortran-parsers.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1268,9 +1268,13 @@ constexpr auto ignore_tkr{
constexpr auto loopCount{
"DIR$ LOOP COUNT" >> construct<CompilerDirective::LoopCount>(
parenthesized(nonemptyList(digitString64)))};
constexpr auto assumeAligned{"DIR$ ASSUME_ALIGNED" >>
optionalList(construct<CompilerDirective::AssumeAligned>(
indirect(designator), ":"_tok >> digitString64))};
TYPE_PARSER(beginDirective >>
sourced(construct<CompilerDirective>(ignore_tkr) ||
construct<CompilerDirective>(loopCount) ||
construct<CompilerDirective>(assumeAligned) ||
construct<CompilerDirective>(
"DIR$" >> many(construct<CompilerDirective::NameValue>(name,
maybe(("="_tok || ":"_tok) >> digitString64))))) /
Expand Down
10 changes: 10 additions & 0 deletions flang/lib/Parser/unparse.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1819,6 +1819,11 @@ class UnparseVisitor {
[&](const CompilerDirective::LoopCount &lcount) {
Walk("!DIR$ LOOP COUNT (", lcount.v, ", ", ")");
},
[&](const std::list<CompilerDirective::AssumeAligned>
&assumeAligned) {
Word("!DIR$ ASSUME_ALIGNED ");
Walk(" ", assumeAligned, ", ");
},
[&](const std::list<CompilerDirective::NameValue> &names) {
Walk("!DIR$ ", names, " ");
},
Expand All @@ -1841,6 +1846,11 @@ class UnparseVisitor {
Walk(std::get<Name>(x.t));
Walk("=", std::get<std::optional<std::uint64_t>>(x.t));
}
void Unparse(const CompilerDirective::AssumeAligned &x) {
Walk(std::get<common::Indirection<Designator>>(x.t));
Put(":");
Walk(std::get<uint64_t>(x.t));
}

// OpenACC Directives & Clauses
void Unparse(const AccAtomicCapture &x) {
Expand Down
57 changes: 57 additions & 0 deletions flang/test/Parser/assume-aligned.f90
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Original file line number Diff line number Diff line change
@@ -0,0 +1,57 @@
! RUN: %flang_fc1 -fdebug-unparse-no-sema %s 2>&1 | FileCheck %s

SUBROUTINE aa(a, nn)
IMPLICIT NONE
INTEGER, INTENT(IN) :: nn
COMPLEX(8), INTENT(INOUT), DIMENSION(1:nn) :: a
INTEGER :: i
!DIR$ assume_aligned a:16
!CHECK: !DIR$ ASSUME_ALIGNED a:16
!DIR$ assume_aligned a (1):16
!CHECK: !DIR$ ASSUME_ALIGNED a(1):16
!DIR$ assume_aligned a(1):16
!CHECK: !DIR$ ASSUME_ALIGNED a(1):16
!DIR$ assume_aligned a(nn):16
!CHECK: !DIR$ ASSUME_ALIGNED a(nn):16
!DIR$ assume_aligned a(44):16
!CHECK: !DIR$ ASSUME_ALIGNED a(44):16
DO i=1,nn
a(i)=a(i)+1.5
END DO
END SUBROUTINE aa

SUBROUTINE bb(v, s, e)
IMPLICIT NONE
INTEGER, INTENT(IN) :: s(3), e(3)
INTEGER :: y,z
REAL(8), INTENT(IN) :: v(s(1):e(1),s(2):e(2),s(3):e(3))
!DIR$ assume_aligned v(s(1),y,z) :64
!CHECK: !DIR$ ASSUME_ALIGNED v(s(1),y,z):64
END SUBROUTINE bb

SUBROUTINE f(n)
IMPLICIT NONE
TYPE node
REAL(KIND=8), POINTER :: a(:,:)
END TYPE NODE

TYPE(NODE), POINTER :: nodes
INTEGER :: i
INTEGER, INTENT(IN) :: n

ALLOCATE(nodes)
ALLOCATE(nodes%a(1000,1000))

!DIR$ ASSUME_ALIGNED nodes%a(1,1) : 16
!CHECK: !DIR$ ASSUME_ALIGNED nodes%a(1,1):16
DO i=1,n
nodes%a(1,i) = nodes%a(1,i)+1
END DO
END SUBROUTINE f

SUBROUTINE g(a, b)
IMPLICIT NONE
INTEGER, INTENT(in) :: a(128), b(128)
!DIR$ ASSUME_ALIGNED a:32, b:64
!CHECK: !DIR$ ASSUME_ALIGNED a:32, b:64
END SUBROUTINE g
2 changes: 1 addition & 1 deletion libc/CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -232,7 +232,7 @@ else()
set(LIBC_LIBRARY_DIR ${CMAKE_BINARY_DIR}/lib${LLVM_LIBDIR_SUFFIX})
endif()
if(LIBC_TARGET_OS_IS_GPU)
set(LIBC_INSTALL_INCLUDE_DIR ${CMAKE_INSTALL_INCLUDEDIR}/${LLVM_DEFAULT_TARGET_TRIPLE})
set(LIBC_INSTALL_INCLUDE_DIR ${CMAKE_INSTALL_INCLUDEDIR}/${LIBC_TARGET_TRIPLE})
else()
set(LIBC_INSTALL_INCLUDE_DIR ${CMAKE_INSTALL_INCLUDEDIR})
endif()
Expand Down
6 changes: 5 additions & 1 deletion libc/lib/CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -77,9 +77,13 @@ install(
)

if(LIBC_TARGET_OS_IS_GPU)
set(gpu_install_dir lib${LLVM_LIBDIR_SUFFIX})
if(LLVM_ENABLE_PER_TARGET_RUNTIME_DIR)
set(gpu_install_dir lib${LLVM_LIBDIR_SUFFIX}/${LLVM_HOST_TRIPLE})
endif()
install(
TARGETS ${added_gpu_archive_targets}
ARCHIVE DESTINATION lib${LLVM_LIBDIR_SUFFIX}
ARCHIVE DESTINATION ${gpu_install_dir}
COMPONENT libc
)
foreach(file ${added_gpu_bitcode_targets})
Expand Down
5 changes: 5 additions & 0 deletions lldb/include/lldb/Interpreter/CommandOptionArgumentTable.h
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Original file line number Diff line number Diff line change
Expand Up @@ -50,6 +50,11 @@ static constexpr OptionEnumValueElement g_sort_option_enumeration[] = {
"name",
"Sort output by symbol name.",
},
{
eSortOrderBySize,
"size",
"Sort output by symbol byte size.",
},
};

// Note that the negation in the argument name causes a slightly confusing
Expand Down
7 changes: 6 additions & 1 deletion lldb/include/lldb/lldb-private-enumerations.h
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Original file line number Diff line number Diff line change
Expand Up @@ -108,7 +108,12 @@ enum ArgumentRepetitionType {
// optional
};

enum SortOrder { eSortOrderNone, eSortOrderByAddress, eSortOrderByName };
enum SortOrder {
eSortOrderNone,
eSortOrderByAddress,
eSortOrderByName,
eSortOrderBySize
};

// LazyBool is for boolean values that need to be calculated lazily. Values
// start off set to eLazyBoolCalculate, and then they can be calculated once
Expand Down
23 changes: 17 additions & 6 deletions lldb/source/Symbol/Symtab.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -124,12 +124,8 @@ void Symtab::Dump(Stream *s, Target *target, SortOrder sort_order,
DumpSymbolHeader(s);

std::multimap<llvm::StringRef, const Symbol *> name_map;
for (const_iterator pos = m_symbols.begin(), end = m_symbols.end();
pos != end; ++pos) {
const char *name = pos->GetName().AsCString();
if (name && name[0])
name_map.insert(std::make_pair(name, &(*pos)));
}
for (const Symbol &symbol : m_symbols)
name_map.emplace(llvm::StringRef(symbol.GetName()), &symbol);

for (const auto &name_to_symbol : name_map) {
const Symbol *symbol = name_to_symbol.second;
Expand All @@ -138,6 +134,21 @@ void Symtab::Dump(Stream *s, Target *target, SortOrder sort_order,
}
} break;

case eSortOrderBySize: {
s->PutCString(" (sorted by size):\n");
DumpSymbolHeader(s);

std::multimap<size_t, const Symbol *, std::greater<size_t>> size_map;
for (const Symbol &symbol : m_symbols)
size_map.emplace(symbol.GetByteSize(), &symbol);

for (const auto &size_to_symbol : size_map) {
const Symbol *symbol = size_to_symbol.second;
s->Indent();
symbol->Dump(s, target, symbol - &m_symbols[0], name_preference);
}
} break;

case eSortOrderByAddress:
s->PutCString(" (sorted by address):\n");
DumpSymbolHeader(s);
Expand Down
11 changes: 11 additions & 0 deletions lldb/test/Shell/SymbolFile/Breakpad/symtab-sorted-by-size.test
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Original file line number Diff line number Diff line change
@@ -0,0 +1,11 @@
# RUN: yaml2obj %S/Inputs/basic-elf.yaml -o %T/symtab.out
# RUN: %lldb %T/symtab.out -o "target symbols add -s symtab.out %S/Inputs/symtab.syms" \
# RUN: -s %s | FileCheck %s

# CHECK: num_symbols = 4 (sorted by size):
# CHECK: [ 0] 0 SX Code 0x0000000000400000 0x00000000000000b0 0x00000000 ___lldb_unnamed_symbol0
# CHECK: [ 3] 0 X Code 0x00000000004000d0 0x0000000000000022 0x00000000 _start
# CHECK: [ 1] 0 X Code 0x00000000004000b0 0x0000000000000010 0x00000000 f1
# CHECK: [ 2] 0 X Code 0x00000000004000c0 0x0000000000000010 0x00000000 f2

image dump symtab -s size symtab.out
7 changes: 7 additions & 0 deletions llvm/include/llvm/IR/DIBuilder.h
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Original file line number Diff line number Diff line change
Expand Up @@ -262,6 +262,13 @@ namespace llvm {
std::optional<unsigned> DWARFAddressSpace = std::nullopt,
StringRef Name = "", DINodeArray Annotations = nullptr);

/// Create a __ptrauth qualifier.
DIDerivedType *createPtrAuthQualifiedType(DIType *FromTy, unsigned Key,
bool IsAddressDiscriminated,
unsigned ExtraDiscriminator,
bool IsaPointer,
bool authenticatesNullValues);

/// Create debugging information entry for a pointer to member.
/// \param PointeeTy Type pointed to by this pointer.
/// \param SizeInBits Size.
Expand Down
124 changes: 101 additions & 23 deletions llvm/include/llvm/IR/DebugInfoMetadata.h
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Original file line number Diff line number Diff line change
Expand Up @@ -745,7 +745,7 @@ class DIType : public DIScope {

unsigned getLine() const { return Line; }
uint64_t getSizeInBits() const { return SizeInBits; }
uint32_t getAlignInBits() const { return SubclassData32; }
uint32_t getAlignInBits() const;
uint32_t getAlignInBytes() const { return getAlignInBits() / CHAR_BIT; }
uint64_t getOffsetInBits() const { return OffsetInBits; }
DIFlags getFlags() const { return Flags; }
Expand Down Expand Up @@ -972,6 +972,40 @@ class DIStringType : public DIType {
///
/// TODO: Split out members (inheritance, fields, methods, etc.).
class DIDerivedType : public DIType {
public:
/// Pointer authentication (__ptrauth) metadata.
struct PtrAuthData {
union {
struct {
unsigned Key : 4;
unsigned IsAddressDiscriminated : 1;
unsigned ExtraDiscriminator : 16;
unsigned IsaPointer : 1;
unsigned AuthenticatesNullValues : 1;
} Data;
unsigned RawData;
} Payload;

PtrAuthData(unsigned FromRawData) { Payload.RawData = FromRawData; }
PtrAuthData(unsigned Key, bool IsDiscr, unsigned Discriminator,
bool IsaPointer, bool AuthenticatesNullValues) {
assert(Key < 16);
assert(Discriminator <= 0xffff);
Payload.Data.Key = Key;
Payload.Data.IsAddressDiscriminated = IsDiscr;
Payload.Data.ExtraDiscriminator = Discriminator;
Payload.Data.IsaPointer = IsaPointer;
Payload.Data.AuthenticatesNullValues = AuthenticatesNullValues;
}
bool operator==(struct PtrAuthData Other) const {
return Payload.RawData == Other.Payload.RawData;
}
bool operator!=(struct PtrAuthData Other) const {
return !(*this == Other);
}
};

private:
friend class LLVMContextImpl;
friend class MDNode;

Expand All @@ -982,59 +1016,70 @@ class DIDerivedType : public DIType {
DIDerivedType(LLVMContext &C, StorageType Storage, unsigned Tag,
unsigned Line, uint64_t SizeInBits, uint32_t AlignInBits,
uint64_t OffsetInBits,
std::optional<unsigned> DWARFAddressSpace, DIFlags Flags,
std::optional<unsigned> DWARFAddressSpace,
std::optional<PtrAuthData> PtrAuthData, DIFlags Flags,
ArrayRef<Metadata *> Ops)
: DIType(C, DIDerivedTypeKind, Storage, Tag, Line, SizeInBits,
AlignInBits, OffsetInBits, Flags, Ops),
DWARFAddressSpace(DWARFAddressSpace) {}
DWARFAddressSpace(DWARFAddressSpace) {
if (PtrAuthData)
SubclassData32 = PtrAuthData->Payload.RawData;
}
~DIDerivedType() = default;
static DIDerivedType *
getImpl(LLVMContext &Context, unsigned Tag, StringRef Name, DIFile *File,
unsigned Line, DIScope *Scope, DIType *BaseType, uint64_t SizeInBits,
uint32_t AlignInBits, uint64_t OffsetInBits,
std::optional<unsigned> DWARFAddressSpace, DIFlags Flags,
std::optional<unsigned> DWARFAddressSpace,
std::optional<PtrAuthData> PtrAuthData, DIFlags Flags,
Metadata *ExtraData, DINodeArray Annotations, StorageType Storage,
bool ShouldCreate = true) {
return getImpl(Context, Tag, getCanonicalMDString(Context, Name), File,
Line, Scope, BaseType, SizeInBits, AlignInBits, OffsetInBits,
DWARFAddressSpace, Flags, ExtraData, Annotations.get(),
Storage, ShouldCreate);
DWARFAddressSpace, PtrAuthData, Flags, ExtraData,
Annotations.get(), Storage, ShouldCreate);
}
static DIDerivedType *
getImpl(LLVMContext &Context, unsigned Tag, MDString *Name, Metadata *File,
unsigned Line, Metadata *Scope, Metadata *BaseType,
uint64_t SizeInBits, uint32_t AlignInBits, uint64_t OffsetInBits,
std::optional<unsigned> DWARFAddressSpace, DIFlags Flags,
std::optional<unsigned> DWARFAddressSpace,
std::optional<PtrAuthData> PtrAuthData, DIFlags Flags,
Metadata *ExtraData, Metadata *Annotations, StorageType Storage,
bool ShouldCreate = true);

TempDIDerivedType cloneImpl() const {
return getTemporary(
getContext(), getTag(), getName(), getFile(), getLine(), getScope(),
getBaseType(), getSizeInBits(), getAlignInBits(), getOffsetInBits(),
getDWARFAddressSpace(), getFlags(), getExtraData(), getAnnotations());
return getTemporary(getContext(), getTag(), getName(), getFile(), getLine(),
getScope(), getBaseType(), getSizeInBits(),
getAlignInBits(), getOffsetInBits(),
getDWARFAddressSpace(), getPtrAuthData(), getFlags(),
getExtraData(), getAnnotations());
}

public:
DEFINE_MDNODE_GET(
DIDerivedType,
(unsigned Tag, MDString *Name, Metadata *File, unsigned Line,
Metadata *Scope, Metadata *BaseType, uint64_t SizeInBits,
uint32_t AlignInBits, uint64_t OffsetInBits,
std::optional<unsigned> DWARFAddressSpace, DIFlags Flags,
Metadata *ExtraData = nullptr, Metadata *Annotations = nullptr),
(Tag, Name, File, Line, Scope, BaseType, SizeInBits, AlignInBits,
OffsetInBits, DWARFAddressSpace, Flags, ExtraData, Annotations))
DEFINE_MDNODE_GET(DIDerivedType,
(unsigned Tag, MDString *Name, Metadata *File,
unsigned Line, Metadata *Scope, Metadata *BaseType,
uint64_t SizeInBits, uint32_t AlignInBits,
uint64_t OffsetInBits,
std::optional<unsigned> DWARFAddressSpace,
std::optional<PtrAuthData> PtrAuthData, DIFlags Flags,
Metadata *ExtraData = nullptr,
Metadata *Annotations = nullptr),
(Tag, Name, File, Line, Scope, BaseType, SizeInBits,
AlignInBits, OffsetInBits, DWARFAddressSpace, PtrAuthData,
Flags, ExtraData, Annotations))
DEFINE_MDNODE_GET(DIDerivedType,
(unsigned Tag, StringRef Name, DIFile *File, unsigned Line,
DIScope *Scope, DIType *BaseType, uint64_t SizeInBits,
uint32_t AlignInBits, uint64_t OffsetInBits,
std::optional<unsigned> DWARFAddressSpace, DIFlags Flags,
std::optional<unsigned> DWARFAddressSpace,
std::optional<PtrAuthData> PtrAuthData, DIFlags Flags,
Metadata *ExtraData = nullptr,
DINodeArray Annotations = nullptr),
(Tag, Name, File, Line, Scope, BaseType, SizeInBits,
AlignInBits, OffsetInBits, DWARFAddressSpace, Flags,
ExtraData, Annotations))
AlignInBits, OffsetInBits, DWARFAddressSpace, PtrAuthData,
Flags, ExtraData, Annotations))

TempDIDerivedType clone() const { return cloneImpl(); }

Expand All @@ -1048,6 +1093,39 @@ class DIDerivedType : public DIType {
return DWARFAddressSpace;
}

std::optional<PtrAuthData> getPtrAuthData() const;

/// \returns The PointerAuth key.
std::optional<unsigned> getPtrAuthKey() const {
if (auto PtrAuthData = getPtrAuthData())
return (unsigned)PtrAuthData->Payload.Data.Key;
return std::nullopt;
}
/// \returns The PointerAuth address discrimination bit.
std::optional<bool> isPtrAuthAddressDiscriminated() const {
if (auto PtrAuthData = getPtrAuthData())
return (bool)PtrAuthData->Payload.Data.IsAddressDiscriminated;
return std::nullopt;
}
/// \returns The PointerAuth extra discriminator.
std::optional<unsigned> getPtrAuthExtraDiscriminator() const {
if (auto PtrAuthData = getPtrAuthData())
return (unsigned)PtrAuthData->Payload.Data.ExtraDiscriminator;
return std::nullopt;
}
/// \returns The PointerAuth IsaPointer bit.
std::optional<bool> isPtrAuthIsaPointer() const {
if (auto PtrAuthData = getPtrAuthData())
return (bool)PtrAuthData->Payload.Data.IsaPointer;
return std::nullopt;
}
/// \returns The PointerAuth authenticates null values bit.
std::optional<bool> getPtrAuthAuthenticatesNullValues() const {
if (auto PtrAuthData = getPtrAuthData())
return (bool)PtrAuthData->Payload.Data.AuthenticatesNullValues;
return std::nullopt;
}

/// Get extra data associated with this derived type.
///
/// Class type for pointer-to-members, objective-c property node for ivars,
Expand Down
1 change: 1 addition & 0 deletions llvm/include/llvm/IR/Intrinsics.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -514,6 +514,7 @@ def llvm_v2048i1_ty : LLVMType<v2048i1>; //2048 x i1

def llvm_v1i8_ty : LLVMType<v1i8>; // 1 x i8
def llvm_v2i8_ty : LLVMType<v2i8>; // 2 x i8
def llvm_v3i8_ty : LLVMType<v3i8>; // 3 x i8
def llvm_v4i8_ty : LLVMType<v4i8>; // 4 x i8
def llvm_v8i8_ty : LLVMType<v8i8>; // 8 x i8
def llvm_v16i8_ty : LLVMType<v16i8>; // 16 x i8
Expand Down
23 changes: 19 additions & 4 deletions llvm/lib/AsmParser/LLParser.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5130,7 +5130,11 @@ bool LLParser::parseDIStringType(MDNode *&Result, bool IsDistinct) {
/// ::= !DIDerivedType(tag: DW_TAG_pointer_type, name: "int", file: !0,
/// line: 7, scope: !1, baseType: !2, size: 32,
/// align: 32, offset: 0, flags: 0, extraData: !3,
/// dwarfAddressSpace: 3)
/// dwarfAddressSpace: 3, ptrAuthKey: 1,
/// ptrAuthIsAddressDiscriminated: true,
/// ptrAuthExtraDiscriminator: 0x1234,
/// ptrAuthIsaPointer: 1, ptrAuthAuthenticatesNullValues:1
/// )
bool LLParser::parseDIDerivedType(MDNode *&Result, bool IsDistinct) {
#define VISIT_MD_FIELDS(OPTIONAL, REQUIRED) \
REQUIRED(tag, DwarfTagField, ); \
Expand All @@ -5145,19 +5149,30 @@ bool LLParser::parseDIDerivedType(MDNode *&Result, bool IsDistinct) {
OPTIONAL(flags, DIFlagField, ); \
OPTIONAL(extraData, MDField, ); \
OPTIONAL(dwarfAddressSpace, MDUnsignedField, (UINT32_MAX, UINT32_MAX)); \
OPTIONAL(annotations, MDField, );
OPTIONAL(annotations, MDField, ); \
OPTIONAL(ptrAuthKey, MDUnsignedField, (0, 7)); \
OPTIONAL(ptrAuthIsAddressDiscriminated, MDBoolField, ); \
OPTIONAL(ptrAuthExtraDiscriminator, MDUnsignedField, (0, 0xffff)); \
OPTIONAL(ptrAuthIsaPointer, MDBoolField, ); \
OPTIONAL(ptrAuthAuthenticatesNullValues, MDBoolField, );
PARSE_MD_FIELDS();
#undef VISIT_MD_FIELDS

std::optional<unsigned> DWARFAddressSpace;
if (dwarfAddressSpace.Val != UINT32_MAX)
DWARFAddressSpace = dwarfAddressSpace.Val;
std::optional<DIDerivedType::PtrAuthData> PtrAuthData;
if (ptrAuthKey.Val)
PtrAuthData = DIDerivedType::PtrAuthData(
(unsigned)ptrAuthKey.Val, ptrAuthIsAddressDiscriminated.Val,
(unsigned)ptrAuthExtraDiscriminator.Val, ptrAuthIsaPointer.Val,
ptrAuthAuthenticatesNullValues.Val);

Result = GET_OR_DISTINCT(DIDerivedType,
(Context, tag.Val, name.Val, file.Val, line.Val,
scope.Val, baseType.Val, size.Val, align.Val,
offset.Val, DWARFAddressSpace, flags.Val,
extraData.Val, annotations.Val));
offset.Val, DWARFAddressSpace, PtrAuthData,
flags.Val, extraData.Val, annotations.Val));
return false;
}

Expand Down
18 changes: 14 additions & 4 deletions llvm/lib/Bitcode/Reader/MetadataLoader.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1556,7 +1556,7 @@ Error MetadataLoader::MetadataLoaderImpl::parseOneMetadata(
break;
}
case bitc::METADATA_DERIVED_TYPE: {
if (Record.size() < 12 || Record.size() > 14)
if (Record.size() < 12 || Record.size() > 15)
return error("Invalid record");

// DWARF address space is encoded as N->getDWARFAddressSpace() + 1. 0 means
Expand All @@ -1566,8 +1566,18 @@ Error MetadataLoader::MetadataLoaderImpl::parseOneMetadata(
DWARFAddressSpace = Record[12] - 1;

Metadata *Annotations = nullptr;
if (Record.size() > 13 && Record[13])
Annotations = getMDOrNull(Record[13]);
std::optional<DIDerivedType::PtrAuthData> PtrAuthData;

// Only look for annotations/ptrauth if both are allocated.
// If not, we can't tell which was intended to be embedded, as both ptrauth
// and annotations have been expected at Record[13] at various times.
if (Record.size() > 14) {
if (Record[13])
Annotations = getMDOrNull(Record[13]);

if (Record[14])
PtrAuthData = DIDerivedType::PtrAuthData(Record[14]);
}

IsDistinct = Record[0];
DINode::DIFlags Flags = static_cast<DINode::DIFlags>(Record[10]);
Expand All @@ -1577,7 +1587,7 @@ Error MetadataLoader::MetadataLoaderImpl::parseOneMetadata(
getMDOrNull(Record[3]), Record[4],
getDITypeRefOrNull(Record[5]),
getDITypeRefOrNull(Record[6]), Record[7], Record[8],
Record[9], DWARFAddressSpace, Flags,
Record[9], DWARFAddressSpace, PtrAuthData, Flags,
getDITypeRefOrNull(Record[11]), Annotations)),
NextMetadataNo);
NextMetadataNo++;
Expand Down
5 changes: 5 additions & 0 deletions llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1804,6 +1804,11 @@ void ModuleBitcodeWriter::writeDIDerivedType(const DIDerivedType *N,

Record.push_back(VE.getMetadataOrNullID(N->getAnnotations().get()));

if (auto PtrAuthData = N->getPtrAuthData())
Record.push_back(PtrAuthData->Payload.RawData);
else
Record.push_back(0);

Stream.EmitRecord(bitc::METADATA_DERIVED_TYPE, Record, Abbrev);
Record.clear();
}
Expand Down
14 changes: 14 additions & 0 deletions llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -803,6 +803,20 @@ void DwarfUnit::constructTypeDIE(DIE &Buffer, const DIDerivedType *DTy) {
if (DTy->getDWARFAddressSpace())
addUInt(Buffer, dwarf::DW_AT_address_class, dwarf::DW_FORM_data4,
*DTy->getDWARFAddressSpace());
if (auto Key = DTy->getPtrAuthKey())
addUInt(Buffer, dwarf::DW_AT_LLVM_ptrauth_key, dwarf::DW_FORM_data1, *Key);
if (auto AddrDisc = DTy->isPtrAuthAddressDiscriminated())
if (AddrDisc.value())
addFlag(Buffer, dwarf::DW_AT_LLVM_ptrauth_address_discriminated);
if (auto Disc = DTy->getPtrAuthExtraDiscriminator())
addUInt(Buffer, dwarf::DW_AT_LLVM_ptrauth_extra_discriminator,
dwarf::DW_FORM_data2, *Disc);
if (auto IsaPointer = DTy->isPtrAuthIsaPointer())
if (*IsaPointer)
addFlag(Buffer, dwarf::DW_AT_LLVM_ptrauth_isa_pointer);
if (auto AuthenticatesNullValues = DTy->getPtrAuthAuthenticatesNullValues())
if (*AuthenticatesNullValues)
addFlag(Buffer, dwarf::DW_AT_LLVM_ptrauth_authenticates_null_values);
}

void DwarfUnit::constructSubprogramArguments(DIE &Buffer, DITypeRefArray Args) {
Expand Down
125 changes: 67 additions & 58 deletions llvm/lib/CodeGen/TypePromotion.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -136,6 +136,7 @@ class IRPromoter {

class TypePromotionImpl {
unsigned TypeSize = 0;
const TargetLowering *TLI = nullptr;
LLVMContext *Ctx = nullptr;
unsigned RegisterBitWidth = 0;
SmallPtrSet<Value *, 16> AllVisited;
Expand Down Expand Up @@ -272,64 +273,58 @@ bool TypePromotionImpl::isSink(Value *V) {

/// Return whether this instruction can safely wrap.
bool TypePromotionImpl::isSafeWrap(Instruction *I) {
// We can support a potentially wrapping instruction (I) if:
// We can support a potentially wrapping Add/Sub instruction (I) if:
// - It is only used by an unsigned icmp.
// - The icmp uses a constant.
// - The wrapping value (I) is decreasing, i.e would underflow - wrapping
// around zero to become a larger number than before.
// - The wrapping instruction (I) also uses a constant.
//
// We can then use the two constants to calculate whether the result would
// wrap in respect to itself in the original bitwidth. If it doesn't wrap,
// just underflows the range, the icmp would give the same result whether the
// result has been truncated or not. We calculate this by:
// - Zero extending both constants, if needed, to RegisterBitWidth.
// - Take the absolute value of I's constant, adding this to the icmp const.
// - Check that this value is not out of range for small type. If it is, it
// means that it has underflowed enough to wrap around the icmp constant.
// This a common pattern emitted to check if a value is within a range.
//
// For example:
//
// %sub = sub i8 %a, 2
// %cmp = icmp ule i8 %sub, 254
// %sub = sub i8 %a, C1
// %cmp = icmp ule i8 %sub, C2
//
// or
//
// %add = add i8 %a, C1
// %cmp = icmp ule i8 %add, C2.
//
// If %a = 0, %sub = -2 == FE == 254
// But if this is evalulated as a i32
// %sub = -2 == FF FF FF FE == 4294967294
// So the unsigned compares (i8 and i32) would not yield the same result.
// We will treat an add as though it were a subtract by -C1. To promote
// the Add/Sub we will zero extend the LHS and the subtracted amount. For Add,
// this means we need to negate the constant, zero extend to RegisterBitWidth,
// and negate in the larger type.
//
// Another way to look at it is:
// %a - 2 <= 254
// %a + 2 <= 254 + 2
// %a <= 256
// And we can't represent 256 in the i8 format, so we don't support it.
// This will produce a value in the range [-zext(C1), zext(X)-zext(C1)] where
// C1 is the subtracted amount. This is either a small unsigned number or a
// large unsigned number in the promoted type.
//
// Whereas:
// Now we need to correct the compare constant C2. Values >= C1 in the
// original add result range have been remapped to large values in the
// promoted range. If the compare constant fell into this range we need to
// remap it as well. We can do this as -(zext(-C2)).
//
// %sub i8 %a, 1
// For example:
//
// %sub = sub i8 %a, 2
// %cmp = icmp ule i8 %sub, 254
//
// If %a = 0, %sub = -1 == FF == 255
// As i32:
// %sub = -1 == FF FF FF FF == 4294967295
// becomes
//
// In this case, the unsigned compare results would be the same and this
// would also be true for ult, uge and ugt:
// - (255 < 254) == (0xFFFFFFFF < 254) == false
// - (255 <= 254) == (0xFFFFFFFF <= 254) == false
// - (255 > 254) == (0xFFFFFFFF > 254) == true
// - (255 >= 254) == (0xFFFFFFFF >= 254) == true
// %zext = zext %a to i32
// %sub = sub i32 %zext, 2
// %cmp = icmp ule i32 %sub, 4294967294
//
// To demonstrate why we can't handle increasing values:
// Another example:
//
// %add = add i8 %a, 2
// %cmp = icmp ult i8 %add, 127
// %sub = sub i8 %a, 1
// %cmp = icmp ule i8 %sub, 254
//
// If %a = 254, %add = 256 == (i8 1)
// As i32:
// %add = 256
// becomes
//
// (1 < 127) != (256 < 127)
// %zext = zext %a to i32
// %sub = sub i32 %zext, 1
// %cmp = icmp ule i32 %sub, 254

unsigned Opc = I->getOpcode();
if (Opc != Instruction::Add && Opc != Instruction::Sub)
Expand All @@ -356,15 +351,23 @@ bool TypePromotionImpl::isSafeWrap(Instruction *I) {
APInt OverflowConst = cast<ConstantInt>(I->getOperand(1))->getValue();
if (Opc == Instruction::Sub)
OverflowConst = -OverflowConst;
if (!OverflowConst.isNonPositive())
return false;

// If the constant is positive, we will end up filling the promoted bits with
// all 1s. Make sure that results in a cheap add constant.
if (!OverflowConst.isNonPositive()) {
// We don't have the true promoted width, just use 64 so we can create an
// int64_t for the isLegalAddImmediate call.
if (OverflowConst.getBitWidth() >= 64)
return false;

APInt NewConst = -((-OverflowConst).zext(64));
if (!TLI->isLegalAddImmediate(NewConst.getSExtValue()))
return false;
}

SafeWrap.insert(I);

// Using C1 = OverflowConst and C2 = ICmpConst, we can either prove that:
// zext(x) + sext(C1) <u zext(C2) if C1 < 0 and C1 >s C2
// zext(x) + sext(C1) <u sext(C2) if C1 < 0 and C1 <=s C2
if (OverflowConst.sgt(ICmpConst)) {
if (OverflowConst.ugt(ICmpConst)) {
LLVM_DEBUG(dbgs() << "IR Promotion: Allowing safe overflow for sext "
<< "const of " << *I << "\n");
return true;
Expand Down Expand Up @@ -487,18 +490,24 @@ void IRPromoter::PromoteTree() {
continue;

if (auto *Const = dyn_cast<ConstantInt>(Op)) {
// For subtract, we don't need to sext the constant. We only put it in
// For subtract, we only need to zext the constant. We only put it in
// SafeWrap because SafeWrap.size() is used elsewhere.
// For cmp, we need to sign extend a constant appearing in either
// operand. For add, we should only sign extend the RHS.
Constant *NewConst =
ConstantInt::get(Const->getContext(),
(SafeWrap.contains(I) &&
(I->getOpcode() == Instruction::ICmp || i == 1) &&
I->getOpcode() != Instruction::Sub)
? Const->getValue().sext(PromotedWidth)
: Const->getValue().zext(PromotedWidth));
I->setOperand(i, NewConst);
// For Add and ICmp we need to find how far the constant is from the
// top of its original unsigned range and place it the same distance
// from the top of its new unsigned range. We can do this by negating
// the constant, zero extending it, then negating in the new type.
APInt NewConst;
if (SafeWrap.contains(I)) {
if (I->getOpcode() == Instruction::ICmp)
NewConst = -((-Const->getValue()).zext(PromotedWidth));
else if (I->getOpcode() == Instruction::Add && i == 1)
NewConst = -((-Const->getValue()).zext(PromotedWidth));
else
NewConst = Const->getValue().zext(PromotedWidth);
} else
NewConst = Const->getValue().zext(PromotedWidth);

I->setOperand(i, ConstantInt::get(Const->getContext(), NewConst));
} else if (isa<UndefValue>(Op))
I->setOperand(i, ConstantInt::get(ExtTy, 0));
}
Expand Down Expand Up @@ -917,7 +926,7 @@ bool TypePromotionImpl::run(Function &F, const TargetMachine *TM,
bool MadeChange = false;
const DataLayout &DL = F.getParent()->getDataLayout();
const TargetSubtargetInfo *SubtargetInfo = TM->getSubtargetImpl(F);
const TargetLowering *TLI = SubtargetInfo->getTargetLowering();
TLI = SubtargetInfo->getTargetLowering();
RegisterBitWidth =
TTI.getRegisterBitWidth(TargetTransformInfo::RGK_Scalar).getFixedValue();
Ctx = &F.getParent()->getContext();
Expand Down
11 changes: 11 additions & 0 deletions llvm/lib/IR/AsmWriter.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2135,6 +2135,17 @@ static void writeDIDerivedType(raw_ostream &Out, const DIDerivedType *N,
Printer.printInt("dwarfAddressSpace", *DWARFAddressSpace,
/* ShouldSkipZero */ false);
Printer.printMetadata("annotations", N->getRawAnnotations());
if (auto Key = N->getPtrAuthKey())
Printer.printInt("ptrAuthKey", *Key);
if (auto AddrDisc = N->isPtrAuthAddressDiscriminated())
Printer.printBool("ptrAuthIsAddressDiscriminated", *AddrDisc);
if (auto Disc = N->getPtrAuthExtraDiscriminator())
Printer.printInt("ptrAuthExtraDiscriminator", *Disc);
if (auto IsaPointer = N->isPtrAuthIsaPointer())
Printer.printBool("ptrAuthIsaPointer", *IsaPointer);
if (auto AuthenticatesNullValues = N->getPtrAuthAuthenticatesNullValues())
Printer.printBool("ptrAuthAuthenticatesNullValues",
*AuthenticatesNullValues);
Out << ")";
}

Expand Down
58 changes: 37 additions & 21 deletions llvm/lib/IR/DIBuilder.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -296,7 +296,20 @@ DIStringType *DIBuilder::createStringType(StringRef Name,

DIDerivedType *DIBuilder::createQualifiedType(unsigned Tag, DIType *FromTy) {
return DIDerivedType::get(VMContext, Tag, "", nullptr, 0, nullptr, FromTy, 0,
0, 0, std::nullopt, DINode::FlagZero);
0, 0, std::nullopt, std::nullopt, DINode::FlagZero);
}

DIDerivedType *DIBuilder::createPtrAuthQualifiedType(
DIType *FromTy, unsigned Key, bool IsAddressDiscriminated,
unsigned ExtraDiscriminator, bool IsaPointer,
bool AuthenticatesNullValues) {
return DIDerivedType::get(
VMContext, dwarf::DW_TAG_LLVM_ptrauth_type, "", nullptr, 0, nullptr,
FromTy, 0, 0, 0, std::nullopt,
std::optional<DIDerivedType::PtrAuthData>({Key, IsAddressDiscriminated,
ExtraDiscriminator, IsaPointer,
AuthenticatesNullValues}),
DINode::FlagZero);
}

DIDerivedType *
Expand All @@ -307,8 +320,8 @@ DIBuilder::createPointerType(DIType *PointeeTy, uint64_t SizeInBits,
// FIXME: Why is there a name here?
return DIDerivedType::get(VMContext, dwarf::DW_TAG_pointer_type, Name,
nullptr, 0, nullptr, PointeeTy, SizeInBits,
AlignInBits, 0, DWARFAddressSpace, DINode::FlagZero,
nullptr, Annotations);
AlignInBits, 0, DWARFAddressSpace, std::nullopt,
DINode::FlagZero, nullptr, Annotations);
}

DIDerivedType *DIBuilder::createMemberPointerType(DIType *PointeeTy,
Expand All @@ -318,7 +331,8 @@ DIDerivedType *DIBuilder::createMemberPointerType(DIType *PointeeTy,
DINode::DIFlags Flags) {
return DIDerivedType::get(VMContext, dwarf::DW_TAG_ptr_to_member_type, "",
nullptr, 0, nullptr, PointeeTy, SizeInBits,
AlignInBits, 0, std::nullopt, Flags, Base);
AlignInBits, 0, std::nullopt, std::nullopt, Flags,
Base);
}

DIDerivedType *
Expand All @@ -327,7 +341,7 @@ DIBuilder::createReferenceType(unsigned Tag, DIType *RTy, uint64_t SizeInBits,
std::optional<unsigned> DWARFAddressSpace) {
assert(RTy && "Unable to create reference type");
return DIDerivedType::get(VMContext, Tag, "", nullptr, 0, nullptr, RTy,
SizeInBits, AlignInBits, 0, DWARFAddressSpace,
SizeInBits, AlignInBits, 0, DWARFAddressSpace, {},
DINode::FlagZero);
}

Expand All @@ -338,15 +352,16 @@ DIDerivedType *DIBuilder::createTypedef(DIType *Ty, StringRef Name,
DINodeArray Annotations) {
return DIDerivedType::get(VMContext, dwarf::DW_TAG_typedef, Name, File,
LineNo, getNonCompileUnitScope(Context), Ty, 0,
AlignInBits, 0, std::nullopt, Flags, nullptr,
Annotations);
AlignInBits, 0, std::nullopt, std::nullopt, Flags,
nullptr, Annotations);
}

DIDerivedType *DIBuilder::createFriend(DIType *Ty, DIType *FriendTy) {
assert(Ty && "Invalid type!");
assert(FriendTy && "Invalid friend type!");
return DIDerivedType::get(VMContext, dwarf::DW_TAG_friend, "", nullptr, 0, Ty,
FriendTy, 0, 0, 0, std::nullopt, DINode::FlagZero);
FriendTy, 0, 0, 0, std::nullopt, std::nullopt,
DINode::FlagZero);
}

DIDerivedType *DIBuilder::createInheritance(DIType *Ty, DIType *BaseTy,
Expand All @@ -358,7 +373,7 @@ DIDerivedType *DIBuilder::createInheritance(DIType *Ty, DIType *BaseTy,
ConstantInt::get(IntegerType::get(VMContext, 32), VBPtrOffset));
return DIDerivedType::get(VMContext, dwarf::DW_TAG_inheritance, "", nullptr,
0, Ty, BaseTy, 0, 0, BaseOffset, std::nullopt,
Flags, ExtraData);
std::nullopt, Flags, ExtraData);
}

DIDerivedType *DIBuilder::createMemberType(
Expand All @@ -368,7 +383,7 @@ DIDerivedType *DIBuilder::createMemberType(
return DIDerivedType::get(VMContext, dwarf::DW_TAG_member, Name, File,
LineNumber, getNonCompileUnitScope(Scope), Ty,
SizeInBits, AlignInBits, OffsetInBits, std::nullopt,
Flags, nullptr, Annotations);
std::nullopt, Flags, nullptr, Annotations);
}

static ConstantAsMetadata *getConstantOrNull(Constant *C) {
Expand All @@ -381,10 +396,10 @@ DIDerivedType *DIBuilder::createVariantMemberType(
DIScope *Scope, StringRef Name, DIFile *File, unsigned LineNumber,
uint64_t SizeInBits, uint32_t AlignInBits, uint64_t OffsetInBits,
Constant *Discriminant, DINode::DIFlags Flags, DIType *Ty) {
return DIDerivedType::get(VMContext, dwarf::DW_TAG_member, Name, File,
LineNumber, getNonCompileUnitScope(Scope), Ty,
SizeInBits, AlignInBits, OffsetInBits, std::nullopt,
Flags, getConstantOrNull(Discriminant));
return DIDerivedType::get(
VMContext, dwarf::DW_TAG_member, Name, File, LineNumber,
getNonCompileUnitScope(Scope), Ty, SizeInBits, AlignInBits, OffsetInBits,
std::nullopt, std::nullopt, Flags, getConstantOrNull(Discriminant));
}

DIDerivedType *DIBuilder::createBitFieldMemberType(
Expand All @@ -395,7 +410,7 @@ DIDerivedType *DIBuilder::createBitFieldMemberType(
return DIDerivedType::get(
VMContext, dwarf::DW_TAG_member, Name, File, LineNumber,
getNonCompileUnitScope(Scope), Ty, SizeInBits, /*AlignInBits=*/0,
OffsetInBits, std::nullopt, Flags,
OffsetInBits, std::nullopt, std::nullopt, Flags,
ConstantAsMetadata::get(ConstantInt::get(IntegerType::get(VMContext, 64),
StorageOffsetInBits)),
Annotations);
Expand All @@ -409,7 +424,8 @@ DIBuilder::createStaticMemberType(DIScope *Scope, StringRef Name, DIFile *File,
Flags |= DINode::FlagStaticMember;
return DIDerivedType::get(VMContext, Tag, Name, File, LineNumber,
getNonCompileUnitScope(Scope), Ty, 0, AlignInBits,
0, std::nullopt, Flags, getConstantOrNull(Val));
0, std::nullopt, std::nullopt, Flags,
getConstantOrNull(Val));
}

DIDerivedType *
Expand All @@ -420,7 +436,7 @@ DIBuilder::createObjCIVar(StringRef Name, DIFile *File, unsigned LineNumber,
return DIDerivedType::get(VMContext, dwarf::DW_TAG_member, Name, File,
LineNumber, getNonCompileUnitScope(File), Ty,
SizeInBits, AlignInBits, OffsetInBits, std::nullopt,
Flags, PropertyNode);
std::nullopt, Flags, PropertyNode);
}

DIObjCProperty *
Expand Down Expand Up @@ -555,10 +571,10 @@ DIDerivedType *DIBuilder::createSetType(DIScope *Scope, StringRef Name,
DIFile *File, unsigned LineNo,
uint64_t SizeInBits,
uint32_t AlignInBits, DIType *Ty) {
auto *R =
DIDerivedType::get(VMContext, dwarf::DW_TAG_set_type, Name, File, LineNo,
getNonCompileUnitScope(Scope), Ty, SizeInBits,
AlignInBits, 0, std::nullopt, DINode::FlagZero);
auto *R = DIDerivedType::get(VMContext, dwarf::DW_TAG_set_type, Name, File,
LineNo, getNonCompileUnitScope(Scope), Ty,
SizeInBits, AlignInBits, 0, std::nullopt,
std::nullopt, DINode::FlagZero);
trackIfUnresolved(R);
return R;
}
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/IR/DebugInfo.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1336,9 +1336,9 @@ LLVMMetadataRef LLVMDIBuilderCreatePointerType(
LLVMDIBuilderRef Builder, LLVMMetadataRef PointeeTy,
uint64_t SizeInBits, uint32_t AlignInBits, unsigned AddressSpace,
const char *Name, size_t NameLen) {
return wrap(unwrap(Builder)->createPointerType(unwrapDI<DIType>(PointeeTy),
SizeInBits, AlignInBits,
AddressSpace, {Name, NameLen}));
return wrap(unwrap(Builder)->createPointerType(
unwrapDI<DIType>(PointeeTy), SizeInBits, AlignInBits, AddressSpace,
{Name, NameLen}));
}

LLVMMetadataRef LLVMDIBuilderCreateStructType(
Expand Down
32 changes: 21 additions & 11 deletions llvm/lib/IR/DebugInfoMetadata.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -34,6 +34,10 @@ cl::opt<bool> EnableFSDiscriminator(
cl::desc("Enable adding flow sensitive discriminators"));
} // namespace llvm

uint32_t DIType::getAlignInBits() const {
return (getTag() == dwarf::DW_TAG_LLVM_ptrauth_type ? 0 : SubclassData32);
}

const DIExpression::FragmentInfo DebugVariable::DefaultFragment = {
std::numeric_limits<uint64_t>::max(), std::numeric_limits<uint64_t>::min()};

Expand Down Expand Up @@ -731,26 +735,32 @@ Constant *DIDerivedType::getDiscriminantValue() const {
return nullptr;
}

DIDerivedType *
DIDerivedType::getImpl(LLVMContext &Context, unsigned Tag, MDString *Name,
Metadata *File, unsigned Line, Metadata *Scope,
Metadata *BaseType, uint64_t SizeInBits,
uint32_t AlignInBits, uint64_t OffsetInBits,
std::optional<unsigned> DWARFAddressSpace, DIFlags Flags,
Metadata *ExtraData, Metadata *Annotations,
StorageType Storage, bool ShouldCreate) {
DIDerivedType *DIDerivedType::getImpl(
LLVMContext &Context, unsigned Tag, MDString *Name, Metadata *File,
unsigned Line, Metadata *Scope, Metadata *BaseType, uint64_t SizeInBits,
uint32_t AlignInBits, uint64_t OffsetInBits,
std::optional<unsigned> DWARFAddressSpace,
std::optional<PtrAuthData> PtrAuthData, DIFlags Flags, Metadata *ExtraData,
Metadata *Annotations, StorageType Storage, bool ShouldCreate) {
assert(isCanonical(Name) && "Expected canonical MDString");
DEFINE_GETIMPL_LOOKUP(DIDerivedType,
(Tag, Name, File, Line, Scope, BaseType, SizeInBits,
AlignInBits, OffsetInBits, DWARFAddressSpace, Flags,
ExtraData, Annotations));
AlignInBits, OffsetInBits, DWARFAddressSpace,
PtrAuthData, Flags, ExtraData, Annotations));
Metadata *Ops[] = {File, Scope, Name, BaseType, ExtraData, Annotations};
DEFINE_GETIMPL_STORE(DIDerivedType,
(Tag, Line, SizeInBits, AlignInBits, OffsetInBits,
DWARFAddressSpace, Flags),
DWARFAddressSpace, PtrAuthData, Flags),
Ops);
}

std::optional<DIDerivedType::PtrAuthData>
DIDerivedType::getPtrAuthData() const {
return getTag() == dwarf::DW_TAG_LLVM_ptrauth_type
? std::optional<PtrAuthData>(PtrAuthData(SubclassData32))
: std::nullopt;
}

DICompositeType *DICompositeType::getImpl(
LLVMContext &Context, unsigned Tag, MDString *Name, Metadata *File,
unsigned Line, Metadata *Scope, Metadata *BaseType, uint64_t SizeInBits,
Expand Down
15 changes: 10 additions & 5 deletions llvm/lib/IR/LLVMContextImpl.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -539,25 +539,29 @@ template <> struct MDNodeKeyImpl<DIDerivedType> {
uint64_t OffsetInBits;
uint32_t AlignInBits;
std::optional<unsigned> DWARFAddressSpace;
std::optional<DIDerivedType::PtrAuthData> PtrAuthData;
unsigned Flags;
Metadata *ExtraData;
Metadata *Annotations;

MDNodeKeyImpl(unsigned Tag, MDString *Name, Metadata *File, unsigned Line,
Metadata *Scope, Metadata *BaseType, uint64_t SizeInBits,
uint32_t AlignInBits, uint64_t OffsetInBits,
std::optional<unsigned> DWARFAddressSpace, unsigned Flags,
Metadata *ExtraData, Metadata *Annotations)
std::optional<unsigned> DWARFAddressSpace,
std::optional<DIDerivedType::PtrAuthData> PtrAuthData,
unsigned Flags, Metadata *ExtraData, Metadata *Annotations)
: Tag(Tag), Name(Name), File(File), Line(Line), Scope(Scope),
BaseType(BaseType), SizeInBits(SizeInBits), OffsetInBits(OffsetInBits),
AlignInBits(AlignInBits), DWARFAddressSpace(DWARFAddressSpace),
Flags(Flags), ExtraData(ExtraData), Annotations(Annotations) {}
PtrAuthData(PtrAuthData), Flags(Flags), ExtraData(ExtraData),
Annotations(Annotations) {}
MDNodeKeyImpl(const DIDerivedType *N)
: Tag(N->getTag()), Name(N->getRawName()), File(N->getRawFile()),
Line(N->getLine()), Scope(N->getRawScope()),
BaseType(N->getRawBaseType()), SizeInBits(N->getSizeInBits()),
OffsetInBits(N->getOffsetInBits()), AlignInBits(N->getAlignInBits()),
DWARFAddressSpace(N->getDWARFAddressSpace()), Flags(N->getFlags()),
DWARFAddressSpace(N->getDWARFAddressSpace()),
PtrAuthData(N->getPtrAuthData()), Flags(N->getFlags()),
ExtraData(N->getRawExtraData()), Annotations(N->getRawAnnotations()) {}

bool isKeyOf(const DIDerivedType *RHS) const {
Expand All @@ -568,7 +572,8 @@ template <> struct MDNodeKeyImpl<DIDerivedType> {
AlignInBits == RHS->getAlignInBits() &&
OffsetInBits == RHS->getOffsetInBits() &&
DWARFAddressSpace == RHS->getDWARFAddressSpace() &&
Flags == RHS->getFlags() && ExtraData == RHS->getRawExtraData() &&
PtrAuthData == RHS->getPtrAuthData() && Flags == RHS->getFlags() &&
ExtraData == RHS->getRawExtraData() &&
Annotations == RHS->getRawAnnotations();
}

Expand Down
1 change: 1 addition & 0 deletions llvm/lib/IR/Verifier.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1223,6 +1223,7 @@ void Verifier::visitDIDerivedType(const DIDerivedType &N) {
N.getTag() == dwarf::DW_TAG_volatile_type ||
N.getTag() == dwarf::DW_TAG_restrict_type ||
N.getTag() == dwarf::DW_TAG_atomic_type ||
N.getTag() == dwarf::DW_TAG_LLVM_ptrauth_type ||
N.getTag() == dwarf::DW_TAG_member ||
(N.getTag() == dwarf::DW_TAG_variable && N.isStaticMember()) ||
N.getTag() == dwarf::DW_TAG_inheritance ||
Expand Down
1 change: 1 addition & 0 deletions llvm/lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def
View file
Original file line number Diff line number Diff line change
Expand Up @@ -284,6 +284,7 @@ const RegisterBankInfo::ValueMapping *getValueMapping(unsigned BankID,
break;
}

assert(Idx < std::size(ValMappings));
assert(Log2_32_Ceil(Size) == Log2_32_Ceil(ValMappings[Idx].BreakDown->Length));
assert(BankID == ValMappings[Idx].BreakDown->RegBank->getID());

Expand Down
14 changes: 0 additions & 14 deletions llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8168,20 +8168,6 @@ void AMDGPUAsmParser::cvtMubufImpl(MCInst &Inst,
bool IsAtomicReturn = false;

if (IsAtomic) {
for (unsigned i = FirstOperandIdx, e = Operands.size(); i != e; ++i) {
AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
if (!Op.isCPol())
continue;
IsAtomicReturn = Op.getImm() & AMDGPU::CPol::GLC;
break;
}

if (!IsAtomicReturn) {
int NewOpc = AMDGPU::getAtomicNoRetOp(Inst.getOpcode());
if (NewOpc != -1)
Inst.setOpcode(NewOpc);
}

IsAtomicReturn = MII.get(Inst.getOpcode()).TSFlags &
SIInstrFlags::IsAtomicRet;
}
Expand Down
88 changes: 29 additions & 59 deletions llvm/lib/Target/AMDGPU/BUFInstructions.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -747,8 +747,7 @@ class MUBUF_AtomicNoRet_Pseudo<string opName, int addrKind,
(outs),
getMUBUFAtomicIns<addrKindCopy, vdataClassCopy, 0, hasRestrictedSOffset>.ret,
getMUBUFAsmOps<addrKindCopy>.ret,
pattern>,
AtomicNoRet<opName # "_" # getAddrName<addrKindCopy>.ret, 0> {
pattern> {
let PseudoInstr = opName # "_" # getAddrName<addrKindCopy>.ret;
let glc_value = 0;
let dlc_value = 0;
Expand All @@ -768,8 +767,7 @@ class MUBUF_AtomicRet_Pseudo<string opName, int addrKind,
(outs vdata_op:$vdata),
getMUBUFAtomicIns<addrKindCopy, vdataClassCopy, 1, hasRestrictedSOffset>.ret,
getMUBUFAsmOps<addrKindCopy>.ret,
pattern>,
AtomicNoRet<opName # "_" # getAddrName<addrKindCopy>.ret, 1> {
pattern> {
let PseudoInstr = opName # "_rtn_" # getAddrName<addrKindCopy>.ret;
let glc_value = 1;
let dlc_value = 0;
Expand Down Expand Up @@ -2511,34 +2509,26 @@ multiclass MUBUF_Real_Atomic_gfx11_Renamed_impl<bits<8> op, bit is_return,
string real_name> {
defvar Rtn = !if(is_return, "_RTN", "");
def _BOTHEN#Rtn#_gfx11 :
MUBUF_Real_Atomic_gfx11_impl<op, NAME # "_BOTHEN" # Rtn, real_name>,
AtomicNoRet<NAME # "_BOTHEN_gfx11", is_return>;
MUBUF_Real_Atomic_gfx11_impl<op, NAME # "_BOTHEN" # Rtn, real_name>;
def _IDXEN#Rtn#_gfx11 :
MUBUF_Real_Atomic_gfx11_impl<op, NAME # "_IDXEN" # Rtn, real_name>,
AtomicNoRet<NAME # "_IDXEN_gfx11", is_return>;
MUBUF_Real_Atomic_gfx11_impl<op, NAME # "_IDXEN" # Rtn, real_name>;
def _OFFEN#Rtn#_gfx11 :
MUBUF_Real_Atomic_gfx11_impl<op, NAME # "_OFFEN" # Rtn, real_name>,
AtomicNoRet<NAME # "_OFFEN_gfx11", is_return>;
MUBUF_Real_Atomic_gfx11_impl<op, NAME # "_OFFEN" # Rtn, real_name>;
def _OFFSET#Rtn#_gfx11 :
MUBUF_Real_Atomic_gfx11_impl<op, NAME # "_OFFSET" # Rtn, real_name>,
AtomicNoRet<NAME # "_OFFSET_gfx11", is_return>;
MUBUF_Real_Atomic_gfx11_impl<op, NAME # "_OFFSET" # Rtn, real_name>;
}

multiclass MUBUF_Real_Atomic_gfx12_Renamed_impl<bits<8> op, bit is_return,
string real_name> {
defvar Rtn = !if(is_return, "_RTN", "");
def _BOTHEN#Rtn#_gfx12 :
MUBUF_Real_Atomic_gfx12_impl<op, NAME # "_VBUFFER_BOTHEN" # Rtn, real_name>,
AtomicNoRet<NAME # "_BOTHEN_gfx12", is_return>;
MUBUF_Real_Atomic_gfx12_impl<op, NAME # "_VBUFFER_BOTHEN" # Rtn, real_name>;
def _IDXEN#Rtn#_gfx12 :
MUBUF_Real_Atomic_gfx12_impl<op, NAME # "_VBUFFER_IDXEN" # Rtn, real_name>,
AtomicNoRet<NAME # "_IDXEN_gfx12", is_return>;
MUBUF_Real_Atomic_gfx12_impl<op, NAME # "_VBUFFER_IDXEN" # Rtn, real_name>;
def _OFFEN#Rtn#_gfx12 :
MUBUF_Real_Atomic_gfx12_impl<op, NAME # "_VBUFFER_OFFEN" # Rtn, real_name>,
AtomicNoRet<NAME # "_OFFEN_gfx12", is_return>;
MUBUF_Real_Atomic_gfx12_impl<op, NAME # "_VBUFFER_OFFEN" # Rtn, real_name>;
def _OFFSET#Rtn#_gfx12 :
MUBUF_Real_Atomic_gfx12_impl<op, NAME # "_VBUFFER_OFFSET" # Rtn, real_name>,
AtomicNoRet<NAME # "_OFFSET_gfx12", is_return>;
MUBUF_Real_Atomic_gfx12_impl<op, NAME # "_VBUFFER_OFFSET" # Rtn, real_name>;
}

multiclass MUBUF_Real_Atomic_gfx11_gfx12_Renamed_impl<bits<8> op, bit is_return,
Expand Down Expand Up @@ -2695,32 +2685,24 @@ multiclass MUBUF_Real_AllAddr_Lds_gfx10<bits<8> op, bit isTFE = 0> {
}
multiclass MUBUF_Real_Atomics_RTN_gfx10<bits<8> op> {
def _BOTHEN_RTN_gfx10 :
MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN_RTN")>,
AtomicNoRet<NAME # "_BOTHEN_gfx10", 1>;
MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN_RTN")>;
def _IDXEN_RTN_gfx10 :
MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_IDXEN_RTN")>,
AtomicNoRet<NAME # "_IDXEN_gfx10", 1>;
MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_IDXEN_RTN")>;
def _OFFEN_RTN_gfx10 :
MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_OFFEN_RTN")>,
AtomicNoRet<NAME # "_OFFEN_gfx10", 1>;
MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_OFFEN_RTN")>;
def _OFFSET_RTN_gfx10 :
MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET_RTN")>,
AtomicNoRet<NAME # "_OFFSET_gfx10", 1>;
MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET_RTN")>;
}
multiclass MUBUF_Real_Atomics_gfx10<bits<8> op> :
MUBUF_Real_Atomics_RTN_gfx10<op> {
def _BOTHEN_gfx10 :
MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN")>,
AtomicNoRet<NAME # "_BOTHEN_gfx10", 0>;
MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN")>;
def _IDXEN_gfx10 :
MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_IDXEN")>,
AtomicNoRet<NAME # "_IDXEN_gfx10", 0>;
MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_IDXEN")>;
def _OFFEN_gfx10 :
MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_OFFEN")>,
AtomicNoRet<NAME # "_OFFEN_gfx10", 0>;
MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_OFFEN")>;
def _OFFSET_gfx10 :
MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET")>,
AtomicNoRet<NAME # "_OFFSET_gfx10", 0>;
MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET")>;
}

defm BUFFER_STORE_BYTE_D16_HI : MUBUF_Real_AllAddr_gfx10<0x019>;
Expand Down Expand Up @@ -2795,36 +2777,26 @@ multiclass MUBUF_Real_AllAddr_Lds_gfx6_gfx7<bits<8> op, bit isTFE = 0> {
}
multiclass MUBUF_Real_Atomics_gfx6_gfx7<bits<8> op> {
def _ADDR64_gfx6_gfx7 :
MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_ADDR64")>,
AtomicNoRet<NAME # "_ADDR64_gfx6_gfx7", 0>;
MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_ADDR64")>;
def _BOTHEN_gfx6_gfx7 :
MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN")>,
AtomicNoRet<NAME # "_BOTHEN_gfx6_gfx7", 0>;
MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN")>;
def _IDXEN_gfx6_gfx7 :
MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_IDXEN")>,
AtomicNoRet<NAME # "_IDXEN_gfx6_gfx7", 0>;
MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_IDXEN")>;
def _OFFEN_gfx6_gfx7 :
MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_OFFEN")>,
AtomicNoRet<NAME # "_OFFEN_gfx6_gfx7", 0>;
MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_OFFEN")>;
def _OFFSET_gfx6_gfx7 :
MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET")>,
AtomicNoRet<NAME # "_OFFSET_gfx6_gfx7", 0>;
MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET")>;

def _ADDR64_RTN_gfx6_gfx7 :
MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_ADDR64_RTN")>,
AtomicNoRet<NAME # "_ADDR64_gfx6_gfx7", 1>;
MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_ADDR64_RTN")>;
def _BOTHEN_RTN_gfx6_gfx7 :
MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN_RTN")>,
AtomicNoRet<NAME # "_BOTHEN_gfx6_gfx7", 1>;
MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN_RTN")>;
def _IDXEN_RTN_gfx6_gfx7 :
MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_IDXEN_RTN")>,
AtomicNoRet<NAME # "_IDXEN_gfx6_gfx7", 1>;
MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_IDXEN_RTN")>;
def _OFFEN_RTN_gfx6_gfx7 :
MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_OFFEN_RTN")>,
AtomicNoRet<NAME # "_OFFEN_gfx6_gfx7", 1>;
MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_OFFEN_RTN")>;
def _OFFSET_RTN_gfx6_gfx7 :
MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET_RTN")>,
AtomicNoRet<NAME # "_OFFSET_gfx6_gfx7", 1>;
MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET_RTN")>;
}

multiclass MUBUF_Real_AllAddr_gfx6_gfx7_gfx10<bits<8> op> :
Expand Down Expand Up @@ -3081,9 +3053,7 @@ class MUBUF_Real_Base_vi <bits<7> op, MUBUF_Pseudo ps, int Enc,
bit has_sccb = ps.has_sccb> :
MUBUF_Real<ps>,
Enc64,
SIMCInstr<ps.PseudoInstr, Enc>,
AtomicNoRet<!subst("_RTN","",NAME), !if(ps.IsAtomicNoRet, 0,
!if(ps.IsAtomicRet, 1, ?))> {
SIMCInstr<ps.PseudoInstr, Enc> {

let Inst{11-0} = !if(ps.has_offset, offset, ?);
let Inst{12} = ps.offen;
Expand Down
129 changes: 57 additions & 72 deletions llvm/lib/Target/AMDGPU/DSInstructions.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -116,19 +116,16 @@ class DS_1A1D_NORET<string opName, RegisterClass rc = VGPR_32>
}

multiclass DS_1A1D_NORET_mc<string opName, RegisterClass rc = VGPR_32> {
def "" : DS_1A1D_NORET<opName, rc>,
AtomicNoRet<opName, 0>;
def "" : DS_1A1D_NORET<opName, rc>;

let has_m0_read = 0 in {
def _gfx9 : DS_1A1D_NORET<opName, rc>,
AtomicNoRet<opName#"_gfx9", 0>;
def _gfx9 : DS_1A1D_NORET<opName, rc>;
}
}

multiclass DS_1A1D_NORET_mc_gfx9<string opName, RegisterClass rc = VGPR_32> {
let has_m0_read = 0 in {
def "" : DS_1A1D_NORET<opName, rc>,
AtomicNoRet<opName, 0>;
def "" : DS_1A1D_NORET<opName, rc>;
}
}

Expand All @@ -144,12 +141,10 @@ class DS_1A2D_NORET<string opName, RegisterClass rc = VGPR_32,
}

multiclass DS_1A2D_NORET_mc<string opName, RegisterClass rc = VGPR_32> {
def "" : DS_1A2D_NORET<opName, rc>,
AtomicNoRet<opName, 0>;
def "" : DS_1A2D_NORET<opName, rc>;

let has_m0_read = 0 in {
def _gfx9 : DS_1A2D_NORET<opName, rc>,
AtomicNoRet<opName#"_gfx9", 0>;
def _gfx9 : DS_1A2D_NORET<opName, rc>;
}
}

Expand Down Expand Up @@ -200,24 +195,17 @@ class DS_1A1D_RET <string opName, RegisterClass rc = VGPR_32,
let IsAtomicRet = 1;
}

multiclass DS_1A1D_RET_mc <string opName, RegisterClass rc = VGPR_32,
string NoRetOp = ""> {
def "" : DS_1A1D_RET<opName, rc>,
AtomicNoRet<NoRetOp, !ne(NoRetOp, "")>;
multiclass DS_1A1D_RET_mc <string opName, RegisterClass rc = VGPR_32> {
def "" : DS_1A1D_RET<opName, rc>;

let has_m0_read = 0 in {
def _gfx9 : DS_1A1D_RET<opName, rc>,
AtomicNoRet<!if(!eq(NoRetOp, ""), "", NoRetOp#"_gfx9"),
!ne(NoRetOp, "")>;
def _gfx9 : DS_1A1D_RET<opName, rc>;
}
}

multiclass DS_1A1D_RET_mc_gfx9 <string opName, RegisterClass rc = VGPR_32,
string NoRetOp = ""> {
multiclass DS_1A1D_RET_mc_gfx9 <string opName, RegisterClass rc = VGPR_32> {
let has_m0_read = 0 in {
def "" : DS_1A1D_RET<opName, rc>,
AtomicNoRet<!if(!eq(NoRetOp, ""), "", NoRetOp),
!ne(NoRetOp, "")>;
def "" : DS_1A1D_RET<opName, rc>;
}
}

Expand All @@ -237,14 +225,11 @@ class DS_1A2D_RET<string opName,

multiclass DS_1A2D_RET_mc<string opName,
RegisterClass rc = VGPR_32,
string NoRetOp = "",
RegisterClass src = rc> {
def "" : DS_1A2D_RET<opName, rc, src>,
AtomicNoRet<NoRetOp, !ne(NoRetOp, "")>;
def "" : DS_1A2D_RET<opName, rc, src>;

let has_m0_read = 0 in {
def _gfx9 : DS_1A2D_RET<opName, rc, src>,
AtomicNoRet<NoRetOp#"_gfx9", !ne(NoRetOp, "")>;
def _gfx9 : DS_1A2D_RET<opName, rc, src>;
}
}

Expand Down Expand Up @@ -489,24 +474,24 @@ def DS_WRITE_ADDTID_B32 : DS_0A1D_NORET<"ds_write_addtid_b32">;

let SubtargetPredicate = HasLdsAtomicAddF64 in {
defm DS_ADD_F64 : DS_1A1D_NORET_mc_gfx9<"ds_add_f64", VReg_64>;
defm DS_ADD_RTN_F64 : DS_1A1D_RET_mc_gfx9<"ds_add_rtn_f64", VReg_64, "ds_add_f64">;
defm DS_ADD_RTN_F64 : DS_1A1D_RET_mc_gfx9<"ds_add_rtn_f64", VReg_64>;
} // End SubtargetPredicate = HasLdsAtomicAddF64

let SubtargetPredicate = HasAtomicDsPkAdd16Insts in {
defm DS_PK_ADD_F16 : DS_1A1D_NORET_mc<"ds_pk_add_f16">;
defm DS_PK_ADD_RTN_F16 : DS_1A1D_RET_mc<"ds_pk_add_rtn_f16", VGPR_32, "ds_pk_add_f16">;
defm DS_PK_ADD_RTN_F16 : DS_1A1D_RET_mc<"ds_pk_add_rtn_f16", VGPR_32>;
defm DS_PK_ADD_BF16 : DS_1A1D_NORET_mc<"ds_pk_add_bf16">;
defm DS_PK_ADD_RTN_BF16 : DS_1A1D_RET_mc<"ds_pk_add_rtn_bf16", VGPR_32, "ds_pk_add_bf16">;
defm DS_PK_ADD_RTN_BF16 : DS_1A1D_RET_mc<"ds_pk_add_rtn_bf16", VGPR_32>;
} // End SubtargetPredicate = HasAtomicDsPkAdd16Insts

defm DS_CMPSTORE_B32 : DS_1A2D_NORET_mc<"ds_cmpstore_b32">;
defm DS_CMPSTORE_F32 : DS_1A2D_NORET_mc<"ds_cmpstore_f32">;
defm DS_CMPSTORE_B64 : DS_1A2D_NORET_mc<"ds_cmpstore_b64", VReg_64>;
defm DS_CMPSTORE_F64 : DS_1A2D_NORET_mc<"ds_cmpstore_f64", VReg_64>;
defm DS_CMPSTORE_RTN_B32 : DS_1A2D_RET_mc<"ds_cmpstore_rtn_b32", VGPR_32, "ds_cmpstore_b32">;
defm DS_CMPSTORE_RTN_F32 : DS_1A2D_RET_mc<"ds_cmpstore_rtn_f32", VGPR_32, "ds_cmpstore_f32">;
defm DS_CMPSTORE_RTN_B64 : DS_1A2D_RET_mc<"ds_cmpstore_rtn_b64", VReg_64, "ds_cmpstore_b64">;
defm DS_CMPSTORE_RTN_F64 : DS_1A2D_RET_mc<"ds_cmpstore_rtn_f64", VReg_64, "ds_cmpstore_f64">;
defm DS_CMPSTORE_RTN_B32 : DS_1A2D_RET_mc<"ds_cmpstore_rtn_b32", VGPR_32>;
defm DS_CMPSTORE_RTN_F32 : DS_1A2D_RET_mc<"ds_cmpstore_rtn_f32", VGPR_32>;
defm DS_CMPSTORE_RTN_B64 : DS_1A2D_RET_mc<"ds_cmpstore_rtn_b64", VReg_64>;
defm DS_CMPSTORE_RTN_F64 : DS_1A2D_RET_mc<"ds_cmpstore_rtn_f64", VReg_64>;

defm DS_MSKOR_B32 : DS_1A2D_NORET_mc<"ds_mskor_b32">;
defm DS_CMPST_B32 : DS_1A2D_NORET_mc<"ds_cmpst_b32">;
Expand Down Expand Up @@ -535,49 +520,49 @@ defm DS_CMPST_F64 : DS_1A2D_NORET_mc<"ds_cmpst_f64", VReg_64>;
defm DS_MIN_F64 : DS_1A1D_NORET_mc<"ds_min_f64", VReg_64>;
defm DS_MAX_F64 : DS_1A1D_NORET_mc<"ds_max_f64", VReg_64>;

defm DS_ADD_RTN_U32 : DS_1A1D_RET_mc<"ds_add_rtn_u32", VGPR_32, "ds_add_u32">;
defm DS_ADD_RTN_U32 : DS_1A1D_RET_mc<"ds_add_rtn_u32", VGPR_32>;

let SubtargetPredicate = HasLDSFPAtomicAdd in {
defm DS_ADD_RTN_F32 : DS_1A1D_RET_mc<"ds_add_rtn_f32", VGPR_32, "ds_add_f32">;
}
defm DS_SUB_RTN_U32 : DS_1A1D_RET_mc<"ds_sub_rtn_u32", VGPR_32, "ds_sub_u32">;
defm DS_RSUB_RTN_U32 : DS_1A1D_RET_mc<"ds_rsub_rtn_u32", VGPR_32, "ds_rsub_u32">;
defm DS_INC_RTN_U32 : DS_1A1D_RET_mc<"ds_inc_rtn_u32", VGPR_32, "ds_inc_u32">;
defm DS_DEC_RTN_U32 : DS_1A1D_RET_mc<"ds_dec_rtn_u32", VGPR_32, "ds_dec_u32">;
defm DS_MIN_RTN_I32 : DS_1A1D_RET_mc<"ds_min_rtn_i32", VGPR_32, "ds_min_i32">;
defm DS_MAX_RTN_I32 : DS_1A1D_RET_mc<"ds_max_rtn_i32", VGPR_32, "ds_max_i32">;
defm DS_MIN_RTN_U32 : DS_1A1D_RET_mc<"ds_min_rtn_u32", VGPR_32, "ds_min_u32">;
defm DS_MAX_RTN_U32 : DS_1A1D_RET_mc<"ds_max_rtn_u32", VGPR_32, "ds_max_u32">;
defm DS_AND_RTN_B32 : DS_1A1D_RET_mc<"ds_and_rtn_b32", VGPR_32, "ds_and_b32">;
defm DS_OR_RTN_B32 : DS_1A1D_RET_mc<"ds_or_rtn_b32", VGPR_32, "ds_or_b32">;
defm DS_XOR_RTN_B32 : DS_1A1D_RET_mc<"ds_xor_rtn_b32", VGPR_32, "ds_xor_b32">;
defm DS_MSKOR_RTN_B32 : DS_1A2D_RET_mc<"ds_mskor_rtn_b32", VGPR_32, "ds_mskor_b32">;
defm DS_CMPST_RTN_B32 : DS_1A2D_RET_mc<"ds_cmpst_rtn_b32", VGPR_32, "ds_cmpst_b32">;
defm DS_CMPST_RTN_F32 : DS_1A2D_RET_mc<"ds_cmpst_rtn_f32", VGPR_32, "ds_cmpst_f32">;
defm DS_MIN_RTN_F32 : DS_1A1D_RET_mc<"ds_min_rtn_f32", VGPR_32, "ds_min_f32">;
defm DS_MAX_RTN_F32 : DS_1A1D_RET_mc<"ds_max_rtn_f32", VGPR_32, "ds_max_f32">;
defm DS_ADD_RTN_F32 : DS_1A1D_RET_mc<"ds_add_rtn_f32", VGPR_32>;
}
defm DS_SUB_RTN_U32 : DS_1A1D_RET_mc<"ds_sub_rtn_u32", VGPR_32>;
defm DS_RSUB_RTN_U32 : DS_1A1D_RET_mc<"ds_rsub_rtn_u32", VGPR_32>;
defm DS_INC_RTN_U32 : DS_1A1D_RET_mc<"ds_inc_rtn_u32", VGPR_32>;
defm DS_DEC_RTN_U32 : DS_1A1D_RET_mc<"ds_dec_rtn_u32", VGPR_32>;
defm DS_MIN_RTN_I32 : DS_1A1D_RET_mc<"ds_min_rtn_i32", VGPR_32>;
defm DS_MAX_RTN_I32 : DS_1A1D_RET_mc<"ds_max_rtn_i32", VGPR_32>;
defm DS_MIN_RTN_U32 : DS_1A1D_RET_mc<"ds_min_rtn_u32", VGPR_32>;
defm DS_MAX_RTN_U32 : DS_1A1D_RET_mc<"ds_max_rtn_u32", VGPR_32>;
defm DS_AND_RTN_B32 : DS_1A1D_RET_mc<"ds_and_rtn_b32", VGPR_32>;
defm DS_OR_RTN_B32 : DS_1A1D_RET_mc<"ds_or_rtn_b32", VGPR_32>;
defm DS_XOR_RTN_B32 : DS_1A1D_RET_mc<"ds_xor_rtn_b32", VGPR_32>;
defm DS_MSKOR_RTN_B32 : DS_1A2D_RET_mc<"ds_mskor_rtn_b32", VGPR_32>;
defm DS_CMPST_RTN_B32 : DS_1A2D_RET_mc<"ds_cmpst_rtn_b32", VGPR_32>;
defm DS_CMPST_RTN_F32 : DS_1A2D_RET_mc<"ds_cmpst_rtn_f32", VGPR_32>;
defm DS_MIN_RTN_F32 : DS_1A1D_RET_mc<"ds_min_rtn_f32", VGPR_32>;
defm DS_MAX_RTN_F32 : DS_1A1D_RET_mc<"ds_max_rtn_f32", VGPR_32>;

defm DS_WRXCHG_RTN_B32 : DS_1A1D_RET_mc<"ds_wrxchg_rtn_b32">;
defm DS_WRXCHG2_RTN_B32 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2_rtn_b32", VReg_64, VGPR_32>;
defm DS_WRXCHG2ST64_RTN_B32 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2st64_rtn_b32", VReg_64, VGPR_32>;

defm DS_ADD_RTN_U64 : DS_1A1D_RET_mc<"ds_add_rtn_u64", VReg_64, "ds_add_u64">;
defm DS_SUB_RTN_U64 : DS_1A1D_RET_mc<"ds_sub_rtn_u64", VReg_64, "ds_sub_u64">;
defm DS_RSUB_RTN_U64 : DS_1A1D_RET_mc<"ds_rsub_rtn_u64", VReg_64, "ds_rsub_u64">;
defm DS_INC_RTN_U64 : DS_1A1D_RET_mc<"ds_inc_rtn_u64", VReg_64, "ds_inc_u64">;
defm DS_DEC_RTN_U64 : DS_1A1D_RET_mc<"ds_dec_rtn_u64", VReg_64, "ds_dec_u64">;
defm DS_MIN_RTN_I64 : DS_1A1D_RET_mc<"ds_min_rtn_i64", VReg_64, "ds_min_i64">;
defm DS_MAX_RTN_I64 : DS_1A1D_RET_mc<"ds_max_rtn_i64", VReg_64, "ds_max_i64">;
defm DS_MIN_RTN_U64 : DS_1A1D_RET_mc<"ds_min_rtn_u64", VReg_64, "ds_min_u64">;
defm DS_MAX_RTN_U64 : DS_1A1D_RET_mc<"ds_max_rtn_u64", VReg_64, "ds_max_u64">;
defm DS_AND_RTN_B64 : DS_1A1D_RET_mc<"ds_and_rtn_b64", VReg_64, "ds_and_b64">;
defm DS_OR_RTN_B64 : DS_1A1D_RET_mc<"ds_or_rtn_b64", VReg_64, "ds_or_b64">;
defm DS_XOR_RTN_B64 : DS_1A1D_RET_mc<"ds_xor_rtn_b64", VReg_64, "ds_xor_b64">;
defm DS_MSKOR_RTN_B64 : DS_1A2D_RET_mc<"ds_mskor_rtn_b64", VReg_64, "ds_mskor_b64">;
defm DS_CMPST_RTN_B64 : DS_1A2D_RET_mc<"ds_cmpst_rtn_b64", VReg_64, "ds_cmpst_b64">;
defm DS_CMPST_RTN_F64 : DS_1A2D_RET_mc<"ds_cmpst_rtn_f64", VReg_64, "ds_cmpst_f64">;
defm DS_MIN_RTN_F64 : DS_1A1D_RET_mc<"ds_min_rtn_f64", VReg_64, "ds_min_f64">;
defm DS_MAX_RTN_F64 : DS_1A1D_RET_mc<"ds_max_rtn_f64", VReg_64, "ds_max_f64">;
defm DS_ADD_RTN_U64 : DS_1A1D_RET_mc<"ds_add_rtn_u64", VReg_64>;
defm DS_SUB_RTN_U64 : DS_1A1D_RET_mc<"ds_sub_rtn_u64", VReg_64>;
defm DS_RSUB_RTN_U64 : DS_1A1D_RET_mc<"ds_rsub_rtn_u64", VReg_64>;
defm DS_INC_RTN_U64 : DS_1A1D_RET_mc<"ds_inc_rtn_u64", VReg_64>;
defm DS_DEC_RTN_U64 : DS_1A1D_RET_mc<"ds_dec_rtn_u64", VReg_64>;
defm DS_MIN_RTN_I64 : DS_1A1D_RET_mc<"ds_min_rtn_i64", VReg_64>;
defm DS_MAX_RTN_I64 : DS_1A1D_RET_mc<"ds_max_rtn_i64", VReg_64>;
defm DS_MIN_RTN_U64 : DS_1A1D_RET_mc<"ds_min_rtn_u64", VReg_64>;
defm DS_MAX_RTN_U64 : DS_1A1D_RET_mc<"ds_max_rtn_u64", VReg_64>;
defm DS_AND_RTN_B64 : DS_1A1D_RET_mc<"ds_and_rtn_b64", VReg_64>;
defm DS_OR_RTN_B64 : DS_1A1D_RET_mc<"ds_or_rtn_b64", VReg_64>;
defm DS_XOR_RTN_B64 : DS_1A1D_RET_mc<"ds_xor_rtn_b64", VReg_64>;
defm DS_MSKOR_RTN_B64 : DS_1A2D_RET_mc<"ds_mskor_rtn_b64", VReg_64>;
defm DS_CMPST_RTN_B64 : DS_1A2D_RET_mc<"ds_cmpst_rtn_b64", VReg_64>;
defm DS_CMPST_RTN_F64 : DS_1A2D_RET_mc<"ds_cmpst_rtn_f64", VReg_64>;
defm DS_MIN_RTN_F64 : DS_1A1D_RET_mc<"ds_min_rtn_f64", VReg_64>;
defm DS_MAX_RTN_F64 : DS_1A1D_RET_mc<"ds_max_rtn_f64", VReg_64>;

defm DS_WRXCHG_RTN_B64 : DS_1A1D_RET_mc<"ds_wrxchg_rtn_b64", VReg_64>;
defm DS_WRXCHG2_RTN_B64 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2_rtn_b64", VReg_128, VReg_64>;
Expand Down Expand Up @@ -740,9 +725,9 @@ def DS_BVH_STACK_RTN_B32 : DS_BVH_STACK<"ds_bvh_stack_rtn_b32">;
let SubtargetPredicate = isGFX12Plus in {

defm DS_COND_SUB_U32 : DS_1A1D_NORET_mc<"ds_cond_sub_u32">;
defm DS_COND_SUB_RTN_U32 : DS_1A1D_RET_mc<"ds_cond_sub_rtn_u32", VGPR_32, "ds_cond_sub_u32">;
defm DS_COND_SUB_RTN_U32 : DS_1A1D_RET_mc<"ds_cond_sub_rtn_u32", VGPR_32>;
defm DS_SUB_CLAMP_U32 : DS_1A1D_NORET_mc<"ds_sub_clamp_u32">;
defm DS_SUB_CLAMP_RTN_U32 : DS_1A1D_RET_mc<"ds_sub_clamp_rtn_u32", VGPR_32, "ds_sub_clamp_u32">;
defm DS_SUB_CLAMP_RTN_U32 : DS_1A1D_RET_mc<"ds_sub_clamp_rtn_u32", VGPR_32>;

multiclass DSAtomicRetNoRetPatIntrinsic_mc<DS_Pseudo inst, DS_Pseudo noRetInst,
ValueType vt, string frag> {
Expand Down
18 changes: 6 additions & 12 deletions llvm/lib/Target/AMDGPU/FLATInstructions.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -541,8 +541,7 @@ multiclass FLAT_Atomic_Pseudo_NO_RTN<
(outs),
(ins VReg_64:$vaddr, data_op:$vdata, flat_offset:$offset, CPol_0:$cpol),
" $vaddr, $vdata$offset$cpol">,
GlobalSaddrTable<0, opName>,
AtomicNoRet <opName, 0> {
GlobalSaddrTable<0, opName> {
let PseudoInstr = NAME;
let FPAtomic = data_vt.isFP;
let AddedComplexity = -1; // Prefer global atomics if available
Expand All @@ -560,8 +559,7 @@ multiclass FLAT_Atomic_Pseudo_RTN<
(outs getLdStRegisterOperand<vdst_rc>.ret:$vdst),
(ins VReg_64:$vaddr, data_op:$vdata, flat_offset:$offset, CPol_GLC1:$cpol),
" $vdst, $vaddr, $vdata$offset$cpol">,
GlobalSaddrTable<0, opName#"_rtn">,
AtomicNoRet <opName, 1> {
GlobalSaddrTable<0, opName#"_rtn"> {
let FPAtomic = data_vt.isFP;
let AddedComplexity = -1; // Prefer global atomics if available
}
Expand Down Expand Up @@ -590,8 +588,7 @@ multiclass FLAT_Global_Atomic_Pseudo_NO_RTN<
(outs),
(ins VReg_64:$vaddr, data_op:$vdata, flat_offset:$offset, CPol_0:$cpol),
" $vaddr, $vdata, off$offset$cpol">,
GlobalSaddrTable<0, opName>,
AtomicNoRet <opName, 0> {
GlobalSaddrTable<0, opName> {
let has_saddr = 1;
let PseudoInstr = NAME;
let FPAtomic = data_vt.isFP;
Expand All @@ -601,8 +598,7 @@ multiclass FLAT_Global_Atomic_Pseudo_NO_RTN<
(outs),
(ins VGPR_32:$vaddr, data_op:$vdata, SReg_64:$saddr, flat_offset:$offset, CPol_0:$cpol),
" $vaddr, $vdata, $saddr$offset$cpol">,
GlobalSaddrTable<1, opName>,
AtomicNoRet <opName#"_saddr", 0> {
GlobalSaddrTable<1, opName> {
let has_saddr = 1;
let enabled_saddr = 1;
let PseudoInstr = NAME#"_SADDR";
Expand All @@ -623,8 +619,7 @@ multiclass FLAT_Global_Atomic_Pseudo_RTN<
(outs vdst_op:$vdst),
(ins VReg_64:$vaddr, data_op:$vdata, flat_offset:$offset, CPol_GLC1:$cpol),
" $vdst, $vaddr, $vdata, off$offset$cpol">,
GlobalSaddrTable<0, opName#"_rtn">,
AtomicNoRet <opName, 1> {
GlobalSaddrTable<0, opName#"_rtn"> {
let has_saddr = 1;
let FPAtomic = data_vt.isFP;
}
Expand All @@ -633,8 +628,7 @@ multiclass FLAT_Global_Atomic_Pseudo_RTN<
(outs vdst_op:$vdst),
(ins VGPR_32:$vaddr, data_op:$vdata, SReg_64:$saddr, flat_offset:$offset, CPol_GLC1:$cpol),
" $vdst, $vaddr, $vdata, $saddr$offset$cpol">,
GlobalSaddrTable<1, opName#"_rtn">,
AtomicNoRet <opName#"_saddr", 1> {
GlobalSaddrTable<1, opName#"_rtn"> {
let has_saddr = 1;
let enabled_saddr = 1;
let PseudoInstr = NAME#"_SADDR_RTN";
Expand Down
3 changes: 0 additions & 3 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1459,9 +1459,6 @@ namespace AMDGPU {
LLVM_READONLY
int getIfAddr64Inst(uint16_t Opcode);

LLVM_READONLY
int getAtomicNoRetOp(uint16_t Opcode);

LLVM_READONLY
int getSOPKOp(uint16_t Opcode);

Expand Down
14 changes: 0 additions & 14 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2591,11 +2591,6 @@ class Commutable_REV <string revOp, bit isOrig> {
bit IsOrig = isOrig;
}

class AtomicNoRet <string noRetOp, bit isRet> {
string NoRetOp = noRetOp;
bit IsRet = isRet;
}

//===----------------------------------------------------------------------===//
// Interpolation opcodes
//===----------------------------------------------------------------------===//
Expand Down Expand Up @@ -2766,15 +2761,6 @@ def getIfAddr64Inst : InstrMapping {
let ValueCols = [["1"]];
}

// Maps an atomic opcode to its returnless version.
def getAtomicNoRetOp : InstrMapping {
let FilterClass = "AtomicNoRet";
let RowFields = ["NoRetOp"];
let ColFields = ["IsRet"];
let KeyCol = ["1"];
let ValueCols = [["0"]];
}

// Maps a GLOBAL to its SADDR form.
def getGlobalSaddrOp : InstrMapping {
let FilterClass = "GlobalSaddrTable";
Expand Down
9 changes: 3 additions & 6 deletions llvm/lib/Target/AMDGPU/SMInstructions.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -277,8 +277,7 @@ class SM_Pseudo_Atomic<string opName,
(ins CPolTy:$cpol)),
!if(isRet, " $sdst", " $sdata") #
", $sbase, " # offsets.Asm # "$cpol",
isRet>,
AtomicNoRet <opNameWithSuffix, isRet> {
isRet> {
let has_offset = offsets.HasOffset;
let has_soffset = offsets.HasSOffset;
let PseudoInstr = opNameWithSuffix;
Expand Down Expand Up @@ -662,8 +661,7 @@ defm S_ATC_PROBE_BUFFER : SM_Real_Probe_vi <0x27>;
//===----------------------------------------------------------------------===//

class SMEM_Atomic_Real_vi <bits<8> op, SM_Atomic_Pseudo ps>
: SMEM_Real_vi <op, ps>,
AtomicNoRet <!subst("_RTN","",NAME), ps.glc> {
: SMEM_Real_vi <op, ps> {

bits<7> sdata;

Expand Down Expand Up @@ -1222,8 +1220,7 @@ defm S_ATC_PROBE : SM_Real_Probe_gfx10 <0x26>;
defm S_ATC_PROBE_BUFFER : SM_Real_Probe_gfx10 <0x27>;

class SMEM_Atomic_Real_gfx10 <bits<8> op, SM_Atomic_Pseudo ps>
: SMEM_Real_gfx10 <op, ps>,
AtomicNoRet <!subst("_RTN","",NAME), ps.glc> {
: SMEM_Real_gfx10 <op, ps> {

bits<7> sdata;

Expand Down
3 changes: 3 additions & 0 deletions llvm/lib/Target/DirectX/DXIL.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -218,6 +218,9 @@ class DXILOpMapping<int opCode, DXILOpClass opClass, Intrinsic intrinsic, string
// Concrete definition of DXIL Operation mapping to corresponding LLVM intrinsic
def Sin : DXILOpMapping<13, unary, int_sin,
"Returns sine(theta) for theta in radians.">;
def Round : DXILOpMapping<26, unary, int_round,
"Returns the input rounded to the nearest integer"
"within a floating-point type.">;
def UMax : DXILOpMapping<39, binary, int_umax,
"Unsigned integer maximum. UMax(a,b) = a > b ? a : b">;
def ThreadId : DXILOpMapping<93, threadId, int_dx_thread_id,
Expand Down
36 changes: 0 additions & 36 deletions llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,14 +15,11 @@
#include "llvm/ADT/MapVector.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/Analysis/BlockFrequencyInfo.h"
#include "llvm/Analysis/DomTreeUpdater.h"
#include "llvm/Analysis/GlobalsModRef.h"
#include "llvm/Analysis/PostDominators.h"
#include "llvm/Analysis/ProfileSummaryInfo.h"
#include "llvm/Analysis/StackSafetyAnalysis.h"
#include "llvm/Analysis/TargetLibraryInfo.h"
#include "llvm/Analysis/ValueTracking.h"
Expand Down Expand Up @@ -180,18 +177,6 @@ static cl::opt<bool> ClWithTls(
"platforms that support this"),
cl::Hidden, cl::init(true));

static cl::opt<bool>
CSkipHotCode("hwasan-skip-hot-code",
cl::desc("Do not instument hot functions based on FDO."),
cl::Hidden, cl::init(false));

static cl::opt<int> HotPercentileCutoff("hwasan-percentile-cutoff-hot",
cl::init(0));

STATISTIC(NumTotalFuncs, "Number of total funcs HWASAN");
STATISTIC(NumInstrumentedFuncs, "Number of HWASAN instrumented funcs");
STATISTIC(NumNoProfileSummaryFuncs, "Number of HWASAN funcs without PS");

// Mode for selecting how to insert frame record info into the stack ring
// buffer.
enum RecordStackHistoryMode {
Expand Down Expand Up @@ -1522,27 +1507,6 @@ void HWAddressSanitizer::sanitizeFunction(Function &F,
if (!F.hasFnAttribute(Attribute::SanitizeHWAddress))
return;

if (F.empty())
return;

NumTotalFuncs++;
if (CSkipHotCode) {
auto &MAMProxy = FAM.getResult<ModuleAnalysisManagerFunctionProxy>(F);
ProfileSummaryInfo *PSI =
MAMProxy.getCachedResult<ProfileSummaryAnalysis>(*F.getParent());
if (PSI && PSI->hasProfileSummary()) {
auto &BFI = FAM.getResult<BlockFrequencyAnalysis>(F);
if ((HotPercentileCutoff.getNumOccurrences() && HotPercentileCutoff >= 0)
? PSI->isFunctionHotInCallGraphNthPercentile(HotPercentileCutoff,
&F, BFI)
: PSI->isFunctionHotInCallGraph(&F, BFI))
return;
} else {
++NumNoProfileSummaryFuncs;
}
}
NumInstrumentedFuncs++;

LLVM_DEBUG(dbgs() << "Function: " << F.getName() << "\n");

SmallVector<InterestingMemoryOperand, 16> OperandsToInstrument;
Expand Down
22 changes: 9 additions & 13 deletions llvm/lib/Transforms/Instrumentation/PGOInstrumentation.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -961,21 +961,16 @@ namespace {
struct PGOUseEdge : public PGOEdge {
using PGOEdge::PGOEdge;

bool CountValid = false;
uint64_t CountValue = 0;
std::optional<uint64_t> Count;

// Set edge count value
void setEdgeCount(uint64_t Value) {
CountValue = Value;
CountValid = true;
}
void setEdgeCount(uint64_t Value) { Count = Value; }

// Return the information string for this object.
std::string infoString() const {
if (!CountValid)
if (!Count)
return PGOEdge::infoString();
return (Twine(PGOEdge::infoString()) + " Count=" + Twine(CountValue))
.str();
return (Twine(PGOEdge::infoString()) + " Count=" + Twine(*Count)).str();
}
};

Expand Down Expand Up @@ -1022,7 +1017,8 @@ static uint64_t sumEdgeCount(const ArrayRef<PGOUseEdge *> Edges) {
for (const auto &E : Edges) {
if (E->Removed)
continue;
Total += E->CountValue;
if (E->Count)
Total += *E->Count;
}
return Total;
}
Expand Down Expand Up @@ -1221,7 +1217,7 @@ bool PGOUseFunc::setInstrumentedCounts(
if (DestInfo.Count && DestInfo.InEdges.size() == 1)
setEdgeCount(E.get(), *DestInfo.Count);
}
if (E->CountValid)
if (E->Count)
continue;
// E's count should have been set from profile. If not, this meenas E skips
// the instrumentation. We set the count to 0.
Expand All @@ -1234,7 +1230,7 @@ bool PGOUseFunc::setInstrumentedCounts(
// unknown edge in Edges vector.
void PGOUseFunc::setEdgeCount(DirectEdges &Edges, uint64_t Value) {
for (auto &E : Edges) {
if (E->CountValid)
if (E->Count)
continue;
E->setEdgeCount(Value);

Expand Down Expand Up @@ -1574,7 +1570,7 @@ void PGOUseFunc::setBranchWeights() {
if (DestBB == nullptr)
continue;
unsigned SuccNum = GetSuccessorNumber(SrcBB, DestBB);
uint64_t EdgeCount = E->CountValue;
uint64_t EdgeCount = *E->Count;
if (EdgeCount > MaxCount)
MaxCount = EdgeCount;
EdgeCounts[SuccNum] = EdgeCount;
Expand Down
16 changes: 14 additions & 2 deletions llvm/test/Assembler/debug-info.ll
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Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s
; RUN: verify-uselistorder %s

; CHECK: !named = !{!0, !0, !1, !2, !3, !4, !5, !6, !7, !8, !8, !9, !10, !11, !12, !13, !14, !15, !16, !17, !18, !19, !20, !21, !22, !23, !24, !25, !26, !27, !27, !28, !29, !30, !31, !32, !33, !34, !35, !36, !37, !38, !39}
!named = !{!0, !1, !2, !3, !4, !5, !6, !7, !8, !9, !10, !11, !12, !13, !14, !15, !16, !17, !18, !19, !20, !21, !22, !23, !24, !25, !26, !27, !28, !29, !30, !31, !32, !33, !34, !35, !36, !37, !38, !39, !40, !41, !42}
; CHECK: !named = !{!0, !0, !1, !2, !3, !4, !5, !6, !7, !8, !8, !9, !10, !11, !12, !13, !14, !15, !16, !17, !18, !19, !20, !21, !22, !23, !24, !25, !26, !27, !27, !28, !29, !30, !31, !32, !33, !34, !35, !36, !37, !38, !39, !40, !41, !42, !43}
!named = !{!0, !1, !2, !3, !4, !5, !6, !7, !8, !9, !10, !11, !12, !13, !14, !15, !16, !17, !18, !19, !20, !21, !22, !23, !24, !25, !26, !27, !28, !29, !30, !31, !32, !33, !34, !35, !36, !37, !38, !39, !40, !41, !42, !43, !44, !45, !46}

; CHECK: !0 = !DISubrange(count: 3, lowerBound: 0)
; CHECK-NEXT: !1 = !DISubrange(count: 3, lowerBound: 4)
Expand Down Expand Up @@ -99,3 +99,15 @@
; CHECK-NEXT: !39 = !DIBasicType(name: "u64.le", size: 64, align: 1, encoding: DW_ATE_unsigned, flags: DIFlagLittleEndian)
!41 = !DIBasicType(name: "u64.be", size: 64, align: 1, encoding: DW_ATE_unsigned, flags: DIFlagBigEndian)
!42 = !DIBasicType(name: "u64.le", size: 64, align: 1, encoding: DW_ATE_unsigned, flags: DIFlagLittleEndian)

; CHECK: !DIDerivedType(tag: DW_TAG_LLVM_ptrauth_type, baseType: !13, ptrAuthKey: 2, ptrAuthIsAddressDiscriminated: true, ptrAuthExtraDiscriminator: 1234, ptrAuthIsaPointer: false, ptrAuthAuthenticatesNullValues: false)
!43 = !DIDerivedType(tag: DW_TAG_LLVM_ptrauth_type, baseType: !15, ptrAuthKey: 2, ptrAuthIsAddressDiscriminated: true, ptrAuthExtraDiscriminator: 1234)

; CHECK: !DIDerivedType(tag: DW_TAG_LLVM_ptrauth_type, baseType: !13, ptrAuthKey: 2, ptrAuthIsAddressDiscriminated: true, ptrAuthExtraDiscriminator: 1234, ptrAuthIsaPointer: true, ptrAuthAuthenticatesNullValues: false)
!44 = !DIDerivedType(tag: DW_TAG_LLVM_ptrauth_type, baseType: !15, ptrAuthKey: 2, ptrAuthIsAddressDiscriminated: true, ptrAuthExtraDiscriminator: 1234, ptrAuthIsaPointer: true)

; CHECK: !DIDerivedType(tag: DW_TAG_LLVM_ptrauth_type, baseType: !13, ptrAuthKey: 2, ptrAuthIsAddressDiscriminated: true, ptrAuthExtraDiscriminator: 1234, ptrAuthIsaPointer: false, ptrAuthAuthenticatesNullValues: true)
!45 = !DIDerivedType(tag: DW_TAG_LLVM_ptrauth_type, baseType: !15, ptrAuthKey: 2, ptrAuthIsAddressDiscriminated: true, ptrAuthExtraDiscriminator: 1234, ptrAuthAuthenticatesNullValues: true)

; CHECK: !DIDerivedType(tag: DW_TAG_LLVM_ptrauth_type, baseType: !13, ptrAuthKey: 2, ptrAuthIsAddressDiscriminated: true, ptrAuthExtraDiscriminator: 1234, ptrAuthIsaPointer: true, ptrAuthAuthenticatesNullValues: true)
!46 = !DIDerivedType(tag: DW_TAG_LLVM_ptrauth_type, baseType: !15, ptrAuthKey: 2, ptrAuthIsAddressDiscriminated: true, ptrAuthExtraDiscriminator: 1234, ptrAuthIsaPointer: true, ptrAuthAuthenticatesNullValues: true)
18 changes: 9 additions & 9 deletions llvm/test/CodeGen/AArch64/and-mask-removal.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -65,9 +65,8 @@ if.end: ; preds = %if.then, %entry
define zeroext i1 @test8_0(i8 zeroext %x) align 2 {
; CHECK-LABEL: test8_0:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: add w8, w0, #74
; CHECK-NEXT: and w8, w8, #0xff
; CHECK-NEXT: cmp w8, #236
; CHECK-NEXT: sub w8, w0, #182
; CHECK-NEXT: cmn w8, #20
; CHECK-NEXT: cset w0, lo
; CHECK-NEXT: ret
entry:
Expand Down Expand Up @@ -508,16 +507,17 @@ define i64 @pr58109(i8 signext %0) {
define i64 @pr58109b(i8 signext %0, i64 %a, i64 %b) {
; CHECK-SD-LABEL: pr58109b:
; CHECK-SD: ; %bb.0:
; CHECK-SD-NEXT: add w8, w0, #1
; CHECK-SD-NEXT: tst w8, #0xfe
; CHECK-SD-NEXT: csel x0, x1, x2, eq
; CHECK-SD-NEXT: and w8, w0, #0xff
; CHECK-SD-NEXT: sub w8, w8, #255
; CHECK-SD-NEXT: cmn w8, #254
; CHECK-SD-NEXT: csel x0, x1, x2, lo
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: pr58109b:
; CHECK-GI: ; %bb.0:
; CHECK-GI-NEXT: add w8, w0, #1
; CHECK-GI-NEXT: and w8, w8, #0xff
; CHECK-GI-NEXT: cmp w8, #2
; CHECK-GI-NEXT: mov w8, #-255 ; =0xffffff01
; CHECK-GI-NEXT: add w8, w8, w0, uxtb
; CHECK-GI-NEXT: cmn w8, #254
; CHECK-GI-NEXT: csel x0, x1, x2, lo
; CHECK-GI-NEXT: ret
%2 = add i8 %0, 1
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AArch64/signed-truncation-check.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -396,7 +396,7 @@ define i1 @add_ultcmp_bad_i24_i8(i24 %x) nounwind {
define i1 @add_ulecmp_bad_i16_i8(i16 %x) nounwind {
; CHECK-LABEL: add_ulecmp_bad_i16_i8:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w0, #1
; CHECK-NEXT: mov w0, #1 // =0x1
; CHECK-NEXT: ret
%tmp0 = add i16 %x, 128 ; 1U << (8-1)
%tmp1 = icmp ule i16 %tmp0, -1 ; when we +1 it, it will wrap to 0
Expand Down
5 changes: 2 additions & 3 deletions llvm/test/CodeGen/AArch64/typepromotion-overflow.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -246,9 +246,8 @@ define i32 @safe_sub_var_imm(ptr nocapture readonly %b) local_unnamed_addr #1 {
; CHECK-LABEL: safe_sub_var_imm:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldrb w8, [x0]
; CHECK-NEXT: add w8, w8, #8
; CHECK-NEXT: and w8, w8, #0xff
; CHECK-NEXT: cmp w8, #252
; CHECK-NEXT: sub w8, w8, #248
; CHECK-NEXT: cmn w8, #4
; CHECK-NEXT: cset w0, hi
; CHECK-NEXT: ret
entry:
Expand Down
31 changes: 31 additions & 0 deletions llvm/test/CodeGen/DirectX/round.ll
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Original file line number Diff line number Diff line change
@@ -0,0 +1,31 @@
; RUN: opt -S -dxil-op-lower < %s | FileCheck %s

; Make sure dxil operation function calls for round are generated for float and half.
; CHECK:call float @dx.op.unary.f32(i32 26, float %{{.*}})
; CHECK:call half @dx.op.unary.f16(i32 26, half %{{.*}})

target datalayout = "e-m:e-p:32:32-i1:32-i8:8-i16:16-i32:32-i64:64-f16:16-f32:32-f64:64-n8:16:32:64"
target triple = "dxil-pc-shadermodel6.7-library"

; Function Attrs: noinline nounwind optnone
define noundef float @round_float(float noundef %a) #0 {
entry:
%a.addr = alloca float, align 4
store float %a, ptr %a.addr, align 4
%0 = load float, ptr %a.addr, align 4
%elt.round = call float @llvm.round.f32(float %0)
ret float %elt.round
}

; Function Attrs: nocallback nofree nosync nounwind readnone speculatable willreturn
declare float @llvm.round.f32(float) #1

; Function Attrs: noinline nounwind optnone
define noundef half @round_half(half noundef %a) #0 {
entry:
%a.addr = alloca half, align 2
store half %a, ptr %a.addr, align 2
%0 = load half, ptr %a.addr, align 2
%elt.round = call half @llvm.round.f16(half %0)
ret half %elt.round
}
5 changes: 2 additions & 3 deletions llvm/test/CodeGen/RISCV/typepromotion-overflow.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -283,9 +283,8 @@ define i32 @safe_sub_var_imm(ptr nocapture readonly %b) local_unnamed_addr #1 {
; CHECK-LABEL: safe_sub_var_imm:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbu a0, 0(a0)
; CHECK-NEXT: addi a0, a0, 8
; CHECK-NEXT: andi a0, a0, 255
; CHECK-NEXT: sltiu a0, a0, 253
; CHECK-NEXT: addi a0, a0, -248
; CHECK-NEXT: sltiu a0, a0, -3
; CHECK-NEXT: xori a0, a0, 1
; CHECK-NEXT: ret
entry:
Expand Down
70 changes: 70 additions & 0 deletions llvm/test/DebugInfo/AArch64/ptrauth.ll
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Original file line number Diff line number Diff line change
@@ -0,0 +1,70 @@
; RUN: llc %s -filetype=obj -mtriple arm64e-apple-darwin -o - \
; RUN: | llvm-dwarfdump - | FileCheck %s

; CHECK: DW_AT_type (0x{{0+}}[[TY:.*]] "void *__ptrauth(4, 0, 0x04d2)")
; CHECK: 0x{{0+}}[[TY]]: DW_TAG_LLVM_ptrauth_type
; CHECK-NEXT: DW_AT_type {{.*}}"void *"
; CHECK-NEXT: DW_AT_LLVM_ptrauth_key (0x04)
; CHECK-NEXT: DW_AT_LLVM_ptrauth_extra_discriminator (0x04d2)

; CHECK: DW_AT_type (0x{{0+}}[[TY:.*]] "void *__ptrauth(4, 1, 0x04d3)")
; CHECK: 0x{{0+}}[[TY]]: DW_TAG_LLVM_ptrauth_type
; CHECK-NEXT: DW_AT_type {{.*}}"void *"
; CHECK-NEXT: DW_AT_LLVM_ptrauth_key (0x04)
; CHECK-NEXT: DW_AT_LLVM_ptrauth_address_discriminated (true)
; CHECK-NEXT: DW_AT_LLVM_ptrauth_extra_discriminator (0x04d3)

; CHECK: DW_AT_type (0x{{0+}}[[TY:.*]] "void *__ptrauth(4, 1, 0x04d4, "isa-pointer")")
; CHECK: 0x{{0+}}[[TY]]: DW_TAG_LLVM_ptrauth_type
; CHECK-NEXT: DW_AT_type {{.*}}"void *"
; CHECK-NEXT: DW_AT_LLVM_ptrauth_key (0x04)
; CHECK-NEXT: DW_AT_LLVM_ptrauth_address_discriminated (true)
; CHECK-NEXT: DW_AT_LLVM_ptrauth_extra_discriminator (0x04d4)
; CHECK-NEXT: DW_AT_LLVM_ptrauth_isa_pointer (true)

; CHECK: DW_AT_type (0x{{0+}}[[TY:.*]] "void *__ptrauth(4, 1, 0x04d5, "authenticates-null-values")")
; CHECK: 0x{{0+}}[[TY]]: DW_TAG_LLVM_ptrauth_type
; CHECK-NEXT: DW_AT_type {{.*}}"void *"
; CHECK-NEXT: DW_AT_LLVM_ptrauth_key (0x04)
; CHECK-NEXT: DW_AT_LLVM_ptrauth_address_discriminated (true)
; CHECK-NEXT: DW_AT_LLVM_ptrauth_extra_discriminator (0x04d5)
; CHECK-NEXT: DW_AT_LLVM_ptrauth_authenticates_null_values (true)

; CHECK: DW_AT_type (0x{{0+}}[[TY:.*]] "void *__ptrauth(4, 1, 0x04d6, "isa-pointer,authenticates-null-values")")
; CHECK: 0x{{0+}}[[TY]]: DW_TAG_LLVM_ptrauth_type
; CHECK-NEXT: DW_AT_type {{.*}}"void *"
; CHECK-NEXT: DW_AT_LLVM_ptrauth_key (0x04)
; CHECK-NEXT: DW_AT_LLVM_ptrauth_address_discriminated (true)
; CHECK-NEXT: DW_AT_LLVM_ptrauth_extra_discriminator (0x04d6)
; CHECK-NEXT: DW_AT_LLVM_ptrauth_isa_pointer (true)
; CHECK-NEXT: DW_AT_LLVM_ptrauth_authenticates_null_values (true)

target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"

@p = common global i8* null, align 8, !dbg !0

!llvm.dbg.cu = !{!10}
!llvm.module.flags = !{!19, !20}

!0 = !DIGlobalVariableExpression(var: !5, expr: !DIExpression())
!1 = !DIGlobalVariableExpression(var: !6, expr: !DIExpression())
!2 = !DIGlobalVariableExpression(var: !7, expr: !DIExpression())
!3 = !DIGlobalVariableExpression(var: !8, expr: !DIExpression())
!4 = !DIGlobalVariableExpression(var: !9, expr: !DIExpression())
!5 = distinct !DIGlobalVariable(name: "p1", scope: !10, file: !11, line: 1, type: !14, isLocal: false, isDefinition: true)
!6 = distinct !DIGlobalVariable(name: "p2", scope: !10, file: !11, line: 1, type: !15, isLocal: false, isDefinition: true)
!7 = distinct !DIGlobalVariable(name: "p3", scope: !10, file: !11, line: 1, type: !16, isLocal: false, isDefinition: true)
!8 = distinct !DIGlobalVariable(name: "p4", scope: !10, file: !11, line: 1, type: !17, isLocal: false, isDefinition: true)
!9 = distinct !DIGlobalVariable(name: "p5", scope: !10, file: !11, line: 1, type: !18, isLocal: false, isDefinition: true)
!10 = distinct !DICompileUnit(language: DW_LANG_C99, file: !11, emissionKind: FullDebug, globals: !13)
!11 = !DIFile(filename: "/tmp/p.c", directory: "/")
!12 = !{}
!13 = !{!0,!1,!2,!3,!4}
!14 = !DIDerivedType(tag: DW_TAG_LLVM_ptrauth_type, baseType: !21, ptrAuthKey: 4, ptrAuthIsAddressDiscriminated: false, ptrAuthExtraDiscriminator: 1234)
!15 = !DIDerivedType(tag: DW_TAG_LLVM_ptrauth_type, baseType: !21, ptrAuthKey: 4, ptrAuthIsAddressDiscriminated: true, ptrAuthExtraDiscriminator: 1235)
!16 = !DIDerivedType(tag: DW_TAG_LLVM_ptrauth_type, baseType: !21, ptrAuthKey: 4, ptrAuthIsAddressDiscriminated: true, ptrAuthExtraDiscriminator: 1236, ptrAuthIsaPointer: true)
!17 = !DIDerivedType(tag: DW_TAG_LLVM_ptrauth_type, baseType: !21, ptrAuthKey: 4, ptrAuthIsAddressDiscriminated: true, ptrAuthExtraDiscriminator: 1237, ptrAuthAuthenticatesNullValues: true)
!18 = !DIDerivedType(tag: DW_TAG_LLVM_ptrauth_type, baseType: !21, ptrAuthKey: 4, ptrAuthIsAddressDiscriminated: true, ptrAuthExtraDiscriminator: 1238, ptrAuthIsaPointer: true, ptrAuthAuthenticatesNullValues: true)
!19 = !{i32 2, !"Dwarf Version", i32 4}
!20 = !{i32 2, !"Debug Info Version", i32 3}
!21 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: null)
14 changes: 0 additions & 14 deletions llvm/test/Instrumentation/HWAddressSanitizer/pgo-opt-out-no-ps.ll
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This file was deleted.

31 changes: 0 additions & 31 deletions llvm/test/Instrumentation/HWAddressSanitizer/pgo-opt-out.ll
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This file was deleted.

7 changes: 4 additions & 3 deletions llvm/test/Transforms/TypePromotion/ARM/icmps.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -4,8 +4,9 @@
define i32 @test_ult_254_inc_imm(i8 zeroext %x) {
; CHECK-LABEL: @test_ult_254_inc_imm(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[ADD:%.*]] = add i8 [[X:%.*]], 1
; CHECK-NEXT: [[CMP:%.*]] = icmp ult i8 [[ADD]], -2
; CHECK-NEXT: [[TMP0:%.*]] = zext i8 [[X:%.*]] to i32
; CHECK-NEXT: [[ADD:%.*]] = add i32 [[TMP0]], -255
; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[ADD]], -2
; CHECK-NEXT: [[RES:%.*]] = select i1 [[CMP]], i32 35, i32 47
; CHECK-NEXT: ret i32 [[RES]]
;
Expand Down Expand Up @@ -368,7 +369,7 @@ if.end:
define i32 @degenerateicmp() {
; CHECK-LABEL: @degenerateicmp(
; CHECK-NEXT: [[TMP1:%.*]] = sub i32 190, 0
; CHECK-NEXT: [[TMP2:%.*]] = icmp ugt i32 225, [[TMP1]]
; CHECK-NEXT: [[TMP2:%.*]] = icmp ugt i32 -31, [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i32 1, i32 0
; CHECK-NEXT: ret i32 [[TMP3]]
;
Expand Down
10 changes: 6 additions & 4 deletions llvm/test/Transforms/TypePromotion/ARM/wrapping.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -89,8 +89,9 @@ define i32 @overflow_add_const_limit(i8 zeroext %a, i8 zeroext %b) {

define i32 @overflow_add_positive_const_limit(i8 zeroext %a) {
; CHECK-LABEL: @overflow_add_positive_const_limit(
; CHECK-NEXT: [[ADD:%.*]] = add i8 [[A:%.*]], 1
; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i8 [[ADD]], -128
; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[A:%.*]] to i32
; CHECK-NEXT: [[ADD:%.*]] = add i32 [[TMP1]], -255
; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[ADD]], -128
; CHECK-NEXT: [[RES:%.*]] = select i1 [[CMP]], i32 8, i32 16
; CHECK-NEXT: ret i32 [[RES]]
;
Expand Down Expand Up @@ -144,8 +145,9 @@ define i32 @safe_add_underflow_neg(i8 zeroext %a) {

define i32 @overflow_sub_negative_const_limit(i8 zeroext %a) {
; CHECK-LABEL: @overflow_sub_negative_const_limit(
; CHECK-NEXT: [[SUB:%.*]] = sub i8 [[A:%.*]], -1
; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i8 [[SUB]], -128
; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[A:%.*]] to i32
; CHECK-NEXT: [[SUB:%.*]] = sub i32 [[TMP1]], 255
; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[SUB]], -128
; CHECK-NEXT: [[RES:%.*]] = select i1 [[CMP]], i32 8, i32 16
; CHECK-NEXT: ret i32 [[RES]]
;
Expand Down
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