20 changes: 14 additions & 6 deletions llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
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Expand Up @@ -456,14 +456,15 @@ class PseudoToVInst<string PseudoInst> {
}

class ToLowerCase<string Upper> {
string L = !subst("VLSEG", "vlseg",
string L = !subst("FF", "ff",
!subst("VLSEG", "vlseg",
!subst("VLSSEG", "vlsseg",
!subst("VSSEG", "vsseg",
!subst("VSSSEG", "vssseg",
!subst("VLOXSEG", "vloxseg",
!subst("VLUXSEG", "vluxseg",
!subst("VSOXSEG", "vsoxseg",
!subst("VSUXSEG", "vsuxseg", Upper))))))));
!subst("VSUXSEG", "vsuxseg", Upper)))))))));
}

// Example: PseudoVLSEG2E32_V_M2 -> int_riscv_vlseg2
Expand Down Expand Up @@ -1744,15 +1745,18 @@ multiclass VPseudoConversionV_W {
defm _W : VPseudoConversion<m.vrclass, m.wvrclass, m, constraint>;
}

multiclass VPseudoUSSegLoad {
multiclass VPseudoUSSegLoad<bit isFF> {
foreach eew = EEWList in {
foreach lmul = MxSet<eew>.m in {
defvar LInfo = lmul.MX;
let VLMul = lmul.value in {
foreach nf = NFSet<lmul>.L in {
defvar vreg = SegRegClass<lmul, nf>.RC;
def nf # "E" # eew # "_V_" # LInfo : VPseudoUSSegLoadNoMask<vreg, eew>;
def nf # "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoUSSegLoadMask<vreg, eew>;
defvar FFStr = !if(isFF, "FF", "");
def nf # "E" # eew # FFStr # "_V_" # LInfo :
VPseudoUSSegLoadNoMask<vreg, eew>;
def nf # "E" # eew # FFStr # "_V_" # LInfo # "_MASK" :
VPseudoUSSegLoadMask<vreg, eew>;
}
}
}
Expand Down Expand Up @@ -3086,7 +3090,7 @@ foreach eew = EEWList in {
//===----------------------------------------------------------------------===//
// 7.8. Vector Load/Store Segment Instructions
//===----------------------------------------------------------------------===//
defm PseudoVLSEG : VPseudoUSSegLoad;
defm PseudoVLSEG : VPseudoUSSegLoad</*fault-only-first*/false>;
defm PseudoVLSSEG : VPseudoSSegLoad;
defm PseudoVLOXSEG : VPseudoISegLoad;
defm PseudoVLUXSEG : VPseudoISegLoad;
Expand All @@ -3095,6 +3099,10 @@ defm PseudoVSSSEG : VPseudoSSegStore;
defm PseudoVSOXSEG : VPseudoISegStore;
defm PseudoVSUXSEG : VPseudoISegStore;

// vlseg<nf>e<eew>ff.v may update VL register
let hasSideEffects = 1, Defs = [VL] in
defm PseudoVLSEG : VPseudoUSSegLoad</*fault-only-first*/true>;

//===----------------------------------------------------------------------===//
// 8. Vector AMO Operations
//===----------------------------------------------------------------------===//
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/attributes.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -47,7 +47,7 @@
; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0"
; RV32C: .attribute 5, "rv32i2p0_c2p0"
; RV32B: .attribute 5, "rv32i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
; RV32V: .attribute 5, "rv32i2p0_v0p9_zvamo0p9_zvlsseg0p9"
; RV32V: .attribute 5, "rv32i2p0_v1p0_zvamo1p0_zvlsseg1p0"
; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh0p1"
; RV32ZBA: .attribute 5, "rv32i2p0_zba0p93"
; RV32ZBB: .attribute 5, "rv32i2p0_zbb0p93"
Expand All @@ -60,7 +60,7 @@
; RV32ZBR: .attribute 5, "rv32i2p0_zbr0p93"
; RV32ZBS: .attribute 5, "rv32i2p0_zbs0p93"
; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93"
; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p9_zfh0p1_zbb0p93_zvamo0p9_zvlsseg0p9"
; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v1p0_zfh0p1_zbb0p93_zvamo1p0_zvlsseg1p0"

; RV64M: .attribute 5, "rv64i2p0_m2p0"
; RV64A: .attribute 5, "rv64i2p0_a2p0"
Expand All @@ -80,8 +80,8 @@
; RV64ZBR: .attribute 5, "rv64i2p0_zbr0p93"
; RV64ZBS: .attribute 5, "rv64i2p0_zbs0p93"
; RV64ZBT: .attribute 5, "rv64i2p0_zbt0p93"
; RV64V: .attribute 5, "rv64i2p0_v0p9_zvamo0p9_zvlsseg0p9"
; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_v0p9_zfh0p1_zbb0p93_zvamo0p9_zvlsseg0p9"
; RV64V: .attribute 5, "rv64i2p0_v1p0_zvamo1p0_zvlsseg1p0"
; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_v1p0_zfh0p1_zbb0p93_zvamo1p0_zvlsseg1p0"


define i32 @addi(i32 %a) {
Expand Down
89 changes: 89 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll
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@@ -0,0 +1,89 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zvlsseg,+experimental-zfh \
; RUN: -verify-machineinstrs < %s | FileCheck %s

declare {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} @llvm.riscv.vlseg2ff.nxv16i16(i16* , i32)
declare {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i1>, i32)

define void @test_vlseg2ff_dead_value(i16* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_dead_value:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vlseg2e16ff.v v0, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} @llvm.riscv.vlseg2ff.nxv16i16(i16* %base, i32 %vl)
%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} %0, 2
store i32 %1, i32* %outvl
ret void
}

define void @test_vlseg2ff_mask_dead_value(<vscale x 16 x i16> %val, i16* %base, i32 %vl, <vscale x 16 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_dead_value:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
; CHECK-NEXT: vlseg2e16ff.v v8, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} %0, 2
store i32 %1, i32* %outvl
ret void
}

define <vscale x 16 x i16> @test_vlseg2ff_dead_vl(i16* %base, i32 %vl) {
; CHECK-LABEL: test_vlseg2ff_dead_vl:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vlseg2e16ff.v v4, (a0)
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} @llvm.riscv.vlseg2ff.nxv16i16(i16* %base, i32 %vl)
%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} %0, 1
ret <vscale x 16 x i16> %1
}

define <vscale x 16 x i16> @test_vlseg2ff_mask_dead_vl(<vscale x 16 x i16> %val, i16* %base, i32 %vl, <vscale x 16 x i1> %mask) {
; CHECK-LABEL: test_vlseg2ff_mask_dead_vl:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv4r.v v4, v8
; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
; CHECK-NEXT: vlseg2e16ff.v v4, (a0), v0.t
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} %0, 1
ret <vscale x 16 x i16> %1
}

define void @test_vlseg2ff_dead_all(i16* %base, i32 %vl) {
; CHECK-LABEL: test_vlseg2ff_dead_all:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vlseg2e16ff.v v0, (a0)
; CHECK-NEXT: ret
entry:
tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} @llvm.riscv.vlseg2ff.nxv16i16(i16* %base, i32 %vl)
ret void
}

define void @test_vlseg2ff_mask_dead_all(<vscale x 16 x i16> %val, i16* %base, i32 %vl, <vscale x 16 x i1> %mask) {
; CHECK-LABEL: test_vlseg2ff_mask_dead_all:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
; CHECK-NEXT: vlseg2e16ff.v v8, (a0), v0.t
; CHECK-NEXT: ret
entry:
tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i32 %vl)
ret void
}
5,239 changes: 5,239 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll
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89 changes: 89 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll
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@@ -0,0 +1,89 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zvlsseg,+experimental-zfh \
; RUN: -verify-machineinstrs < %s | FileCheck %s

declare {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.nxv16i16(i16* , i64)
declare {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i1>, i64)

define void @test_vlseg2ff_dead_value(i16* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_dead_value:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vlseg2e16ff.v v0, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.nxv16i16(i16* %base, i64 %vl)
%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 2
store i64 %1, i64* %outvl
ret void
}

define void @test_vlseg2ff_mask_dead_value(<vscale x 16 x i16> %val, i16* %base, i64 %vl, <vscale x 16 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_dead_value:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
; CHECK-NEXT: vlseg2e16ff.v v8, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 2
store i64 %1, i64* %outvl
ret void
}

define <vscale x 16 x i16> @test_vlseg2ff_dead_vl(i16* %base, i64 %vl) {
; CHECK-LABEL: test_vlseg2ff_dead_vl:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vlseg2e16ff.v v4, (a0)
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.nxv16i16(i16* %base, i64 %vl)
%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 1
ret <vscale x 16 x i16> %1
}

define <vscale x 16 x i16> @test_vlseg2ff_mask_dead_vl(<vscale x 16 x i16> %val, i16* %base, i64 %vl, <vscale x 16 x i1> %mask) {
; CHECK-LABEL: test_vlseg2ff_mask_dead_vl:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv4r.v v4, v8
; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
; CHECK-NEXT: vlseg2e16ff.v v4, (a0), v0.t
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 1
ret <vscale x 16 x i16> %1
}

define void @test_vlseg2ff_dead_all(i16* %base, i64 %vl) {
; CHECK-LABEL: test_vlseg2ff_dead_all:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vlseg2e16ff.v v0, (a0)
; CHECK-NEXT: ret
entry:
tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.nxv16i16(i16* %base, i64 %vl)
ret void
}

define void @test_vlseg2ff_mask_dead_all(<vscale x 16 x i16> %val, i16* %base, i64 %vl, <vscale x 16 x i1> %mask) {
; CHECK-LABEL: test_vlseg2ff_mask_dead_all:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
; CHECK-NEXT: vlseg2e16ff.v v8, (a0), v0.t
; CHECK-NEXT: ret
entry:
tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i64 %vl)
ret void
}
5,681 changes: 5,681 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll
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8 changes: 4 additions & 4 deletions llvm/test/MC/RISCV/attribute-arch.s
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Original file line number Diff line number Diff line change
Expand Up @@ -40,7 +40,7 @@
# CHECK: attribute 5, "rv32i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"

.attribute arch, "rv32iv"
# CHECK: attribute 5, "rv32i2p0_v0p9"
# CHECK: attribute 5, "rv32i2p0_v1p0"

.attribute arch, "rv32izba"
# CHECK: attribute 5, "rv32i2p0_zba0p93"
Expand Down Expand Up @@ -79,7 +79,7 @@
# CHECK: attribute 5, "rv32i2p0_f2p0_zfh0p1"

.attribute arch, "rv32ivzvamo_zvlsseg"
# CHECK: attribute 5, "rv32i2p0_v0p9_zvamo0p9_zvlsseg0p9"
# CHECK: attribute 5, "rv32i2p0_v1p0_zvamo1p0_zvlsseg1p0"

.attribute arch, "rv32iv_zvamo0p9_zvlsseg"
# CHECK: attribute 5, "rv32i2p0_v0p9_zvamo0p9_zvlsseg0p9"
.attribute arch, "rv32iv_zvamo1p0_zvlsseg"
# CHECK: attribute 5, "rv32i2p0_v1p0_zvamo1p0_zvlsseg1p0"