83 changes: 83 additions & 0 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-xchg-region.mir
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@@ -0,0 +1,83 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX6 %s
# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX7 %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX7 %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX9 %s
# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX9 %s


---
name: atomicrmw_xchg_s32_region
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; GFX6-LABEL: name: atomicrmw_xchg_s32_region
; GFX6: liveins: $vgpr0, $vgpr1
; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX6: $m0 = S_MOV_B32 -1
; GFX6: [[DS_WRXCHG_RTN_B32_:%[0-9]+]]:vgpr_32 = DS_WRXCHG_RTN_B32 [[COPY]], [[COPY1]], 0, 1, implicit $m0, implicit $exec :: (load store seq_cst 4, addrspace 2)
; GFX6: $vgpr0 = COPY [[DS_WRXCHG_RTN_B32_]]
; GFX7-LABEL: name: atomicrmw_xchg_s32_region
; GFX7: liveins: $vgpr0, $vgpr1
; GFX7: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX7: $m0 = S_MOV_B32 -1
; GFX7: [[DS_WRXCHG_RTN_B32_:%[0-9]+]]:vgpr_32 = DS_WRXCHG_RTN_B32 [[COPY]], [[COPY1]], 0, 1, implicit $m0, implicit $exec :: (load store seq_cst 4, addrspace 2)
; GFX7: $vgpr0 = COPY [[DS_WRXCHG_RTN_B32_]]
; GFX9-LABEL: name: atomicrmw_xchg_s32_region
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9: [[DS_WRXCHG_RTN_B32_:%[0-9]+]]:vgpr_32 = DS_WRXCHG_RTN_B32 [[COPY]], [[COPY1]], 0, 1, implicit $m0, implicit $exec :: (load store seq_cst 4, addrspace 2)
; GFX9: $vgpr0 = COPY [[DS_WRXCHG_RTN_B32_]]
%0:vgpr(p2) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s32) = G_ATOMICRMW_XCHG %0(p2), %1 :: (load store seq_cst 4, addrspace 2)
$vgpr0 = COPY %2
...

---
name: atomicrmw_xchg_s32_region_gep4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; GFX6-LABEL: name: atomicrmw_xchg_s32_region_gep4
; GFX6: liveins: $vgpr0, $vgpr1
; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4, implicit $exec
; GFX6: %3:vgpr_32, dead %5:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX6: $m0 = S_MOV_B32 -1
; GFX6: [[DS_WRXCHG_RTN_B32_:%[0-9]+]]:vgpr_32 = DS_WRXCHG_RTN_B32 %3, [[COPY1]], 0, 1, implicit $m0, implicit $exec :: (load store seq_cst 4, addrspace 2)
; GFX6: $vgpr0 = COPY [[DS_WRXCHG_RTN_B32_]]
; GFX7-LABEL: name: atomicrmw_xchg_s32_region_gep4
; GFX7: liveins: $vgpr0, $vgpr1
; GFX7: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX7: $m0 = S_MOV_B32 -1
; GFX7: [[DS_WRXCHG_RTN_B32_:%[0-9]+]]:vgpr_32 = DS_WRXCHG_RTN_B32 [[COPY]], [[COPY1]], 4, 1, implicit $m0, implicit $exec :: (load store seq_cst 4, addrspace 2)
; GFX7: $vgpr0 = COPY [[DS_WRXCHG_RTN_B32_]]
; GFX9-LABEL: name: atomicrmw_xchg_s32_region_gep4
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9: [[DS_WRXCHG_RTN_B32_:%[0-9]+]]:vgpr_32 = DS_WRXCHG_RTN_B32 [[COPY]], [[COPY1]], 4, 1, implicit $m0, implicit $exec :: (load store seq_cst 4, addrspace 2)
; GFX9: $vgpr0 = COPY [[DS_WRXCHG_RTN_B32_]]
%0:vgpr(p2) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s32) = G_CONSTANT i32 4
%3:vgpr(p2) = G_PTR_ADD %0, %2
%4:vgpr(s32) = G_ATOMICRMW_XCHG %3(p2), %1 :: (load store seq_cst 4, addrspace 2)
$vgpr0 = COPY %4
...
91 changes: 91 additions & 0 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
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Expand Up @@ -1547,3 +1547,94 @@ body: |
S_SETPC_B64 undef $sgpr30_sgpr31
...
---
name: test_phi_v2s1
tracksRegLiveness: true

body: |
; CHECK-LABEL: name: test_phi_v2s1
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C1]](s32)
; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C2]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C2]]
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[AND]](s32), [[AND1]]
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C2]]
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C2]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[AND2]](s32), [[AND3]]
; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY3]](s32), [[C]]
; CHECK: G_BRCOND [[ICMP2]](s1), %bb.1
; CHECK: G_BR %bb.2
; CHECK: bb.1:
; CHECK: successors: %bb.2(0x80000000)
; CHECK: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C3]](s32)
; CHECK: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY2]](<2 x s16>)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C3]](s32)
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C4]]
; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C4]]
; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND4]](s32), [[AND5]]
; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C4]]
; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C4]]
; CHECK: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND6]](s32), [[AND7]]
; CHECK: G_BR %bb.2
; CHECK: bb.2:
; CHECK: [[PHI:%[0-9]+]]:_(s1) = G_PHI [[ICMP]](s1), %bb.0, [[ICMP3]](s1), %bb.1
; CHECK: [[PHI1:%[0-9]+]]:_(s1) = G_PHI [[ICMP1]](s1), %bb.0, [[ICMP4]](s1), %bb.1
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s1)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI1]](s1)
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C5]]
; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C5]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND8]](s32), [[AND9]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31
bb.0:
successors: %bb.1, %bb.2
liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(<2 x s16>) = COPY $vgpr1
%2:_(<2 x s16>) = COPY $vgpr2
%3:_(s32) = COPY $vgpr1
%4:_(s32) = G_CONSTANT i32 0
%5:_(<2 x s1>) = G_ICMP intpred(eq), %0, %1
%6:_(s1) = G_ICMP intpred(eq), %3, %4
G_BRCOND %6, %bb.1
G_BR %bb.2
bb.1:
successors: %bb.2
%7:_(<2 x s1>) = G_ICMP intpred(ne), %0, %2
G_BR %bb.2
bb.2:
%8:_(<2 x s1>) = G_PHI %5, %bb.0, %7, %bb.1
%9:_(<2 x s32>) = G_ZEXT %8
$vgpr0_vgpr1 = COPY %9
S_SETPC_B64 undef $sgpr30_sgpr31
...
234 changes: 234 additions & 0 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptr-add.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -143,3 +143,237 @@ body: |
%2:_(p999) = G_PTR_ADD %0, %1
$vgpr0_vgpr1 = COPY %2
...

---
name: test_gep_v2p1_v2i64
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; CHECK-LABEL: name: test_gep_v2p1_v2i64
; CHECK: [[COPY:%[0-9]+]]:_(<2 x p1>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
; CHECK: [[UV:%[0-9]+]]:_(p1), [[UV1:%[0-9]+]]:_(p1) = G_UNMERGE_VALUES [[COPY]](<2 x p1>)
; CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>)
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[UV]], [[UV2]](s64)
; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[UV1]], [[UV3]](s64)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p1>) = G_BUILD_VECTOR [[PTR_ADD]](p1), [[PTR_ADD1]](p1)
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x p1>)
%0:_(<2 x p1>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(<2 x s64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
%2:_(<2 x p1>) = G_PTR_ADD %0, %1
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %2
...

---
name: test_gep_v2p3_v2s32
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CHECK-LABEL: name: test_gep_v2p3_v2s32
; CHECK: [[COPY:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; CHECK: [[UV:%[0-9]+]]:_(p3), [[UV1:%[0-9]+]]:_(p3) = G_UNMERGE_VALUES [[COPY]](<2 x p3>)
; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[UV]], [[UV2]](s32)
; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p3) = G_PTR_ADD [[UV1]], [[UV3]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p3>) = G_BUILD_VECTOR [[PTR_ADD]](p3), [[PTR_ADD1]](p3)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x p3>)
%0:_(<2 x p3>) = COPY $vgpr0_vgpr1
%1:_(<2 x s32>) = COPY $vgpr2_vgpr3
%2:_(<2 x p3>) = G_PTR_ADD %0, %1
$vgpr0_vgpr1 = COPY %2
...

---
name: test_gep_global_s16_idx
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2
; CHECK-LABEL: name: test_gep_global_s16_idx
; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY1]](s32)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ANYEXT]], 16
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[SEXT_INREG]](s64)
; CHECK: $vgpr0_vgpr1 = COPY [[PTR_ADD]](p1)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
%2:_(s16) = G_TRUNC %1
%3:_(p1) = G_PTR_ADD %0, %2
$vgpr0_vgpr1 = COPY %3
...

---
name: test_gep_global_s32_idx
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2
; CHECK-LABEL: name: test_gep_global_s32_idx
; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[SEXT]](s64)
; CHECK: $vgpr0_vgpr1 = COPY [[PTR_ADD]](p1)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
%2:_(p1) = G_PTR_ADD %0, %1
$vgpr0_vgpr1 = COPY %2
...

---
name: test_gep_global_s96_idx
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4
; CHECK-LABEL: name: test_gep_global_s96_idx
; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:_(s96) = COPY $vgpr2_vgpr3_vgpr4
; CHECK: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY1]](s96)
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[TRUNC]](s64)
; CHECK: $vgpr0_vgpr1 = COPY [[PTR_ADD]](p1)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s96) = COPY $vgpr2_vgpr3_vgpr4
%2:_(p1) = G_PTR_ADD %0, %1
$vgpr0_vgpr1 = COPY %2
...

---
name: test_gep_local_i16_idx
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; CHECK-LABEL: name: test_gep_local_i16_idx
; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[SEXT_INREG]](s32)
; CHECK: $vgpr0 = COPY [[PTR_ADD]](p3)
%0:_(p3) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %1
%3:_(p3) = G_PTR_ADD %0, %2
$vgpr0 = COPY %3
...

---
name: test_gep_local_i64_idx
body: |
bb.0:
liveins: $vgpr0, $vgpr1_vgpr2
; CHECK-LABEL: name: test_gep_local_i64_idx
; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr1_vgpr2
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[TRUNC]](s32)
; CHECK: $vgpr0 = COPY [[PTR_ADD]](p3)
%0:_(p3) = COPY $vgpr0
%1:_(s64) = COPY $vgpr1_vgpr2
%2:_(p3) = G_PTR_ADD %0, %1
$vgpr0 = COPY %2
...

---
name: test_gep_v2p1_v2i32
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5
; CHECK-LABEL: name: test_gep_v2p1_v2i32
; CHECK: [[COPY:%[0-9]+]]:_(<2 x p1>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr4_vgpr5
; CHECK: [[UV:%[0-9]+]]:_(p1), [[UV1:%[0-9]+]]:_(p1) = G_UNMERGE_VALUES [[COPY]](<2 x p1>)
; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[UV2]](s32)
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[UV]], [[SEXT]](s64)
; CHECK: [[SEXT1:%[0-9]+]]:_(s64) = G_SEXT [[UV3]](s32)
; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[UV1]], [[SEXT1]](s64)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p1>) = G_BUILD_VECTOR [[PTR_ADD]](p1), [[PTR_ADD1]](p1)
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x p1>)
%0:_(<2 x p1>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(<2 x s32>) = COPY $vgpr4_vgpr5
%2:_(<2 x p1>) = G_PTR_ADD %0, %1
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %2
...

---
name: test_gep_v2p1_v2i96
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6, $vgpr7_vgpr8_vgpr9
; CHECK-LABEL: name: test_gep_v2p1_v2i96
; CHECK: [[COPY:%[0-9]+]]:_(<2 x p1>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK: [[COPY1:%[0-9]+]]:_(s96) = COPY $vgpr4_vgpr5_vgpr6
; CHECK: [[COPY2:%[0-9]+]]:_(s96) = COPY $vgpr7_vgpr8_vgpr9
; CHECK: [[UV:%[0-9]+]]:_(p1), [[UV1:%[0-9]+]]:_(p1) = G_UNMERGE_VALUES [[COPY]](<2 x p1>)
; CHECK: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY1]](s96)
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[UV]], [[TRUNC]](s64)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[COPY2]](s96)
; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[UV1]], [[TRUNC1]](s64)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p1>) = G_BUILD_VECTOR [[PTR_ADD]](p1), [[PTR_ADD1]](p1)
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x p1>)
%0:_(<2 x p1>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s96) = COPY $vgpr4_vgpr5_vgpr6
%2:_(s96) = COPY $vgpr7_vgpr8_vgpr9
%3:_(<2 x s96>) = G_BUILD_VECTOR %1, %2
%4:_(<2 x p1>) = G_PTR_ADD %0, %3
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %4
...

---
name: test_gep_v2p3_v2s16
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2
; CHECK-LABEL: name: test_gep_v2p3_v2s16
; CHECK: [[COPY:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
; CHECK: [[UV:%[0-9]+]]:_(p3), [[UV1:%[0-9]+]]:_(p3) = G_UNMERGE_VALUES [[COPY]](<2 x p3>)
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[UV]], [[SEXT_INREG]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p3) = G_PTR_ADD [[UV1]], [[SEXT_INREG1]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p3>) = G_BUILD_VECTOR [[PTR_ADD]](p3), [[PTR_ADD1]](p3)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x p3>)
%0:_(<2 x p3>) = COPY $vgpr0_vgpr1
%1:_(<2 x s16>) = COPY $vgpr2
%2:_(<2 x p3>) = G_PTR_ADD %0, %1
$vgpr0_vgpr1 = COPY %2
...

---
name: test_gep_v2p3_v2s64
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; CHECK-LABEL: name: test_gep_v2p3_v2s64
; CHECK: [[COPY:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; CHECK: [[UV:%[0-9]+]]:_(p3), [[UV1:%[0-9]+]]:_(p3) = G_UNMERGE_VALUES [[COPY]](<2 x p3>)
; CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>)
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[UV2]](s64)
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[UV]], [[TRUNC]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[UV3]](s64)
; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p3) = G_PTR_ADD [[UV1]], [[TRUNC1]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p3>) = G_BUILD_VECTOR [[PTR_ADD]](p3), [[PTR_ADD1]](p3)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x p3>)
%0:_(<2 x p3>) = COPY $vgpr0_vgpr1
%1:_(<2 x s64>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
%2:_(<2 x p3>) = G_PTR_ADD %0, %1
$vgpr0_vgpr1 = COPY %2
...