10 changes: 5 additions & 5 deletions llvm/lib/Target/ARM/ARMISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4952,7 +4952,7 @@ SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
Opcode = ARMISD::CSINC;
std::swap(TrueVal, FalseVal);
std::swap(TVal, FVal);
CC = ISD::getSetCCInverse(CC, true);
CC = ISD::getSetCCInverse(CC, LHS.getValueType());
}

if (Opcode) {
Expand All @@ -4962,7 +4962,7 @@ SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
HasLowerConstantMaterializationCost(FVal, TVal, Subtarget)) {
std::swap(TrueVal, FalseVal);
std::swap(TVal, FVal);
CC = ISD::getSetCCInverse(CC, true);
CC = ISD::getSetCCInverse(CC, LHS.getValueType());
}

// Attempt to use ZR checking TVal is 0, possibly inverting the condition
Expand All @@ -4971,7 +4971,7 @@ SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
if (FVal == 0 && Opcode != ARMISD::CSINC) {
std::swap(TrueVal, FalseVal);
std::swap(TVal, FVal);
CC = ISD::getSetCCInverse(CC, true);
CC = ISD::getSetCCInverse(CC, LHS.getValueType());
}
if (TVal == 0)
TrueVal = DAG.getRegister(ARM::ZR, MVT::i32);
Expand Down Expand Up @@ -5015,7 +5015,7 @@ SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
if (CondCode == ARMCC::LT || CondCode == ARMCC::LE ||
CondCode == ARMCC::VC || CondCode == ARMCC::NE) {
CC = ISD::getSetCCInverse(CC, true);
CC = ISD::getSetCCInverse(CC, LHS.getValueType());
std::swap(TrueVal, FalseVal);
}
}
Expand Down Expand Up @@ -14226,7 +14226,7 @@ static SDValue PerformHWLoopCombine(SDNode *N,
return SDValue();

if (Negate)
CC = ISD::getSetCCInverse(CC, true);
CC = ISD::getSetCCInverse(CC, /* Integer inverse */ MVT::i32);

auto IsTrueIfZero = [](ISD::CondCode CC, int Imm) {
return (CC == ISD::SETEQ && Imm == 0) ||
Expand Down
6 changes: 4 additions & 2 deletions llvm/lib/Target/Mips/MipsISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -709,7 +709,8 @@ static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,
SDValue True = N->getOperand(1);

SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
SetCC.getOperand(1),
ISD::getSetCCInverse(CC, SetCC.getValueType()));

return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
}
Expand Down Expand Up @@ -743,7 +744,8 @@ static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,
if (Diff == -1) {
ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
SetCC.getOperand(1),
ISD::getSetCCInverse(CC, SetCC.getValueType()));
return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True);
}

Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3597,7 +3597,7 @@ SDValue IntegerCompareEliminator::getSETCCInGPR(SDValue Compare,

if (ConvOpts == SetccInGPROpts::ZExtInvert ||
ConvOpts == SetccInGPROpts::SExtInvert)
CC = ISD::getSetCCInverse(CC, true);
CC = ISD::getSetCCInverse(CC, InputVT);

bool Inputs32Bit = InputVT == MVT::i32;

Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2693,7 +2693,7 @@ static unsigned getVectorComparisonOrInvert(ISD::CondCode CC, CmpMode Mode,
return Opcode;
}

CC = ISD::getSetCCInverse(CC, Mode == CmpMode::Int);
CC = ISD::getSetCCInverse(CC, Mode == CmpMode::Int ? MVT::i32 : MVT::f32);
if (unsigned Opcode = getVectorComparison(CC, Mode)) {
Invert = true;
return Opcode;
Expand Down
9 changes: 4 additions & 5 deletions llvm/lib/Target/X86/X86ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -36887,9 +36887,8 @@ combineVSelectWithAllOnesOrZeros(SDNode *N, SelectionDAG &DAG,

if (TValIsAllZeros || FValIsAllOnes) {
SDValue CC = Cond.getOperand(2);
ISD::CondCode NewCC =
ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
Cond.getOperand(0).getValueType().isInteger());
ISD::CondCode NewCC = ISD::getSetCCInverse(
cast<CondCodeSDNode>(CC)->get(), Cond.getOperand(0).getValueType());
Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1),
NewCC);
std::swap(LHS, RHS);
Expand Down Expand Up @@ -37411,7 +37410,7 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
SDValue Other;
if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
Other = RHS;
CC = ISD::getSetCCInverse(CC, true);
CC = ISD::getSetCCInverse(CC, VT.getVectorElementType());
} else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
Other = LHS;
}
Expand Down Expand Up @@ -37483,7 +37482,7 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
SDValue Other;
if (ISD::isBuildVectorAllOnes(LHS.getNode())) {
Other = RHS;
CC = ISD::getSetCCInverse(CC, true);
CC = ISD::getSetCCInverse(CC, VT.getVectorElementType());
} else if (ISD::isBuildVectorAllOnes(RHS.getNode())) {
Other = LHS;
}
Expand Down