diff --git a/llvm/test/CodeGen/PowerPC/aix-p9-insert-extract.ll b/llvm/test/CodeGen/PowerPC/aix-p9-insert-extract.ll
diff --git a/llvm/test/CodeGen/PowerPC/aix64-cc-byval.ll b/llvm/test/CodeGen/PowerPC/aix64-cc-byval.ll
@@ -24,7 +24,7 @@ entry:
 ; CHECK:          STD killed renamable $x3, 0, %fixed-stack.0 :: (store (s64) into %fixed-stack.0, align 16)
 ; CHECK-NEXT:     renamable $x3 = LBZ8 4, %fixed-stack.0 :: (dereferenceable load (s8)
 
-; CHECKASM-LABEL: .test_byval_5Byte:
+; ASM-LABEL: .test_byval_5Byte:
 
 ; ASM:       std 3, 48(1)
 ; ASM-NEXT:  lbz 3, 52(1)
@@ -49,7 +49,7 @@ entry:
 ; CHECK:          STD killed renamable $x3, 0, %fixed-stack.0 :: (store (s64) into %fixed-stack.0, align 16)
 ; CHECK-NEXT:     renamable $x3 = LBZ8 5, %fixed-stack.0 :: (dereferenceable load (s8)
 
-; CHECKASM-LABEL: .test_byval_6Byte:
+; ASM-LABEL: .test_byval_6Byte:
 
 ; ASM:       std 3, 48(1)
 ; ASM-NEXT:  lbz 3, 53(1)
@@ -74,7 +74,7 @@ entry:
 ; CHECK:          STD killed renamable $x3, 0, %fixed-stack.0 :: (store (s64) into %fixed-stack.0, align 16)
 ; CHECK-NEXT:     renamable $x3 = LBZ8 6, %fixed-stack.0 :: (dereferenceable load (s8)
 
-; CHECKASM-LABEL: .test_byval_7Byte:
+; ASM-LABEL: .test_byval_7Byte:
 
 ; ASM:       std 3, 48(1)
 ; ASM-NEXT:  lbz 3, 54(1)
@@ -101,7 +101,7 @@ entry:
 ; CHECK-DAG:      STD killed renamable $x[[SCRATCH]], 0, %fixed-stack.0 :: (store (s64) into %fixed-stack.0, align 16)
 
 
-; CHECKASM-LABEL: .test_byval_8Byte:
+; ASM-LABEL: .test_byval_8Byte:
 
 ; ASM:       mr [[SCRATCH:[0-9]+]], 3
 ; ASM-DAG:   clrldi  3, 3, 56
@@ -137,7 +137,7 @@ declare void @test_byval_64Byte(%struct.S64* byval(%struct.S64) align 1)
 ; CHECK-NEXT:  BL8_NOP <mcsymbol .test_byval_64Byte[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1
 ; CHECK-NEXT:  ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
-; CHECKASM-LABEL: .test_byval_64Byte:
+; ASM-LABEL: .call_test_byval_64Byte:
 
 ; ASM:         stdu 1, -112(1)
 ; ASM-NEXT:    ld [[REG:[0-9]+]], L..C{{[0-9]+}}(2)

diff --git a/llvm/test/CodeGen/PowerPC/atomics-indexed.ll b/llvm/test/CodeGen/PowerPC/atomics-indexed.ll
@@ -28,10 +28,6 @@ define i8 @load_x_i8_seq_cst([100000 x i8]* %mem) {
 ; PPC64-NEXT:    bne- cr7, .+4
 ; PPC64-NEXT:    isync
 ; PPC64-NEXT:    blr
-; CHECK-PPC32: lwsync
-; CHECK-PPC64: cmpw [[CR:cr[0-9]+]], [[VAL]], [[VAL]]
-; CHECK-PPC64: bne- [[CR]], .+4
-; CHECK-PPC64: isync
   %ptr = getelementptr inbounds [100000 x i8], [100000 x i8]* %mem, i64 0, i64 90000
   %val = load atomic i8, i8* %ptr seq_cst, align 1
   ret i8 %val
@@ -54,10 +50,6 @@ define i16 @load_x_i16_acquire([100000 x i16]* %mem) {
 ; PPC64-NEXT:    bne- cr7, .+4
 ; PPC64-NEXT:    isync
 ; PPC64-NEXT:    blr
-; CHECK-PPC32: lwsync
-; CHECK-PPC64: cmpw [[CR:cr[0-9]+]], [[VAL]], [[VAL]]
-; CHECK-PPC64: bne- [[CR]], .+4
-; CHECK-PPC64: isync
   %ptr = getelementptr inbounds [100000 x i16], [100000 x i16]* %mem, i64 0, i64 90000
   %val = load atomic i16, i16* %ptr acquire, align 2
   ret i16 %val

diff --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-stfiw.ll b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-stfiw.ll
@@ -28,10 +28,6 @@ define dso_local void @test_stfiw(i32* %cia, double %da) {
 ; CHECK-32BIT:       # %bb.0: # %entry
 ; CHECK-32BIT-NEXT:    stfiwx 1, 0, 3
 ; CHECK-32BIT-NEXT:    blr
-; CHECK-PWR9-LABEL: test_stfiw:
-; CHECK-PWR9:       # %bb.0: # %entry
-; CHECK-PWR9-NEXT:    stxsiwx 1, 0, 3
-; CHECK-PWR9-NEXT:    blr
 entry:
   %0 = bitcast i32* %cia to i8*
   tail call void @llvm.ppc.stfiw(i8* %0, double %da)
@@ -53,10 +49,6 @@ define dso_local void @test_xl_stfiw(i32* %cia, double %da) {
 ; CHECK-32BIT:       # %bb.0: # %entry
 ; CHECK-32BIT-NEXT:    stfiwx 1, 0, 3
 ; CHECK-32BIT-NEXT:    blr
-; CHECK-PWR9-LABEL: test_xl_stfiw:
-; CHECK-PWR9:       # %bb.0: # %entry
-; CHECK-PWR9-NEXT:    stxsiwx 1, 0, 3
-; CHECK-PWR9-NEXT:    blr
 entry:
   %0 = bitcast i32* %cia to i8*
   tail call void @llvm.ppc.stfiw(i8* %0, double %da)

diff --git a/llvm/test/CodeGen/PowerPC/complex-return.ll b/llvm/test/CodeGen/PowerPC/complex-return.ll
@@ -27,7 +27,7 @@ entry:
 ; CHECK-DAG: lfd 1
 ; CHECK-DAG: lfd 2
 ; CHECK-DAG: lfd 3
-; CHECK_DAG: lfd 4
+; CHECK-DAG: lfd 4
 
 define { float, float } @oof() nounwind {
 entry:

diff --git a/llvm/test/CodeGen/PowerPC/duplicate-returns-for-tailcall.ll b/llvm/test/CodeGen/PowerPC/duplicate-returns-for-tailcall.ll
@@ -43,7 +43,7 @@ if.then6:                                         ; preds = %if.end4
   %call7 = tail call fastcc signext i32 @call3(i32 signext %a, i32 signext %b, i32 signext %c)
   br label %return
 ; tail calling a fastcc function from a ccc function is supported.
-; CHECK_LABEL: if.then13:
+; CHECK-LABEL: if.then6:
 ; CHECK:       %[[T2:[a-zA-Z0-9]+]] = tail call fastcc signext i32 @call3
 ; CHECK-NEXT:  ret i32 %[[T2]]
 

diff --git a/llvm/test/CodeGen/PowerPC/fast-isel-conversion.ll b/llvm/test/CodeGen/PowerPC/fast-isel-conversion.ll
@@ -267,7 +267,6 @@ entry:
 ; CHECK-NEXT: li
 ; CHECK-NEXT: lfiwzx
 ; CHECK-NEXT: fcfidu
-; CHECKLE: fcfidu
 ; PPC970-NOT: lfiwzx
 ; PPC970-NOT: fcfidu
 ; SPE: efdcfui

diff --git a/llvm/test/CodeGen/PowerPC/float-to-int.ll b/llvm/test/CodeGen/PowerPC/float-to-int.ll
@@ -25,7 +25,7 @@ define i64 @foo(float %a) nounwind {
 ; CHECK-VSX: ld 3,
 ; CHECK-VSX: blr
 
-; CHECK-LABEL-P9: @foo
+; CHECK-P9-LABEL: @foo
 ; CHECK-P9: xscvdpsxds [[REG:[0-9]+]], 1
 ; CHECK-P9: stfd [[REG]],
 ; CHECK-P9: ld 3,
@@ -48,7 +48,7 @@ define i64 @foo2(double %a) nounwind {
 ; CHECK-VSX: ld 3,
 ; CHECK-VSX: blr
 
-; CHECK-LABEL-P9: @foo2
+; CHECK-P9-LABEL: @foo2
 ; CHECK-P9: xscvdpsxds [[REG:[0-9]+]], 1
 ; CHECK-P9: stfd [[REG]],
 ; CHECK-P9: ld 3,
@@ -71,7 +71,7 @@ define i64 @foo3(float %a) nounwind {
 ; CHECK-VSX: ld 3,
 ; CHECK-VSX: blr
 
-; CHECK-LABEL-P9: @foo3
+; CHECK-P9-LABEL: @foo3
 ; CHECK-P9: xscvdpuxds [[REG:[0-9]+]], 1
 ; CHECK-P9: stfd [[REG]],
 ; CHECK-P9: ld 3,
@@ -94,7 +94,7 @@ define i64 @foo4(double %a) nounwind {
 ; CHECK-VSX: ld 3,
 ; CHECK-VSX: blr
 
-; CHECK-LABEL-P9: @foo4
+; CHECK-P9-LABEL: @foo4
 ; CHECK-P9: xscvdpuxds [[REG:[0-9]+]], 1
 ; CHECK-P9: stfd [[REG]],
 ; CHECK-P9: ld 3,

diff --git a/llvm/test/CodeGen/PowerPC/fpscr-intrinsics.ll b/llvm/test/CodeGen/PowerPC/fpscr-intrinsics.ll
@@ -7,15 +7,6 @@
 ; RUN:   FileCheck %s --check-prefix=CHECK-AIX32
 
 define dso_local void @mtfsb0() local_unnamed_addr #0 {
-; CHECK-PWR8-LABEL: mtfsb0:
-; CHECK-PWR8:       # %bb.0: # %entry
-; CHECK-PWR8-NEXT:    mtfsb0 10
-; CHECK-PWR8-NEXT:    blr
-;
-; CHECK-PWR7-LABEL: mtfsb0:
-; CHECK-PWR7:       # %bb.0: # %entry
-; CHECK-PWR7-NEXT:    mtfsb0 10
-; CHECK-PWR7-NEXT:    blr
 ; CHECK-LABEL: mtfsb0:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mtfsb0 10
@@ -36,15 +27,6 @@ entry:
 }
 
 define dso_local void @mtfsb1() local_unnamed_addr #0 {
-; CHECK-PWR8-LABEL: mtfsb1:
-; CHECK-PWR8:       # %bb.0: # %entry
-; CHECK-PWR8-NEXT:    mtfsb1 0
-; CHECK-PWR8-NEXT:    blr
-;
-; CHECK-PWR7-LABEL: mtfsb1:
-; CHECK-PWR7:       # %bb.0: # %entry
-; CHECK-PWR7-NEXT:    mtfsb1 0
-; CHECK-PWR7-NEXT:    blr
 ; CHECK-LABEL: mtfsb1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mtfsb1 0

diff --git a/llvm/test/CodeGen/PowerPC/jaggedstructs.ll b/llvm/test/CodeGen/PowerPC/jaggedstructs.ll
@@ -36,7 +36,7 @@ entry:
 ; CHECK-DAG: lbz {{[0-9]+}}, 167(1)
 ; CHECK-DAG: lhz {{[0-9]+}}, 165(1)
 ; CHECK-DAG: stb {{[0-9]+}}, 55(1)
-; CHECK-DAG-DAG: sth {{[0-9]+}}, 53(1)
+; CHECK-DAG: sth {{[0-9]+}}, 53(1)
 ; CHECK-DAG: lbz {{[0-9]+}}, 175(1)
 ; CHECK-DAG: lwz {{[0-9]+}}, 171(1)
 ; CHECK-DAG: stb {{[0-9]+}}, 63(1)

diff --git a/llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll b/llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
@@ -2496,7 +2496,6 @@ entry:
   ret double %vecext
 
 
-; CHECK-AIXT: xxlor 1, 34, 34
 }
 
 ; Function Attrs: norecurse nounwind readnone
@@ -2520,8 +2519,6 @@ define double @getd1(<2 x double> %vd) {
 entry:
   %vecext = extractelement <2 x double> %vd, i32 1
   ret double %vecext
-
-
 }
 
 ; Function Attrs: norecurse nounwind readnone

diff --git a/llvm/test/CodeGen/PowerPC/ppc-passname.ll b/llvm/test/CodeGen/PowerPC/ppc-passname.ll
@@ -42,7 +42,7 @@
 
 ; RUN: llc -mtriple=powerpc64le-unknown-unknown < %s -debug-pass=Structure -stop-after=ppc-early-ret -o /dev/null 2>&1 | FileCheck %s -check-prefix=STOP-AFTER-EARLY-RET
 ; STOP-AFTER-EARLY-RET: -ppc-early-ret
-; STOP-AFTER-ERALY-RET-NOT: "ppc-early-ret" pass is not registered.
+; STOP-AFTER-EARLY-RET-NOT: "ppc-early-ret" pass is not registered.
 ; STOP-AFTER-EARLY-RET: PowerPC Early-Return Creation
 
 

diff --git a/llvm/test/CodeGen/PowerPC/ppc64-sibcall-shrinkwrap.ll b/llvm/test/CodeGen/PowerPC/ppc64-sibcall-shrinkwrap.ll
@@ -28,12 +28,6 @@ exit:
     i32 %bf.load)
   ret i8 %call.i
 
-; CHECK-SCO-SHRK-LABEL: _ZNK5clang9NamedDecl23getLinkageAndVisibilityEv:
-; CHECK-SCO-SHRK: b LVComputationKind
-; CHECK-SCO-SHRK: #TC_RETURNd8
-; CHECK-SCO-SHRK: stdu 1, -{{[0-9]+}}(1)
-; CHECK-SCO-SHRK: bl __assert_fail
-;
 ; CHECK-SCO-ONLY-LABEL: _ZNK5clang9NamedDecl23getLinkageAndVisibilityEv:
 ; CHECK-SCO-ONLY: stdu 1, -{{[0-9]+}}(1)
 ; CHECK-SCO-ONLY: b LVComputationKind

diff --git a/llvm/test/CodeGen/PowerPC/testComparesigeuc.ll b/llvm/test/CodeGen/PowerPC/testComparesigeuc.ll
@@ -76,7 +76,6 @@ entry:
   %conv3 = zext i1 %cmp to i8
   store i8 %conv3, i8* @glob
   ret void
-; CHECK_LABEL: test_igeuc_store:
 }
 
 ; Function Attrs: norecurse nounwind

diff --git a/llvm/test/CodeGen/PowerPC/testComparesigeui.ll b/llvm/test/CodeGen/PowerPC/testComparesigeui.ll
@@ -75,7 +75,6 @@ entry:
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @glob
   ret void
-; CHECK_LABEL: test_igeuc_store:
 }
 
 ; Function Attrs: norecurse nounwind

diff --git a/llvm/test/CodeGen/PowerPC/testComparesigeus.ll b/llvm/test/CodeGen/PowerPC/testComparesigeus.ll
@@ -75,7 +75,6 @@ entry:
   %conv3 = zext i1 %cmp to i16
   store i16 %conv3, i16* @glob
   ret void
-; CHECK_LABEL: test_igeus_store:
 }
 
 ; Function Attrs: norecurse nounwind

diff --git a/llvm/test/CodeGen/PowerPC/testComparesigtsll.ll b/llvm/test/CodeGen/PowerPC/testComparesigtsll.ll
@@ -83,7 +83,6 @@ define void @test_igtsll_store(i64 %a, i64 %b) {
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    std r3, 0(r4)
 ; CHECK-NEXT:    blr
-; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r3, r4
 entry:
   %cmp = icmp sgt i64 %a, %b
   %conv1 = zext i1 %cmp to i64
@@ -105,7 +104,6 @@ define void @test_igtsll_sext_store(i64 %a, i64 %b) {
 ; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    std r3, 0(r4)
 ; CHECK-NEXT:    blr
-; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r3, r4
 entry:
   %cmp = icmp sgt i64 %a, %b
   %conv1 = sext i1 %cmp to i64

diff --git a/llvm/test/CodeGen/PowerPC/testComparesiltsll.ll b/llvm/test/CodeGen/PowerPC/testComparesiltsll.ll
@@ -65,7 +65,6 @@ define dso_local void @test_iltsll_store(i64 %a, i64 %b) {
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    std r3, glob@toc@l(r5)
 ; CHECK-NEXT:    blr
-; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r4, r3
 entry:
   %cmp = icmp slt i64 %a, %b
   %conv1 = zext i1 %cmp to i64
@@ -86,7 +85,6 @@ define dso_local void @test_iltsll_sext_store(i64 %a, i64 %b) {
 ; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    std r3, glob@toc@l(r5)
 ; CHECK-NEXT:    blr
-; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r4, r3
 entry:
   %cmp = icmp slt i64 %a, %b
   %conv1 = sext i1 %cmp to i64

diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgeuc.ll b/llvm/test/CodeGen/PowerPC/testComparesllgeuc.ll
@@ -75,7 +75,6 @@ entry:
   %conv3 = zext i1 %cmp to i8
   store i8 %conv3, i8* @glob
   ret void
-; CHECK_LABEL: test_llgeuc_store:
 }
 
 ; Function Attrs: norecurse nounwind

diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgeui.ll b/llvm/test/CodeGen/PowerPC/testComparesllgeui.ll
@@ -75,7 +75,6 @@ entry:
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @glob
   ret void
-; CHECK_LABEL: test_igeuc_store:
 }
 
 ; Function Attrs: norecurse nounwind

diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgeus.ll b/llvm/test/CodeGen/PowerPC/testComparesllgeus.ll
@@ -75,7 +75,6 @@ entry:
   %conv3 = zext i1 %cmp to i16
   store i16 %conv3, i16* @glob
   ret void
-; CHECK_LABEL: test_llgeus_store:
 }
 
 ; Function Attrs: norecurse nounwind

diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgtsll.ll b/llvm/test/CodeGen/PowerPC/testComparesllgtsll.ll
@@ -83,7 +83,6 @@ define void @test_llgtsll_store(i64 %a, i64 %b) {
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    std r3, 0(r4)
 ; CHECK-NEXT:    blr
-; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r3, r4
 entry:
   %cmp = icmp sgt i64 %a, %b
   %conv1 = zext i1 %cmp to i64
@@ -105,7 +104,6 @@ define void @test_llgtsll_sext_store(i64 %a, i64 %b) {
 ; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    std r3, 0(r4)
 ; CHECK-NEXT:    blr
-; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r3, r4
 entry:
   %cmp = icmp sgt i64 %a, %b
   %conv1 = sext i1 %cmp to i64

diff --git a/llvm/test/CodeGen/PowerPC/testComparesllltsll.ll b/llvm/test/CodeGen/PowerPC/testComparesllltsll.ll
@@ -65,7 +65,6 @@ define dso_local void @test_llltsll_store(i64 %a, i64 %b) {
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    std r3, glob@toc@l(r5)
 ; CHECK-NEXT:    blr
-; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r4, r3
 entry:
   %cmp = icmp slt i64 %a, %b
   %conv1 = zext i1 %cmp to i64
@@ -86,7 +85,6 @@ define dso_local void @test_llltsll_sext_store(i64 %a, i64 %b) {
 ; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    std r3, glob@toc@l(r5)
 ; CHECK-NEXT:    blr
-; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r4, r3
 entry:
   %cmp = icmp slt i64 %a, %b
   %conv1 = sext i1 %cmp to i64

diff --git a/llvm/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll b/llvm/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll
@@ -35,7 +35,7 @@ entry:
 ; CHECK-BE-DAG: sldi [[SHAMREG:[0-9]+]], [[ANDCREG]], 5
 ; CHECK-BE: mfvsrd [[TOGPR:[0-9]+]],
 ; CHECK-BE: srd [[RSHREG:[0-9]+]], [[TOGPR]], [[SHAMREG]]
-; CHECk-BE: extsw 3, [[RSHREG]]
+; CHECK-BE: extsw 3, [[RSHREG]]
 }
 
 ; Function Attrs: norecurse nounwind readnone

diff --git a/llvm/test/CodeGen/PowerPC/vec_xxpermdi.ll b/llvm/test/CodeGen/PowerPC/vec_xxpermdi.ll
@@ -159,7 +159,7 @@ define <2 x double> @test_le_vec_xxpermdi_v2f64_undef_2(<2 x double> %VA) {
       %0 = shufflevector <2 x double> %VA, <2 x double> undef, <2 x i32> <i32 1, i32 0>
       ret <2 x double> %0
 ; CHECK-LE-LABEL: @test_le_vec_xxpermdi_v2f64_undef_2
-; CHCECK-LE: xxswapd 34, 34
+; CHECK-LE: xxswapd 34, 34
 }
 
 define <2 x double> @test_le_vec_xxpermdi_v2f64_undef_3(<2 x double> %VA) {
@@ -266,7 +266,7 @@ define <2 x double> @test_be_vec_xxpermdi_v2f64_undef_2(<2 x double> %VA) {
       %0 = shufflevector <2 x double> %VA, <2 x double> undef, <2 x i32> <i32 1, i32 0>
       ret <2 x double> %0
 ; CHECK-BE-LABEL: @test_be_vec_xxpermdi_v2f64_undef_2
-; CHCECK-LE: xxswapd 34, 34
+; CHECK-LE: xxswapd 34, 34
 }
 
 define <2 x double> @test_be_vec_xxpermdi_v2f64_undef_3(<2 x double> %VA) {

diff --git a/llvm/test/CodeGen/PowerPC/vrsave-inline-asm.ll b/llvm/test/CodeGen/PowerPC/vrsave-inline-asm.ll
@@ -29,7 +29,7 @@ entry:
   ret i32 %0
 }
 
-; CHECK-LABEl: moveToVRSave:
+; CHECK-LABEL: moveToVRSave:
 ; CHECK:         mtvrsave 3
 
 ; CHECK-LABEL: moveFromVRSave: