4 changes: 2 additions & 2 deletions clang/utils/TableGen/SveEmitter.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1163,7 +1163,7 @@ void SVEEmitter::createIntrinsic(
uint64_t MemEltType = R->getValueAsInt("MemEltType");

int64_t Flags = 0;
for (const Record *FlagRec : R->getValueAsListOfConstDefs("Flags"))
for (const Record *FlagRec : R->getValueAsListOfDefs("Flags"))
Flags |= FlagRec->getValueAsInt("Value");

// Create a dummy TypeSpec for non-overloaded builtins.
Expand Down Expand Up @@ -1193,7 +1193,7 @@ void SVEEmitter::createIntrinsic(
for (auto TS : TypeSpecs) {
// Collate a list of range/option checks for the immediates.
SmallVector<ImmCheck, 2> ImmChecks;
for (const Record *ImmR : R->getValueAsListOfConstDefs("ImmChecks")) {
for (const Record *ImmR : R->getValueAsListOfDefs("ImmChecks")) {
int64_t ArgIdx = ImmR->getValueAsInt("ImmArgIdx");
int64_t EltSizeArgIdx = ImmR->getValueAsInt("TypeContextArgIdx");
int64_t Kind = ImmR->getValueAsDef("Kind")->getValueAsInt("Value");
Expand Down
4 changes: 2 additions & 2 deletions libc/utils/HdrGen/PublicAPICommand.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -109,7 +109,7 @@ static AttributeMap collectAttributeMacros(const SpecMap &Spec,
static void emitAttributeMacroDecls(const AttributeMap &MacroAttr,
llvm::raw_ostream &OS) {
for (auto &[Macro, Attr] : MacroAttr) {
std::vector<llvm::Record *> Instances =
std::vector<const llvm::Record *> Instances =
Attr->getValueAsListOfDefs("Instances");
llvm::SmallVector<std::pair<AttributeStyle, const llvm::Record *>> Styles;
std::transform(Instances.begin(), Instances.end(),
Expand Down Expand Up @@ -190,7 +190,7 @@ static void emitAttributeMacroDecls(const AttributeMap &MacroAttr,

static void emitAttributeMacroForFunction(const llvm::Record *FunctionSpec,
llvm::raw_ostream &OS) {
std::vector<llvm::Record *> Attributes =
std::vector<const llvm::Record *> Attributes =
FunctionSpec->getValueAsListOfDefs("Attributes");
llvm::interleave(
Attributes.begin(), Attributes.end(),
Expand Down
14 changes: 7 additions & 7 deletions libc/utils/LibcTableGenUtil/APIIndexer.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -81,36 +81,36 @@ std::string APIIndexer::getTypeAsString(const llvm::Record *TypeRecord) {

void APIIndexer::indexStandardSpecDef(const llvm::Record *StandardSpec) {
auto HeaderSpecList = StandardSpec->getValueAsListOfDefs("Headers");
for (llvm::Record *HeaderSpec : HeaderSpecList) {
for (const llvm::Record *HeaderSpec : HeaderSpecList) {
llvm::StringRef Header = HeaderSpec->getValueAsString("Name");
if (!StdHeader.has_value() || Header == StdHeader) {
PublicHeaders.emplace(Header);
auto MacroSpecList = HeaderSpec->getValueAsListOfDefs("Macros");
// TODO: Trigger a fatal error on duplicate specs.
for (llvm::Record *MacroSpec : MacroSpecList)
for (const llvm::Record *MacroSpec : MacroSpecList)
MacroSpecMap[std::string(MacroSpec->getValueAsString("Name"))] =
MacroSpec;

auto TypeSpecList = HeaderSpec->getValueAsListOfDefs("Types");
for (llvm::Record *TypeSpec : TypeSpecList)
for (const llvm::Record *TypeSpec : TypeSpecList)
TypeSpecMap[std::string(TypeSpec->getValueAsString("Name"))] = TypeSpec;

auto FunctionSpecList = HeaderSpec->getValueAsListOfDefs("Functions");
for (llvm::Record *FunctionSpec : FunctionSpecList) {
for (const llvm::Record *FunctionSpec : FunctionSpecList) {
auto FunctionName = std::string(FunctionSpec->getValueAsString("Name"));
FunctionSpecMap[FunctionName] = FunctionSpec;
FunctionToHeaderMap[FunctionName] = std::string(Header);
}

auto EnumerationSpecList =
HeaderSpec->getValueAsListOfDefs("Enumerations");
for (llvm::Record *EnumerationSpec : EnumerationSpecList) {
for (const llvm::Record *EnumerationSpec : EnumerationSpecList) {
EnumerationSpecMap[std::string(
EnumerationSpec->getValueAsString("Name"))] = EnumerationSpec;
}

auto ObjectSpecList = HeaderSpec->getValueAsListOfDefs("Objects");
for (llvm::Record *ObjectSpec : ObjectSpecList) {
for (const llvm::Record *ObjectSpec : ObjectSpecList) {
auto ObjectName = std::string(ObjectSpec->getValueAsString("Name"));
ObjectSpecMap[ObjectName] = ObjectSpec;
ObjectToHeaderMap[ObjectName] = std::string(Header);
Expand All @@ -124,7 +124,7 @@ void APIIndexer::indexPublicAPIDef(const llvm::Record *PublicAPI) {
// requested is from an included standard. Such a check is done while
// generating the API.
auto MacroDefList = PublicAPI->getValueAsListOfDefs("Macros");
for (llvm::Record *MacroDef : MacroDefList)
for (const llvm::Record *MacroDef : MacroDefList)
MacroDefsMap[std::string(MacroDef->getValueAsString("Name"))] = MacroDef;

auto TypeList = PublicAPI->getValueAsListOfStrings("Types");
Expand Down
12 changes: 6 additions & 6 deletions llvm/include/llvm/TableGen/DirectiveEmitter.h
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Original file line number Diff line number Diff line change
Expand Up @@ -136,23 +136,23 @@ class Directive : public BaseRecord {
Directive(const Record *Def) : BaseRecord(Def) {}

std::vector<const Record *> getAllowedClauses() const {
return Def->getValueAsListOfConstDefs("allowedClauses");
return Def->getValueAsListOfDefs("allowedClauses");
}

std::vector<const Record *> getAllowedOnceClauses() const {
return Def->getValueAsListOfConstDefs("allowedOnceClauses");
return Def->getValueAsListOfDefs("allowedOnceClauses");
}

std::vector<const Record *> getAllowedExclusiveClauses() const {
return Def->getValueAsListOfConstDefs("allowedExclusiveClauses");
return Def->getValueAsListOfDefs("allowedExclusiveClauses");
}

std::vector<const Record *> getRequiredClauses() const {
return Def->getValueAsListOfConstDefs("requiredClauses");
return Def->getValueAsListOfDefs("requiredClauses");
}

std::vector<const Record *> getLeafConstructs() const {
return Def->getValueAsListOfConstDefs("leafConstructs");
return Def->getValueAsListOfDefs("leafConstructs");
}

Record *getAssociation() const { return Def->getValueAsDef("association"); }
Expand Down Expand Up @@ -204,7 +204,7 @@ class Clause : public BaseRecord {
}

std::vector<const Record *> getClauseVals() const {
return Def->getValueAsListOfConstDefs("allowedClauseValues");
return Def->getValueAsListOfDefs("allowedClauseValues");
}

bool isValueOptional() const { return Def->getValueAsBit("isValueOptional"); }
Expand Down
5 changes: 1 addition & 4 deletions llvm/include/llvm/TableGen/Record.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1916,10 +1916,7 @@ class Record {
/// This method looks up the specified field and returns its value as a
/// vector of records, throwing an exception if the field does not exist or
/// if the value is not the right type.
std::vector<Record*> getValueAsListOfDefs(StringRef FieldName) const;
// Temporary function to help staged migration to const Record pointers.
std::vector<const Record *>
getValueAsListOfConstDefs(StringRef FieldName) const;
std::vector<const Record *> getValueAsListOfDefs(StringRef FieldName) const;

/// This method looks up the specified field and returns its value as a
/// vector of integers, throwing an exception if the field does not exist or
Expand Down
16 changes: 1 addition & 15 deletions llvm/lib/TableGen/Record.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3047,22 +3047,8 @@ ListInit *Record::getValueAsListInit(StringRef FieldName) const {
"' exists but does not have a list value");
}

std::vector<Record*>
Record::getValueAsListOfDefs(StringRef FieldName) const {
ListInit *List = getValueAsListInit(FieldName);
std::vector<Record*> Defs;
for (Init *I : List->getValues()) {
if (DefInit *DI = dyn_cast<DefInit>(I))
Defs.push_back(DI->getDef());
else
PrintFatalError(getLoc(), "Record `" + getName() + "', field `" +
FieldName + "' list is not entirely DefInit!");
}
return Defs;
}

std::vector<const Record *>
Record::getValueAsListOfConstDefs(StringRef FieldName) const {
Record::getValueAsListOfDefs(StringRef FieldName) const {
ListInit *List = getValueAsListInit(FieldName);
std::vector<const Record *> Defs;
for (const Init *I : List->getValues()) {
Expand Down
4 changes: 2 additions & 2 deletions llvm/utils/TableGen/AsmWriterEmitter.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -597,7 +597,7 @@ emitRegisterNameString(raw_ostream &O, StringRef AltName,
} else {
// Make sure the register has an alternate name for this index.
std::vector<const Record *> AltNameList =
Reg.TheDef->getValueAsListOfConstDefs("RegAltNameIndices");
Reg.TheDef->getValueAsListOfDefs("RegAltNameIndices");
unsigned Idx = 0, e;
for (e = AltNameList.size();
Idx < e && (AltNameList[Idx]->getName() != AltName); ++Idx)
Expand Down Expand Up @@ -1012,7 +1012,7 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
if (PassSubtarget) {
// We only consider ReqFeatures predicates if PassSubtarget
std::vector<const Record *> RF =
CGA.TheDef->getValueAsListOfConstDefs("Predicates");
CGA.TheDef->getValueAsListOfDefs("Predicates");
copy_if(RF, std::back_inserter(ReqFeatures), [](const Record *R) {
return R->getValueAsBit("AssemblerMatcherPredicate");
});
Expand Down
4 changes: 2 additions & 2 deletions llvm/utils/TableGen/Common/CodeGenHwModes.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -39,8 +39,8 @@ LLVM_DUMP_METHOD
void HwMode::dump() const { dbgs() << Name << ": " << Features << '\n'; }

HwModeSelect::HwModeSelect(const Record *R, CodeGenHwModes &CGH) {
std::vector<const Record *> Modes = R->getValueAsListOfConstDefs("Modes");
std::vector<const Record *> Objects = R->getValueAsListOfConstDefs("Objects");
std::vector<const Record *> Modes = R->getValueAsListOfDefs("Modes");
std::vector<const Record *> Objects = R->getValueAsListOfDefs("Objects");
if (Modes.size() != Objects.size()) {
PrintError(
R->getLoc(),
Expand Down
4 changes: 2 additions & 2 deletions llvm/utils/TableGen/Common/CodeGenInstruction.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -485,8 +485,8 @@ CodeGenInstruction::CodeGenInstruction(const Record *R)
isCodeGenOnly = R->getValueAsBit("isCodeGenOnly");
isPseudo = R->getValueAsBit("isPseudo");
isMeta = R->getValueAsBit("isMeta");
ImplicitDefs = R->getValueAsListOfConstDefs("Defs");
ImplicitUses = R->getValueAsListOfConstDefs("Uses");
ImplicitDefs = R->getValueAsListOfDefs("Defs");
ImplicitUses = R->getValueAsListOfDefs("Uses");

// This flag is only inferred from the pattern.
hasChain = false;
Expand Down
14 changes: 6 additions & 8 deletions llvm/utils/TableGen/Common/CodeGenRegisters.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -80,7 +80,7 @@ void CodeGenSubRegIndex::updateComponents(CodeGenRegBank &RegBank) {
return;

std::vector<const Record *> Comps =
TheDef->getValueAsListOfConstDefs("ComposedOf");
TheDef->getValueAsListOfDefs("ComposedOf");
if (!Comps.empty()) {
if (Comps.size() != 2)
PrintFatalError(TheDef->getLoc(),
Expand All @@ -93,7 +93,7 @@ void CodeGenSubRegIndex::updateComponents(CodeGenRegBank &RegBank) {
}

std::vector<const Record *> Parts =
TheDef->getValueAsListOfConstDefs("CoveringSubRegIndices");
TheDef->getValueAsListOfDefs("CoveringSubRegIndices");
if (!Parts.empty()) {
if (Parts.size() < 2)
PrintFatalError(TheDef->getLoc(),
Expand Down Expand Up @@ -169,9 +169,8 @@ CodeGenRegister::CodeGenRegister(const Record *R, unsigned Enum)

void CodeGenRegister::buildObjectGraph(CodeGenRegBank &RegBank) {
std::vector<const Record *> SRIs =
TheDef->getValueAsListOfConstDefs("SubRegIndices");
std::vector<const Record *> SRs =
TheDef->getValueAsListOfConstDefs("SubRegs");
TheDef->getValueAsListOfDefs("SubRegIndices");
std::vector<const Record *> SRs = TheDef->getValueAsListOfDefs("SubRegs");

if (SRIs.size() != SRs.size())
PrintFatalError(TheDef->getLoc(),
Expand Down Expand Up @@ -629,7 +628,7 @@ struct TupleExpander : SetTheory::Expander {
void expand(SetTheory &ST, const Record *Def,
SetTheory::RecSet &Elts) override {
std::vector<const Record *> Indices =
Def->getValueAsListOfConstDefs("SubRegIndices");
Def->getValueAsListOfDefs("SubRegIndices");
unsigned Dim = Indices.size();
ListInit *SubRegs = Def->getValueAsListInit("SubRegs");
if (Dim != SubRegs->size())
Expand Down Expand Up @@ -764,8 +763,7 @@ CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank,
: TheDef(R), Name(std::string(R->getName())),
TopoSigs(RegBank.getNumTopoSigs()), EnumValue(-1), TSFlags(0) {
GeneratePressureSet = R->getValueAsBit("GeneratePressureSet");
std::vector<const Record *> TypeList =
R->getValueAsListOfConstDefs("RegTypes");
std::vector<const Record *> TypeList = R->getValueAsListOfDefs("RegTypes");
if (TypeList.empty())
PrintFatalError(R->getLoc(), "RegTypes list must not be empty!");
for (unsigned i = 0, e = TypeList.size(); i != e; ++i) {
Expand Down
50 changes: 21 additions & 29 deletions llvm/utils/TableGen/Common/CodeGenSchedule.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -310,13 +310,13 @@ static void processSTIPredicate(STIPredicateFunction &Fn,
// definitions. Each unique opcode will be associated with an OpcodeInfo
// object.
for (const Record *Def : Fn.getDefinitions()) {
ConstRecVec Classes = Def->getValueAsListOfConstDefs("Classes");
ConstRecVec Classes = Def->getValueAsListOfDefs("Classes");
for (const Record *EC : Classes) {
const Record *Pred = EC->getValueAsDef("Predicate");
if (!Predicate2Index.contains(Pred))
Predicate2Index[Pred] = NumUniquePredicates++;

ConstRecVec Opcodes = EC->getValueAsListOfConstDefs("Opcodes");
ConstRecVec Opcodes = EC->getValueAsListOfDefs("Opcodes");
for (const Record *Opcode : Opcodes) {
if (!Opcode2Index.contains(Opcode)) {
Opcode2Index[Opcode] = OpcodeMappings.size();
Expand All @@ -341,14 +341,14 @@ static void processSTIPredicate(STIPredicateFunction &Fn,
// Construct a OpcodeInfo object for every unique opcode declared by an
// InstructionEquivalenceClass definition.
for (const Record *Def : Fn.getDefinitions()) {
ConstRecVec Classes = Def->getValueAsListOfConstDefs("Classes");
ConstRecVec Classes = Def->getValueAsListOfDefs("Classes");
const Record *SchedModel = Def->getValueAsDef("SchedModel");
unsigned ProcIndex = ProcModelMap.find(SchedModel)->second;
APInt ProcMask(ProcModelMap.size(), 0);
ProcMask.setBit(ProcIndex);

for (const Record *EC : Classes) {
ConstRecVec Opcodes = EC->getValueAsListOfConstDefs("Opcodes");
ConstRecVec Opcodes = EC->getValueAsListOfDefs("Opcodes");

std::vector<int64_t> OpIndices =
EC->getValueAsListOfInts("OperandIndices");
Expand Down Expand Up @@ -669,7 +669,7 @@ void CodeGenSchedModels::collectSchedRW() {
for (CodeGenSchedRW &CGRW : SchedWrites) {
if (!CGRW.IsSequence)
continue;
findRWs(CGRW.TheDef->getValueAsListOfConstDefs("Writes"), CGRW.Sequence,
findRWs(CGRW.TheDef->getValueAsListOfDefs("Writes"), CGRW.Sequence,
/*IsRead=*/false);
}
// Initialize Aliases vectors.
Expand Down Expand Up @@ -857,8 +857,7 @@ void CodeGenSchedModels::collectSchedClasses() {
Record *ItinDef = Inst->TheDef->getValueAsDef("Itinerary");
IdxVec Writes, Reads;
if (!Inst->TheDef->isValueUnset("SchedRW"))
findRWs(Inst->TheDef->getValueAsListOfConstDefs("SchedRW"), Writes,
Reads);
findRWs(Inst->TheDef->getValueAsListOfDefs("SchedRW"), Writes, Reads);

// ProcIdx == 0 indicates the class applies to all processors.
unsigned SCIdx = addSchedClass(ItinDef, Writes, Reads, /*ProcIndices*/ {0});
Expand Down Expand Up @@ -920,8 +919,7 @@ void CodeGenSchedModels::collectSchedClasses() {
<< InstName);
IdxVec Writes;
IdxVec Reads;
findRWs(RWDef->getValueAsListOfConstDefs("OperandReadWrites"), Writes,
Reads);
findRWs(RWDef->getValueAsListOfDefs("OperandReadWrites"), Writes, Reads);
LLVM_DEBUG({
for (unsigned WIdx : Writes)
dbgs() << " " << SchedWrites[WIdx].Name;
Expand Down Expand Up @@ -1130,8 +1128,7 @@ void CodeGenSchedModels::collectProcItins() {
if (!ProcModel.hasItineraries())
continue;

ConstRecVec ItinRecords =
ProcModel.ItinsDef->getValueAsListOfConstDefs("IID");
ConstRecVec ItinRecords = ProcModel.ItinsDef->getValueAsListOfDefs("IID");
assert(!ItinRecords.empty() && "ProcModel.hasItineraries is incorrect");

// Populate ItinDefList with Itinerary records.
Expand Down Expand Up @@ -1224,8 +1221,7 @@ void CodeGenSchedModels::inferFromItinClass(const Record *ItinClassDef,
// For all ItinRW entries.
bool HasMatch = false;
for (const Record *Rec : PM.ItinRWDefs) {
ConstRecVec Matched =
Rec->getValueAsListOfConstDefs("MatchedItinClasses");
ConstRecVec Matched = Rec->getValueAsListOfDefs("MatchedItinClasses");
if (!llvm::is_contained(Matched, ItinClassDef))
continue;
if (HasMatch)
Expand All @@ -1234,8 +1230,7 @@ void CodeGenSchedModels::inferFromItinClass(const Record *ItinClassDef,
" in ItinResources for " + PM.ModelName);
HasMatch = true;
IdxVec Writes, Reads;
findRWs(Rec->getValueAsListOfConstDefs("OperandReadWrites"), Writes,
Reads);
findRWs(Rec->getValueAsListOfDefs("OperandReadWrites"), Writes, Reads);
inferFromRW(Writes, Reads, FromClassIdx, PIdx);
}
}
Expand All @@ -1257,7 +1252,7 @@ void CodeGenSchedModels::inferFromInstRWs(unsigned SCIdx) {
if (II == IE)
continue;
IdxVec Writes, Reads;
findRWs(Rec->getValueAsListOfConstDefs("OperandReadWrites"), Writes, Reads);
findRWs(Rec->getValueAsListOfDefs("OperandReadWrites"), Writes, Reads);
unsigned PIdx = getProcModel(Rec->getValueAsDef("SchedModel")).Index;
inferFromRW(Writes, Reads, SCIdx, PIdx); // May mutate SchedClasses.
SchedClasses[SCIdx].InstRWProcIndices.insert(PIdx);
Expand Down Expand Up @@ -1350,8 +1345,7 @@ bool PredTransitions::mutuallyExclusive(Record *PredDef,

const CodeGenSchedRW &SchedRW = SchedModels.getSchedRW(PC.RWIdx, PC.IsRead);
assert(SchedRW.HasVariants && "PredCheck must refer to a SchedVariant");
ConstRecVec Variants =
SchedRW.TheDef->getValueAsListOfConstDefs("Variants");
ConstRecVec Variants = SchedRW.TheDef->getValueAsListOfDefs("Variants");
if (any_of(Variants, [PredDef](const Record *R) {
return R->getValueAsDef("Predicate") == PredDef;
})) {
Expand Down Expand Up @@ -1498,7 +1492,7 @@ void PredTransitions::pushVariant(const TransVariant &VInfo, bool IsRead) {
Record *PredDef = VInfo.VarOrSeqDef->getValueAsDef("Predicate");
Trans.PredTerm.emplace_back(IsRead, VInfo.RWIdx, PredDef);
ConstRecVec SelectedDefs =
VInfo.VarOrSeqDef->getValueAsListOfConstDefs("Selected");
VInfo.VarOrSeqDef->getValueAsListOfDefs("Selected");
SchedModels.findRWs(SelectedDefs, SelectedRWs, IsRead);
} else {
assert(VInfo.VarOrSeqDef->isSubClassOf("WriteSequence") &&
Expand Down Expand Up @@ -1769,8 +1763,7 @@ bool CodeGenSchedModels::hasSuperGroup(ConstRecVec &SubUnits,
for (const Record *ProcResourceDef : PM.ProcResourceDefs) {
if (!ProcResourceDef->isSubClassOf("ProcResGroup"))
continue;
ConstRecVec SuperUnits =
ProcResourceDef->getValueAsListOfConstDefs("Resources");
ConstRecVec SuperUnits = ProcResourceDef->getValueAsListOfDefs("Resources");
auto RI = SubUnits.begin(), RE = SubUnits.end();
for (; RI != RE; ++RI) {
if (!is_contained(SuperUnits, *RI)) {
Expand All @@ -1789,12 +1782,12 @@ void CodeGenSchedModels::verifyProcResourceGroups(CodeGenProcModel &PM) {
if (!PM.ProcResourceDefs[i]->isSubClassOf("ProcResGroup"))
continue;
ConstRecVec CheckUnits =
PM.ProcResourceDefs[i]->getValueAsListOfConstDefs("Resources");
PM.ProcResourceDefs[i]->getValueAsListOfDefs("Resources");
for (unsigned j = i + 1; j < e; ++j) {
if (!PM.ProcResourceDefs[j]->isSubClassOf("ProcResGroup"))
continue;
ConstRecVec OtherUnits =
PM.ProcResourceDefs[j]->getValueAsListOfConstDefs("Resources");
PM.ProcResourceDefs[j]->getValueAsListOfDefs("Resources");
if (std::find_first_of(CheckUnits.begin(), CheckUnits.end(),
OtherUnits.begin(),
OtherUnits.end()) != CheckUnits.end()) {
Expand Down Expand Up @@ -1833,7 +1826,7 @@ void CodeGenSchedModels::collectRegisterFiles() {
"Invalid RegisterFile with zero physical registers");
}

ConstRecVec RegisterClasses = RF->getValueAsListOfConstDefs("RegClasses");
ConstRecVec RegisterClasses = RF->getValueAsListOfDefs("RegClasses");
std::vector<int64_t> RegisterCosts = RF->getValueAsListOfInts("RegCosts");
ListInit *MoveElimInfo = RF->getValueAsListInit("AllowMoveElimination");
for (unsigned I = 0, E = RegisterClasses.size(); I < E; ++I) {
Expand Down Expand Up @@ -1871,8 +1864,7 @@ void CodeGenSchedModels::collectProcResources() {
Record *RWModelDef = RW->getValueAsDef("SchedModel");
unsigned PIdx = getProcModel(RWModelDef).Index;
IdxVec Writes, Reads;
findRWs(RW->getValueAsListOfConstDefs("OperandReadWrites"), Writes,
Reads);
findRWs(RW->getValueAsListOfDefs("OperandReadWrites"), Writes, Reads);
collectRWResources(Writes, Reads, PIdx);
}

Expand Down Expand Up @@ -2016,7 +2008,7 @@ void CodeGenSchedModels::collectItinProcResources(const Record *ItinClassDef) {
// For all ItinRW entries.
bool HasMatch = false;
for (const Record *R : PM.ItinRWDefs) {
ConstRecVec Matched = R->getValueAsListOfConstDefs("MatchedItinClasses");
ConstRecVec Matched = R->getValueAsListOfDefs("MatchedItinClasses");
if (!llvm::is_contained(Matched, ItinClassDef))
continue;
if (HasMatch)
Expand All @@ -2025,7 +2017,7 @@ void CodeGenSchedModels::collectItinProcResources(const Record *ItinClassDef) {
" in ItinResources for " + PM.ModelName);
HasMatch = true;
IdxVec Writes, Reads;
findRWs(R->getValueAsListOfConstDefs("OperandReadWrites"), Writes, Reads);
findRWs(R->getValueAsListOfDefs("OperandReadWrites"), Writes, Reads);
collectRWResources(Writes, Reads, PIdx);
}
}
Expand Down Expand Up @@ -2192,7 +2184,7 @@ bool CodeGenProcModel::isUnsupported(const CodeGenInstruction &Inst) const {

bool CodeGenProcModel::hasReadOfWrite(const Record *WriteDef) const {
for (auto &RADef : ReadAdvanceDefs) {
ConstRecVec ValidWrites = RADef->getValueAsListOfConstDefs("ValidWrites");
ConstRecVec ValidWrites = RADef->getValueAsListOfDefs("ValidWrites");
if (is_contained(ValidWrites, WriteDef))
return true;
}
Expand Down
8 changes: 4 additions & 4 deletions llvm/utils/TableGen/Common/CodeGenTarget.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -133,7 +133,7 @@ bool CodeGenTarget::getAllowRegisterRenaming() const {
///
const Record *CodeGenTarget::getAsmParser() const {
std::vector<const Record *> LI =
TargetRec->getValueAsListOfConstDefs("AssemblyParsers");
TargetRec->getValueAsListOfDefs("AssemblyParsers");
if (AsmParserNum >= LI.size())
PrintFatalError("Target does not have an AsmParser #" +
Twine(AsmParserNum) + "!");
Expand All @@ -145,7 +145,7 @@ const Record *CodeGenTarget::getAsmParser() const {
///
const Record *CodeGenTarget::getAsmParserVariant(unsigned Idx) const {
std::vector<const Record *> LI =
TargetRec->getValueAsListOfConstDefs("AssemblyParserVariants");
TargetRec->getValueAsListOfDefs("AssemblyParserVariants");
if (Idx >= LI.size())
PrintFatalError("Target does not have an AsmParserVariant #" + Twine(Idx) +
"!");
Expand All @@ -163,7 +163,7 @@ unsigned CodeGenTarget::getAsmParserVariantCount() const {
///
const Record *CodeGenTarget::getAsmWriter() const {
std::vector<const Record *> LI =
TargetRec->getValueAsListOfConstDefs("AssemblyWriters");
TargetRec->getValueAsListOfDefs("AssemblyWriters");
if (AsmWriterNum >= LI.size())
PrintFatalError("Target does not have an AsmWriter #" +
Twine(AsmWriterNum) + "!");
Expand Down Expand Up @@ -407,7 +407,7 @@ ComplexPattern::ComplexPattern(const Record *R) {
Ty = R->getValueAsDef("Ty");
NumOperands = R->getValueAsInt("NumOperands");
SelectFunc = std::string(R->getValueAsString("SelectFunc"));
RootNodes = R->getValueAsListOfConstDefs("RootNodes");
RootNodes = R->getValueAsListOfDefs("RootNodes");

// FIXME: This is a hack to statically increase the priority of patterns which
// maps a sub-dag to a complex pattern. e.g. favors LEA over ADD. To get best
Expand Down
2 changes: 1 addition & 1 deletion llvm/utils/TableGen/Common/PredicateExpander.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -297,7 +297,7 @@ void PredicateExpander::expandOpcodeSwitchStatement(
void PredicateExpander::expandStatement(raw_ostream &OS, const Record *Rec) {
// Assume that padding has been added by the caller.
if (Rec->isSubClassOf("MCOpcodeSwitchStatement")) {
expandOpcodeSwitchStatement(OS, Rec->getValueAsListOfConstDefs("Cases"),
expandOpcodeSwitchStatement(OS, Rec->getValueAsListOfDefs("Cases"),
Rec->getValueAsDef("DefaultCase"));
return;
}
Expand Down
4 changes: 2 additions & 2 deletions llvm/utils/TableGen/CompressInstEmitter.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -479,7 +479,7 @@ void CompressInstEmitter::evaluateCompressPat(const Record *Rec) {

// Get the target features for the CompressPat.
std::vector<const Record *> PatReqFeatures;
std::vector<const Record *> RF = Rec->getValueAsListOfConstDefs("Predicates");
std::vector<const Record *> RF = Rec->getValueAsListOfDefs("Predicates");
copy_if(RF, std::back_inserter(PatReqFeatures), [](const Record *R) {
return R->getValueAsBit("AssemblerMatcherPredicate");
});
Expand Down Expand Up @@ -688,7 +688,7 @@ void CompressInstEmitter::emitCompressInstEmitter(raw_ostream &OS,
// Add Dest instruction required features.
std::vector<const Record *> ReqFeatures;
std::vector<const Record *> RF =
Dest.TheDef->getValueAsListOfConstDefs("Predicates");
Dest.TheDef->getValueAsListOfDefs("Predicates");
copy_if(RF, std::back_inserter(ReqFeatures), [](const Record *R) {
return R->getValueAsBit("AssemblerMatcherPredicate");
});
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6 changes: 3 additions & 3 deletions llvm/utils/TableGen/DFAPacketizerEmitter.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -108,7 +108,7 @@ int DFAPacketizerEmitter::collectAllFuncUnits(
int totalFUs = 0;
// Parse functional units for all the itineraries.
for (const Record *Proc : ProcItinList) {
std::vector<const Record *> FUs = Proc->getValueAsListOfConstDefs("FU");
std::vector<const Record *> FUs = Proc->getValueAsListOfDefs("FU");

LLVM_DEBUG(dbgs() << " FU:"
<< " (" << FUs.size() << " FUs) " << Proc->getName());
Expand Down Expand Up @@ -139,7 +139,7 @@ int DFAPacketizerEmitter::collectAllComboFuncs(
int numCombos = 0;
for (unsigned i = 0, N = ComboFuncList.size(); i < N; ++i) {
const Record *Func = ComboFuncList[i];
std::vector<const Record *> FUs = Func->getValueAsListOfConstDefs("CFD");
std::vector<const Record *> FUs = Func->getValueAsListOfDefs("CFD");

LLVM_DEBUG(dbgs() << " CFD:" << i << " (" << FUs.size() << " combo FUs) "
<< Func->getName() << "\n");
Expand All @@ -151,7 +151,7 @@ int DFAPacketizerEmitter::collectAllComboFuncs(
const Record *FuncData = FUs[j];
const Record *ComboFunc = FuncData->getValueAsDef("TheComboFunc");
const std::vector<const Record *> FuncList =
FuncData->getValueAsListOfConstDefs("FuncList");
FuncData->getValueAsListOfDefs("FuncList");
const std::string &ComboFuncName = std::string(ComboFunc->getName());
uint64_t ComboBit = FUNameToBitsMap[ComboFuncName];
uint64_t ComboResources = ComboBit;
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6 changes: 3 additions & 3 deletions llvm/utils/TableGen/DXILEmitter.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -116,7 +116,7 @@ DXILOperationDesc::DXILOperationDesc(const Record *R) {
}

// Get overload records
std::vector<const Record *> Recs = R->getValueAsListOfConstDefs("overloads");
std::vector<const Record *> Recs = R->getValueAsListOfDefs("overloads");

// Sort records in ascending order of DXIL version
AscendingSortByVersion(Recs);
Expand All @@ -126,7 +126,7 @@ DXILOperationDesc::DXILOperationDesc(const Record *R) {
}

// Get stage records
Recs = R->getValueAsListOfConstDefs("stages");
Recs = R->getValueAsListOfDefs("stages");

if (Recs.empty()) {
PrintFatalError(R, Twine("Atleast one specification of valid stage for ") +
Expand All @@ -141,7 +141,7 @@ DXILOperationDesc::DXILOperationDesc(const Record *R) {
}

// Get attribute records
Recs = R->getValueAsListOfConstDefs("attributes");
Recs = R->getValueAsListOfDefs("attributes");

// Sort records in ascending order of DXIL version
AscendingSortByVersion(Recs);
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4 changes: 2 additions & 2 deletions llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2681,7 +2681,7 @@ void GICombinerEmitter::gatherRules(std::vector<RuleMatcher> &ActiveRules,
ArrayRef<const Record *> RulesAndGroups) {
for (const Record *Rec : RulesAndGroups) {
if (!Rec->isValueUnset("Rules")) {
gatherRules(ActiveRules, Rec->getValueAsListOfConstDefs("Rules"));
gatherRules(ActiveRules, Rec->getValueAsListOfDefs("Rules"));
continue;
}

Expand Down Expand Up @@ -2720,7 +2720,7 @@ void GICombinerEmitter::run(raw_ostream &OS) {

Records.startTimer("Gather rules");
std::vector<RuleMatcher> Rules;
gatherRules(Rules, Combiner->getValueAsListOfConstDefs("Rules"));
gatherRules(Rules, Combiner->getValueAsListOfDefs("Rules"));
if (ErrorsPrinted)
PrintFatalError(Combiner->getLoc(), "Failed to parse one or more rules");

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2 changes: 1 addition & 1 deletion llvm/utils/TableGen/InstrDocsEmitter.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -214,7 +214,7 @@ static void EmitInstrDocs(const RecordKeeper &RK, raw_ostream &OS) {

// Predicates.
std::vector<const Record *> Predicates =
II->TheDef->getValueAsListOfConstDefs("Predicates");
II->TheDef->getValueAsListOfDefs("Predicates");
if (!Predicates.empty()) {
OS << "Predicates: ";
ListSeparator LS;
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2 changes: 1 addition & 1 deletion llvm/utils/TableGen/MacroFusionPredicatorEmitter.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -101,7 +101,7 @@ void MacroFusionPredicatorEmitter::emitMacroFusionImpl(

for (const Record *Fusion : Fusions) {
std::vector<const Record *> Predicates =
Fusion->getValueAsListOfConstDefs("Predicates");
Fusion->getValueAsListOfDefs("Predicates");
bool IsCommutable = Fusion->getValueAsBit("IsCommutable");

OS << "bool is" << Fusion->getName() << "(\n";
Expand Down
2 changes: 1 addition & 1 deletion llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -172,7 +172,7 @@ static void emitRISCVProcs(const RecordKeeper &RK, raw_ostream &OS) {
// Iterate on all definition records.
for (const Record *Rec :
RK.getAllDerivedDefinitionsIfDefined("RISCVProcessorModel")) {
const std::vector<Record *> &Features =
const std::vector<const Record *> &Features =
Rec->getValueAsListOfDefs("Features");
bool FastScalarUnalignedAccess = any_of(Features, [&](auto &Feature) {
return Feature->getValueAsString("Name") == "unaligned-scalar-mem";
Expand Down
35 changes: 16 additions & 19 deletions llvm/utils/TableGen/SubtargetEmitter.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -284,7 +284,7 @@ unsigned SubtargetEmitter::FeatureKeyValues(raw_ostream &OS,
<< "\"" << CommandLineName << "\", "
<< "\"" << Desc << "\", " << Target << "::" << Name << ", ";

ConstRecVec ImpliesList = Feature->getValueAsListOfConstDefs("Implies");
ConstRecVec ImpliesList = Feature->getValueAsListOfDefs("Implies");

printFeatureMask(OS, ImpliesList, FeatureMap);

Expand Down Expand Up @@ -320,9 +320,9 @@ unsigned SubtargetEmitter::CPUKeyValues(raw_ostream &OS,

for (const Record *Processor : ProcessorList) {
StringRef Name = Processor->getValueAsString("Name");
ConstRecVec FeatureList = Processor->getValueAsListOfConstDefs("Features");
ConstRecVec FeatureList = Processor->getValueAsListOfDefs("Features");
ConstRecVec TuneFeatureList =
Processor->getValueAsListOfConstDefs("TuneFeatures");
Processor->getValueAsListOfDefs("TuneFeatures");

// Emit as "{ "cpu", "description", 0, { f1 , f2 , ... fn } },".
OS << " { "
Expand Down Expand Up @@ -354,7 +354,7 @@ void SubtargetEmitter::FormItineraryStageString(const std::string &Name,
std::string &ItinString,
unsigned &NStages) {
// Get states list
ConstRecVec StageList = ItinData->getValueAsListOfConstDefs("Stages");
ConstRecVec StageList = ItinData->getValueAsListOfDefs("Stages");

// For each stage
unsigned N = NStages = StageList.size();
Expand All @@ -367,7 +367,7 @@ void SubtargetEmitter::FormItineraryStageString(const std::string &Name,
ItinString += " { " + itostr(Cycles) + ", ";

// Get unit list
ConstRecVec UnitList = Stage->getValueAsListOfConstDefs("Units");
ConstRecVec UnitList = Stage->getValueAsListOfDefs("Units");

// For each unit
for (unsigned j = 0, M = UnitList.size(); j < M;) {
Expand Down Expand Up @@ -415,7 +415,7 @@ void SubtargetEmitter::FormItineraryBypassString(const std::string &Name,
const Record *ItinData,
std::string &ItinString,
unsigned NOperandCycles) {
ConstRecVec BypassList = ItinData->getValueAsListOfConstDefs("Bypasses");
ConstRecVec BypassList = ItinData->getValueAsListOfDefs("Bypasses");
unsigned N = BypassList.size();
unsigned i = 0;
ListSeparator LS;
Expand Down Expand Up @@ -445,7 +445,7 @@ void SubtargetEmitter::EmitStageAndOperandCycleData(
if (!ItinsDefSet.insert(ProcModel.ItinsDef).second)
continue;

ConstRecVec FUs = ProcModel.ItinsDef->getValueAsListOfConstDefs("FU");
ConstRecVec FUs = ProcModel.ItinsDef->getValueAsListOfDefs("FU");
if (FUs.empty())
continue;

Expand All @@ -459,7 +459,7 @@ void SubtargetEmitter::EmitStageAndOperandCycleData(

OS << "} // end namespace " << Name << "FU\n";

ConstRecVec BPs = ProcModel.ItinsDef->getValueAsListOfConstDefs("BP");
ConstRecVec BPs = ProcModel.ItinsDef->getValueAsListOfDefs("BP");
if (!BPs.empty()) {
OS << "\n// Pipeline forwarding paths for itineraries \"" << Name
<< "\"\n"
Expand Down Expand Up @@ -1005,7 +1005,7 @@ void SubtargetEmitter::ExpandProcResources(
const Record *PRDef = PRVec[i];
ConstRecVec SubResources;
if (PRDef->isSubClassOf("ProcResGroup"))
SubResources = PRDef->getValueAsListOfConstDefs("Resources");
SubResources = PRDef->getValueAsListOfDefs("Resources");
else {
SubResources.push_back(PRDef);
PRDef = SchedModels.findProcResUnits(PRDef, PM, PRDef->getLoc());
Expand All @@ -1027,7 +1027,7 @@ void SubtargetEmitter::ExpandProcResources(
for (const Record *PR : PM.ProcResourceDefs) {
if (PR == PRDef || !PR->isSubClassOf("ProcResGroup"))
continue;
ConstRecVec SuperResources = PR->getValueAsListOfConstDefs("Resources");
ConstRecVec SuperResources = PR->getValueAsListOfDefs("Resources");
ConstRecIter SubI = SubResources.begin(), SubE = SubResources.end();
for (; SubI != SubE; ++SubI) {
if (!is_contained(SuperResources, *SubI)) {
Expand Down Expand Up @@ -1104,18 +1104,16 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
if (RWDef) {
Writes.clear();
Reads.clear();
SchedModels.findRWs(
RWDef->getValueAsListOfConstDefs("OperandReadWrites"), Writes,
Reads);
SchedModels.findRWs(RWDef->getValueAsListOfDefs("OperandReadWrites"),
Writes, Reads);
}
}
if (Writes.empty()) {
// Check this processor's itinerary class resources.
for (const Record *I : ProcModel.ItinRWDefs) {
ConstRecVec Matched =
I->getValueAsListOfConstDefs("MatchedItinClasses");
ConstRecVec Matched = I->getValueAsListOfDefs("MatchedItinClasses");
if (is_contained(Matched, SC.ItinClassDef)) {
SchedModels.findRWs(I->getValueAsListOfConstDefs("OperandReadWrites"),
SchedModels.findRWs(I->getValueAsListOfDefs("OperandReadWrites"),
Writes, Reads);
break;
}
Expand Down Expand Up @@ -1165,8 +1163,7 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
SCDesc.RetireOOO |= WriteRes->getValueAsBit("RetireOOO");

// Create an entry for each ProcResource listed in WriteRes.
ConstRecVec PRVec =
WriteRes->getValueAsListOfConstDefs("ProcResources");
ConstRecVec PRVec = WriteRes->getValueAsListOfDefs("ProcResources");
std::vector<int64_t> ReleaseAtCycles =
WriteRes->getValueAsListOfInts("ReleaseAtCycles");

Expand Down Expand Up @@ -1276,7 +1273,7 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
break;
}
ConstRecVec ValidWrites =
ReadAdvance->getValueAsListOfConstDefs("ValidWrites");
ReadAdvance->getValueAsListOfDefs("ValidWrites");
IdxVec WriteIDs;
if (ValidWrites.empty())
WriteIDs.push_back(0);
Expand Down
2 changes: 1 addition & 1 deletion llvm/utils/TableGen/X86RecognizableInstr.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -154,7 +154,7 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
UID(uid), Spec(&tables.specForUID(uid)) {
// Check for 64-bit inst which does not require REX
// FIXME: Is there some better way to check for In64BitMode?
for (const Record *Predicate : Rec->getValueAsListOfConstDefs("Predicates")) {
for (const Record *Predicate : Rec->getValueAsListOfDefs("Predicates")) {
if (Predicate->getName().contains("Not64Bit") ||
Predicate->getName().contains("In32Bit")) {
Is32Bit = true;
Expand Down
2 changes: 1 addition & 1 deletion mlir/lib/TableGen/Predicate.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -82,7 +82,7 @@ const llvm::Record *CombinedPred::getCombinerDef() const {
std::vector<const llvm::Record *> CombinedPred::getChildren() const {
assert(def->getValue("children") &&
"CombinedPred must have a value 'children'");
return def->getValueAsListOfConstDefs("children");
return def->getValueAsListOfDefs("children");
}

namespace {
Expand Down
4 changes: 2 additions & 2 deletions mlir/tools/mlir-tblgen/BytecodeDialectGen.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -437,14 +437,14 @@ static bool emitBCRW(const RecordKeeper &records, raw_ostream &os) {
it->getValueAsString("dialect") != selectedBcDialect)
continue;
dialectAttrOrType[it->getValueAsString("dialect")].attr =
it->getValueAsListOfConstDefs("elems");
it->getValueAsListOfDefs("elems");
}
for (const Record *it : records.getAllDerivedDefinitions("DialectTypes")) {
if (!selectedBcDialect.empty() &&
it->getValueAsString("dialect") != selectedBcDialect)
continue;
dialectAttrOrType[it->getValueAsString("dialect")].type =
it->getValueAsListOfConstDefs("elems");
it->getValueAsListOfDefs("elems");
}

if (dialectAttrOrType.size() != 1)
Expand Down
4 changes: 2 additions & 2 deletions mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -167,7 +167,7 @@ std::vector<Availability> getAvailabilities(const Record &def) {

if (def.getValue("availability")) {
std::vector<const Record *> availDefs =
def.getValueAsListOfConstDefs("availability");
def.getValueAsListOfDefs("availability");
availabilities.reserve(availDefs.size());
for (const Record *avail : availDefs)
availabilities.emplace_back(avail);
Expand Down Expand Up @@ -1451,7 +1451,7 @@ static bool emitCapabilityImplication(const RecordKeeper &recordKeeper,
continue;

std::vector<const Record *> impliedCapsDefs =
def.getValueAsListOfConstDefs("implies");
def.getValueAsListOfDefs("implies");
os << " case spirv::Capability::" << enumerant.getSymbol()
<< ": {static const spirv::Capability implies[" << impliedCapsDefs.size()
<< "] = {";
Expand Down