10 changes: 5 additions & 5 deletions llvm/test/CodeGen/Hexagon/bit-bitsplit-at.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -7,23 +7,23 @@

target triple = "hexagon"

define hidden fastcc i32 @fred(i32 %a0) unnamed_addr #0 {
define fastcc i32 @fred(i32 %a0, i8* %a1, i1 %a2, i1 %a3) #0 {
b1:
%v2 = lshr i32 %a0, 16
%v3 = trunc i32 %v2 to i8
br i1 undef, label %b6, label %b4
br i1 %a2, label %b6, label %b4

b4: ; preds = %b1
%v5 = and i32 %a0, 65535
br i1 undef, label %b8, label %b9
br i1 %a3, label %b8, label %b9

b6: ; preds = %b1
%v7 = and i32 %a0, 65535
br label %b9

b8: ; preds = %b4
store i8 %v3, i8* undef, align 2
unreachable
store i8 %v3, i8* %a1, align 2
ret i32 1

b9: ; preds = %b6, %b4
%v10 = phi i32 [ %v7, %b6 ], [ %v5, %b4 ]
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4 changes: 3 additions & 1 deletion llvm/test/CodeGen/Hexagon/bit-extract-off.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -7,13 +7,15 @@

target triple = "hexagon"

@g0 = global double zeroinitializer, align 8

define hidden i32 @fred([101 x double]* %a0, i32 %a1, i32* %a2, i32* %a3) #0 {
b4:
br label %b5

b5: ; preds = %b5, %b4
%v6 = call double @fabs(double undef) #1
store double %v6, double* undef, align 8
store double %v6, double* @g0, align 8
br label %b5
}

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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Hexagon/bit-has.ll
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Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s
; REQUIRES: asserts

; This used to crash. Check for some sane output.
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8 changes: 4 additions & 4 deletions llvm/test/CodeGen/Hexagon/bitconvert-vector.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -11,15 +11,15 @@ declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #0
declare <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32>, <32 x i32>, i32) #0
declare <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32>, <32 x i32>, i32) #0

define void @fred() #1 {
define void @fred(<64 x i16>* %a0, <32 x i32>* %a1) #1 {
entry:
%t0 = bitcast <64 x i16> zeroinitializer to <32 x i32>
%t1 = tail call <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32> %t0, <32 x i32> undef, i32 2)
%t2 = tail call <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32> undef, <32 x i32> %t1, i32 -2)
%t3 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %t2)
store <64 x i16> zeroinitializer, <64 x i16>* undef, align 128
store <32 x i32> %t3, <32 x i32>* undef, align 128
unreachable
store <64 x i16> zeroinitializer, <64 x i16>* %a0, align 128
store <32 x i32> %t3, <32 x i32>* %a1, align 128
ret void
}


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14 changes: 7 additions & 7 deletions llvm/test/CodeGen/Hexagon/build-vector-shuffle.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -4,14 +4,14 @@

target triple = "hexagon"

define void @hex_interleaved.s0.__outermost() local_unnamed_addr #0 {
define void @f0(<16 x i32>* %a0) #0 {
entry:
%0 = icmp eq i32 undef, 0
%sel2 = select i1 %0, <32 x i16> undef, <32 x i16> zeroinitializer
%1 = bitcast <32 x i16> %sel2 to <16 x i32>
%2 = tail call <16 x i32> @llvm.hexagon.V6.vshuffh(<16 x i32> %1)
store <16 x i32> %2, <16 x i32>* undef, align 2
unreachable
%v0 = icmp eq i32 undef, 0
%v1 = select i1 %v0, <32 x i16> undef, <32 x i16> zeroinitializer
%v2 = bitcast <32 x i16> %v1 to <16 x i32>
%v3 = tail call <16 x i32> @llvm.hexagon.V6.vshuffh(<16 x i32> %v2)
store <16 x i32> %v3, <16 x i32>* %a0, align 2
ret void
}

; Function Attrs: nounwind readnone
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9 changes: 4 additions & 5 deletions llvm/test/CodeGen/Hexagon/callR_noreturn.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -5,18 +5,17 @@
%s.1 = type { [1 x %s.2], i32, [4 x i8] }
%s.2 = type { [16 x i32] }

; Function Attrs: noreturn nounwind
define hidden void @f0() #0 section ".text.compat" {
define hidden void @f0(void (%s.0*)* %a0) #0 {
b0:
br i1 undef, label %b2, label %b1

b1: ; preds = %b0
unreachable
ret void

b2: ; preds = %b0
call void undef(%s.0* undef) #1
call void %a0(%s.0* null) #1
unreachable
}

attributes #0 = { noreturn nounwind }
attributes #1 = { noreturn }
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Hexagon/cext-check.ll
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Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
; RUN: llc -march=hexagon -hexagon-eif=0 -ifcvt-limit=0 < %s | FileCheck %s
; RUN: llc -march=hexagon -hexagon-eif=0 -ifcvt-limit=0 -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s
; Check that we constant extended instructions only when necessary.

define i32 @cext_test1(i32* %a) nounwind {
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Hexagon/cfgopt-fall-through.ll
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Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -march=hexagon -verify-machineinstrs -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s
; REQUIRES: asserts

; Check for some sane output. This test used to crash.
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/Hexagon/convert_const_i1_to_i8.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -2,12 +2,12 @@
; CHECK-NOT: .space {{[0-9][0-9][0-9][0-9]}}
; CHECK: q{{[0-3]}} = vand(v{{[0-9]*}},r{{[0-9]*}})

define void @convert_const_i1_to_i8() #0 {
define void @convert_const_i1_to_i8(<32 x i32>* %a0) #0 {
entry:
%v0 = load <32 x i32>, <32 x i32>* undef, align 128
%v0 = load <32 x i32>, <32 x i32>* %a0, align 128
%v1 = tail call <32 x i32> @llvm.hexagon.V6.vrdelta.128B(<32 x i32> %v0, <32 x i32> undef)
%v2 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> <i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <32 x i32> undef, <32 x i32> %v1)
store <32 x i32> %v2, <32 x i32>* null, align 128
store <32 x i32> %v2, <32 x i32>* %a0, align 128
ret void
}

Expand Down
71 changes: 32 additions & 39 deletions llvm/test/CodeGen/Hexagon/copy-to-combine-dbg.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,54 +4,47 @@

target triple = "hexagon"

define i32 @fred(i32 %p) local_unnamed_addr #0 !dbg !6 {
entry:
br label %cond.end

cond.end: ; preds = %entry
br i1 undef, label %cond.false.i, label %for.body.lr.ph.i

for.body.lr.ph.i: ; preds = %cond.end
tail call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !10, metadata !12) #0, !dbg !13
br label %for.body.i

cond.false.i: ; preds = %cond.end
unreachable

for.body.i: ; preds = %for.inc.i, %for.body.lr.ph.i
%inc.sink37.i = phi i32 [ 0, %for.body.lr.ph.i ], [ %inc.i, %for.inc.i ]
%call.i = tail call i8* undef(i32 12, i8* undef) #0
br label %for.inc.i

for.inc.i: ; preds = %for.body.i
%inc.i = add nuw i32 %inc.sink37.i, 1
%cmp1.i = icmp ult i32 %inc.i, %p
br i1 %cmp1.i, label %for.body.i, label %PQ_AllocMem.exit.loopexit

PQ_AllocMem.exit.loopexit: ; preds = %for.inc.i
unreachable
; Function Attrs: nounwind
define i32 @f0(i32 %a0, i8* (i32, i8*)* %a1) local_unnamed_addr #0 !dbg !5 {
b0:
br label %b1

b1: ; preds = %b0
call void @llvm.dbg.value(metadata i32 0, metadata !8, metadata !DIExpression()), !dbg !10
br label %b2

b2: ; preds = %b3, %b1
%v0 = phi i32 [ 0, %b1 ], [ %v2, %b3 ]
%v1 = tail call i8* %a1(i32 12, i8* null) #0
br label %b3

b3: ; preds = %b2
%v2 = add nuw i32 %v0, 1
%v3 = icmp ult i32 %v2, %a0
br i1 %v3, label %b2, label %b4

b4: ; preds = %b3
ret i32 0
}

declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1
; Function Attrs: nounwind readnone speculatable
declare void @llvm.dbg.value(metadata, metadata, metadata) #1

attributes #0 = { nounwind }
attributes #1 = { nounwind readnone }
attributes #1 = { nounwind readnone speculatable }

!llvm.dbg.cu = !{!0}
!llvm.module.flags = !{!3, !4}
!llvm.ident = !{!5}

!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 4.0.0 (http://llvm.org/git/clang.git 37afcb099ac2b001f4c826da7ca1d077b67a508c) (http://llvm.org/git/llvm.git 5887f1c75b3ba216850c834b186efdd3e54b7d4f)", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !2)
!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 4.0.0 (http://llvm.org/git/clang.git 37afcb099ac2b001f4c826da7ca1d077b67a508c) (http://llvm.org/git/llvm.git 5887f1c75b3ba216850c834b186efdd3e54b7d4f)", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2)
!1 = !DIFile(filename: "file.c", directory: "/")
!2 = !{}
!3 = !{i32 2, !"Dwarf Version", i32 4}
!4 = !{i32 2, !"Debug Info Version", i32 3}
!5 = !{!"clang version 4.0.0 (http://llvm.org/git/clang.git 37afcb099ac2b001f4c826da7ca1d077b67a508c) (http://llvm.org/git/llvm.git 5887f1c75b3ba216850c834b186efdd3e54b7d4f)"}
!6 = distinct !DISubprogram(name: "fred", scope: !1, file: !1, line: 116, type: !7, isLocal: false, isDefinition: true, scopeLine: 121, flags: DIFlagPrototyped, isOptimized: true, unit: !0, retainedNodes: !9)
!7 = !DISubroutineType(types: !2)
!8 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
!9 = !{!10}
!10 = !DILocalVariable(name: "Count", scope: !6, file: !1, line: 1, type: !8)
!11 = distinct !DILocation(line: 1, column: 1, scope: !6)
!12 = !DIExpression()
!13 = !DILocation(line: 1, column: 1, scope: !6, inlinedAt: !11)
!5 = distinct !DISubprogram(name: "fred", scope: !1, file: !1, line: 116, type: !6, isLocal: false, isDefinition: true, scopeLine: 121, flags: DIFlagPrototyped, isOptimized: true, unit: !0, retainedNodes: !7)
!6 = !DISubroutineType(types: !2)
!7 = !{!8}
!8 = !DILocalVariable(name: "Count", scope: !5, file: !1, line: 1, type: !9)
!9 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
!10 = !DILocation(line: 1, column: 1, scope: !5, inlinedAt: !11)
!11 = distinct !DILocation(line: 1, column: 1, scope: !5)
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Hexagon/dealloc-store.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -22,7 +22,7 @@ target triple = "hexagon"
define void @f0(%s.6* %a0, i8 zeroext %a1) {
; look for a dealloc_return in a packet with nothing else.
;
; CHECK: if (p{{[0-3]}}) memw(
; CHECK: memw(r1+#0) = r0
; CHECK: }
; CHECK: {
; CHECK-NEXT: dealloc_return
Expand Down
67 changes: 8 additions & 59 deletions llvm/test/CodeGen/Hexagon/dont_rotate_pregs_at_O2.ll
View file
Original file line number Diff line number Diff line change
@@ -1,68 +1,17 @@
; RUN: llc -O2 -march=hexagon -hexagon-eif=0 < %s | FileCheck %s
; RUN: llc -march=hexagon -O2 < %s | FileCheck %s

; Make sure we are not rotating registers at O2.
; CHECK-NOT: p1 =
; CHECK-NOT: p2 =

target triple = "hexagon-unknown-linux-gnu"

; Function Attrs: nounwind readnone
define i32 @f0(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5) #0 {
define i32 @f0(i32 %a0, i32 %a1) #0 {
b0:
%v0 = icmp slt i32 %a0, %a1
br i1 %v0, label %b1, label %b2

b1: ; preds = %b0
%v1 = mul nsw i32 %a1, %a0
br label %b2

b2: ; preds = %b1, %b0
%v2 = phi i32 [ %v1, %b1 ], [ 0, %b0 ]
%v3 = icmp sgt i32 %a0, %a1
br i1 %v3, label %b3, label %b4

b3: ; preds = %b2
%v4 = mul nsw i32 %a2, %a1
%v5 = add nsw i32 %v4, %a0
%v6 = add nsw i32 %v5, %a3
%v7 = add nsw i32 %v6, %v2
br label %b4

b4: ; preds = %b3, %b2
%v8 = phi i32 [ %v7, %b3 ], [ %v2, %b2 ]
%v9 = icmp sgt i32 %a2, %a3
br i1 %v9, label %b5, label %b6

b5: ; preds = %b4
%v10 = mul nsw i32 %a3, %a2
%v11 = add nsw i32 %v8, %v10
br label %b6
b1:
ret i32 0

b6: ; preds = %b5, %b4
%v12 = phi i32 [ %v11, %b5 ], [ %v8, %b4 ]
%v13 = icmp sgt i32 %a3, %a2
br i1 %v13, label %b7, label %b8

b7: ; preds = %b6
%v14 = sdiv i32 %a3, 2
%v15 = mul nsw i32 %v14, %a0
%v16 = add nsw i32 %v15, %v12
br label %b8

b8: ; preds = %b7, %b6
%v17 = phi i32 [ %v16, %b7 ], [ %v12, %b6 ]
%v18 = icmp slt i32 %a4, %a5
br i1 %v18, label %b9, label %b10

b9: ; preds = %b8
%v19 = mul i32 %a4, %a3
%v20 = mul i32 %v19, %a5
%v21 = add nsw i32 %v17, %v20
br label %b10

b10: ; preds = %b9, %b8
%v22 = phi i32 [ %v21, %b9 ], [ %v17, %b8 ]
ret i32 %v22
b2:
%v1 = icmp slt i32 %a1, 100
%v2 = select i1 %v1, i32 123, i32 321
ret i32 %v2
}

attributes #0 = { nounwind readnone "target-cpu"="hexagonv55" }
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Hexagon/expand-condsets-dead-bad.ll
View file
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -march=hexagon -verify-machineinstrs -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s
; REQUIRES: asserts

; Check for some output other than crashing.
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Hexagon/expand-condsets-dead-pred.ll
View file
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -march=hexagon -verify-machineinstrs -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s
; REQUIRES: asserts

; Check for some output (as opposed to a crash).
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Hexagon/expand-vstorerw-undef.ll
View file
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s

; After register allocation it is possible to have a spill of a register
; that is only partially defined. That in itself it fine, but creates a
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Hexagon/ignore-terminal-mbb.ll
View file
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s

; CHECK-NOT: if{{.*}}jump{{.*}}-1
; CHECK: memw
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/Hexagon/indirect-br.ll
View file
Original file line number Diff line number Diff line change
@@ -1,14 +1,14 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s

;CHECK: jumpr r{{[0-9]+}}
; CHECK: jumpr r{{[0-9]+}}

define i32 @check_indirect_br(i8* %target) nounwind {
entry:
indirectbr i8* %target, [label %test_label]
indirectbr i8* %target, [label %test_label]

test_label:
br label %ret
br label %ret

ret:
ret i32 -1
ret i32 -1
}
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Hexagon/isel-global-offset-alignment.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -27,7 +27,7 @@ b3: ; preds = %b1, %b0
%v8 = getelementptr i16, i16* %v7, i32 88
%v9 = bitcast i16* %v8 to <8 x i16>*
store <8 x i16> zeroinitializer, <8 x i16>* %v9, align 8
unreachable
ret void
}

attributes #0 = { norecurse nounwind }
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Hexagon/isel-setcc-i1.ll
View file
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s

; Check that this compiles successfully.
; CHECK: if (p0)
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Hexagon/isel-simplify-crash.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -22,7 +22,7 @@ b5: ; preds = %b1
ret void

b11: ; preds = %b1
unreachable
ret void
}

attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-length64b,+hvxv60" }
21 changes: 10 additions & 11 deletions llvm/test/CodeGen/Hexagon/long-calls.ll
View file
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
; RUN: llc -march=hexagon -enable-save-restore-long < %s | FileCheck %s
; RUN: llc -march=hexagon -enable-save-restore-long -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s

; Check that the -long-calls feature is supported by the backend.

Expand All @@ -7,7 +7,7 @@
define i64 @test_longcall(i32 %x, i32 %y) #0 {
entry:
%add = add nsw i32 %x, 5
%call = tail call i64 @foo(i32 %add) #6
%call = tail call i64 @foo(i32 %add) #1
%conv = sext i32 %y to i64
%add1 = add nsw i64 %call, %conv
ret i64 %add1
Expand All @@ -17,15 +17,15 @@ entry:
define i64 @test_longtailcall(i32 %x, i32 %y) #1 {
entry:
%add = add nsw i32 %x, 5
%call = tail call i64 @foo(i32 %add) #6
%call = tail call i64 @foo(i32 %add) #1
ret i64 %call
}

; CHECK: call ##bar
define i64 @test_longnoret(i32 %x, i32 %y) #2 {
entry:
%add = add nsw i32 %x, 5
%0 = tail call i64 @bar(i32 %add) #7
%0 = tail call i64 @bar(i32 %add) #6
unreachable
}

Expand All @@ -36,7 +36,7 @@ entry:
define i64 @test_shortcall(i32 %x, i32 %y) #3 {
entry:
%add = add nsw i32 %x, 5
%call = tail call i64 @foo(i32 %add) #6
%call = tail call i64 @foo(i32 %add) #1
%conv = sext i32 %y to i64
%add1 = add nsw i64 %call, %conv
ret i64 %add1
Expand All @@ -46,20 +46,20 @@ entry:
define i64 @test_shorttailcall(i32 %x, i32 %y) #4 {
entry:
%add = add nsw i32 %x, 5
%call = tail call i64 @foo(i32 %add) #6
%call = tail call i64 @foo(i32 %add) #1
ret i64 %call
}

; CHECK: call bar
define i64 @test_shortnoret(i32 %x, i32 %y) #5 {
entry:
%add = add nsw i32 %x, 5
%0 = tail call i64 @bar(i32 %add) #7
%0 = tail call i64 @bar(i32 %add) #6
unreachable
}

declare i64 @foo(i32) #6
declare i64 @bar(i32) #7
declare i64 @foo(i32) #1
declare i64 @bar(i32) #6

attributes #0 = { minsize nounwind "target-cpu"="hexagonv60" "target-features"="+long-calls" }
attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+long-calls" }
Expand All @@ -69,5 +69,4 @@ attributes #3 = { minsize nounwind "target-cpu"="hexagonv60" "target-features"="
attributes #4 = { nounwind "target-cpu"="hexagonv60" "target-features"="-long-calls" }
attributes #5 = { noreturn nounwind "target-cpu"="hexagonv60" "target-features"="-long-calls" }

attributes #6 = { noreturn "target-cpu"="hexagonv60" }
attributes #7 = { noreturn nounwind "target-cpu"="hexagonv60" }
attributes #6 = { noreturn nounwind "target-cpu"="hexagonv60" }
40 changes: 7 additions & 33 deletions llvm/test/CodeGen/Hexagon/lower-extract-subvector.ll
View file
Original file line number Diff line number Diff line change
@@ -1,46 +1,20 @@
; RUN: llc -march=hexagon -O3 < %s | FileCheck %s
; RUN: llc -march=hexagon < %s | FileCheck %s

; This test checks if we custom lower extract_subvector. If we cannot
; custom lower extract_subvector this test makes the compiler crash.

; CHECK: vmem
target triple = "hexagon-unknown--elf"

; Function Attrs: nounwind
define void @__processed() #0 {
entry:
br label %"for matrix.s0.y"

"for matrix.s0.y": ; preds = %"for matrix.s0.y", %entry
br i1 undef, label %"produce processed", label %"for matrix.s0.y"

"produce processed": ; preds = %"for matrix.s0.y"
br i1 undef, label %"for processed.s0.ty.ty.preheader", label %"consume processed"

"for processed.s0.ty.ty.preheader": ; preds = %"produce processed"
br i1 undef, label %"for denoised.s0.y.preheader", label %"consume denoised"

"for denoised.s0.y.preheader": ; preds = %"for processed.s0.ty.ty.preheader"
unreachable

"consume denoised": ; preds = %"for processed.s0.ty.ty.preheader"
br i1 undef, label %"consume deinterleaved", label %if.then.i164

if.then.i164: ; preds = %"consume denoised"
unreachable

"consume deinterleaved": ; preds = %"consume denoised"
%0 = tail call <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32> undef, <32 x i32> undef, i32 -2)
%1 = bitcast <64 x i32> %0 to <128 x i16>
%2 = shufflevector <128 x i16> %1, <128 x i16> undef, <64 x i32> <i32 64, i32 65, i32 66, i32 67, i32 68, i32 69, i32 70, i32 71, i32 72, i32 73, i32 74, i32 75, i32 76, i32 77, i32 78, i32 79, i32 80, i32 81, i32 82, i32 83, i32 84, i32 85, i32 86, i32 87, i32 88, i32 89, i32 90, i32 91, i32 92, i32 93, i32 94, i32 95, i32 96, i32 97, i32 98, i32 99, i32 100, i32 101, i32 102, i32 103, i32 104, i32 105, i32 106, i32 107, i32 108, i32 109, i32 110, i32 111, i32 112, i32 113, i32 114, i32 115, i32 116, i32 117, i32 118, i32 119, i32 120, i32 121, i32 122, i32 123, i32 124, i32 125, i32 126, i32 127>
store <64 x i16> %2, <64 x i16>* undef, align 128
unreachable

"consume processed": ; preds = %"produce processed"
define void @f0(<64 x i16>* %a0) #0 {
b0:
%v0 = tail call <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32> undef, <32 x i32> undef, i32 -2)
%v1 = bitcast <64 x i32> %v0 to <128 x i16>
%v2 = shufflevector <128 x i16> %v1, <128 x i16> undef, <64 x i32> <i32 64, i32 65, i32 66, i32 67, i32 68, i32 69, i32 70, i32 71, i32 72, i32 73, i32 74, i32 75, i32 76, i32 77, i32 78, i32 79, i32 80, i32 81, i32 82, i32 83, i32 84, i32 85, i32 86, i32 87, i32 88, i32 89, i32 90, i32 91, i32 92, i32 93, i32 94, i32 95, i32 96, i32 97, i32 98, i32 99, i32 100, i32 101, i32 102, i32 103, i32 104, i32 105, i32 106, i32 107, i32 108, i32 109, i32 110, i32 111, i32 112, i32 113, i32 114, i32 115, i32 116, i32 117, i32 118, i32 119, i32 120, i32 121, i32 122, i32 123, i32 124, i32 125, i32 126, i32 127>
store <64 x i16> %v2, <64 x i16>* %a0, align 128
ret void
}

; Function Attrs: nounwind readnone
declare <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32>, <32 x i32>, i32) #1

attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/Hexagon/mux-undef.ll
View file
Original file line number Diff line number Diff line change
@@ -1,18 +1,18 @@
; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s
;
; Make sure this test compiles successfully.
; CHECK: jumpr r31
; CHECK: call foo

target triple = "hexagon--elf"

; Function Attrs: nounwind
define i32 @fred() #0 {
define i32 @fred(i1 %a0) #0 {
b0:
call void @foo() #0
br label %b1

b1: ; preds = %b0
br i1 undef, label %b2, label %b3
br i1 %a0, label %b2, label %b3

b2: ; preds = %b1
br label %b3
Expand Down
88 changes: 44 additions & 44 deletions llvm/test/CodeGen/Hexagon/newvalueSameReg.ll
View file
Original file line number Diff line number Diff line change
@@ -1,63 +1,63 @@
; RUN: llc -march=hexagon -hexagon-expand-condsets=0 < %s | FileCheck %s
; RUN: llc -march=hexagon -hexagon-expand-condsets=0 -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s
;
; Expand-condsets eliminates the "mux" instruction, which is what this
; testcase is checking.

%struct._Dnk_filet.1 = type { i16, i8, i32, i8*, i8*, i8*, i8*, i8*, i8*, i32*, [2 x i32], i8*, i8*, i8*, %struct._Mbstatet.0, i8*, [8 x i8], i8 }
%struct._Mbstatet.0 = type { i32, i16, i16 }

@_Stdout = external global %struct._Dnk_filet.1
@.str = external unnamed_addr constant [23 x i8], align 8

; Test that we don't generate a new value compare if the operands are
; the same register.

; CHECK-NOT: cmp.eq([[REG0:(r[0-9]+)]].new,[[REG0]])
; CHECK: cmp.eq([[REG1:(r[0-9]+)]],[[REG1]])

%s.0 = type { i16, i8, i32, i8*, i8*, i8*, i8*, i8*, i8*, i32*, [2 x i32], i8*, i8*, i8*, %s.1, i8*, [8 x i8], i8 }
%s.1 = type { i32, i16, i16 }

@g0 = external global %s.0
@g1 = external unnamed_addr constant [23 x i8], align 8

; Function Attrs: nounwind
declare void @fprintf(%struct._Dnk_filet.1* nocapture, i8* nocapture readonly, ...) #1

define void @main() #0 {
entry:
%0 = load i32*, i32** undef, align 4
%1 = load i32, i32* undef, align 4
br i1 undef, label %if.end, label %_ZNSt6vectorIbSaIbEE3endEv.exit

_ZNSt6vectorIbSaIbEE3endEv.exit:
%2 = icmp slt i32 %1, 0
%sub5.i.i.i = lshr i32 %1, 5
%add619.i.i.i = add i32 %sub5.i.i.i, -134217728
%sub5.i.pn.i.i = select i1 %2, i32 %add619.i.i.i, i32 %sub5.i.i.i
%storemerge2.i.i = getelementptr inbounds i32, i32* %0, i32 %sub5.i.pn.i.i
%cmp.i.i = icmp ult i32* %storemerge2.i.i, %0
%.mux = select i1 %cmp.i.i, i32 0, i32 1
br i1 undef, label %_ZNSt6vectorIbSaIbEE3endEv.exit57, label %if.end

_ZNSt6vectorIbSaIbEE3endEv.exit57:
%3 = icmp slt i32 %1, 0
%sub5.i.i.i44 = lshr i32 %1, 5
%add619.i.i.i45 = add i32 %sub5.i.i.i44, -134217728
%sub5.i.pn.i.i46 = select i1 %3, i32 %add619.i.i.i45, i32 %sub5.i.i.i44
%storemerge2.i.i47 = getelementptr inbounds i32, i32* %0, i32 %sub5.i.pn.i.i46
%cmp.i38 = icmp ult i32* %storemerge2.i.i47, %0
%.reg2mem.sroa.0.sroa.0.0.load14.i.reload = select i1 %cmp.i38, i32 0, i32 1
%cmp = icmp eq i32 %.mux, %.reg2mem.sroa.0.sroa.0.0.load14.i.reload
br i1 %cmp, label %if.end, label %if.then

if.then:
call void (%struct._Dnk_filet.1*, i8*, ...) @fprintf(%struct._Dnk_filet.1* @_Stdout, i8* getelementptr inbounds ([23 x i8], [23 x i8]* @.str, i32 0, i32 0), i32 %.mux, i32 %.reg2mem.sroa.0.sroa.0.0.load14.i.reload) #1
declare void @f0(%s.0* nocapture, i8* nocapture readonly, ...) #0

define void @f1() #1 {
b0:
%v0 = load i32*, i32** undef, align 4
%v1 = load i32, i32* undef, align 4
br i1 undef, label %b4, label %b1

b1: ; preds = %b0
%v2 = icmp slt i32 %v1, 0
%v3 = lshr i32 %v1, 5
%v4 = add i32 %v3, -134217728
%v5 = select i1 %v2, i32 %v4, i32 %v3
%v6 = getelementptr inbounds i32, i32* %v0, i32 %v5
%v7 = icmp ult i32* %v6, %v0
%v8 = select i1 %v7, i32 0, i32 1
br i1 undef, label %b2, label %b4

b2: ; preds = %b1
%v9 = icmp slt i32 %v1, 0
%v10 = lshr i32 %v1, 5
%v11 = add i32 %v10, -134217728
%v12 = select i1 %v9, i32 %v11, i32 %v10
%v13 = getelementptr inbounds i32, i32* %v0, i32 %v12
%v14 = icmp ult i32* %v13, %v0
%v15 = select i1 %v14, i32 0, i32 1
%v16 = icmp eq i32 %v8, %v15
br i1 %v16, label %b4, label %b3

b3: ; preds = %b2
call void (%s.0*, i8*, ...) @f0(%s.0* @g0, i8* getelementptr inbounds ([23 x i8], [23 x i8]* @g1, i32 0, i32 0), i32 %v8, i32 %v15) #0
unreachable

if.end:
br i1 undef, label %_ZNSt6vectorIbSaIbEED2Ev.exit, label %if.then.i.i.i
b4: ; preds = %b2, %b1, %b0
br i1 undef, label %b6, label %b5

if.then.i.i.i:
b5: ; preds = %b4
unreachable

_ZNSt6vectorIbSaIbEED2Ev.exit:
b6: ; preds = %b4
ret void
}

attributes #0 = { "target-cpu"="hexagonv5" }
attributes #1 = { nounwind "target-cpu"="hexagonv5" }
attributes #0 = { nounwind "target-cpu"="hexagonv5" }
attributes #1 = { "target-cpu"="hexagonv5" }
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Hexagon/newvaluejump-kill.ll
View file
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
; RUN: llc -march=hexagon -O3 -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -march=hexagon -O3 -verify-machineinstrs -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s
;
; Check that this testcase compiles successfully and that a new-value jump
; has been created.
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Hexagon/packetize-impdef-1.ll
View file
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s
; REQUIRES: asserts

; Test that the compiler doesn't assert because IMPLICIT_DEF instructions are
Expand Down
25 changes: 12 additions & 13 deletions llvm/test/CodeGen/Hexagon/peephole-kill-flags.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,22 +6,21 @@
target triple = "hexagon"

; Function Attrs: nounwind
define void @fred() #0 {
entry:
br label %for.cond
define i32 @f0(i32* %a0, i32 %a1) #0 {
b0:
br label %b1

for.cond: ; preds = %entry
%0 = load i32, i32* undef, align 4
%mul = mul nsw i32 2, %0
%cmp = icmp slt i32 undef, %mul
br i1 %cmp, label %for.body, label %for.end13
b1: ; preds = %b0
%v0 = load i32, i32* %a0, align 4
%v1 = mul nsw i32 2, %v0
%v2 = icmp slt i32 %a1, %v1
br i1 %v2, label %b2, label %b3

for.body: ; preds = %for.cond
unreachable
b2: ; preds = %b1
ret i32 0

for.end13: ; preds = %for.cond
ret void
b3: ; preds = %b1
ret i32 %v1
}

attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }

50 changes: 26 additions & 24 deletions llvm/test/CodeGen/Hexagon/postinc-offset.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,36 +6,38 @@
; CHECK-NOT: memw([[REG0]]+#0) =
; CHECK: }

define void @main() #0 {
cond.end.6:
store i32 -1, i32* undef, align 8, !tbaa !0
br label %polly.stmt.for.body.i

if.then:
define void @f0(i32* %a0) #0 {
b0:
store i32 -1, i32* %a0, align 8, !tbaa !0
br label %b4

b1: ; preds = %b3
unreachable

if.end:
b2: ; preds = %b3
ret void

polly.stmt.for.body.i24:
%0 = extractelement <2 x i32> %add.ip_vec, i32 1
br i1 undef, label %if.end, label %if.then

polly.stmt.for.body.i:
%add.ip_vec30 = phi <2 x i32> [ %add.ip_vec, %polly.stmt.for.body.i ], [ zeroinitializer, %cond.end.6 ]
%scevgep.phi = phi i32* [ %scevgep.inc, %polly.stmt.for.body.i ], [ undef, %cond.end.6 ]
%polly.indvar = phi i32 [ %polly.indvar_next, %polly.stmt.for.body.i ], [ 0, %cond.end.6 ]
%vector_ptr = bitcast i32* %scevgep.phi to <2 x i32>*
%_p_vec_full = load <2 x i32>, <2 x i32>* %vector_ptr, align 8
%add.ip_vec = add <2 x i32> %_p_vec_full, %add.ip_vec30
%polly.indvar_next = add nsw i32 %polly.indvar, 2
%polly.loop_cond = icmp slt i32 %polly.indvar, 4
%scevgep.inc = getelementptr i32, i32* %scevgep.phi, i32 2
br i1 %polly.loop_cond, label %polly.stmt.for.body.i, label %polly.stmt.for.body.i24
b3: ; preds = %b4
%v0 = extractelement <2 x i32> %v6, i32 1
br i1 undef, label %b2, label %b1

b4: ; preds = %b4, %b0
%v1 = phi <2 x i32> [ %v6, %b4 ], [ zeroinitializer, %b0 ]
%v2 = phi i32* [ %v9, %b4 ], [ %a0, %b0 ]
%v3 = phi i32 [ %v7, %b4 ], [ 0, %b0 ]
%v4 = bitcast i32* %v2 to <2 x i32>*
%v5 = load <2 x i32>, <2 x i32>* %v4, align 8
%v6 = add <2 x i32> %v5, %v1
%v7 = add nsw i32 %v3, 2
%v8 = icmp slt i32 %v3, 4
%v9 = getelementptr i32, i32* %v2, i32 2
br i1 %v8, label %b4, label %b3
}

attributes #0 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }

!0 = !{!"int", !1}
!1 = !{!"omnipotent char", !2}
!2 = !{!"Simple C/C++ TBAA"}
!0 = !{!1, !1, i64 0}
!1 = !{!"int", !2}
!2 = !{!"omnipotent char", !3}
!3 = !{!"Simple C/C++ TBAA"}
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Hexagon/rdf-extra-livein.ll
View file
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -march=hexagon -verify-machineinstrs -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s
; Verify that the code compiles successfully.
; CHECK: call printf

Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/Hexagon/redundant-branching2.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@ target triple = "hexagon-unknown--elf"
declare void @f0() #0

; Function Attrs: nounwind
define void @f1(i8* nocapture readonly %a0, i32 %a1) #0 {
define void @f1(i8* %a0, i32 %a1, i8* %a2, i32* %a3) #0 {
b0:
br i1 undef, label %b8, label %b1

Expand All @@ -28,7 +28,7 @@ b2: ; preds = %b1
br label %b3

b3: ; preds = %b6, %b2
%v3 = phi i8* [ undef, %b2 ], [ %v17, %b6 ]
%v3 = phi i8* [ %a2, %b2 ], [ %v17, %b6 ]
%v4 = phi i8* [ %v0, %b2 ], [ null, %b6 ]
%v5 = phi i32 [ 1, %b2 ], [ 0, %b6 ]
br i1 %v2, label %b4, label %b5
Expand Down Expand Up @@ -60,12 +60,12 @@ b6: ; preds = %b5, %b4
%v23 = lshr i32 %v22, 1
%v24 = add nuw nsw i32 %v23, %v19
%v25 = add nsw i32 %v24, 0
store i32 %v25, i32* null, align 4
store i32 %v25, i32* %a3, align 4
%v26 = icmp eq i32 %v5, undef
br i1 %v26, label %b7, label %b3

b7: ; preds = %b6
unreachable
ret void

b8: ; preds = %b1, %b0
ret void
Expand Down
19 changes: 5 additions & 14 deletions llvm/test/CodeGen/Hexagon/rotl-i64.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2,26 +2,17 @@
; CHECK: rol

; Function Attrs: nounwind
define fastcc void @f0() #0 {
b0:
br label %b1

b1: ; preds = %b1, %b0
br i1 undef, label %b2, label %b1

b2: ; preds = %b1
br label %b3

b3: ; preds = %b3, %b2
%v0 = load i64, i64* undef, align 8, !tbaa !0
define fastcc void @f0(i64* %a0) #0 {
b0: ; preds = %b3, %b2
%v0 = load i64, i64* %a0, align 8, !tbaa !0
%v1 = lshr i64 %v0, 8
%v2 = shl i64 %v0, 56
%v3 = or i64 %v2, %v1
%v4 = xor i64 %v3, 0
%v5 = xor i64 %v4, 0
%v6 = add i64 0, %v5
store i64 %v6, i64* undef, align 8, !tbaa !0
br label %b3
store i64 %v6, i64* %a0, align 8, !tbaa !0
ret void
}

attributes #0 = { nounwind "target-cpu"="hexagonv60" }
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/Hexagon/signed_immediates.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -83,9 +83,9 @@ define void @foo11(i64* %a, i64 %b) {
}

; s12Ext
; CHECK: if (p0.new) r0 = #-1
; CHECK: r1 = mux(p0,#-1,r0)
define i32 @foo12(i32 %a, i1 %b) {
br i1 %b, label %x, label %y
br i1 %b, label %x, label %y
x:
ret i32 -1
y:
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/Hexagon/store-widen-subreg.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -36,10 +36,10 @@
%s.27 = type { i16, i16, i32, i32, i32 }

; Function Attrs: nounwind
define hidden void @f0() local_unnamed_addr #0 {
define void @f0(i64* %a0, i1 %a1) #0 {
b0:
%v0 = load i64, i64* undef, align 8
br i1 undef, label %b1, label %b2
%v0 = load i64, i64* %a0, align 8
br i1 %a1, label %b1, label %b2

b1: ; preds = %b0
%v1 = trunc i64 %v0 to i32
Expand All @@ -50,10 +50,10 @@ b1: ; preds = %b0
store i8 1, i8* %v4, align 1
%v5 = getelementptr inbounds %s.0, %s.0* %v2, i32 0, i32 6
store i8 1, i8* %v5, align 1
unreachable
ret void

b2: ; preds = %b0
unreachable
ret void
}

attributes #0 = { nounwind }
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Hexagon/swp-carried-1.ll
View file
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
; RUN: llc -march=hexagon -rdf-opt=0 -disable-hexagon-misched < %s | FileCheck %s
; RUN: llc -march=hexagon -rdf-opt=0 -disable-hexagon-misched -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s

; Test that we generate the correct code when a loop carried value
; is scheduled one stage earlier than it's use. The code in
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Hexagon/swp-change-deps.ll
View file
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s

; Test that we generate the correct offsets for loads in the prolog
; after removing dependences on a post-increment instructions of the
Expand Down
14 changes: 4 additions & 10 deletions llvm/test/CodeGen/Hexagon/swp-check-offset.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,13 +15,13 @@
; CHECK-V65: }{{[ \t]*}}:mem_noshuf

; Function Attrs: nounwind
define void @f0() #0 {
define i32 @f0(i8** %a0) #0 {
b0:
br i1 undef, label %b1, label %b4
br label %b1

b1: ; preds = %b1, %b0
%v0 = phi i32 [ %v7, %b1 ], [ 0, %b0 ]
%v1 = getelementptr inbounds i8*, i8** undef, i32 %v0
%v1 = getelementptr inbounds i8*, i8** %a0, i32 %v0
%v2 = load i8*, i8** %v1, align 4
%v3 = bitcast i8* %v2 to i32*
store i32 0, i32* %v3, align 4
Expand All @@ -34,13 +34,7 @@ b1: ; preds = %b1, %b0
br i1 %v8, label %b2, label %b1

b2: ; preds = %b1
br i1 undef, label %b3, label %b4

b3: ; preds = %b2
unreachable

b4: ; preds = %b2, %b0
unreachable
ret i32 %v7
}

attributes #0 = { nounwind }
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Hexagon/swp-const-tc1.ll
View file
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
; RUN: llc -march=hexagon -enable-pipeliner -enable-pipeliner-opt-size \
; RUN: -verify-machineinstrs \
; RUN: -verify-machineinstrs -hexagon-initial-cfg-cleanup=0 \
; RUN: -enable-aa-sched-mi=false -hexagon-expand-condsets=0 \
; RUN: < %s | FileCheck %s

Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Hexagon/swp-dep-neg-offset.ll
View file
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
; RUN: llc -march=hexagon -enable-pipeliner < %s | FileCheck %s
; RUN: llc -march=hexagon -enable-pipeliner -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s

; Test that the code that changes the dependences does not allow
; a load with a negative offset to be overlapped with the post
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/Hexagon/swp-epilog-phi2.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -14,9 +14,9 @@
%s.11 = type { i32, i32, i8* }

; Function Attrs: nounwind
define void @f0(%s.0* %a0) #0 {
define void @f0(%s.0* %a0, i8* %a1, i16* %a2, i16** %a3, i16** %a4) #0 {
b0:
%v0 = load i8, i8* undef, align 1, !tbaa !0
%v0 = load i8, i8* %a1, align 1, !tbaa !0
%v1 = icmp eq i8 %v0, 1
br i1 %v1, label %b1, label %b2

Expand All @@ -26,7 +26,7 @@ b0:
; CHECK: }{{[ \t]*}}:endloop0

b1: ; preds = %b1, %b0
%v2 = phi i16* [ %v17, %b1 ], [ undef, %b0 ]
%v2 = phi i16* [ %v17, %b1 ], [ %a2, %b0 ]
%v3 = phi i32 [ %v18, %b1 ], [ 0, %b0 ]
%v4 = getelementptr inbounds %s.0, %s.0* %a0, i32 0, i32 25, i32 10, i32 %v3
%v5 = load i8, i8* %v4, align 1, !tbaa !0
Expand All @@ -35,16 +35,16 @@ b1: ; preds = %b1, %b0
%v8 = getelementptr inbounds %s.0, %s.0* %a0, i32 0, i32 25, i32 10, i32 %v7
%v9 = load i8, i8* %v8, align 1, !tbaa !0
%v10 = or i16 0, %v6
%v11 = load i8, i8* undef, align 1, !tbaa !0
%v11 = load i8, i8* %a1, align 1, !tbaa !0
%v12 = zext i8 %v11 to i16
%v13 = shl nuw i16 %v12, 8
%v14 = or i16 %v10, %v13
%v15 = or i16 %v14, 0
%v16 = getelementptr inbounds i16, i16* %v2, i32 1
store i16* %v16, i16** null, align 4, !tbaa !3
store i16* %v16, i16** %a3, align 4, !tbaa !3
store i16 %v15, i16* %v2, align 2, !tbaa !5
%v17 = getelementptr inbounds i16, i16* %v2, i32 2
store i16* %v17, i16** null, align 4, !tbaa !3
store i16* %v17, i16** %a4, align 4, !tbaa !3
store i16 0, i16* %v16, align 2, !tbaa !5
%v18 = add nsw i32 %v3, 8
%v19 = icmp slt i32 %v18, undef
Expand Down
13 changes: 5 additions & 8 deletions llvm/test/CodeGen/Hexagon/swp-epilog-phi4.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,16 +8,16 @@
; CHECK-NOT: r{{[0-9]+}} = r{{[0-9]+}}

; Function Attrs: nounwind
define void @f0(i32 %a0, i32* %a1, [1000 x i32]* %a2) #0 {
define void @f0(i32 %a0, i32* %a1, [1000 x i32]* %a2, i32* %a3, i32* %a4) #0 {
b0:
br i1 undef, label %b1, label %b3
br label %b1

b1: ; preds = %b1, %b0
%v0 = phi i32 [ %v8, %b1 ], [ 1, %b0 ]
%v1 = load i32, i32* null, align 4, !tbaa !0
%v1 = load i32, i32* %a3, align 4, !tbaa !0
%v2 = getelementptr inbounds i32, i32* %a1, i32 %v0
%v3 = load i32, i32* %v2, align 4, !tbaa !0
%v4 = load i32, i32* undef, align 4, !tbaa !0
%v4 = load i32, i32* %a4, align 4, !tbaa !0
%v5 = mul nsw i32 %v4, %v3
%v6 = add nsw i32 %v5, %v1
%v7 = getelementptr inbounds [1000 x i32], [1000 x i32]* %a2, i32 %v0, i32 0
Expand All @@ -26,10 +26,7 @@ b1: ; preds = %b1, %b0
%v9 = icmp eq i32 %v8, %a0
br i1 %v9, label %b2, label %b1

b2: ; preds = %b1
unreachable

b3: ; preds = %b0
b2: ; preds = %b0
ret void
}

Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Hexagon/swp-epilog-phi6.ll
View file
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
; RUN: llc -march=hexagon -O2 -debug-only=pipeliner < %s -o - 2>&1 > /dev/null | FileCheck %s
; RUN: llc -march=hexagon -O2 -debug-only=pipeliner -hexagon-initial-cfg-cleanup=0 < %s -o - 2>&1 > /dev/null | FileCheck %s
; REQUIRES: asserts

; Test that the phi in the first epilog block is getter the correct
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Hexagon/swp-epilog-phi8.ll
View file
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
; RUN: llc -march=hexagon -mno-pairing -mno-compound < %s | FileCheck %s
; RUN: llc -march=hexagon -mno-pairing -mno-compound -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s

; Test that we generate the correct phi names in the epilog when the pipeliner
; schedules a phi and it's loop definition in different stages, e.g., a phi is
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Hexagon/swp-epilog-phi9.ll
View file
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s

; Test that we generate the correct Phi name in the last couple of epilog
; blocks, when there are 3 epilog blocks. The Phi was scheduled in stage
Expand Down
3 changes: 2 additions & 1 deletion llvm/test/CodeGen/Hexagon/swp-epilog-phis.ll
View file
Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
; RUN: llc -march=hexagon -enable-pipeliner -pipeliner-max-stages=2 \
; RUN: -pipeliner-ignore-recmii -disable-hexagon-nv-schedule -stats -o /dev/null\
; RUN: -pipeliner-ignore-recmii -disable-hexagon-nv-schedule \
; RUN: -hexagon-initial-cfg-cleanup=0 -stats -o /dev/null \
; RUN: -enable-aa-sched-mi < %s 2>&1 | FileCheck %s --check-prefix=STATS
; REQUIRES: asserts
;
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Hexagon/swp-kernel-phi1.ll
View file
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
; RUN: llc -march=hexagon -enable-pipeliner-opt-size < %s | FileCheck %s
; RUN: llc -march=hexagon -enable-pipeliner-opt-size -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s

; Test that we generate the correct names for the phis in the kernel for the
; incoming values. In this case, the loop contains a phi and has another phi
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Hexagon/swp-loop-carried-unknown.ll
View file
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s

; Test that the pipeliner schedules a store before the load in which there is a
; loop carried dependence. Previously, the loop carried dependence wasn't added
Expand Down
7 changes: 4 additions & 3 deletions llvm/test/CodeGen/Hexagon/swp-lots-deps.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@
; STATS: 1 pipeliner - Number of loops software pipelined

; Function Attrs: nounwind
define void @f0(i32 %a0) #0 {
define i64 @f0(i32 %a0, i32* %a1) #0 {
b0:
%v0 = icmp slt i32 %a0, 123469
br i1 %v0, label %b1, label %b4
Expand All @@ -21,7 +21,7 @@ b2: ; preds = %b2, %b1
%v6 = phi i64 [ undef, %b1 ], [ %v11, %b2 ]
%v7 = tail call i64 @llvm.hexagon.M2.vdmacs.s0(i64 %v5, i64 %v6, i64 %v6)
%v8 = tail call i64 @llvm.hexagon.S2.packhl(i32 undef, i32 %v4)
%v9 = load i32, i32* undef, align 4, !tbaa !0
%v9 = load i32, i32* %a1, align 4, !tbaa !0
%v10 = tail call i64 @llvm.hexagon.M2.vdmacs.s0(i64 %v2, i64 %v6, i64 %v8)
%v11 = tail call i64 @llvm.hexagon.S2.packhl(i32 %v9, i32 undef)
%v12 = tail call i64 @llvm.hexagon.M2.vdmacs.s0(i64 %v1, i64 %v6, i64 %v11)
Expand All @@ -36,7 +36,8 @@ b3: ; preds = %b2
b4: ; preds = %b3, %b0
%v16 = phi i64 [ %v10, %b3 ], [ undef, %b0 ]
%v17 = phi i64 [ %v7, %b3 ], [ undef, %b0 ]
unreachable
%v18 = add i64 %v16, %v17
ret i64 %v18
}

; Function Attrs: nounwind readnone
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Hexagon/swp-phi-dep.ll
View file
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
; RUN: llc -march=hexagon -enable-pipeliner -pipeliner-max-stages=2 < %s | FileCheck %s
; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 -enable-pipeliner -pipeliner-max-stages=2 < %s | FileCheck %s

; Check that the pipelined code uses the proper address in the
; prolog and the kernel. The bug occurs when the address computation
Expand Down
14 changes: 7 additions & 7 deletions llvm/test/CodeGen/Hexagon/swp-reuse-phi-6.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,20 +13,20 @@
; CHECK: }{{[ \t]*}}:endloop0

; Function Attrs: nounwind
define void @f0(i32 %a0, i32 %a1) local_unnamed_addr #0 {
define void @f0(i32 %a0, i32 %a1, i8* %a2, <16 x i32>* %a3) #0 {
b0:
%v0 = shl nsw i32 %a0, 1
%v1 = sub i32 0, %v0
%v2 = sub i32 0, %a0
%v3 = getelementptr inbounds i8, i8* undef, i32 %v1
%v4 = getelementptr inbounds i8, i8* undef, i32 %v2
%v5 = getelementptr inbounds i8, i8* undef, i32 %a0
%v6 = getelementptr inbounds i8, i8* undef, i32 %v0
%v3 = getelementptr inbounds i8, i8* %a2, i32 %v1
%v4 = getelementptr inbounds i8, i8* %a2, i32 %v2
%v5 = getelementptr inbounds i8, i8* %a2, i32 %a0
%v6 = getelementptr inbounds i8, i8* %a2, i32 %v0
%v7 = getelementptr inbounds i8, i8* %v6, i32 64
%v8 = bitcast i8* %v7 to <16 x i32>*
%v9 = getelementptr inbounds i8, i8* %v5, i32 64
%v10 = bitcast i8* %v9 to <16 x i32>*
%v11 = getelementptr inbounds i8, i8* undef, i32 64
%v11 = getelementptr inbounds i8, i8* %a2, i32 64
%v12 = bitcast i8* %v11 to <16 x i32>*
%v13 = getelementptr inbounds i8, i8* %v4, i32 64
%v14 = bitcast i8* %v13 to <16 x i32>*
Expand All @@ -35,7 +35,7 @@ b0:
br label %b1

b1: ; preds = %b1, %b0
%v17 = phi <16 x i32>* [ %v59, %b1 ], [ undef, %b0 ]
%v17 = phi <16 x i32>* [ %v59, %b1 ], [ %a3, %b0 ]
%v18 = phi <16 x i32>* [ %v34, %b1 ], [ %v8, %b0 ]
%v19 = phi <16 x i32>* [ %v32, %b1 ], [ %v10, %b0 ]
%v20 = phi <16 x i32>* [ %v30, %b1 ], [ %v12, %b0 ]
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Hexagon/swp-tfri.ll
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Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
; RUN: llc -march=hexagon -enable-pipeliner -stats -o /dev/null < %s 2>&1 | FileCheck %s --check-prefix=STATS
; RUN: llc -march=hexagon -enable-pipeliner -hexagon-initial-cfg-cleanup=0 -stats -o /dev/null < %s 2>&1 | FileCheck %s --check-prefix=STATS
; REQUIRES: asserts

; Check that we handle the case when a value is first defined in the loop.
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Hexagon/tail-dup-subreg-map.ll
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Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s
; REQUIRES: asserts

; When tail-duplicating a block with PHI nodes that use subregisters, the
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Hexagon/tfr-mux-nvj.ll
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Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
; RUN: llc -march=hexagon -O2 -hexagon-expand-condsets=0 < %s | FileCheck %s
; RUN: llc -march=hexagon -O2 -hexagon-expand-condsets=0 -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s

; CHECK: mux
; CHECK: cmp{{.*\.new}}
Expand Down
83 changes: 42 additions & 41 deletions llvm/test/CodeGen/Hexagon/v60-cur.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -4,44 +4,45 @@

; CHECK: v{{[0-9]*}}.cur

define void @conv3x3_i(i8* noalias nocapture readonly %iptr0, i32 %shift, i32 %width) #0 {
entry:
br i1 undef, label %for.body.lr.ph, label %for.end

for.body.lr.ph:
br label %for.body

for.body:
%iptr0.pn = phi i8* [ %iptr0, %for.body.lr.ph ], [ %iptr0.addr.0121, %for.body ]
%j.0115 = phi i32 [ 0, %for.body.lr.ph ], [ %add, %for.body ]
%sline000.0114 = phi <16 x i32> [ zeroinitializer, %for.body.lr.ph ], [ %1, %for.body ]
%sline100.0113 = phi <16 x i32> [ zeroinitializer, %for.body.lr.ph ], [ zeroinitializer, %for.body ]
%iptr0.addr.0121 = getelementptr inbounds i8, i8* %iptr0.pn, i32 64
%0 = bitcast i8* %iptr0.addr.0121 to <16 x i32>*
%1 = load <16 x i32>, <16 x i32>* %0, align 64, !tbaa !1
%2 = load <16 x i32>, <16 x i32>* null, align 64, !tbaa !1
%3 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %1, <16 x i32> %sline000.0114, i32 4)
%4 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> zeroinitializer, <16 x i32> %sline100.0113, i32 4)
%5 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %2, <16 x i32> zeroinitializer, i32 4)
%6 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %3, <16 x i32> %sline000.0114)
%7 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %5, <16 x i32> zeroinitializer)
%8 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32> %6, i32 0, i32 0)
%9 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %8, <32 x i32> zeroinitializer, i32 undef, i32 0)
%10 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %9, <32 x i32> undef, i32 undef, i32 0)
%11 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %10)
%12 = tail call <16 x i32> @llvm.hexagon.V6.vasrwh(<16 x i32> %11, <16 x i32> undef, i32 %shift)
%13 = tail call <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32> undef, <16 x i32> %12)
store <16 x i32> %13, <16 x i32>* undef, align 64, !tbaa !1
%14 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> zeroinitializer, <32 x i32> %7, i32 undef, i32 1)
%15 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %14)
%16 = tail call <16 x i32> @llvm.hexagon.V6.vasrwh(<16 x i32> %15, <16 x i32> undef, i32 %shift)
%17 = tail call <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32> %16, <16 x i32> undef)
store <16 x i32> %17, <16 x i32>* undef, align 64, !tbaa !1
%add = add nsw i32 %j.0115, 64
%cmp = icmp slt i32 %add, %width
br i1 %cmp, label %for.body, label %for.end

for.end:
; Function Attrs: nounwind
define void @f0(i8* noalias nocapture readonly %a0, i32 %a1, i32 %a2, <16 x i32>* %a3, <16 x i32>* %a4) #0 {
b0:
br i1 undef, label %b1, label %b3

b1: ; preds = %b0
br label %b2

b2: ; preds = %b2, %b1
%v0 = phi i8* [ %a0, %b1 ], [ %v4, %b2 ]
%v1 = phi i32 [ 0, %b1 ], [ %v23, %b2 ]
%v2 = phi <16 x i32> [ zeroinitializer, %b1 ], [ %v6, %b2 ]
%v3 = phi <16 x i32> [ zeroinitializer, %b1 ], [ zeroinitializer, %b2 ]
%v4 = getelementptr inbounds i8, i8* %v0, i32 64
%v5 = bitcast i8* %v4 to <16 x i32>*
%v6 = load <16 x i32>, <16 x i32>* %v5, align 64, !tbaa !0
%v7 = load <16 x i32>, <16 x i32>* %a3, align 64, !tbaa !0
%v8 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v6, <16 x i32> %v2, i32 4)
%v9 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> zeroinitializer, <16 x i32> %v3, i32 4)
%v10 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v7, <16 x i32> zeroinitializer, i32 4)
%v11 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v8, <16 x i32> %v2)
%v12 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v10, <16 x i32> zeroinitializer)
%v13 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32> %v11, i32 0, i32 0)
%v14 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v13, <32 x i32> zeroinitializer, i32 undef, i32 0)
%v15 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v14, <32 x i32> undef, i32 undef, i32 0)
%v16 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v15)
%v17 = tail call <16 x i32> @llvm.hexagon.V6.vasrwh(<16 x i32> %v16, <16 x i32> undef, i32 %a1)
%v18 = tail call <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32> undef, <16 x i32> %v17)
store <16 x i32> %v18, <16 x i32>* %a3, align 64, !tbaa !0
%v19 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> zeroinitializer, <32 x i32> %v12, i32 undef, i32 1)
%v20 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v19)
%v21 = tail call <16 x i32> @llvm.hexagon.V6.vasrwh(<16 x i32> %v20, <16 x i32> undef, i32 %a1)
%v22 = tail call <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32> %v21, <16 x i32> undef)
store <16 x i32> %v22, <16 x i32>* %a4, align 64, !tbaa !0
%v23 = add nsw i32 %v1, 64
%v24 = icmp slt i32 %v23, %a2
br i1 %v24, label %b2, label %b3

b3: ; preds = %b2, %b0
ret void
}

Expand All @@ -56,6 +57,6 @@ declare <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32>, <16 x i32>) #1
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
attributes #1 = { nounwind readnone }

!1 = !{!2, !2, i64 0}
!2 = !{!"omnipotent char", !3, i64 0}
!3 = !{!"Simple C/C++ TBAA"}
!0 = !{!1, !1, i64 0}
!1 = !{!"omnipotent char", !2, i64 0}
!2 = !{!"Simple C/C++ TBAA"}
26 changes: 4 additions & 22 deletions llvm/test/CodeGen/Hexagon/v60-halide-vcombinei8.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,33 +6,15 @@
target triple = "hexagon-unknown--elf"

; Function Attrs: norecurse nounwind
define void @f0() #0 {
b0:
br i1 undef, label %b6, label %b1

b1: ; preds = %b0
br i1 undef, label %b2, label %b6, !prof !1

b2: ; preds = %b1
br label %b3

b3: ; preds = %b5, %b2
br i1 undef, label %b4, label %b5, !prof !1

b4: ; preds = %b3
%v0 = load <64 x i8>, <64 x i8>* undef, align 1
define void @f0(<64 x i8>* %a0) #0 {
b0: ; preds = %b3
%v0 = load <64 x i8>, <64 x i8>* %a0, align 1
%v1 = shufflevector <64 x i8> %v0, <64 x i8> undef, <128 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63, i32 64, i32 65, i32 66, i32 67, i32 68, i32 69, i32 70, i32 71, i32 72, i32 73, i32 74, i32 75, i32 76, i32 77, i32 78, i32 79, i32 80, i32 81, i32 82, i32 83, i32 84, i32 85, i32 86, i32 87, i32 88, i32 89, i32 90, i32 91, i32 92, i32 93, i32 94, i32 95, i32 96, i32 97, i32 98, i32 99, i32 100, i32 101, i32 102, i32 103, i32 104, i32 105, i32 106, i32 107, i32 108, i32 109, i32 110, i32 111, i32 112, i32 113, i32 114, i32 115, i32 116, i32 117, i32 118, i32 119, i32 120, i32 121, i32 122, i32 123, i32 124, i32 125, i32 126, i32 127>
%v2 = bitcast <128 x i8> %v1 to <32 x i32>
%v3 = tail call <32 x i32> @llvm.hexagon.V6.vaddb.dv(<32 x i32> undef, <32 x i32> %v2)
%v4 = bitcast <32 x i32> %v3 to <128 x i8>
%v5 = shufflevector <128 x i8> %v4, <128 x i8> undef, <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63>
store <64 x i8> %v5, <64 x i8>* undef, align 1, !tbaa !2
br label %b5

b5: ; preds = %b4, %b3
br i1 undef, label %b6, label %b3

b6: ; preds = %b5, %b1, %b0
store <64 x i8> %v5, <64 x i8>* %a0, align 1, !tbaa !2
ret void
}

Expand Down
59 changes: 29 additions & 30 deletions llvm/test/CodeGen/Hexagon/vassign-to-combine.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,41 +16,40 @@ declare <64 x i32> @llvm.hexagon.V6.vadduhsat.dv.128B(<64 x i32>, <64 x i32>) #0
declare <64 x i32> @llvm.hexagon.V6.vaddubh.128B(<32 x i32>, <32 x i32>) #0
declare <64 x i32> @llvm.hexagon.V6.vmpyub.128B(<32 x i32>, i32) #0

define void @foo() local_unnamed_addr #1 {
entry:
%0 = load <32 x i32>, <32 x i32>* undef, align 128
%1 = load <32 x i32>, <32 x i32>* null, align 128
define void @f0(<32 x i32>* %a0, <32 x i32>* %a1) local_unnamed_addr #1 {
b0:
%v0 = load <32 x i32>, <32 x i32>* %a0, align 128
%v1 = load <32 x i32>, <32 x i32>* %a1, align 128
br i1 undef, label %b2, label %b1

b1: ; preds = %entry
%2 = tail call <32 x i32> @llvm.hexagon.V6.vlalignbi.128B(<32 x i32> %0, <32 x i32> %1, i32 1)
%3 = tail call <64 x i32> @llvm.hexagon.V6.vmpyub.128B(<32 x i32> %2, i32 33686018) #1
%4 = tail call <64 x i32> @llvm.hexagon.V6.vadduhsat.dv.128B(<64 x i32> undef, <64 x i32> %3) #1
%5 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %4)
%6 = tail call <32 x i32> @llvm.hexagon.V6.vabsdiffuh.128B(<32 x i32> %5, <32 x i32> undef) #1
%7 = tail call <64 x i32> @llvm.hexagon.V6.vaddubh.128B(<32 x i32> %6, <32 x i32> undef)
%8 = tail call <64 x i32> @llvm.hexagon.V6.vaddh.dv.128B(<64 x i32> undef, <64 x i32> %7) #1
%9 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %8) #1
%10 = tail call <32 x i32> @llvm.hexagon.V6.vsathub.128B(<32 x i32> %9, <32 x i32> undef) #1
store <32 x i32> %10, <32 x i32>* undef, align 128
b1: ; preds = %b0
%v2 = tail call <32 x i32> @llvm.hexagon.V6.vlalignbi.128B(<32 x i32> %v0, <32 x i32> %v1, i32 1)
%v3 = tail call <64 x i32> @llvm.hexagon.V6.vmpyub.128B(<32 x i32> %v2, i32 33686018) #1
%v4 = tail call <64 x i32> @llvm.hexagon.V6.vadduhsat.dv.128B(<64 x i32> undef, <64 x i32> %v3) #1
%v5 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v4)
%v6 = tail call <32 x i32> @llvm.hexagon.V6.vabsdiffuh.128B(<32 x i32> %v5, <32 x i32> undef) #1
%v7 = tail call <64 x i32> @llvm.hexagon.V6.vaddubh.128B(<32 x i32> %v6, <32 x i32> undef)
%v8 = tail call <64 x i32> @llvm.hexagon.V6.vaddh.dv.128B(<64 x i32> undef, <64 x i32> %v7) #1
%v9 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v8) #1
%v10 = tail call <32 x i32> @llvm.hexagon.V6.vsathub.128B(<32 x i32> %v9, <32 x i32> undef) #1
store <32 x i32> %v10, <32 x i32>* %a0, align 128
br label %b2

b2: ; preds = %b1, %entry
%c2.host31.sroa.3.2.unr.ph = phi <32 x i32> [ zeroinitializer, %b1 ], [ %0, %entry ]
%c2.host31.sroa.0.2.unr.ph = phi <32 x i32> [ %0, %b1 ], [ %1, %entry ]
%11 = tail call <32 x i32> @llvm.hexagon.V6.vlalignbi.128B(<32 x i32> %c2.host31.sroa.3.2.unr.ph, <32 x i32> %c2.host31.sroa.0.2.unr.ph, i32 1)
%12 = tail call <64 x i32> @llvm.hexagon.V6.vmpyub.128B(<32 x i32> %11, i32 33686018) #1
%13 = tail call <64 x i32> @llvm.hexagon.V6.vadduhsat.dv.128B(<64 x i32> undef, <64 x i32> %12) #1
%14 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %13)
%15 = tail call <32 x i32> @llvm.hexagon.V6.vabsdiffuh.128B(<32 x i32> %14, <32 x i32> undef) #1
%16 = tail call <64 x i32> @llvm.hexagon.V6.vaddubh.128B(<32 x i32> %15, <32 x i32> undef)
%17 = tail call <64 x i32> @llvm.hexagon.V6.vaddh.dv.128B(<64 x i32> undef, <64 x i32> %16) #1
%18 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %17) #1
%19 = tail call <32 x i32> @llvm.hexagon.V6.vsathub.128B(<32 x i32> %18, <32 x i32> undef) #1
store <32 x i32> %19, <32 x i32>* undef, align 128
b2: ; preds = %b1, %b0
%v11 = phi <32 x i32> [ zeroinitializer, %b1 ], [ %v0, %b0 ]
%v12 = phi <32 x i32> [ %v0, %b1 ], [ %v1, %b0 ]
%v13 = tail call <32 x i32> @llvm.hexagon.V6.vlalignbi.128B(<32 x i32> %v11, <32 x i32> %v12, i32 1)
%v14 = tail call <64 x i32> @llvm.hexagon.V6.vmpyub.128B(<32 x i32> %v13, i32 33686018) #1
%v15 = tail call <64 x i32> @llvm.hexagon.V6.vadduhsat.dv.128B(<64 x i32> undef, <64 x i32> %v14) #1
%v16 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v15)
%v17 = tail call <32 x i32> @llvm.hexagon.V6.vabsdiffuh.128B(<32 x i32> %v16, <32 x i32> undef) #1
%v18 = tail call <64 x i32> @llvm.hexagon.V6.vaddubh.128B(<32 x i32> %v17, <32 x i32> undef)
%v19 = tail call <64 x i32> @llvm.hexagon.V6.vaddh.dv.128B(<64 x i32> undef, <64 x i32> %v18) #1
%v20 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v19) #1
%v21 = tail call <32 x i32> @llvm.hexagon.V6.vsathub.128B(<32 x i32> %v20, <32 x i32> undef) #1
store <32 x i32> %v21, <32 x i32>* %a1, align 128
ret void
}

attributes #0 = { nounwind readnone }
attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }

attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/Hexagon/vect/vect-bool-isel-crash.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
target triple = "hexagon"

define void @fred() #0 {
define void @fred(i32* %a0, i8* %a1) #0 {
b0:
%v1 = icmp sgt <8 x i32> undef, undef
%v2 = extractelement <8 x i1> %v1, i32 4
Expand All @@ -18,13 +18,13 @@ b0:
%v8 = add nsw i32 %v7, %v5
%v9 = add nsw i32 0, %v8
%v10 = add nsw i32 0, %v9
%v11 = load i32, i32* undef, align 4
%v11 = load i32, i32* %a0, align 4
%v12 = mul nsw i32 %v11, %v10
%v13 = add nsw i32 %v12, 16384
%v14 = ashr i32 %v13, 15
%v15 = select i1 undef, i32 %v14, i32 255
%v16 = trunc i32 %v15 to i8
store i8 %v16, i8* undef, align 1
store i8 %v16, i8* %a1, align 1
ret void
}

Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/Hexagon/vect/zext-v4i1.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
target triple = "hexagon"

define void @fred(<8 x i16>* %a0) #0 {
define i32 @fred(<8 x i16>* %a0) #0 {
b0:
switch i32 undef, label %b14 [
i32 5, label %b2
Expand All @@ -31,10 +31,10 @@ b2: ; preds = %b0
br i1 %v12, label %b14, label %b13

b13: ; preds = %b2
unreachable
ret i32 1

b14: ; preds = %b2, %b1, %b0
ret void
ret i32 0
}

attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-length64b,+hvxv60" }
62 changes: 28 additions & 34 deletions llvm/test/CodeGen/Hexagon/vload-postinc-sel.ll
View file
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s
; CHECK: = vmem(r{{[0-9]+}}++#1)

target triple = "hexagon-unknown--elf"
Expand All @@ -11,39 +11,33 @@ declare <64 x i32> @llvm.hexagon.V6.vaddh.dv.128B(<64 x i32>, <64 x i32>) #0
declare <64 x i32> @llvm.hexagon.V6.vadduhsat.dv.128B(<64 x i32>, <64 x i32>) #0
declare <32 x i32> @llvm.hexagon.V6.vabsdiffuh.128B(<32 x i32>, <32 x i32>) #0

define void @fred() #1 {
entry:
br i1 undef, label %b1, label %call_destructor.exit

b1: ; preds = %entry
br label %b2

b2: ; preds = %b1, %b2
%c2.host32.sroa.3.0 = phi <128 x i8> [ %5, %b2 ], [ undef, %b1 ]
%sobel_halide.s0.x.x = phi i32 [ %17, %b2 ], [ 0, %b1 ]
%0 = add nsw i32 %sobel_halide.s0.x.x, undef
%1 = shl i32 %0, 7
%2 = add nsw i32 %1, 128
%3 = getelementptr inbounds i8, i8* undef, i32 %2
%4 = bitcast i8* %3 to <128 x i8>*
%5 = load <128 x i8>, <128 x i8>* %4, align 128
%6 = bitcast <128 x i8> %c2.host32.sroa.3.0 to <32 x i32>
%7 = tail call <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32> undef, <32 x i32> %6, i32 1)
%8 = tail call <64 x i32> @llvm.hexagon.V6.vzb.128B(<32 x i32> %7) #1
%9 = tail call <64 x i32> @llvm.hexagon.V6.vadduhsat.dv.128B(<64 x i32> undef, <64 x i32> %8) #1
%10 = tail call <64 x i32> @llvm.hexagon.V6.vadduhsat.dv.128B(<64 x i32> %9, <64 x i32> undef) #1
%11 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %10)
%12 = tail call <32 x i32> @llvm.hexagon.V6.vabsdiffuh.128B(<32 x i32> undef, <32 x i32> %11) #1
%13 = tail call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> %12, <32 x i32> undef)
%14 = tail call <64 x i32> @llvm.hexagon.V6.vaddh.dv.128B(<64 x i32> undef, <64 x i32> %13) #1
%15 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %14) #1
%16 = tail call <32 x i32> @llvm.hexagon.V6.vsathub.128B(<32 x i32> %15, <32 x i32> undef) #1
store <32 x i32> %16, <32 x i32>* undef, align 128
%17 = add nuw nsw i32 %sobel_halide.s0.x.x, 1
br label %b2

call_destructor.exit: ; preds = %entry
ret void
define void @f0(i8* %a0, <32 x i32>* %a1) #1 {
b0:
br label %b1

b1: ; preds = %b2, %b1
%v0 = phi <128 x i8> [ %v7, %b1 ], [ undef, %b0 ]
%v1 = phi i32 [ %v19, %b1 ], [ 0, %b0 ]
%v2 = add nsw i32 %v1, undef
%v3 = shl i32 %v2, 7
%v4 = add nsw i32 %v3, 128
%v5 = getelementptr inbounds i8, i8* %a0, i32 %v4
%v6 = bitcast i8* %v5 to <128 x i8>*
%v7 = load <128 x i8>, <128 x i8>* %v6, align 128
%v8 = bitcast <128 x i8> %v0 to <32 x i32>
%v9 = tail call <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32> undef, <32 x i32> %v8, i32 1)
%v10 = tail call <64 x i32> @llvm.hexagon.V6.vzb.128B(<32 x i32> %v9) #1
%v11 = tail call <64 x i32> @llvm.hexagon.V6.vadduhsat.dv.128B(<64 x i32> undef, <64 x i32> %v10) #1
%v12 = tail call <64 x i32> @llvm.hexagon.V6.vadduhsat.dv.128B(<64 x i32> %v11, <64 x i32> undef) #1
%v13 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v12)
%v14 = tail call <32 x i32> @llvm.hexagon.V6.vabsdiffuh.128B(<32 x i32> undef, <32 x i32> %v13) #1
%v15 = tail call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> %v14, <32 x i32> undef)
%v16 = tail call <64 x i32> @llvm.hexagon.V6.vaddh.dv.128B(<64 x i32> undef, <64 x i32> %v15) #1
%v17 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v16) #1
%v18 = tail call <32 x i32> @llvm.hexagon.V6.vsathub.128B(<32 x i32> %v17, <32 x i32> undef) #1
store <32 x i32> %v18, <32 x i32>* %a1, align 128
%v19 = add nuw nsw i32 %v1, 1
br label %b1
}

declare <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32>, <32 x i32>, i32) #0
Expand Down