2 changes: 1 addition & 1 deletion llvm/docs/AMDGPU/gfx7_data_mimg_atomic_cmp.rst
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Expand Up @@ -21,7 +21,7 @@ Optionally may serve as an output data:
* :ref:`dmask<amdgpu_synid_dmask>` may specify 2 data elements for 32-bit-per-pixel surfaces or 4 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.

Note. The surface data format is indicated in the image resource constant but not in the instruction.
Note: the surface data format is indicated in the image resource constant but not in the instruction.


*Operands:* :ref:`v<amdgpu_synid_v>`
2 changes: 1 addition & 1 deletion llvm/docs/AMDGPU/gfx7_data_mimg_atomic_reg.rst
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Expand Up @@ -21,6 +21,6 @@ Optionally may serve as an output data:
* :ref:`dmask<amdgpu_synid_dmask>` may specify 1 data element for 32-bit-per-pixel surfaces or 2 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.

Note. The surface data format is indicated in the image resource constant but not in the instruction.
Note: the surface data format is indicated in the image resource constant but not in the instruction.

*Operands:* :ref:`v<amdgpu_synid_v>`
3 changes: 2 additions & 1 deletion llvm/docs/AMDGPU/gfx7_fimm32.rst
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Expand Up @@ -10,5 +10,6 @@
imm32
===========================

An :ref:`integer_number<amdgpu_synid_integer_number>` or a :ref:`floating-point_number<amdgpu_synid_floating-point_number>`. The value is converted to *f32* as described :ref:`here<amdgpu_synid_lit_conv>`.
A :ref:`floating-point_number<amdgpu_synid_floating-point_number>`, an :ref:`integer_number<amdgpu_synid_integer_number>`, or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`.
The value is converted to *f32* as described :ref:`here<amdgpu_synid_fp_conv>`.

35 changes: 24 additions & 11 deletions llvm/docs/AMDGPU/gfx7_hwreg.rst
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Expand Up @@ -14,26 +14,30 @@ Bits of a hardware register being accessed.

The bits of this operand have the following meaning:

============ ===================================
Bits Description
============ ===================================
5:0 Register *id*.
10:6 First bit *offset* (0..31).
15:11 *Size* in bits (1..32).
============ ===================================
======= ===================== ============
Bits Description Value Range
======= ===================== ============
5:0 Register *id*. 0..63
10:6 First bit *offset*. 0..31
15:11 *Size* in bits. 1..32
======= ===================== ============

This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or using the syntax described below.
This operand may be specified as one of the following:

* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF.
* An *hwreg* value described below.

==================================== ============================================================================
Syntax Description
Hwreg Value Syntax Description
==================================== ============================================================================
hwreg({0..63}) All bits of a register indicated by its *id*.
hwreg(<*name*>) All bits of a register indicated by its *name*.
hwreg({0..63}, {0..31}, {1..32}) Register bits indicated by register *id*, first bit *offset* and *size*.
hwreg(<*name*>, {0..31}, {1..32}) Register bits indicated by register *name*, first bit *offset* and *size*.
==================================== ============================================================================

Register *id*, *offset* and *size* must be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`.
Numeric values may be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`
or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.

Defined register *names* include:

Expand All @@ -53,7 +57,16 @@ Examples:

.. parsed-literal::
s_getreg_b32 s2, 0x6
reg = 1
offset = 2
size = 4
hwreg_enc = reg | (offset << 6) | ((size - 1) << 11)
s_getreg_b32 s2, 0x1881
s_getreg_b32 s2, hwreg_enc // the same as above
s_getreg_b32 s2, hwreg(1, 2, 4) // the same as above
s_getreg_b32 s2, hwreg(reg, offset, size) // the same as above
s_getreg_b32 s2, hwreg(15)
s_getreg_b32 s2, hwreg(51, 1, 31)
s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1)
Expand Down
21 changes: 14 additions & 7 deletions llvm/docs/AMDGPU/gfx7_label.rst
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Expand Up @@ -12,19 +12,26 @@ label

A branch target which is a 16-bit signed integer treated as a PC-relative dword offset.

This operand may be specified as:
This operand may be specified as one of the following:

* An :ref:`integer_number<amdgpu_synid_integer_number>`. The number is truncated to 16 bits.
* An :ref:`absolute_expression<amdgpu_synid_absolute_expression>` which must start with an :ref:`integer_number<amdgpu_synid_integer_number>`. The value of the expression is truncated to 16 bits.
* A :ref:`symbol<amdgpu_synid_symbol>` (for example, a label). The value is handled as a 16-bit PC-relative dword offset to be resolved by a linker.
* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.
* A :ref:`symbol<amdgpu_synid_symbol>` (for example, a label) representing a relocatable address in the same compilation unit where it is referred from. The value is handled as a 16-bit PC-relative dword offset to be resolved by a linker.

Examples:

.. parsed-literal::
offset = 30
s_branch loop_end
s_branch 2 + offset
label_1:
label_2 = . + 4
s_branch 32
loop_end:
s_branch offset + 2
s_branch label_1
s_branch label_2
s_branch label_3
s_branch label_4
label_3 = label_2 + 4
label_4:
62 changes: 42 additions & 20 deletions llvm/docs/AMDGPU/gfx7_msg.rst
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Expand Up @@ -12,32 +12,38 @@ msg

A 16-bit message code. The bits of this operand have the following meaning:

============ ======================================================
Bits Description
============ ======================================================
3:0 Message *type*.
6:4 Optional *operation*.
9:7 Optional *parameters*.
15:10 Unused.
============ ======================================================

This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or using the syntax described below:

======================================== ========================================================================
Syntax Description
======================================== ========================================================================
sendmsg(<*type*>) A message identified by its *type*.
sendmsg(<*type*>, <*op*>) A message identified by its *type* and *operation*.
sendmsg(<*type*>, <*op*>, <*stream*>) A message identified by its *type* and *operation* with a stream *id*.
======================================== ========================================================================
============ =============================== ===============
Bits Description Value Range
============ =============================== ===============
3:0 Message *type*. 0..15
6:4 Optional *operation*. 0..7
7:7 Unused. \-
9:8 Optional *stream*. 0..3
15:10 Unused. \-
============ =============================== ===============

This operand may be specified as one of the following:

* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF.
* A *sendmsg* value described below.

==================================== ====================================================
Sendmsg Value Syntax Description
==================================== ====================================================
sendmsg(<*type*>) A message identified by its *type*.
sendmsg(<*type*>,<*op*>) A message identified by its *type* and *operation*.
sendmsg(<*type*>,<*op*>,<*stream*>) A message identified by its *type* and *operation*
with a stream *id*.
==================================== ====================================================

*Type* may be specified using message *name* or message *id*.

*Op* may be specified using operation *name* or operation *id*.

Stream *id* is an integer in the range 0..3.

Message *id*, operation *id* and stream *id* must be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`.
Numeric values may be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`
or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.

Each message type supports specific operations:

Expand All @@ -58,15 +64,31 @@ Each message type supports specific operations:
\ SYSMSG_OP_TTRACE_PC 4 \-
================= ========== ============================== ============ ==========

*Sendmsg* arguments are validated depending on how *type* value is specified:

* If message *type* is specified by name, arguments values must satisfy limitations detailed in the table above.
* If message *type* is specified as a number, each argument must not exceed corresponding value range (see the first table).

Examples:

.. parsed-literal::
// numeric message code
msg = 0x10
s_sendmsg 0x12
s_sendmsg msg + 2
// sendmsg with strict arguments validation
s_sendmsg sendmsg(MSG_INTERRUPT)
s_sendmsg sendmsg(2, GS_OP_CUT)
s_sendmsg sendmsg(MSG_GS, GS_OP_EMIT)
s_sendmsg sendmsg(MSG_GS, 2)
s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_EMIT_CUT, 1)
s_sendmsg sendmsg(MSG_SYSMSG, SYSMSG_OP_TTRACE_PC)
// sendmsg with validation of value range only
msg = 2
op = 3
stream = 1
s_sendmsg sendmsg(msg, op, stream)
s_sendmsg sendmsg(2, GS_OP_CUT)
2 changes: 1 addition & 1 deletion llvm/docs/AMDGPU/gfx7_simm16.rst
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Expand Up @@ -10,5 +10,5 @@
imm16
===========================

An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 16 bits and then sign-extended to 32 bits.
An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.

2 changes: 1 addition & 1 deletion llvm/docs/AMDGPU/gfx7_uimm16.rst
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Expand Up @@ -10,5 +10,5 @@
imm16
===========================

An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 16 bits and then zero-extended to 32 bits.
An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..65535.

46 changes: 28 additions & 18 deletions llvm/docs/AMDGPU/gfx7_waitcnt.rst
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Expand Up @@ -14,29 +14,31 @@ Counts of outstanding instructions to wait for.

The bits of this operand have the following meaning:

============ ======================================================
Bits Description
============ ======================================================
3:0 VM_CNT: vector memory operations count.
6:4 EXP_CNT: export count.
12:8 LGKM_CNT: LDS, GDS, Constant and Message count.
============ ======================================================
===== ================================================ ============
Bits Description Value Range
===== ================================================ ============
3:0 VM_CNT: vector memory operations count. 0..15
6:4 EXP_CNT: export count. 0..7
12:8 LGKM_CNT: LDS, GDS, Constant and Message count. 0..31
===== ================================================ ============

This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_synid_integer_number>`
or as a combination of the following symbolic helpers:
This operand may be specified as one of the following:

* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF.
* A combination of *vmcnt*, *expcnt*, *lgkmcnt* and other values described below.

====================== ======================================================================
Syntax Description
====================== ======================================================================
vmcnt(<*N*>) VM_CNT value. *N* must not exceed the largest VM_CNT value.
expcnt(<*N*>) EXP_CNT value. *N* must not exceed the largest EXP_CNT value.
lgkmcnt(<*N*>) LGKM_CNT value. *N* must not exceed the largest LGKM_CNT value.
vmcnt_sat(<*N*>) VM_CNT value computed as min(*N*, the largest VM_CNT value).
expcnt_sat(<*N*>) EXP_CNT value computed as min(*N*, the largest EXP_CNT value).
lgkmcnt_sat(<*N*>) LGKM_CNT value computed as min(*N*, the largest LGKM_CNT value).
vmcnt(<*N*>) A VM_CNT value. *N* must not exceed the largest VM_CNT value.
expcnt(<*N*>) An EXP_CNT value. *N* must not exceed the largest EXP_CNT value.
lgkmcnt(<*N*>) An LGKM_CNT value. *N* must not exceed the largest LGKM_CNT value.
vmcnt_sat(<*N*>) A VM_CNT value computed as min(*N*, the largest VM_CNT value).
expcnt_sat(<*N*>) An EXP_CNT value computed as min(*N*, the largest EXP_CNT value).
lgkmcnt_sat(<*N*>) An LGKM_CNT value computed as min(*N*, the largest LGKM_CNT value).
====================== ======================================================================

These helpers may be specified in any order. Ampersands and commas may be used as optional separators.
These values may be specified in any order. Spaces, ampersands and commas may be used as optional separators.

*N* is either an
:ref:`integer number<amdgpu_synid_integer_number>` or an
Expand All @@ -46,10 +48,18 @@ Examples:

.. parsed-literal::
s_waitcnt 0
vm_cnt = 1
exp_cnt = 2
lgkm_cnt = 3
cnt = vm_cnt | (exp_cnt << 4) | (lgkm_cnt << 8)
s_waitcnt cnt
s_waitcnt 1 | (2 << 4) | (3 << 8) // the same as above
s_waitcnt vmcnt(1) expcnt(2) lgkmcnt(3) // the same as above
s_waitcnt vmcnt(vm_cnt) expcnt(exp_cnt) lgkmcnt(lgkm_cnt) // the same as above
s_waitcnt vmcnt(1)
s_waitcnt expcnt(2) lgkmcnt(3)
s_waitcnt vmcnt(1) expcnt(2) lgkmcnt(3)
s_waitcnt vmcnt(1), expcnt(2), lgkmcnt(3)
s_waitcnt vmcnt(1) & lgkmcnt_sat(100) & expcnt(2)
2 changes: 1 addition & 1 deletion llvm/docs/AMDGPU/gfx8_bimm16.rst
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Expand Up @@ -10,5 +10,5 @@
imm16
===========================

An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 16 bits.
A 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.

2 changes: 1 addition & 1 deletion llvm/docs/AMDGPU/gfx8_bimm32.rst
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Expand Up @@ -10,5 +10,5 @@
imm32
===========================

An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 32 bits.
An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value is truncated to 32 bits.

2 changes: 1 addition & 1 deletion llvm/docs/AMDGPU/gfx8_data_mimg_atomic_cmp.rst
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Expand Up @@ -21,7 +21,7 @@ Optionally may serve as an output data:
* :ref:`dmask<amdgpu_synid_dmask>` may specify 2 data elements for 32-bit-per-pixel surfaces or 4 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.

Note. The surface data format is indicated in the image resource constant but not in the instruction.
Note: the surface data format is indicated in the image resource constant but not in the instruction.


*Operands:* :ref:`v<amdgpu_synid_v>`
2 changes: 1 addition & 1 deletion llvm/docs/AMDGPU/gfx8_data_mimg_atomic_reg.rst
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Expand Up @@ -21,6 +21,6 @@ Optionally may serve as an output data:
* :ref:`dmask<amdgpu_synid_dmask>` may specify 1 data element for 32-bit-per-pixel surfaces or 2 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.

Note. The surface data format is indicated in the image resource constant but not in the instruction.
Note: the surface data format is indicated in the image resource constant but not in the instruction.

*Operands:* :ref:`v<amdgpu_synid_v>`
3 changes: 2 additions & 1 deletion llvm/docs/AMDGPU/gfx8_fimm16.rst
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Expand Up @@ -10,5 +10,6 @@
imm32
===========================

An :ref:`integer_number<amdgpu_synid_integer_number>` or a :ref:`floating-point_number<amdgpu_synid_floating-point_number>`. The number is converted to *f16* as described :ref:`here<amdgpu_synid_lit_conv>`.
A :ref:`floating-point_number<amdgpu_synid_floating-point_number>`, an :ref:`integer_number<amdgpu_synid_integer_number>`, or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`.
The value is converted to *f16* as described :ref:`here<amdgpu_synid_fp_conv>`.

3 changes: 2 additions & 1 deletion llvm/docs/AMDGPU/gfx8_fimm32.rst
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Expand Up @@ -10,5 +10,6 @@
imm32
===========================

An :ref:`integer_number<amdgpu_synid_integer_number>` or a :ref:`floating-point_number<amdgpu_synid_floating-point_number>`. The value is converted to *f32* as described :ref:`here<amdgpu_synid_lit_conv>`.
A :ref:`floating-point_number<amdgpu_synid_floating-point_number>`, an :ref:`integer_number<amdgpu_synid_integer_number>`, or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`.
The value is converted to *f32* as described :ref:`here<amdgpu_synid_fp_conv>`.

35 changes: 24 additions & 11 deletions llvm/docs/AMDGPU/gfx8_hwreg.rst
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Expand Up @@ -14,26 +14,30 @@ Bits of a hardware register being accessed.

The bits of this operand have the following meaning:

============ ===================================
Bits Description
============ ===================================
5:0 Register *id*.
10:6 First bit *offset* (0..31).
15:11 *Size* in bits (1..32).
============ ===================================
======= ===================== ============
Bits Description Value Range
======= ===================== ============
5:0 Register *id*. 0..63
10:6 First bit *offset*. 0..31
15:11 *Size* in bits. 1..32
======= ===================== ============

This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or using the syntax described below.
This operand may be specified as one of the following:

* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF.
* An *hwreg* value described below.

==================================== ============================================================================
Syntax Description
Hwreg Value Syntax Description
==================================== ============================================================================
hwreg({0..63}) All bits of a register indicated by its *id*.
hwreg(<*name*>) All bits of a register indicated by its *name*.
hwreg({0..63}, {0..31}, {1..32}) Register bits indicated by register *id*, first bit *offset* and *size*.
hwreg(<*name*>, {0..31}, {1..32}) Register bits indicated by register *name*, first bit *offset* and *size*.
==================================== ============================================================================

Register *id*, *offset* and *size* must be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`.
Numeric values may be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`
or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.

Defined register *names* include:

Expand All @@ -53,7 +57,16 @@ Examples:

.. parsed-literal::
s_getreg_b32 s2, 0x6
reg = 1
offset = 2
size = 4
hwreg_enc = reg | (offset << 6) | ((size - 1) << 11)
s_getreg_b32 s2, 0x1881
s_getreg_b32 s2, hwreg_enc // the same as above
s_getreg_b32 s2, hwreg(1, 2, 4) // the same as above
s_getreg_b32 s2, hwreg(reg, offset, size) // the same as above
s_getreg_b32 s2, hwreg(15)
s_getreg_b32 s2, hwreg(51, 1, 31)
s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1)
Expand Down
66 changes: 66 additions & 0 deletions llvm/docs/AMDGPU/gfx8_imask.rst
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@@ -0,0 +1,66 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid8_imask:

imask
===========================

This operand is a mask which controls indexing mode for operands of subsequent instructions.
Bits 0, 1 and 2 control indexing of *src0*, *src1* and *src2*, while bit 3 controls indexing of *dst*.
Value 1 enables indexing and value 0 disables it.

===== ========================================
Bit Meaning
===== ========================================
0 Enables or disables *src0* indexing.
1 Enables or disables *src1* indexing.
2 Enables or disables *src2* indexing.
3 Enables or disables *dst* indexing.
===== ========================================

This operand may be specified as one of the following:

* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..15.
* A *gpr_idx* value described below.

==================================== ===========================================
Gpr_idx Value Syntax Description
==================================== ===========================================
gpr_idx(*<operands>*) Enable indexing for specified *operands*
and disable it for the rest.
*Operands* is a comma-separated list of
values which may include:

* "SRC0" - enable *src0* indexing.

* "SRC1" - enable *src1* indexing.

* "SRC2" - enable *src2* indexing.

* "DST" - enable *dst* indexing.

Each of these values may be specified only
once.

*Operands* list may be empty; this syntax
disables indexing for all operands.
==================================== ===========================================

Examples:

.. parsed-literal::

s_set_gpr_idx_mode 0
s_set_gpr_idx_mode gpr_idx() // the same as above

s_set_gpr_idx_mode 15
s_set_gpr_idx_mode gpr_idx(DST,SRC0,SRC1,SRC2) // the same as above
s_set_gpr_idx_mode gpr_idx(SRC0,SRC1,SRC2,DST) // the same as above

s_set_gpr_idx_mode gpr_idx(DST,SRC1)

25 changes: 0 additions & 25 deletions llvm/docs/AMDGPU/gfx8_imm4.rst
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21 changes: 14 additions & 7 deletions llvm/docs/AMDGPU/gfx8_label.rst
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Expand Up @@ -12,19 +12,26 @@ label

A branch target which is a 16-bit signed integer treated as a PC-relative dword offset.

This operand may be specified as:
This operand may be specified as one of the following:

* An :ref:`integer_number<amdgpu_synid_integer_number>`. The number is truncated to 16 bits.
* An :ref:`absolute_expression<amdgpu_synid_absolute_expression>` which must start with an :ref:`integer_number<amdgpu_synid_integer_number>`. The value of the expression is truncated to 16 bits.
* A :ref:`symbol<amdgpu_synid_symbol>` (for example, a label). The value is handled as a 16-bit PC-relative dword offset to be resolved by a linker.
* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.
* A :ref:`symbol<amdgpu_synid_symbol>` (for example, a label) representing a relocatable address in the same compilation unit where it is referred from. The value is handled as a 16-bit PC-relative dword offset to be resolved by a linker.

Examples:

.. parsed-literal::
offset = 30
s_branch loop_end
s_branch 2 + offset
label_1:
label_2 = . + 4
s_branch 32
loop_end:
s_branch offset + 2
s_branch label_1
s_branch label_2
s_branch label_3
s_branch label_4
label_3 = label_2 + 4
label_4:
62 changes: 42 additions & 20 deletions llvm/docs/AMDGPU/gfx8_msg.rst
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Expand Up @@ -12,32 +12,38 @@ msg

A 16-bit message code. The bits of this operand have the following meaning:

============ ======================================================
Bits Description
============ ======================================================
3:0 Message *type*.
6:4 Optional *operation*.
9:7 Optional *parameters*.
15:10 Unused.
============ ======================================================

This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or using the syntax described below:

======================================== ========================================================================
Syntax Description
======================================== ========================================================================
sendmsg(<*type*>) A message identified by its *type*.
sendmsg(<*type*>, <*op*>) A message identified by its *type* and *operation*.
sendmsg(<*type*>, <*op*>, <*stream*>) A message identified by its *type* and *operation* with a stream *id*.
======================================== ========================================================================
============ =============================== ===============
Bits Description Value Range
============ =============================== ===============
3:0 Message *type*. 0..15
6:4 Optional *operation*. 0..7
7:7 Unused. \-
9:8 Optional *stream*. 0..3
15:10 Unused. \-
============ =============================== ===============

This operand may be specified as one of the following:

* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF.
* A *sendmsg* value described below.

==================================== ====================================================
Sendmsg Value Syntax Description
==================================== ====================================================
sendmsg(<*type*>) A message identified by its *type*.
sendmsg(<*type*>,<*op*>) A message identified by its *type* and *operation*.
sendmsg(<*type*>,<*op*>,<*stream*>) A message identified by its *type* and *operation*
with a stream *id*.
==================================== ====================================================

*Type* may be specified using message *name* or message *id*.

*Op* may be specified using operation *name* or operation *id*.

Stream *id* is an integer in the range 0..3.

Message *id*, operation *id* and stream *id* must be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`.
Numeric values may be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`
or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.

Each message type supports specific operations:

Expand All @@ -58,15 +64,31 @@ Each message type supports specific operations:
\ SYSMSG_OP_TTRACE_PC 4 \-
================= ========== ============================== ============ ==========

*Sendmsg* arguments are validated depending on how *type* value is specified:

* If message *type* is specified by name, arguments values must satisfy limitations detailed in the table above.
* If message *type* is specified as a number, each argument must not exceed corresponding value range (see the first table).

Examples:

.. parsed-literal::
// numeric message code
msg = 0x10
s_sendmsg 0x12
s_sendmsg msg + 2
// sendmsg with strict arguments validation
s_sendmsg sendmsg(MSG_INTERRUPT)
s_sendmsg sendmsg(2, GS_OP_CUT)
s_sendmsg sendmsg(MSG_GS, GS_OP_EMIT)
s_sendmsg sendmsg(MSG_GS, 2)
s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_EMIT_CUT, 1)
s_sendmsg sendmsg(MSG_SYSMSG, SYSMSG_OP_TTRACE_PC)
// sendmsg with validation of value range only
msg = 2
op = 3
stream = 1
s_sendmsg sendmsg(msg, op, stream)
s_sendmsg sendmsg(2, GS_OP_CUT)
3 changes: 2 additions & 1 deletion llvm/docs/AMDGPU/gfx8_perm_smem.rst
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Expand Up @@ -12,7 +12,8 @@ imm3

A bit mask which indicates request permissions.

This operand must be specified as an :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 7 bits, but only 3 low bits are significant.
This operand must be specified as an :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`.
The value is truncated to 7 bits, but only 3 low bits are significant.

============ ==============================
Bit Number Description
Expand Down
2 changes: 1 addition & 1 deletion llvm/docs/AMDGPU/gfx8_simm16.rst
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Expand Up @@ -10,5 +10,5 @@
imm16
===========================

An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 16 bits and then sign-extended to 32 bits.
An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.

2 changes: 1 addition & 1 deletion llvm/docs/AMDGPU/gfx8_uimm16.rst
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Expand Up @@ -10,5 +10,5 @@
imm16
===========================

An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 16 bits and then zero-extended to 32 bits.
An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..65535.

46 changes: 28 additions & 18 deletions llvm/docs/AMDGPU/gfx8_waitcnt.rst
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Expand Up @@ -14,29 +14,31 @@ Counts of outstanding instructions to wait for.

The bits of this operand have the following meaning:

============ ======================================================
Bits Description
============ ======================================================
3:0 VM_CNT: vector memory operations count.
6:4 EXP_CNT: export count.
11:8 LGKM_CNT: LDS, GDS, Constant and Message count.
============ ======================================================
===== ================================================ ============
Bits Description Value Range
===== ================================================ ============
3:0 VM_CNT: vector memory operations count. 0..15
6:4 EXP_CNT: export count. 0..7
11:8 LGKM_CNT: LDS, GDS, Constant and Message count. 0..15
===== ================================================ ============

This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_synid_integer_number>`
or as a combination of the following symbolic helpers:
This operand may be specified as one of the following:

* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF.
* A combination of *vmcnt*, *expcnt*, *lgkmcnt* and other values described below.

====================== ======================================================================
Syntax Description
====================== ======================================================================
vmcnt(<*N*>) VM_CNT value. *N* must not exceed the largest VM_CNT value.
expcnt(<*N*>) EXP_CNT value. *N* must not exceed the largest EXP_CNT value.
lgkmcnt(<*N*>) LGKM_CNT value. *N* must not exceed the largest LGKM_CNT value.
vmcnt_sat(<*N*>) VM_CNT value computed as min(*N*, the largest VM_CNT value).
expcnt_sat(<*N*>) EXP_CNT value computed as min(*N*, the largest EXP_CNT value).
lgkmcnt_sat(<*N*>) LGKM_CNT value computed as min(*N*, the largest LGKM_CNT value).
vmcnt(<*N*>) A VM_CNT value. *N* must not exceed the largest VM_CNT value.
expcnt(<*N*>) An EXP_CNT value. *N* must not exceed the largest EXP_CNT value.
lgkmcnt(<*N*>) An LGKM_CNT value. *N* must not exceed the largest LGKM_CNT value.
vmcnt_sat(<*N*>) A VM_CNT value computed as min(*N*, the largest VM_CNT value).
expcnt_sat(<*N*>) An EXP_CNT value computed as min(*N*, the largest EXP_CNT value).
lgkmcnt_sat(<*N*>) An LGKM_CNT value computed as min(*N*, the largest LGKM_CNT value).
====================== ======================================================================

These helpers may be specified in any order. Ampersands and commas may be used as optional separators.
These values may be specified in any order. Spaces, ampersands and commas may be used as optional separators.

*N* is either an
:ref:`integer number<amdgpu_synid_integer_number>` or an
Expand All @@ -46,10 +48,18 @@ Examples:

.. parsed-literal::
s_waitcnt 0
vm_cnt = 1
exp_cnt = 2
lgkm_cnt = 3
cnt = vm_cnt | (exp_cnt << 4) | (lgkm_cnt << 8)
s_waitcnt cnt
s_waitcnt 1 | (2 << 4) | (3 << 8) // the same as above
s_waitcnt vmcnt(1) expcnt(2) lgkmcnt(3) // the same as above
s_waitcnt vmcnt(vm_cnt) expcnt(exp_cnt) lgkmcnt(lgkm_cnt) // the same as above
s_waitcnt vmcnt(1)
s_waitcnt expcnt(2) lgkmcnt(3)
s_waitcnt vmcnt(1) expcnt(2) lgkmcnt(3)
s_waitcnt vmcnt(1), expcnt(2), lgkmcnt(3)
s_waitcnt vmcnt(1) & lgkmcnt_sat(100) & expcnt(2)
2 changes: 1 addition & 1 deletion llvm/docs/AMDGPU/gfx9_bimm16.rst
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Expand Up @@ -10,5 +10,5 @@
imm16
===========================

An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 16 bits.
A 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.

2 changes: 1 addition & 1 deletion llvm/docs/AMDGPU/gfx9_bimm32.rst
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Expand Up @@ -10,5 +10,5 @@
imm32
===========================

An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 32 bits.
An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value is truncated to 32 bits.

2 changes: 1 addition & 1 deletion llvm/docs/AMDGPU/gfx9_data_mimg_atomic_cmp.rst
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Expand Up @@ -21,7 +21,7 @@ Optionally may serve as an output data:
* :ref:`dmask<amdgpu_synid_dmask>` may specify 2 data elements for 32-bit-per-pixel surfaces or 4 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.

Note. The surface data format is indicated in the image resource constant but not in the instruction.
Note: the surface data format is indicated in the image resource constant but not in the instruction.


*Operands:* :ref:`v<amdgpu_synid_v>`
2 changes: 1 addition & 1 deletion llvm/docs/AMDGPU/gfx9_data_mimg_atomic_reg.rst
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Expand Up @@ -21,6 +21,6 @@ Optionally may serve as an output data:
* :ref:`dmask<amdgpu_synid_dmask>` may specify 1 data element for 32-bit-per-pixel surfaces or 2 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.

Note. The surface data format is indicated in the image resource constant but not in the instruction.
Note: the surface data format is indicated in the image resource constant but not in the instruction.

*Operands:* :ref:`v<amdgpu_synid_v>`
3 changes: 2 additions & 1 deletion llvm/docs/AMDGPU/gfx9_fimm16.rst
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Expand Up @@ -10,5 +10,6 @@
imm32
===========================

An :ref:`integer_number<amdgpu_synid_integer_number>` or a :ref:`floating-point_number<amdgpu_synid_floating-point_number>`. The number is converted to *f16* as described :ref:`here<amdgpu_synid_lit_conv>`.
A :ref:`floating-point_number<amdgpu_synid_floating-point_number>`, an :ref:`integer_number<amdgpu_synid_integer_number>`, or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`.
The value is converted to *f16* as described :ref:`here<amdgpu_synid_fp_conv>`.

3 changes: 2 additions & 1 deletion llvm/docs/AMDGPU/gfx9_fimm32.rst
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Expand Up @@ -10,5 +10,6 @@
imm32
===========================

An :ref:`integer_number<amdgpu_synid_integer_number>` or a :ref:`floating-point_number<amdgpu_synid_floating-point_number>`. The value is converted to *f32* as described :ref:`here<amdgpu_synid_lit_conv>`.
A :ref:`floating-point_number<amdgpu_synid_floating-point_number>`, an :ref:`integer_number<amdgpu_synid_integer_number>`, or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`.
The value is converted to *f32* as described :ref:`here<amdgpu_synid_fp_conv>`.

35 changes: 24 additions & 11 deletions llvm/docs/AMDGPU/gfx9_hwreg.rst
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Expand Up @@ -14,26 +14,30 @@ Bits of a hardware register being accessed.

The bits of this operand have the following meaning:

============ ===================================
Bits Description
============ ===================================
5:0 Register *id*.
10:6 First bit *offset* (0..31).
15:11 *Size* in bits (1..32).
============ ===================================
======= ===================== ============
Bits Description Value Range
======= ===================== ============
5:0 Register *id*. 0..63
10:6 First bit *offset*. 0..31
15:11 *Size* in bits. 1..32
======= ===================== ============

This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or using the syntax described below.
This operand may be specified as one of the following:

* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF.
* An *hwreg* value described below.

==================================== ============================================================================
Syntax Description
Hwreg Value Syntax Description
==================================== ============================================================================
hwreg({0..63}) All bits of a register indicated by its *id*.
hwreg(<*name*>) All bits of a register indicated by its *name*.
hwreg({0..63}, {0..31}, {1..32}) Register bits indicated by register *id*, first bit *offset* and *size*.
hwreg(<*name*>, {0..31}, {1..32}) Register bits indicated by register *name*, first bit *offset* and *size*.
==================================== ============================================================================

Register *id*, *offset* and *size* must be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`.
Numeric values may be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`
or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.

Defined register *names* include:

Expand All @@ -54,7 +58,16 @@ Examples:

.. parsed-literal::
s_getreg_b32 s2, 0x6
reg = 1
offset = 2
size = 4
hwreg_enc = reg | (offset << 6) | ((size - 1) << 11)
s_getreg_b32 s2, 0x1881
s_getreg_b32 s2, hwreg_enc // the same as above
s_getreg_b32 s2, hwreg(1, 2, 4) // the same as above
s_getreg_b32 s2, hwreg(reg, offset, size) // the same as above
s_getreg_b32 s2, hwreg(15)
s_getreg_b32 s2, hwreg(51, 1, 31)
s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1)
Expand Down
66 changes: 66 additions & 0 deletions llvm/docs/AMDGPU/gfx9_imask.rst
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@@ -0,0 +1,66 @@
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid9_imask:

imask
===========================

This operand is a mask which controls indexing mode for operands of subsequent instructions.
Bits 0, 1 and 2 control indexing of *src0*, *src1* and *src2*, while bit 3 controls indexing of *dst*.
Value 1 enables indexing and value 0 disables it.

===== ========================================
Bit Meaning
===== ========================================
0 Enables or disables *src0* indexing.
1 Enables or disables *src1* indexing.
2 Enables or disables *src2* indexing.
3 Enables or disables *dst* indexing.
===== ========================================

This operand may be specified as one of the following:

* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..15.
* A *gpr_idx* value described below.

==================================== ===========================================
Gpr_idx Value Syntax Description
==================================== ===========================================
gpr_idx(*<operands>*) Enable indexing for specified *operands*
and disable it for the rest.
*Operands* is a comma-separated list of
values which may include:

* "SRC0" - enable *src0* indexing.

* "SRC1" - enable *src1* indexing.

* "SRC2" - enable *src2* indexing.

* "DST" - enable *dst* indexing.

Each of these values may be specified only
once.

*Operands* list may be empty; this syntax
disables indexing for all operands.
==================================== ===========================================

Examples:

.. parsed-literal::

s_set_gpr_idx_mode 0
s_set_gpr_idx_mode gpr_idx() // the same as above

s_set_gpr_idx_mode 15
s_set_gpr_idx_mode gpr_idx(DST,SRC0,SRC1,SRC2) // the same as above
s_set_gpr_idx_mode gpr_idx(SRC0,SRC1,SRC2,DST) // the same as above

s_set_gpr_idx_mode gpr_idx(DST,SRC1)

25 changes: 0 additions & 25 deletions llvm/docs/AMDGPU/gfx9_imm4.rst
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21 changes: 14 additions & 7 deletions llvm/docs/AMDGPU/gfx9_label.rst
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Expand Up @@ -12,19 +12,26 @@ label

A branch target which is a 16-bit signed integer treated as a PC-relative dword offset.

This operand may be specified as:
This operand may be specified as one of the following:

* An :ref:`integer_number<amdgpu_synid_integer_number>`. The number is truncated to 16 bits.
* An :ref:`absolute_expression<amdgpu_synid_absolute_expression>` which must start with an :ref:`integer_number<amdgpu_synid_integer_number>`. The value of the expression is truncated to 16 bits.
* A :ref:`symbol<amdgpu_synid_symbol>` (for example, a label). The value is handled as a 16-bit PC-relative dword offset to be resolved by a linker.
* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.
* A :ref:`symbol<amdgpu_synid_symbol>` (for example, a label) representing a relocatable address in the same compilation unit where it is referred from. The value is handled as a 16-bit PC-relative dword offset to be resolved by a linker.

Examples:

.. parsed-literal::
offset = 30
s_branch loop_end
s_branch 2 + offset
label_1:
label_2 = . + 4
s_branch 32
loop_end:
s_branch offset + 2
s_branch label_1
s_branch label_2
s_branch label_3
s_branch label_4
label_3 = label_2 + 4
label_4:
64 changes: 43 additions & 21 deletions llvm/docs/AMDGPU/gfx9_msg.rst
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Expand Up @@ -12,32 +12,38 @@ msg

A 16-bit message code. The bits of this operand have the following meaning:

============ ======================================================
Bits Description
============ ======================================================
3:0 Message *type*.
6:4 Optional *operation*.
9:7 Optional *parameters*.
15:10 Unused.
============ ======================================================

This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or using the syntax described below:

======================================== ========================================================================
Syntax Description
======================================== ========================================================================
sendmsg(<*type*>) A message identified by its *type*.
sendmsg(<*type*>, <*op*>) A message identified by its *type* and *operation*.
sendmsg(<*type*>, <*op*>, <*stream*>) A message identified by its *type* and *operation* with a stream *id*.
======================================== ========================================================================
============ =============================== ===============
Bits Description Value Range
============ =============================== ===============
3:0 Message *type*. 0..15
6:4 Optional *operation*. 0..7
7:7 Unused. \-
9:8 Optional *stream*. 0..3
15:10 Unused. \-
============ =============================== ===============

This operand may be specified as one of the following:

* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF.
* A *sendmsg* value described below.

==================================== ====================================================
Sendmsg Value Syntax Description
==================================== ====================================================
sendmsg(<*type*>) A message identified by its *type*.
sendmsg(<*type*>,<*op*>) A message identified by its *type* and *operation*.
sendmsg(<*type*>,<*op*>,<*stream*>) A message identified by its *type* and *operation*
with a stream *id*.
==================================== ====================================================

*Type* may be specified using message *name* or message *id*.

*Op* may be specified using operation *name* or operation *id*.

Stream *id* is an integer in the range 0..3.

Message *id*, operation *id* and stream *id* must be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`.
Numeric values may be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`
or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.

Each message type supports specific operations:

Expand All @@ -60,16 +66,32 @@ Each message type supports specific operations:
\ SYSMSG_OP_TTRACE_PC 4 \-
================= ========== ============================== ============ ==========

*Sendmsg* arguments are validated depending on how *type* value is specified:

* If message *type* is specified by name, arguments values must satisfy limitations detailed in the table above.
* If message *type* is specified as a number, each argument must not exceed corresponding value range (see the first table).

Examples:

.. parsed-literal::
// numeric message code
msg = 0x10
s_sendmsg 0x12
s_sendmsg msg + 2
// sendmsg with strict arguments validation
s_sendmsg sendmsg(MSG_INTERRUPT)
s_sendmsg sendmsg(MSG_GET_DOORBELL)
s_sendmsg sendmsg(2, GS_OP_CUT)
s_sendmsg sendmsg(MSG_GS, GS_OP_EMIT)
s_sendmsg sendmsg(MSG_GS, 2)
s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_EMIT_CUT, 1)
s_sendmsg sendmsg(MSG_SYSMSG, SYSMSG_OP_TTRACE_PC)
s_sendmsg sendmsg(MSG_GET_DOORBELL)
// sendmsg with validation of value range only
msg = 2
op = 3
stream = 1
s_sendmsg sendmsg(msg, op, stream)
s_sendmsg sendmsg(2, GS_OP_CUT)
3 changes: 2 additions & 1 deletion llvm/docs/AMDGPU/gfx9_perm_smem.rst
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Expand Up @@ -12,7 +12,8 @@ imm3

A bit mask which indicates request permissions.

This operand must be specified as an :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 7 bits, but only 3 low bits are significant.
This operand must be specified as an :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`.
The value is truncated to 7 bits, but only 3 low bits are significant.

============ ==============================
Bit Number Description
Expand Down
2 changes: 1 addition & 1 deletion llvm/docs/AMDGPU/gfx9_simm16.rst
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Expand Up @@ -10,5 +10,5 @@
imm16
===========================

An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 16 bits and then sign-extended to 32 bits.
An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.

2 changes: 1 addition & 1 deletion llvm/docs/AMDGPU/gfx9_uimm16.rst
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Expand Up @@ -10,5 +10,5 @@
imm16
===========================

An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 16 bits and then zero-extended to 32 bits.
An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..65535.

49 changes: 29 additions & 20 deletions llvm/docs/AMDGPU/gfx9_waitcnt.rst
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Expand Up @@ -14,30 +14,31 @@ Counts of outstanding instructions to wait for.

The bits of this operand have the following meaning:

============ ======================================================
Bits Description
============ ======================================================
3:0 VM_CNT: vector memory operations count, lower bits.
6:4 EXP_CNT: export count.
11:8 LGKM_CNT: LDS, GDS, Constant and Message count.
15:14 VM_CNT: vector memory operations count, upper bits.
============ ======================================================

This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_synid_integer_number>`
or as a combination of the following symbolic helpers:
========== ========= ================================================ ============
High Bits Low Bits Description Value Range
========== ========= ================================================ ============
15:14 3:0 VM_CNT: vector memory operations count. 0..63
\- 6:4 EXP_CNT: export count. 0..7
\- 11:8 LGKM_CNT: LDS, GDS, Constant and Message count. 0..15
========== ========= ================================================ ============

This operand may be specified as one of the following:

* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF.
* A combination of *vmcnt*, *expcnt*, *lgkmcnt* and other values described below.

====================== ======================================================================
Syntax Description
====================== ======================================================================
vmcnt(<*N*>) VM_CNT value. *N* must not exceed the largest VM_CNT value.
expcnt(<*N*>) EXP_CNT value. *N* must not exceed the largest EXP_CNT value.
lgkmcnt(<*N*>) LGKM_CNT value. *N* must not exceed the largest LGKM_CNT value.
vmcnt_sat(<*N*>) VM_CNT value computed as min(*N*, the largest VM_CNT value).
expcnt_sat(<*N*>) EXP_CNT value computed as min(*N*, the largest EXP_CNT value).
lgkmcnt_sat(<*N*>) LGKM_CNT value computed as min(*N*, the largest LGKM_CNT value).
vmcnt(<*N*>) A VM_CNT value. *N* must not exceed the largest VM_CNT value.
expcnt(<*N*>) An EXP_CNT value. *N* must not exceed the largest EXP_CNT value.
lgkmcnt(<*N*>) An LGKM_CNT value. *N* must not exceed the largest LGKM_CNT value.
vmcnt_sat(<*N*>) A VM_CNT value computed as min(*N*, the largest VM_CNT value).
expcnt_sat(<*N*>) An EXP_CNT value computed as min(*N*, the largest EXP_CNT value).
lgkmcnt_sat(<*N*>) An LGKM_CNT value computed as min(*N*, the largest LGKM_CNT value).
====================== ======================================================================

These helpers may be specified in any order. Ampersands and commas may be used as optional separators.
These values may be specified in any order. Spaces, ampersands and commas may be used as optional separators.

*N* is either an
:ref:`integer number<amdgpu_synid_integer_number>` or an
Expand All @@ -47,10 +48,18 @@ Examples:

.. parsed-literal::
s_waitcnt 0
vm_cnt = 1
exp_cnt = 2
lgkm_cnt = 3
cnt = vm_cnt | (exp_cnt << 4) | (lgkm_cnt << 8)
s_waitcnt cnt
s_waitcnt 1 | (2 << 4) | (3 << 8) // the same as above
s_waitcnt vmcnt(1) expcnt(2) lgkmcnt(3) // the same as above
s_waitcnt vmcnt(vm_cnt) expcnt(exp_cnt) lgkmcnt(lgkm_cnt) // the same as above
s_waitcnt vmcnt(1)
s_waitcnt expcnt(2) lgkmcnt(3)
s_waitcnt vmcnt(1) expcnt(2) lgkmcnt(3)
s_waitcnt vmcnt(1), expcnt(2), lgkmcnt(3)
s_waitcnt vmcnt(1) & lgkmcnt_sat(100) & expcnt(2)
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