diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -18,6 +18,7 @@
 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
 #include "llvm/MC/MCFixedLenDisassembler.h"
 #include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/Endian.h"
@@ -31,10 +32,12 @@ typedef MCDisassembler::DecodeStatus DecodeStatus;
 
 namespace {
 class RISCVDisassembler : public MCDisassembler {
+  std::unique_ptr<MCInstrInfo const> const MCII;
 
 public:
-  RISCVDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
-      : MCDisassembler(STI, Ctx) {}
+  RISCVDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
+                    MCInstrInfo const *MCII)
+      : MCDisassembler(STI, Ctx), MCII(MCII) {}
 
   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
                               ArrayRef<uint8_t> Bytes, uint64_t Address,
@@ -45,7 +48,7 @@ class RISCVDisassembler : public MCDisassembler {
 static MCDisassembler *createRISCVDisassembler(const Target &T,
                                                const MCSubtargetInfo &STI,
                                                MCContext &Ctx) {
-  return new RISCVDisassembler(STI, Ctx);
+  return new RISCVDisassembler(STI, Ctx, T.createMCInstrInfo());
 }
 
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVDisassembler() {
@@ -148,6 +151,33 @@ static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo,
   return MCDisassembler::Success;
 }
 
+static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint64_t RegNo,
+                                          uint64_t Address,
+                                          const void *Decoder) {
+  if (RegNo >= 32)
+    return MCDisassembler::Fail;
+
+  Register Reg = RISCV::V0 + RegNo;
+  Inst.addOperand(MCOperand::createReg(Reg));
+  return MCDisassembler::Success;
+}
+
+static DecodeStatus decodeVMaskReg(MCInst &Inst, uint64_t RegNo,
+                                   uint64_t Address, const void *Decoder) {
+  Register Reg = RISCV::NoRegister;
+  switch (RegNo) {
+  default:
+    return MCDisassembler::Fail;
+  case 0:
+    Reg = RISCV::V0;
+    break;
+  case 1:
+    break;
+  }
+  Inst.addOperand(MCOperand::createReg(Reg));
+  return MCDisassembler::Success;
+}
+
 // Add implied SP operand for instructions *SP compressed instructions. The SP
 // operand isn't explicitly encoded in the instruction.
 static void addImplySP(MCInst &Inst, int64_t Address, const void *Decoder) {

diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
@@ -150,6 +150,39 @@ void RISCVInstPrinter::printAtomicMemOp(const MCInst *MI, unsigned OpNo,
   return;
 }
 
+void RISCVInstPrinter::printVTypeI(const MCInst *MI, unsigned OpNo,
+                                   const MCSubtargetInfo &STI, raw_ostream &O) {
+  unsigned Imm = MI->getOperand(OpNo).getImm();
+  unsigned Sew = (Imm >> 2) & 0x7;
+  unsigned Lmul = Imm & 0x3;
+
+  Lmul = 0x1 << Lmul;
+  Sew = 0x1 << (Sew + 3);
+  O << "e" << Sew << ",m" << Lmul;
+}
+
+void RISCVInstPrinter::printVMaskReg(const MCInst *MI, unsigned OpNo,
+                                     const MCSubtargetInfo &STI,
+                                     raw_ostream &O) {
+  const MCOperand &MO = MI->getOperand(OpNo);
+
+  assert(MO.isReg() && "printVMaskReg can only print register operands");
+  if (MO.getReg() == RISCV::NoRegister)
+    return;
+  O << ", ";
+  printRegName(O, MO.getReg());
+  O << ".t";
+}
+
+void RISCVInstPrinter::printSImm5Plus1(const MCInst *MI, unsigned OpNo,
+                                       const MCSubtargetInfo &STI,
+                                       raw_ostream &O) {
+  const MCOperand &MO = MI->getOperand(OpNo);
+
+  assert(MO.isImm() && "printSImm5Plus1 can only print constant operands");
+  O << MO.getImm() + 1;
+}
+
 const char *RISCVInstPrinter::getRegisterName(unsigned RegNo) {
   return getRegisterName(RegNo, ArchRegNames ? RISCV::NoRegAltName
                                              : RISCV::ABIRegAltName);

diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
@@ -40,6 +40,12 @@ class RISCVInstPrinter : public MCInstPrinter {
                    raw_ostream &O);
   void printAtomicMemOp(const MCInst *MI, unsigned OpNo,
                         const MCSubtargetInfo &STI, raw_ostream &O);
+  void printVTypeI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
+                   raw_ostream &O);
+  void printVMaskReg(const MCInst *MI, unsigned OpNo,
+                     const MCSubtargetInfo &STI, raw_ostream &O);
+  void printSImm5Plus1(const MCInst *MI, unsigned OpNo,
+                       const MCSubtargetInfo &STI, raw_ostream &O);
 
   // Autogenerated by tblgen.
   void printInstruction(const MCInst *MI, uint64_t Address,

diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
@@ -80,6 +80,10 @@ class RISCVMCCodeEmitter : public MCCodeEmitter {
   unsigned getImmOpValue(const MCInst &MI, unsigned OpNo,
                          SmallVectorImpl<MCFixup> &Fixups,
                          const MCSubtargetInfo &STI) const;
+
+  unsigned getVMaskReg(const MCInst &MI, unsigned OpNo,
+                       SmallVectorImpl<MCFixup> &Fixups,
+                       const MCSubtargetInfo &STI) const;
 };
 } // end anonymous namespace
 
@@ -374,4 +378,20 @@ unsigned RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
   return 0;
 }
 
+unsigned RISCVMCCodeEmitter::getVMaskReg(const MCInst &MI, unsigned OpNo,
+                                         SmallVectorImpl<MCFixup> &Fixups,
+                                         const MCSubtargetInfo &STI) const {
+  MCOperand MO = MI.getOperand(OpNo);
+  assert(MO.isReg() && "Expected a register.");
+
+  switch (MO.getReg()) {
+  default:
+    llvm_unreachable("Invalid mask register.");
+  case RISCV::V0:
+    return 0;
+  case RISCV::NoRegister:
+    return 1;
+  }
+}
+
 #include "RISCVGenMCCodeEmitter.inc"
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
@@ -147,6 +147,14 @@ def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
                             AssemblerPredicate<(all_of FeatureRVCHints),
                             "RVC Hint Instructions">;
 
+def FeatureStdExtV
+    : SubtargetFeature<"experimental-v", "HasStdExtV", "true",
+                       "'V' (Vector Instructions)",
+                       [FeatureStdExtF]>;
+def HasStdExtV : Predicate<"Subtarget->hasStdExtV()">,
+                           AssemblerPredicate<(all_of FeatureStdExtV),
+                           "'V' (Vector Instructions)">;
+
 def Feature64Bit
     : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;
 def IsRV64 : Predicate<"Subtarget->is64Bit()">,

diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
@@ -49,6 +49,19 @@ def InstFormatCB     : InstFormat<15>;
 def InstFormatCJ     : InstFormat<16>;
 def InstFormatOther  : InstFormat<17>;
 
+class RISCVVConstraint<bits<4> val> {
+  bits<4> Value = val;
+}
+def NoConstraint : RISCVVConstraint<0>;
+def WidenV       : RISCVVConstraint<1>;
+def WidenW       : RISCVVConstraint<2>;
+def WidenCvt     : RISCVVConstraint<3>;
+def Narrow       : RISCVVConstraint<4>;
+def Iota         : RISCVVConstraint<5>;
+def SlideUp      : RISCVVConstraint<6>;
+def Vrgather     : RISCVVConstraint<7>;
+def Vcompress    : RISCVVConstraint<8>;
+
 // The following opcode names match those given in Table 19.1 in the
 // RISC-V User-level ISA specification ("RISC-V base opcode map").
 class RISCVOpcode<bits<7> val> {
@@ -71,6 +84,7 @@ def OPC_MSUB      : RISCVOpcode<0b1000111>;
 def OPC_NMSUB     : RISCVOpcode<0b1001011>;
 def OPC_NMADD     : RISCVOpcode<0b1001111>;
 def OPC_OP_FP     : RISCVOpcode<0b1010011>;
+def OPC_OP_V      : RISCVOpcode<0b1010111>;
 def OPC_BRANCH    : RISCVOpcode<0b1100011>;
 def OPC_JALR      : RISCVOpcode<0b1100111>;
 def OPC_JAL       : RISCVOpcode<0b1101111>;
@@ -99,6 +113,10 @@ class RVInst<dag outs, dag ins, string opcodestr, string argstr,
   let Pattern = pattern;
 
   let TSFlags{4-0} = format.Value;
+
+  // Defaults
+  RISCVVConstraint RVVConstraint = NoConstraint;
+  let TSFlags{8-5} = RVVConstraint.Value;
 }
 
 // Pseudo instructions

diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td b/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
@@ -0,0 +1,300 @@
+//===-- RISCVInstrFormatsV.td - RISCV V Instruction Formats --*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+//  This file describes the RISC-V V extension instruction formats.
+//
+//===----------------------------------------------------------------------===//
+
+class RISCVVFormat<bits<3> val> {
+  bits<3> Value = val;
+}
+def OPIVV : RISCVVFormat<0b000>;
+def OPFVV : RISCVVFormat<0b001>;
+def OPMVV : RISCVVFormat<0b010>;
+def OPIVI : RISCVVFormat<0b011>;
+def OPIVX : RISCVVFormat<0b100>;
+def OPFVF : RISCVVFormat<0b101>;
+def OPMVX : RISCVVFormat<0b110>;
+
+class RISCVMOP<bits<3> val> {
+  bits<3> Value = val;
+}
+def MOPLDUnitStrideU : RISCVMOP<0b000>;
+def MOPLDStridedU    : RISCVMOP<0b010>;
+def MOPLDIndexedU    : RISCVMOP<0b011>;
+def MOPLDUnitStrideS : RISCVMOP<0b100>;
+def MOPLDStridedS    : RISCVMOP<0b110>;
+def MOPLDIndexedS    : RISCVMOP<0b111>;
+
+def MOPSTUnitStride  : RISCVMOP<0b000>;
+def MOPSTStrided     : RISCVMOP<0b010>;
+def MOPSTIndexedOrder: RISCVMOP<0b011>;
+def MOPSTIndexedUnOrd: RISCVMOP<0b111>;
+
+class RISCVLSUMOP<bits<5> val> {
+  bits<5> Value = val;
+}
+def LUMOPUnitStride  : RISCVLSUMOP<0b00000>;
+def LUMOPUnitStrideWholeReg : RISCVLSUMOP<0b01000>;
+def LUMOPUnitStrideFF: RISCVLSUMOP<0b10000>;
+def SUMOPUnitStride  : RISCVLSUMOP<0b00000>;
+def SUMOPUnitStrideWholeReg : RISCVLSUMOP<0b01000>;
+
+class RISCVWidth<bits<3> val> {
+  bits<3> Value = val;
+}
+def LSWidthVByte : RISCVWidth<0b000>;
+def LSWidthVHalf : RISCVWidth<0b101>;
+def LSWidthVWord : RISCVWidth<0b110>;
+def LSWidthVSEW  : RISCVWidth<0b111>;
+
+class RVInstSetVLi<dag outs, dag ins, string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
+  bits<5> rs1;
+  bits<5> rd;
+  bits<11> vtypei;
+
+  let Inst{31} = 0;
+  let Inst{30-20} = vtypei;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = 0b111;
+  let Inst{11-7} = rd;
+  let Opcode = OPC_OP_V.Value;
+
+  let Defs = [VTYPE, VL];
+}
+
+class RVInstSetVL<dag outs, dag ins, string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+  bits<5> rs2;
+  bits<5> rs1;
+  bits<5> rd;
+
+  let Inst{31} = 1;
+  let Inst{30-25} = 0b000000;
+  let Inst{24-20} = rs2;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = 0b111;
+  let Inst{11-7} = rd;
+  let Opcode = OPC_OP_V.Value;
+
+  let Defs = [VTYPE, VL];
+}
+
+class RVInstVV<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
+               string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+  bits<5> vs2;
+  bits<5> vs1;
+  bits<5> vd;
+  bit vm;
+
+  let Inst{31-26} = funct6;
+  let Inst{25} = vm;
+  let Inst{24-20} = vs2;
+  let Inst{19-15} = vs1;
+  let Inst{14-12} = opv.Value;
+  let Inst{11-7} = vd;
+  let Opcode = OPC_OP_V.Value;
+
+  let Uses = [VTYPE, VL];
+}
+
+class RVInstVX<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
+                string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+  bits<5> vs2;
+  bits<5> rs1;
+  bits<5> vd;
+  bit vm;
+
+  let Inst{31-26} = funct6;
+  let Inst{25} = vm;
+  let Inst{24-20} = vs2;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = opv.Value;
+  let Inst{11-7} = vd;
+  let Opcode = OPC_OP_V.Value;
+
+  let Uses = [VTYPE, VL];
+}
+
+class RVInstV2<bits<6> funct6, bits<5> vs2, RISCVVFormat opv, dag outs, dag ins,
+                string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+  bits<5> rs1;
+  bits<5> vd;
+  bit vm;
+
+  let Inst{31-26} = funct6;
+  let Inst{25} = vm;
+  let Inst{24-20} = vs2;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = opv.Value;
+  let Inst{11-7} = vd;
+  let Opcode = OPC_OP_V.Value;
+
+  let Uses = [VTYPE, VL];
+}
+
+class RVInstIVI<bits<6> funct6, dag outs, dag ins, string opcodestr,
+                string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+  bits<5> vs2;
+  bits<5> imm;
+  bits<5> vd;
+  bit vm;
+
+  let Inst{31-26} = funct6;
+  let Inst{25} = vm;
+  let Inst{24-20} = vs2;
+  let Inst{19-15} = imm;
+  let Inst{14-12} = 0b011;
+  let Inst{11-7} = vd;
+  let Opcode = OPC_OP_V.Value;
+
+  let Uses = [VTYPE, VL];
+}
+
+class RVInstV<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, dag outs,
+              dag ins, string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+  bits<5> vs2;
+  bits<5> vd;
+  bit vm;
+
+  let Inst{31-26} = funct6;
+  let Inst{25} = vm;
+  let Inst{24-20} = vs2;
+  let Inst{19-15} = vs1;
+  let Inst{14-12} = opv.Value;
+  let Inst{11-7} = vd;
+  let Opcode = OPC_OP_V.Value;
+
+  let Uses = [VTYPE, VL];
+}
+
+class RVInstVLU<bits<3> nf, RISCVMOP mop, RISCVLSUMOP lumop,
+                RISCVWidth width, dag outs, dag ins, string opcodestr,
+                string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+  bits<5> rs1;
+  bits<5> vd;
+  bit vm;
+
+  let Inst{31-29} = nf;
+  let Inst{28-26} = mop.Value;
+  let Inst{25} = vm;
+  let Inst{24-20} = lumop.Value;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = width.Value;
+  let Inst{11-7} = vd;
+  let Opcode = OPC_LOAD_FP.Value;
+
+  let Uses = [VTYPE, VL];
+}
+
+class RVInstVLS<bits<3> nf, RISCVMOP mop, RISCVWidth width,
+                dag outs, dag ins, string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+  bits<5> rs2;
+  bits<5> rs1;
+  bits<5> vd;
+  bit vm;
+
+  let Inst{31-29} = nf;
+  let Inst{28-26} = mop.Value;
+  let Inst{25} = vm;
+  let Inst{24-20} = rs2;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = width.Value;
+  let Inst{11-7} = vd;
+  let Opcode = OPC_LOAD_FP.Value;
+
+  let Uses = [VTYPE, VL];
+}
+
+class RVInstVLX<bits<3> nf, RISCVMOP mop, RISCVWidth width,
+                dag outs, dag ins, string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+  bits<5> vs2;
+  bits<5> rs1;
+  bits<5> vd;
+  bit vm;
+
+  let Inst{31-29} = nf;
+  let Inst{28-26} = mop.Value;
+  let Inst{25} = vm;
+  let Inst{24-20} = vs2;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = width.Value;
+  let Inst{11-7} = vd;
+  let Opcode = OPC_LOAD_FP.Value;
+
+  let Uses = [VTYPE, VL];
+}
+
+class RVInstVSU<bits<3> nf, RISCVMOP mop, RISCVLSUMOP sumop,
+                RISCVWidth width, dag outs, dag ins, string opcodestr,
+                string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+  bits<5> rs1;
+  bits<5> vs3;
+  bit vm;
+
+  let Inst{31-29} = nf;
+  let Inst{28-26} = mop.Value;
+  let Inst{25} = vm;
+  let Inst{24-20} = sumop.Value;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = width.Value;
+  let Inst{11-7} = vs3;
+  let Opcode = OPC_STORE_FP.Value;
+
+  let Uses = [VTYPE, VL];
+}
+
+class RVInstVSS<bits<3> nf, RISCVMOP mop, RISCVWidth width,
+                dag outs, dag ins, string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+  bits<5> rs2;
+  bits<5> rs1;
+  bits<5> vs3;
+  bit vm;
+
+  let Inst{31-29} = nf;
+  let Inst{28-26} = mop.Value;
+  let Inst{25} = vm;
+  let Inst{24-20} = rs2;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = width.Value;
+  let Inst{11-7} = vs3;
+  let Opcode = OPC_STORE_FP.Value;
+
+  let Uses = [VTYPE, VL];
+}
+
+class RVInstVSX<bits<3> nf, RISCVMOP mop, RISCVWidth width,
+                dag outs, dag ins, string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+  bits<5> vs2;
+  bits<5> rs1;
+  bits<5> vs3;
+  bit vm;
+
+  let Inst{31-29} = nf;
+  let Inst{28-26} = mop.Value;
+  let Inst{25} = vm;
+  let Inst{24-20} = vs2;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = width.Value;
+  let Inst{11-7} = vs3;
+  let Opcode = OPC_STORE_FP.Value;
+
+  let Uses = [VTYPE, VL];
+}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -133,5 +133,24 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
 protected:
   const RISCVSubtarget &STI;
 };
-}
+
+namespace RISCV {
+// Match with the definitions in RISCVInstrFormatsV.td
+enum RVVConstraintType {
+  NoConstraint = 0,
+  WidenV = 1,
+  WidenW = 2,
+  WidenCvt = 3,
+  Narrow = 4,
+  Iota = 5,
+  SlideUp = 6,
+  Vrgather = 7,
+  Vcompress = 8,
+
+  ConstraintOffset = 5,
+  ConstraintMask = 0b1111
+};
+} // end namespace RISCV
+
+} // end namespace llvm
 #endif
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1177,3 +1177,4 @@ include "RISCVInstrInfoF.td"
 include "RISCVInstrInfoD.td"
 include "RISCVInstrInfoC.td"
 include "RISCVInstrInfoB.td"
+include "RISCVInstrInfoV.td"
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -35,6 +35,8 @@ static_assert(RISCV::F31_F == RISCV::F0_F + 31,
 static_assert(RISCV::F1_D == RISCV::F0_D + 1, "Register list not consecutive");
 static_assert(RISCV::F31_D == RISCV::F0_D + 31,
               "Register list not consecutive");
+static_assert(RISCV::V1 == RISCV::V0 + 1, "Register list not consecutive");
+static_assert(RISCV::V31 == RISCV::V0 + 31, "Register list not consecutive");
 
 RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode)
     : RISCVGenRegisterInfo(RISCV::X1, /*DwarfFlavour*/0, /*EHFlavor*/0,

diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -33,7 +33,21 @@ class RISCVReg64<RISCVReg32 subreg> : Register<""> {
   let AltNames = subreg.AltNames;
 }
 
+class RISCVRegWithSubRegs<bits<5> Enc, string n, list<Register> subregs,
+                          list<string> alt = []>
+      : RegisterWithSubRegs<n, subregs> {
+  let HWEncoding{4-0} = Enc;
+  let AltNames = alt;
+}
+
 def ABIRegAltName : RegAltNameIndex;
+
+def sub_vrm2    : SubRegIndex<64, -1>;
+def sub_vrm2_hi : SubRegIndex<64, -1>;
+def sub_vrm4    : SubRegIndex<128, -1>;
+def sub_vrm4_hi : SubRegIndex<128, -1>;
+def sub_vrm8    : SubRegIndex<256, -1>;
+def sub_vrm8_hi : SubRegIndex<256, -1>;
 } // Namespace = "RISCV"
 
 // Integer registers
@@ -233,3 +247,88 @@ def FPR64C : RegisterClass<"RISCV", [f64], 64, (add
   (sequence "F%u_D", 10, 15),
   (sequence "F%u_D", 8, 9)
 )>;
+
+// Vector registers
+let RegAltNameIndices = [ABIRegAltName] in {
+  foreach Index = 0-31 in {
+    def V#Index : RISCVReg<Index, "v"#Index, ["v"#Index]>, DwarfRegNum<[!add(Index, 64)]>;
+  }
+
+  foreach Index = [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22,
+                   24, 26, 28, 30] in {
+    def V#Index#M2 : RISCVRegWithSubRegs<Index, "v"#Index,
+                       [!cast<Register>("V"#Index),
+                        !cast<Register>("V"#!add(Index, 1))],
+                       ["v"#Index]>,
+                     DwarfRegAlias<!cast<Register>("V"#Index)> {
+      let SubRegIndices = [sub_vrm2, sub_vrm2_hi];
+    }
+  }
+
+  foreach Index = [0, 4, 8, 12, 16, 20, 24, 28] in {
+    def V#Index#M4 : RISCVRegWithSubRegs<Index, "v"#Index,
+                       [!cast<Register>("V"#Index#"M2"),
+                        !cast<Register>("V"#!add(Index, 2)#"M2")],
+                       ["v"#Index]>,
+                     DwarfRegAlias<!cast<Register>("V"#Index)> {
+      let SubRegIndices = [sub_vrm4, sub_vrm4_hi];
+    }
+  }
+
+  foreach Index = [0, 8, 16, 24] in {
+    def V#Index#M8 : RISCVRegWithSubRegs<Index, "v"#Index,
+                       [!cast<Register>("V"#Index#"M4"),
+                        !cast<Register>("V"#!add(Index, 4)#"M4")],
+                       ["v"#Index]>,
+                     DwarfRegAlias<!cast<Register>("V"#Index)> {
+      let SubRegIndices = [sub_vrm8, sub_vrm8_hi];
+    }
+  }
+
+  def VTYPE  : RISCVReg<0, "vtype", ["vtype"]>;
+  def VL     : RISCVReg<0, "vl", ["vl"]>;
+}
+
+class RegisterTypes<list<ValueType> reg_types> {
+  list<ValueType> types = reg_types;
+}
+
+// The order of registers represents the preferred allocation sequence,
+// meaning caller-save regs are listed before callee-save.
+def VR : RegisterClass<"RISCV", [nxv8i8, nxv4i16, nxv2i32, nxv1i64],
+                         64, (add
+    (sequence "V%u", 25, 31),
+    (sequence "V%u", 8, 24),
+    (sequence "V%u", 0, 7)
+  )> {
+  let Size = 64;
+}
+
+def VRM2 : RegisterClass<"RISCV", [nxv16i8, nxv8i16, nxv4i32, nxv2i64], 64,
+                         (add V26M2, V28M2, V30M2, V8M2, V10M2, V12M2, V14M2, V16M2,
+                              V18M2, V20M2, V22M2, V24M2, V0M2, V2M2, V4M2, V6M2)> {
+  let Size = 128;
+}
+
+def VRM4 : RegisterClass<"RISCV", [nxv32i8, nxv16i16, nxv8i32, nxv4i64], 64,
+                         (add V28M4, V8M4, V12M4, V16M4, V20M4, V24M4, V0M4, V4M4)> {
+  let Size = 256;
+}
+
+def VRM8 : RegisterClass<"RISCV", [nxv32i16, nxv16i32, nxv8i64], 64,
+                         (add V8M8, V16M8, V24M8, V0M8)> {
+  let Size = 512;
+}
+
+def VMaskVT : RegisterTypes<[nxv1i1, nxv2i1, nxv4i1, nxv8i1, nxv16i1, nxv32i1]>;
+
+def VM : RegisterClass<"RISCV", VMaskVT.types, 64, (add
+    (sequence "V%u", 25, 31),
+    (sequence "V%u", 8, 24),
+    (sequence "V%u", 0, 7))> {
+  let Size = 64;
+}
+
+def VMV0 : RegisterClass<"RISCV", VMaskVT.types, 64, (add V0)> {
+  let Size = 64;
+}
diff --git a/llvm/lib/Target/RISCV/RISCVSchedRocket32.td b/llvm/lib/Target/RISCV/RISCVSchedRocket32.td
@@ -17,6 +17,7 @@ def Rocket32Model : SchedMachineModel {
   let LoadLatency = 3;
   let MispredictPenalty = 3;
   let CompleteModel = 1;
+  let UnsupportedFeatures = [HasStdExtV];
 }
 
 //===----------------------------------------------------------------------===//

diff --git a/llvm/lib/Target/RISCV/RISCVSchedRocket64.td b/llvm/lib/Target/RISCV/RISCVSchedRocket64.td
@@ -16,6 +16,7 @@ def Rocket64Model : SchedMachineModel {
   let IssueWidth = 1;        // 1 micro-ops are dispatched per cycle.
   let LoadLatency = 3;
   let MispredictPenalty = 3;
+  let UnsupportedFeatures = [HasStdExtV];
 }
 
 //===----------------------------------------------------------------------===//

diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -50,6 +50,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
   bool HasStdExtZbs = false;
   bool HasStdExtZbt = false;
   bool HasStdExtZbproposedc = false;
+  bool HasStdExtV = false;
   bool HasRV64 = false;
   bool IsRV32E = false;
   bool EnableLinkerRelax = false;
@@ -110,6 +111,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
   bool hasStdExtZbs() const { return HasStdExtZbs; }
   bool hasStdExtZbt() const { return HasStdExtZbt; }
   bool hasStdExtZbproposedc() const { return HasStdExtZbproposedc; }
+  bool hasStdExtV() const { return HasStdExtV; }
   bool is64Bit() const { return HasRV64; }
   bool isRV32E() const { return IsRV32E; }
   bool enableLinkerRelax() const { return EnableLinkerRelax; }

diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -353,8 +353,19 @@ def : SysReg<"tdata3", 0x7A3>;
 //===-----------------------------------------------
 def : SysReg<"dcsr", 0x7B0>;
 def : SysReg<"dpc", 0x7B1>;
+
 // "dscratch" is an alternative name for "dscratch0" which appeared in earlier
 // drafts of the RISC-V debug spec
 let AltName = "dscratch" in
 def : SysReg<"dscratch0", 0x7B2>;
 def : SysReg<"dscratch1", 0x7B3>;
+
+//===-----------------------------------------------
+// User Vector CSRs
+//===-----------------------------------------------
+def : SysReg<"vstart", 0x008>;
+def : SysReg<"vxsat", 0x009>;
+def : SysReg<"vxrm", 0x00A>;
+def : SysReg<"vl", 0xC20>;
+def : SysReg<"vtype", 0xC21>;
+def : SysReg<"vlenb", 0xC22>;
diff --git a/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
@@ -45,7 +45,7 @@ enum {
   InstFormatCJ = 16,
   InstFormatOther = 17,
 
-  InstFormatMask = 31
+  InstFormatMask = 31,
 };
 
 // RISC-V Specific Machine Operand Flags

diff --git a/llvm/test/MC/RISCV/rvv/add.s b/llvm/test/MC/RISCV/rvv/add.s
@@ -0,0 +1,339 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-v - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vadd.vv v8, v4, v20, v0.t
+# CHECK-INST: vadd.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x00]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 00 <unknown>
+
+vadd.vv v8, v4, v20
+# CHECK-INST: vadd.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x02]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 02 <unknown>
+
+vadd.vx v8, v4, a0, v0.t
+# CHECK-INST: vadd.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x00]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 00 <unknown>
+
+vadd.vx v8, v4, a0
+# CHECK-INST: vadd.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x02]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 02 <unknown>
+
+vadd.vi v8, v4, 15, v0.t
+# CHECK-INST: vadd.vi v8, v4, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x00]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 00 <unknown>
+
+vadd.vi v8, v4, 15
+# CHECK-INST: vadd.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x02]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 02 <unknown>
+
+vwaddu.vv v8, v4, v20, v0.t
+# CHECK-INST: vwaddu.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xc0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a c0 <unknown>
+
+vwaddu.vv v8, v4, v20
+# CHECK-INST: vwaddu.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xc2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a c2 <unknown>
+
+vwaddu.vx v8, v4, a0, v0.t
+# CHECK-INST: vwaddu.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0xc0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 c0 <unknown>
+
+vwaddu.vx v8, v4, a0
+# CHECK-INST: vwaddu.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0xc2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 c2 <unknown>
+
+vwadd.vv v8, v4, v20, v0.t
+# CHECK-INST: vwadd.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xc4]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a c4 <unknown>
+
+vwadd.vv v8, v4, v20
+# CHECK-INST: vwadd.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xc6]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a c6 <unknown>
+
+vwadd.vx v8, v4, a0, v0.t
+# CHECK-INST: vwadd.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0xc4]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 c4 <unknown>
+
+vwadd.vx v8, v4, a0
+# CHECK-INST: vwadd.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0xc6]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 c6 <unknown>
+
+vwaddu.wv v8, v4, v20, v0.t
+# CHECK-INST: vwaddu.wv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xd0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a d0 <unknown>
+
+vwaddu.wv v8, v4, v20
+# CHECK-INST: vwaddu.wv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xd2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a d2 <unknown>
+
+vwaddu.wx v8, v4, a0, v0.t
+# CHECK-INST: vwaddu.wx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0xd0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 d0 <unknown>
+
+vwaddu.wx v8, v4, a0
+# CHECK-INST: vwaddu.wx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0xd2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 d2 <unknown>
+
+vwadd.wv v8, v4, v20, v0.t
+# CHECK-INST: vwadd.wv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xd4]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a d4 <unknown>
+
+vwadd.wv v8, v4, v20
+# CHECK-INST: vwadd.wv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xd6]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a d6 <unknown>
+
+vwadd.wx v8, v4, a0, v0.t
+# CHECK-INST: vwadd.wx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0xd4]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 d4 <unknown>
+
+vwadd.wx v8, v4, a0
+# CHECK-INST: vwadd.wx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0xd6]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 d6 <unknown>
+
+vadc.vvm v8, v4, v20, v0
+# CHECK-INST: vadc.vvm v8, v4, v20, v0
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x40]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 40 <unknown>
+
+vadc.vxm v8, v4, a0, v0
+# CHECK-INST: vadc.vxm v8, v4, a0, v0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x40]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 40 <unknown>
+
+vadc.vim v8, v4, 15, v0
+# CHECK-INST: vadc.vim v8, v4, 15, v0
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x40]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 40 <unknown>
+
+vmadc.vvm v8, v4, v20, v0
+# CHECK-INST: vmadc.vvm v8, v4, v20, v0
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x44]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 44 <unknown>
+
+vmadc.vxm v8, v4, a0, v0
+# CHECK-INST: vmadc.vxm v8, v4, a0, v0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x44]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 44 <unknown>
+
+vmadc.vim v8, v4, 15, v0
+# CHECK-INST: vmadc.vim v8, v4, 15, v0
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x44]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 44 <unknown>
+
+vmadc.vv v8, v4, v20
+# CHECK-INST: vmadc.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x46]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 46 <unknown>
+
+vmadc.vx v8, v4, a0
+# CHECK-INST: vmadc.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x46]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 46 <unknown>
+
+vmadc.vi v8, v4, 15
+# CHECK-INST: vmadc.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x46]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 46 <unknown>
+
+vsaddu.vv v8, v4, v20, v0.t
+# CHECK-INST: vsaddu.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x80]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 80 <unknown>
+
+vsaddu.vv v8, v4, v20
+# CHECK-INST: vsaddu.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x82]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 82 <unknown>
+
+vsaddu.vx v8, v4, a0, v0.t
+# CHECK-INST: vsaddu.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x80]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 80 <unknown>
+
+vsaddu.vx v8, v4, a0
+# CHECK-INST: vsaddu.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x82]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 82 <unknown>
+
+vsaddu.vi v8, v4, 15, v0.t
+# CHECK-INST: vsaddu.vi v8, v4, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x80]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 80 <unknown>
+
+vsaddu.vi v8, v4, 15
+# CHECK-INST: vsaddu.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x82]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 82 <unknown>
+
+vsadd.vv v8, v4, v20, v0.t
+# CHECK-INST: vsadd.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x84]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 84 <unknown>
+
+vsadd.vv v8, v4, v20
+# CHECK-INST: vsadd.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x86]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 86 <unknown>
+
+vsadd.vx v8, v4, a0, v0.t
+# CHECK-INST: vsadd.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x84]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 84 <unknown>
+
+vsadd.vx v8, v4, a0
+# CHECK-INST: vsadd.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x86]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 86 <unknown>
+
+vsadd.vi v8, v4, 15, v0.t
+# CHECK-INST: vsadd.vi v8, v4, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x84]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 84 <unknown>
+
+vsadd.vi v8, v4, 15
+# CHECK-INST: vsadd.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x86]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 86 <unknown>
+
+vaadd.vv v8, v4, v20, v0.t
+# CHECK-INST: vaadd.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x24]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 24 <unknown>
+
+vaadd.vv v8, v4, v20
+# CHECK-INST: vaadd.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x26]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 26 <unknown>
+
+vaadd.vx v8, v4, a0, v0.t
+# CHECK-INST: vaadd.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0x24]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 24 <unknown>
+
+vaadd.vx v8, v4, a0
+# CHECK-INST: vaadd.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0x26]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 26 <unknown>
+
+vaaddu.vv v8, v4, v20, v0.t
+# CHECK-INST: vaaddu.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x20]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 20 <unknown>
+
+vaaddu.vv v8, v4, v20
+# CHECK-INST: vaaddu.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x22]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 22 <unknown>
+
+vaaddu.vx v8, v4, a0, v0.t
+# CHECK-INST: vaaddu.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0x20]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 20 <unknown>
+
+vaaddu.vx v8, v4, a0
+# CHECK-INST: vaaddu.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0x22]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 22 <unknown>
+
+vwcvt.x.x.v v8, v4, v0.t
+# CHECK-INST: vwcvt.x.x.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x40,0xc4]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 40 c4 <unknown>
+
+vwcvt.x.x.v v8, v4
+# CHECK-INST: vwadd.vx v8, v4, zero
+# CHECK-ENCODING: [0x57,0x64,0x40,0xc6]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 40 c6 <unknown>
+
+vwcvtu.x.x.v v8, v4, v0.t
+# CHECK-INST: vwcvtu.x.x.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x40,0xc0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 40 c0 <unknown>
+
+vwcvtu.x.x.v v8, v4
+# CHECK-INST: vwaddu.vx v8, v4, zero
+# CHECK-ENCODING: [0x57,0x64,0x40,0xc2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 40 c2 <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/and.s b/llvm/test/MC/RISCV/rvv/and.s
@@ -0,0 +1,45 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-v - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vand.vv v8, v4, v20, v0.t
+# CHECK-INST: vand.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x24]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 24 <unknown>
+
+vand.vv v8, v4, v20
+# CHECK-INST: vand.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x26]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 26 <unknown>
+
+vand.vx v8, v4, a0, v0.t
+# CHECK-INST: vand.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x24]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 24 <unknown>
+
+vand.vx v8, v4, a0
+# CHECK-INST: vand.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x26]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 26 <unknown>
+
+vand.vi v8, v4, 15, v0.t
+# CHECK-INST: vand.vi v8, v4, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x24]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 24 <unknown>
+
+vand.vi v8, v4, 15
+# CHECK-INST: vand.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x26]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 26 <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/clip.s b/llvm/test/MC/RISCV/rvv/clip.s
@@ -0,0 +1,81 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-v - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vnclipu.wv v8, v4, v20, v0.t
+# CHECK-INST: vnclipu.wv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xb8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a b8 <unknown>
+
+vnclipu.wv v8, v4, v20
+# CHECK-INST: vnclipu.wv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xba]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a ba <unknown>
+
+vnclipu.wx v8, v4, a0, v0.t
+# CHECK-INST: vnclipu.wx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0xb8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 b8 <unknown>
+
+vnclipu.wx v8, v4, a0
+# CHECK-INST: vnclipu.wx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0xba]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 ba <unknown>
+
+vnclipu.wi v8, v4, 31, v0.t
+# CHECK-INST: vnclipu.wi v8, v4, 31, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0xb8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 4f b8 <unknown>
+
+vnclipu.wi v8, v4, 31
+# CHECK-INST: vnclipu.wi v8, v4, 31
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0xba]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 4f ba <unknown>
+
+vnclip.wv v8, v4, v20, v0.t
+# CHECK-INST: vnclip.wv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xbc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a bc <unknown>
+
+vnclip.wv v8, v4, v20
+# CHECK-INST: vnclip.wv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xbe]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a be <unknown>
+
+vnclip.wx v8, v4, a0, v0.t
+# CHECK-INST: vnclip.wx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0xbc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 bc <unknown>
+
+vnclip.wx v8, v4, a0
+# CHECK-INST: vnclip.wx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0xbe]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 be <unknown>
+
+vnclip.wi v8, v4, 31, v0.t
+# CHECK-INST: vnclip.wi v8, v4, 31, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0xbc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 4f bc <unknown>
+
+vnclip.wi v8, v4, 31
+# CHECK-INST: vnclip.wi v8, v4, 31
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0xbe]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 4f be <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/compare.s b/llvm/test/MC/RISCV/rvv/compare.s
@@ -0,0 +1,345 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-v - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vmseq.vv v8, v4, v20, v0.t
+# CHECK-INST: vmseq.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x60]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 60 <unknown>
+
+vmseq.vv v8, v4, v20
+# CHECK-INST: vmseq.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x62]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 62 <unknown>
+
+vmseq.vx v8, v4, a0, v0.t
+# CHECK-INST: vmseq.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x60]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 60 <unknown>
+
+vmseq.vx v8, v4, a0
+# CHECK-INST: vmseq.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x62]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 62 <unknown>
+
+vmseq.vi v8, v4, 15, v0.t
+# CHECK-INST: vmseq.vi v8, v4, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x60]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 60 <unknown>
+
+vmseq.vi v8, v4, 15
+# CHECK-INST: vmseq.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x62]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 62 <unknown>
+
+vmsne.vv v8, v4, v20, v0.t
+# CHECK-INST: vmsne.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x64]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 64 <unknown>
+
+vmsne.vv v8, v4, v20
+# CHECK-INST: vmsne.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x66]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 66 <unknown>
+
+vmsne.vx v8, v4, a0, v0.t
+# CHECK-INST: vmsne.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x64]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 64 <unknown>
+
+vmsne.vx v8, v4, a0
+# CHECK-INST: vmsne.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x66]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 66 <unknown>
+
+vmsne.vi v8, v4, 15, v0.t
+# CHECK-INST: vmsne.vi v8, v4, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x64]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 64 <unknown>
+
+vmsne.vi v8, v4, 15
+# CHECK-INST: vmsne.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x66]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 66 <unknown>
+
+vmsltu.vv v8, v4, v20, v0.t
+# CHECK-INST: vmsltu.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x68]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 68 <unknown>
+
+vmsltu.vv v8, v4, v20
+# CHECK-INST: vmsltu.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x6a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 6a <unknown>
+
+vmsltu.vx v8, v4, a0, v0.t
+# CHECK-INST: vmsltu.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x68]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 68 <unknown>
+
+vmsltu.vx v8, v4, a0
+# CHECK-INST: vmsltu.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x6a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 6a <unknown>
+
+vmslt.vv v8, v4, v20, v0.t
+# CHECK-INST: vmslt.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x6c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 6c <unknown>
+
+vmslt.vv v8, v4, v20
+# CHECK-INST: vmslt.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x6e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 6e <unknown>
+
+vmslt.vx v8, v4, a0, v0.t
+# CHECK-INST: vmslt.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x6c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 6c <unknown>
+
+vmslt.vx v8, v4, a0
+# CHECK-INST: vmslt.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x6e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 6e <unknown>
+
+vmsleu.vv v8, v4, v20, v0.t
+# CHECK-INST: vmsleu.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x70]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 70 <unknown>
+
+vmsleu.vv v8, v4, v20
+# CHECK-INST: vmsleu.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x72]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 72 <unknown>
+
+vmsleu.vx v8, v4, a0, v0.t
+# CHECK-INST: vmsleu.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x70]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 70 <unknown>
+
+vmsleu.vx v8, v4, a0
+# CHECK-INST: vmsleu.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x72]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 72 <unknown>
+
+vmsleu.vi v8, v4, 15, v0.t
+# CHECK-INST: vmsleu.vi v8, v4, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x70]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 70 <unknown>
+
+vmsleu.vi v8, v4, 15
+# CHECK-INST: vmsleu.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x72]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 72 <unknown>
+
+vmsle.vv v8, v4, v20, v0.t
+# CHECK-INST: vmsle.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x74]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 74 <unknown>
+
+vmsle.vv v8, v4, v20
+# CHECK-INST: vmsle.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x76]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 76 <unknown>
+
+vmsle.vx v8, v4, a0, v0.t
+# CHECK-INST: vmsle.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x74]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 74 <unknown>
+
+vmsle.vx v8, v4, a0
+# CHECK-INST: vmsle.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x76]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 76 <unknown>
+
+vmsle.vi v8, v4, 15, v0.t
+# CHECK-INST: vmsle.vi v8, v4, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x74]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 74 <unknown>
+
+vmsle.vi v8, v4, 15
+# CHECK-INST: vmsle.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x76]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 76 <unknown>
+
+vmsgtu.vx v8, v4, a0, v0.t
+# CHECK-INST: vmsgtu.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x78]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 78 <unknown>
+
+vmsgtu.vx v8, v4, a0
+# CHECK-INST: vmsgtu.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x7a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 7a <unknown>
+
+vmsgtu.vi v8, v4, 15, v0.t
+# CHECK-INST: vmsgtu.vi v8, v4, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x78]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 78 <unknown>
+
+vmsgtu.vi v8, v4, 15
+# CHECK-INST: vmsgtu.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x7a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 7a <unknown>
+
+vmsgt.vx v8, v4, a0, v0.t
+# CHECK-INST: vmsgt.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x7c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 7c <unknown>
+
+vmsgt.vx v8, v4, a0
+# CHECK-INST: vmsgt.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x7e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 7e <unknown>
+
+vmsgt.vi v8, v4, 15, v0.t
+# CHECK-INST: vmsgt.vi v8, v4, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x7c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 7c <unknown>
+
+vmsgt.vi v8, v4, 15
+# CHECK-INST: vmsgt.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x7e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 7e <unknown>
+
+vmsgtu.vv v8, v20, v4, v0.t
+# CHECK-INST: vmsltu.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x68]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 68 <unknown>
+
+vmsgtu.vv v8, v20, v4
+# CHECK-INST: vmsltu.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x6a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 6a <unknown>
+
+vmsgt.vv v8, v20, v4, v0.t
+# CHECK-INST: vmslt.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x6c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 6c <unknown>
+
+vmsgt.vv v8, v20, v4
+# CHECK-INST: vmslt.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x6e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 6e <unknown>
+
+vmsgeu.vv v8, v20, v4, v0.t
+# CHECK-INST: vmsleu.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x70]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 70 <unknown>
+
+vmsgeu.vv v8, v20, v4
+# CHECK-INST: vmsleu.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x72]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 72 <unknown>
+
+vmsge.vv v8, v20, v4, v0.t
+# CHECK-INST: vmsle.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x74]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 74 <unknown>
+
+vmsge.vv v8, v20, v4
+# CHECK-INST: vmsle.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x76]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 76 <unknown>
+
+vmsltu.vi v8, v4, 16, v0.t
+# CHECK-INST: vmsleu.vi v8, v4, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x70]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 70 <unknown>
+
+vmsltu.vi v8, v4, 16
+# CHECK-INST: vmsleu.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x72]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 72 <unknown>
+
+vmslt.vi v8, v4, 16, v0.t
+# CHECK-INST: vmsle.vi v8, v4, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x74]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 74 <unknown>
+
+vmslt.vi v8, v4, 16
+# CHECK-INST: vmsle.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x76]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 76 <unknown>
+
+vmsgeu.vi v8, v4, 16, v0.t
+# CHECK-INST: vmsgtu.vi v8, v4, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x78]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 78 <unknown>
+
+vmsgeu.vi v8, v4, 16
+# CHECK-INST: vmsgtu.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x7a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 7a <unknown>
+
+vmsge.vi v8, v4, 16, v0.t
+# CHECK-INST: vmsgt.vi v8, v4, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x7c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 7c <unknown>
+
+vmsge.vi v8, v4, 16
+# CHECK-INST: vmsgt.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x7e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 7e <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/convert.s b/llvm/test/MC/RISCV/rvv/convert.s
@@ -0,0 +1,189 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-v - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vfcvt.xu.f.v v8, v4, v0.t
+# CHECK-INST: vfcvt.xu.f.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x40,0x88]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 40 88 <unknown>
+
+vfcvt.xu.f.v v8, v4
+# CHECK-INST: vfcvt.xu.f.v v8, v4
+# CHECK-ENCODING: [0x57,0x14,0x40,0x8a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 40 8a <unknown>
+
+vfcvt.x.f.v v8, v4, v0.t
+# CHECK-INST: vfcvt.x.f.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x94,0x40,0x88]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 94 40 88 <unknown>
+
+vfcvt.x.f.v v8, v4
+# CHECK-INST: vfcvt.x.f.v v8, v4
+# CHECK-ENCODING: [0x57,0x94,0x40,0x8a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 94 40 8a <unknown>
+
+vfcvt.f.xu.v v8, v4, v0.t
+# CHECK-INST: vfcvt.f.xu.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x41,0x88]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 41 88 <unknown>
+
+vfcvt.f.xu.v v8, v4
+# CHECK-INST: vfcvt.f.xu.v v8, v4
+# CHECK-ENCODING: [0x57,0x14,0x41,0x8a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 41 8a <unknown>
+
+vfcvt.f.x.v v8, v4, v0.t
+# CHECK-INST: vfcvt.f.x.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x94,0x41,0x88]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 94 41 88 <unknown>
+
+vfcvt.f.x.v v8, v4
+# CHECK-INST: vfcvt.f.x.v v8, v4
+# CHECK-ENCODING: [0x57,0x94,0x41,0x8a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 94 41 8a <unknown>
+
+vfwcvt.xu.f.v v8, v4, v0.t
+# CHECK-INST: vfwcvt.xu.f.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x44,0x88]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 44 88 <unknown>
+
+vfwcvt.xu.f.v v8, v4
+# CHECK-INST: vfwcvt.xu.f.v v8, v4
+# CHECK-ENCODING: [0x57,0x14,0x44,0x8a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 44 8a <unknown>
+
+vfwcvt.x.f.v v8, v4, v0.t
+# CHECK-INST: vfwcvt.x.f.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x94,0x44,0x88]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 94 44 88 <unknown>
+
+vfwcvt.x.f.v v8, v4
+# CHECK-INST: vfwcvt.x.f.v v8, v4
+# CHECK-ENCODING: [0x57,0x94,0x44,0x8a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 94 44 8a <unknown>
+
+vfwcvt.f.xu.v v8, v4, v0.t
+# CHECK-INST: vfwcvt.f.xu.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x45,0x88]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 45 88 <unknown>
+
+vfwcvt.f.xu.v v8, v4
+# CHECK-INST: vfwcvt.f.xu.v v8, v4
+# CHECK-ENCODING: [0x57,0x14,0x45,0x8a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 45 8a <unknown>
+
+vfwcvt.f.x.v v8, v4, v0.t
+# CHECK-INST: vfwcvt.f.x.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x94,0x45,0x88]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 94 45 88 <unknown>
+
+vfwcvt.f.x.v v8, v4
+# CHECK-INST: vfwcvt.f.x.v v8, v4
+# CHECK-ENCODING: [0x57,0x94,0x45,0x8a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 94 45 8a <unknown>
+
+vfwcvt.f.f.v v8, v4, v0.t
+# CHECK-INST: vfwcvt.f.f.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x46,0x88]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 46 88 <unknown>
+
+vfwcvt.f.f.v v8, v4
+# CHECK-INST: vfwcvt.f.f.v v8, v4
+# CHECK-ENCODING: [0x57,0x14,0x46,0x8a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 46 8a <unknown>
+
+vfncvt.xu.f.w v8, v4, v0.t
+# CHECK-INST: vfncvt.xu.f.w v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x48,0x88]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 48 88 <unknown>
+
+vfncvt.xu.f.w v8, v4
+# CHECK-INST: vfncvt.xu.f.w v8, v4
+# CHECK-ENCODING: [0x57,0x14,0x48,0x8a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 48 8a <unknown>
+
+vfncvt.x.f.w v8, v4, v0.t
+# CHECK-INST: vfncvt.x.f.w v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x94,0x48,0x88]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 94 48 88 <unknown>
+
+vfncvt.x.f.w v8, v4
+# CHECK-INST: vfncvt.x.f.w v8, v4
+# CHECK-ENCODING: [0x57,0x94,0x48,0x8a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 94 48 8a <unknown>
+
+vfncvt.f.xu.w v8, v4, v0.t
+# CHECK-INST: vfncvt.f.xu.w v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x49,0x88]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 49 88 <unknown>
+
+vfncvt.f.xu.w v8, v4
+# CHECK-INST: vfncvt.f.xu.w v8, v4
+# CHECK-ENCODING: [0x57,0x14,0x49,0x8a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 49 8a <unknown>
+
+vfncvt.f.x.w v8, v4, v0.t
+# CHECK-INST: vfncvt.f.x.w v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x94,0x49,0x88]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 94 49 88 <unknown>
+
+vfncvt.f.x.w v8, v4
+# CHECK-INST: vfncvt.f.x.w v8, v4
+# CHECK-ENCODING: [0x57,0x94,0x49,0x8a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 94 49 8a <unknown>
+
+vfncvt.f.f.w v8, v4, v0.t
+# CHECK-INST: vfncvt.f.f.w v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x88]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 88 <unknown>
+
+vfncvt.f.f.w v8, v4
+# CHECK-INST: vfncvt.f.f.w v8, v4
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x8a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 8a <unknown>
+
+vfncvt.rod.f.f.w v8, v4, v0.t
+# CHECK-INST: vfncvt.rod.f.f.w v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x94,0x4a,0x88]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 94 4a 88 <unknown>
+
+vfncvt.rod.f.f.w v8, v4
+# CHECK-INST: vfncvt.rod.f.f.w v8, v4
+# CHECK-ENCODING: [0x57,0x94,0x4a,0x8a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 94 4a 8a <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/div.s b/llvm/test/MC/RISCV/rvv/div.s
@@ -0,0 +1,105 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-v - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vdivu.vv v8, v4, v20, v0.t
+# CHECK-INST: vdivu.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x80]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 80 <unknown>
+
+vdivu.vv v8, v4, v20
+# CHECK-INST: vdivu.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x82]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 82 <unknown>
+
+vdivu.vx v8, v4, a0, v0.t
+# CHECK-INST: vdivu.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0x80]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 80 <unknown>
+
+vdivu.vx v8, v4, a0
+# CHECK-INST: vdivu.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0x82]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 82 <unknown>
+
+vdiv.vv v8, v4, v20, v0.t
+# CHECK-INST: vdiv.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x84]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 84 <unknown>
+
+vdiv.vv v8, v4, v20
+# CHECK-INST: vdiv.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x86]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 86 <unknown>
+
+vdiv.vx v8, v4, a0, v0.t
+# CHECK-INST: vdiv.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0x84]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 84 <unknown>
+
+vdiv.vx v8, v4, a0
+# CHECK-INST: vdiv.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0x86]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 86 <unknown>
+
+vremu.vv v8, v4, v20, v0.t
+# CHECK-INST: vremu.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x88]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 88 <unknown>
+
+vremu.vv v8, v4, v20
+# CHECK-INST: vremu.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x8a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 8a <unknown>
+
+vremu.vx v8, v4, a0, v0.t
+# CHECK-INST: vremu.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0x88]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 88 <unknown>
+
+vremu.vx v8, v4, a0
+# CHECK-INST: vremu.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0x8a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 8a <unknown>
+
+vrem.vv v8, v4, v20, v0.t
+# CHECK-INST: vrem.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x8c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 8c <unknown>
+
+vrem.vv v8, v4, v20
+# CHECK-INST: vrem.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x8e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 8e <unknown>
+
+vrem.vx v8, v4, a0, v0.t
+# CHECK-INST: vrem.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0x8c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 8c <unknown>
+
+vrem.vx v8, v4, a0
+# CHECK-INST: vrem.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0x8e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 8e <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/fadd.s b/llvm/test/MC/RISCV/rvv/fadd.s
@@ -0,0 +1,81 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-v - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vfadd.vv v8, v4, v20, v0.t
+# CHECK-INST: vfadd.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x00]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 00 <unknown>
+
+vfadd.vv v8, v4, v20
+# CHECK-INST: vfadd.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x02]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 02 <unknown>
+
+vfadd.vf v8, v4, fa0, v0.t
+# CHECK-INST: vfadd.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x00]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 00 <unknown>
+
+vfadd.vf v8, v4, fa0
+# CHECK-INST: vfadd.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x02]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 02 <unknown>
+
+vfwadd.vv v8, v4, v20, v0.t
+# CHECK-INST: vfwadd.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xc0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a c0 <unknown>
+
+vfwadd.vv v8, v4, v20
+# CHECK-INST: vfwadd.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xc2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a c2 <unknown>
+
+vfwadd.vf v8, v4, fa0, v0.t
+# CHECK-INST: vfwadd.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xc0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 c0 <unknown>
+
+vfwadd.vf v8, v4, fa0
+# CHECK-INST: vfwadd.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0xc2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 c2 <unknown>
+
+vfwadd.wv v8, v4, v20, v0.t
+# CHECK-INST: vfwadd.wv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xd0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a d0 <unknown>
+
+vfwadd.wv v8, v4, v20
+# CHECK-INST: vfwadd.wv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xd2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a d2 <unknown>
+
+vfwadd.wf v8, v4, fa0, v0.t
+# CHECK-INST: vfwadd.wf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xd0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 d0 <unknown>
+
+vfwadd.wf v8, v4, fa0
+# CHECK-INST: vfwadd.wf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0xd2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 d2 <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/fcompare.s b/llvm/test/MC/RISCV/rvv/fcompare.s
@@ -0,0 +1,153 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-v - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vmfeq.vv v8, v4, v20, v0.t
+# CHECK-INST: vmfeq.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x60]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 60 <unknown>
+
+vmfeq.vv v8, v4, v20
+# CHECK-INST: vmfeq.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x62]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 62 <unknown>
+
+vmfeq.vf v8, v4, fa0, v0.t
+# CHECK-INST: vmfeq.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x60]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 60 <unknown>
+
+vmfeq.vf v8, v4, fa0
+# CHECK-INST: vmfeq.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x62]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 62 <unknown>
+
+vmfne.vv v8, v4, v20, v0.t
+# CHECK-INST: vmfne.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x70]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 70 <unknown>
+
+vmfne.vv v8, v4, v20
+# CHECK-INST: vmfne.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x72]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 72 <unknown>
+
+vmfne.vf v8, v4, fa0, v0.t
+# CHECK-INST: vmfne.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x70]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 70 <unknown>
+
+vmfne.vf v8, v4, fa0
+# CHECK-INST: vmfne.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x72]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 72 <unknown>
+
+vmflt.vv v8, v4, v20, v0.t
+# CHECK-INST: vmflt.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x6c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 6c <unknown>
+
+vmflt.vv v8, v4, v20
+# CHECK-INST: vmflt.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x6e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 6e <unknown>
+
+vmflt.vf v8, v4, fa0, v0.t
+# CHECK-INST: vmflt.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x6c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 6c <unknown>
+
+vmflt.vf v8, v4, fa0
+# CHECK-INST: vmflt.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x6e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 6e <unknown>
+
+vmfle.vv v8, v4, v20, v0.t
+# CHECK-INST: vmfle.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x64]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 64 <unknown>
+
+vmfle.vv v8, v4, v20
+# CHECK-INST: vmfle.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x66]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 66 <unknown>
+
+vmfle.vf v8, v4, fa0, v0.t
+# CHECK-INST: vmfle.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x64]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 64 <unknown>
+
+vmfle.vf v8, v4, fa0
+# CHECK-INST: vmfle.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x66]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 66 <unknown>
+
+vmfgt.vf v8, v4, fa0, v0.t
+# CHECK-INST: vmfgt.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x74]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 74 <unknown>
+
+vmfgt.vf v8, v4, fa0
+# CHECK-INST: vmfgt.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x76]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 76 <unknown>
+
+vmfge.vf v8, v4, fa0, v0.t
+# CHECK-INST: vmfge.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x7c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 7c <unknown>
+
+vmfge.vf v8, v4, fa0
+# CHECK-INST: vmfge.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x7e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 7e <unknown>
+
+vmfgt.vv v8, v20, v4, v0.t
+# CHECK-INST: vmflt.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x6c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 6c <unknown>
+
+vmfgt.vv v8, v20, v4
+# CHECK-INST: vmflt.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x6e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 6e <unknown>
+
+vmfge.vv v8, v20, v4, v0.t
+# CHECK-INST: vmfle.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x64]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 64 <unknown>
+
+vmfge.vv v8, v20, v4
+# CHECK-INST: vmfle.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x66]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 66 <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/fdiv.s b/llvm/test/MC/RISCV/rvv/fdiv.s
@@ -0,0 +1,45 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-v - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vfdiv.vv v8, v4, v20, v0.t
+# CHECK-INST: vfdiv.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x80]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 80 <unknown>
+
+vfdiv.vv v8, v4, v20
+# CHECK-INST: vfdiv.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x82]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 82 <unknown>
+
+vfdiv.vf v8, v4, fa0, v0.t
+# CHECK-INST: vfdiv.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x80]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 80 <unknown>
+
+vfdiv.vf v8, v4, fa0
+# CHECK-INST: vfdiv.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x82]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 82 <unknown>
+
+vfrdiv.vf v8, v4, fa0, v0.t
+# CHECK-INST: vfrdiv.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x84]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 84 <unknown>
+
+vfrdiv.vf v8, v4, fa0
+# CHECK-INST: vfrdiv.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x86]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 86 <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/fmacc.s b/llvm/test/MC/RISCV/rvv/fmacc.s
@@ -0,0 +1,297 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-v - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vfmacc.vv v8, v20, v4, v0.t
+# CHECK-INST: vfmacc.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xb0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a b0 <unknown>
+
+vfmacc.vv v8, v20, v4
+# CHECK-INST: vfmacc.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xb2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a b2 <unknown>
+
+vfmacc.vf v8, fa0, v4, v0.t
+# CHECK-INST: vfmacc.vf v8, fa0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xb0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 b0 <unknown>
+
+vfmacc.vf v8, fa0, v4
+# CHECK-INST: vfmacc.vf v8, fa0, v4
+# CHECK-ENCODING: [0x57,0x54,0x45,0xb2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 b2 <unknown>
+
+vfnmacc.vv v8, v20, v4, v0.t
+# CHECK-INST: vfnmacc.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xb4]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a b4 <unknown>
+
+vfnmacc.vv v8, v20, v4
+# CHECK-INST: vfnmacc.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xb6]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a b6 <unknown>
+
+vfnmacc.vf v8, fa0, v4, v0.t
+# CHECK-INST: vfnmacc.vf v8, fa0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xb4]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 b4 <unknown>
+
+vfnmacc.vf v8, fa0, v4
+# CHECK-INST: vfnmacc.vf v8, fa0, v4
+# CHECK-ENCODING: [0x57,0x54,0x45,0xb6]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 b6 <unknown>
+
+vfmsac.vv v8, v20, v4, v0.t
+# CHECK-INST: vfmsac.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xb8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a b8 <unknown>
+
+vfmsac.vv v8, v20, v4
+# CHECK-INST: vfmsac.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xba]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a ba <unknown>
+
+vfmsac.vf v8, fa0, v4, v0.t
+# CHECK-INST: vfmsac.vf v8, fa0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xb8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 b8 <unknown>
+
+vfmsac.vf v8, fa0, v4
+# CHECK-INST: vfmsac.vf v8, fa0, v4
+# CHECK-ENCODING: [0x57,0x54,0x45,0xba]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 ba <unknown>
+
+vfnmsac.vv v8, v20, v4, v0.t
+# CHECK-INST: vfnmsac.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xbc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a bc <unknown>
+
+vfnmsac.vv v8, v20, v4
+# CHECK-INST: vfnmsac.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xbe]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a be <unknown>
+
+vfnmsac.vf v8, fa0, v4, v0.t
+# CHECK-INST: vfnmsac.vf v8, fa0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xbc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 bc <unknown>
+
+vfnmsac.vf v8, fa0, v4
+# CHECK-INST: vfnmsac.vf v8, fa0, v4
+# CHECK-ENCODING: [0x57,0x54,0x45,0xbe]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 be <unknown>
+
+vfmadd.vv v8, v20, v4, v0.t
+# CHECK-INST: vfmadd.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xa0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a a0 <unknown>
+
+vfmadd.vv v8, v20, v4
+# CHECK-INST: vfmadd.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xa2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a a2 <unknown>
+
+vfmadd.vf v8, fa0, v4, v0.t
+# CHECK-INST: vfmadd.vf v8, fa0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xa0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 a0 <unknown>
+
+vfmadd.vf v8, fa0, v4
+# CHECK-INST: vfmadd.vf v8, fa0, v4
+# CHECK-ENCODING: [0x57,0x54,0x45,0xa2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 a2 <unknown>
+
+vfnmadd.vv v8, v20, v4, v0.t
+# CHECK-INST: vfnmadd.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xa4]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a a4 <unknown>
+
+vfnmadd.vv v8, v20, v4
+# CHECK-INST: vfnmadd.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xa6]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a a6 <unknown>
+
+vfnmadd.vf v8, fa0, v4, v0.t
+# CHECK-INST: vfnmadd.vf v8, fa0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xa4]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 a4 <unknown>
+
+vfnmadd.vf v8, fa0, v4
+# CHECK-INST: vfnmadd.vf v8, fa0, v4
+# CHECK-ENCODING: [0x57,0x54,0x45,0xa6]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 a6 <unknown>
+
+vfmsub.vv v8, v20, v4, v0.t
+# CHECK-INST: vfmsub.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xa8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a a8 <unknown>
+
+vfmsub.vv v8, v20, v4
+# CHECK-INST: vfmsub.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xaa]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a aa <unknown>
+
+vfmsub.vf v8, fa0, v4, v0.t
+# CHECK-INST: vfmsub.vf v8, fa0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xa8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 a8 <unknown>
+
+vfmsub.vf v8, fa0, v4
+# CHECK-INST: vfmsub.vf v8, fa0, v4
+# CHECK-ENCODING: [0x57,0x54,0x45,0xaa]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 aa <unknown>
+
+vfnmsub.vv v8, v20, v4, v0.t
+# CHECK-INST: vfnmsub.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xac]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a ac <unknown>
+
+vfnmsub.vv v8, v20, v4
+# CHECK-INST: vfnmsub.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xae]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a ae <unknown>
+
+vfnmsub.vf v8, fa0, v4, v0.t
+# CHECK-INST: vfnmsub.vf v8, fa0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xac]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 ac <unknown>
+
+vfnmsub.vf v8, fa0, v4
+# CHECK-INST: vfnmsub.vf v8, fa0, v4
+# CHECK-ENCODING: [0x57,0x54,0x45,0xae]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 ae <unknown>
+
+vfwmacc.vv v8, v20, v4, v0.t
+# CHECK-INST: vfwmacc.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xf0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a f0 <unknown>
+
+vfwmacc.vv v8, v20, v4
+# CHECK-INST: vfwmacc.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xf2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a f2 <unknown>
+
+vfwmacc.vf v8, fa0, v4, v0.t
+# CHECK-INST: vfwmacc.vf v8, fa0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xf0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 f0 <unknown>
+
+vfwmacc.vf v8, fa0, v4
+# CHECK-INST: vfwmacc.vf v8, fa0, v4
+# CHECK-ENCODING: [0x57,0x54,0x45,0xf2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 f2 <unknown>
+
+vfwnmacc.vv v8, v20, v4, v0.t
+# CHECK-INST: vfwnmacc.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xf4]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a f4 <unknown>
+
+vfwnmacc.vv v8, v20, v4
+# CHECK-INST: vfwnmacc.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xf6]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a f6 <unknown>
+
+vfwnmacc.vf v8, fa0, v4, v0.t
+# CHECK-INST: vfwnmacc.vf v8, fa0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xf4]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 f4 <unknown>
+
+vfwnmacc.vf v8, fa0, v4
+# CHECK-INST: vfwnmacc.vf v8, fa0, v4
+# CHECK-ENCODING: [0x57,0x54,0x45,0xf6]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 f6 <unknown>
+
+vfwmsac.vv v8, v20, v4, v0.t
+# CHECK-INST: vfwmsac.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xf8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a f8 <unknown>
+
+vfwmsac.vv v8, v20, v4
+# CHECK-INST: vfwmsac.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xfa]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a fa <unknown>
+
+vfwmsac.vf v8, fa0, v4, v0.t
+# CHECK-INST: vfwmsac.vf v8, fa0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xf8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 f8 <unknown>
+
+vfwmsac.vf v8, fa0, v4
+# CHECK-INST: vfwmsac.vf v8, fa0, v4
+# CHECK-ENCODING: [0x57,0x54,0x45,0xfa]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 fa <unknown>
+
+vfwnmsac.vv v8, v20, v4, v0.t
+# CHECK-INST: vfwnmsac.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xfc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a fc <unknown>
+
+vfwnmsac.vv v8, v20, v4
+# CHECK-INST: vfwnmsac.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xfe]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a fe <unknown>
+
+vfwnmsac.vf v8, fa0, v4, v0.t
+# CHECK-INST: vfwnmsac.vf v8, fa0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xfc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 fc <unknown>
+
+vfwnmsac.vf v8, fa0, v4
+# CHECK-INST: vfwnmsac.vf v8, fa0, v4
+# CHECK-ENCODING: [0x57,0x54,0x45,0xfe]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 fe <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/fminmax.s b/llvm/test/MC/RISCV/rvv/fminmax.s
@@ -0,0 +1,57 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-v - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vfmin.vv v8, v4, v20, v0.t
+# CHECK-INST: vfmin.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x10]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 10 <unknown>
+
+vfmin.vv v8, v4, v20
+# CHECK-INST: vfmin.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x12]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 12 <unknown>
+
+vfmin.vf v8, v4, fa0, v0.t
+# CHECK-INST: vfmin.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x10]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 10 <unknown>
+
+vfmin.vf v8, v4, fa0
+# CHECK-INST: vfmin.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x12]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 12 <unknown>
+
+vfmax.vv v8, v4, v20, v0.t
+# CHECK-INST: vfmax.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x18]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 18 <unknown>
+
+vfmax.vv v8, v4, v20
+# CHECK-INST: vfmax.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x1a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 1a <unknown>
+
+vfmax.vf v8, v4, fa0, v0.t
+# CHECK-INST: vfmax.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x18]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 18 <unknown>
+
+vfmax.vf v8, v4, fa0
+# CHECK-INST: vfmax.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x1a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 1a <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/fmul.s b/llvm/test/MC/RISCV/rvv/fmul.s
@@ -0,0 +1,57 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-v - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vfmul.vv v8, v4, v20, v0.t
+# CHECK-INST: vfmul.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x90]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 90 <unknown>
+
+vfmul.vv v8, v4, v20
+# CHECK-INST: vfmul.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x92]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 92 <unknown>
+
+vfmul.vf v8, v4, fa0, v0.t
+# CHECK-INST: vfmul.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x90]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 90 <unknown>
+
+vfmul.vf v8, v4, fa0
+# CHECK-INST: vfmul.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x92]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 92 <unknown>
+
+vfwmul.vv v8, v4, v20, v0.t
+# CHECK-INST: vfwmul.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xe0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a e0 <unknown>
+
+vfwmul.vv v8, v4, v20
+# CHECK-INST: vfwmul.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xe2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a e2 <unknown>
+
+vfwmul.vf v8, v4, fa0, v0.t
+# CHECK-INST: vfwmul.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xe0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 e0 <unknown>
+
+vfwmul.vf v8, v4, fa0
+# CHECK-INST: vfwmul.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0xe2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 e2 <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/fmv.s b/llvm/test/MC/RISCV/rvv/fmv.s
@@ -0,0 +1,27 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-v - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vfmv.v.f v8, fa0
+# CHECK-INST: vfmv.v.f v8, fa0
+# CHECK-ENCODING: [0x57,0x54,0x05,0x5e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 05 5e <unknown>
+
+vfmv.f.s fa0, v4
+# CHECK-INST: vfmv.f.s fa0, v4
+# CHECK-ENCODING: [0x57,0x15,0x40,0x42]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 15 40 42 <unknown>
+
+vfmv.s.f v8, fa0
+# CHECK-INST: vfmv.s.f v8, fa0
+# CHECK-ENCODING: [0x57,0x54,0x05,0x42]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 05 42 <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/fothers.s b/llvm/test/MC/RISCV/rvv/fothers.s
@@ -0,0 +1,39 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-v - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vfsqrt.v v8, v4, v0.t
+# CHECK-INST: vfsqrt.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x40,0x8c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 40 8c <unknown>
+
+vfsqrt.v v8, v4
+# CHECK-INST: vfsqrt.v v8, v4
+# CHECK-ENCODING: [0x57,0x14,0x40,0x8e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 40 8e <unknown>
+
+vfclass.v v8, v4, v0.t
+# CHECK-INST: vfclass.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x48,0x8c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 48 8c <unknown>
+
+vfclass.v v8, v4
+# CHECK-INST: vfclass.v v8, v4
+# CHECK-ENCODING: [0x57,0x14,0x48,0x8e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 48 8e <unknown>
+
+vfmerge.vfm v8, v4, fa0, v0
+# CHECK-INST: vfmerge.vfm v8, v4, fa0, v0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x5c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 5c <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/freduction.s b/llvm/test/MC/RISCV/rvv/freduction.s
@@ -0,0 +1,81 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-v - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vfredosum.vs v8, v4, v20, v0.t
+# CHECK-INST: vfredosum.vs v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x0c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 0c <unknown>
+
+vfredosum.vs v8, v4, v20
+# CHECK-INST: vfredosum.vs v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x0e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 0e <unknown>
+
+vfredsum.vs v8, v4, v20, v0.t
+# CHECK-INST: vfredsum.vs v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x04]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 04 <unknown>
+
+vfredsum.vs v8, v4, v20
+# CHECK-INST: vfredsum.vs v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x06]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 06 <unknown>
+
+vfredmax.vs v8, v4, v20, v0.t
+# CHECK-INST: vfredmax.vs v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x1c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 1c <unknown>
+
+vfredmax.vs v8, v4, v20
+# CHECK-INST: vfredmax.vs v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x1e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 1e <unknown>
+
+vfredmin.vs v8, v4, v20, v0.t
+# CHECK-INST: vfredmin.vs v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x14]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 14 <unknown>
+
+vfredmin.vs v8, v4, v20
+# CHECK-INST: vfredmin.vs v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x16]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 16 <unknown>
+
+vfwredosum.vs v8, v4, v20, v0.t
+# CHECK-INST: vfwredosum.vs v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xcc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a cc <unknown>
+
+vfwredosum.vs v8, v4, v20
+# CHECK-INST: vfwredosum.vs v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xce]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a ce <unknown>
+
+vfwredsum.vs v8, v4, v20, v0.t
+# CHECK-INST: vfwredsum.vs v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xc4]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a c4 <unknown>
+
+vfwredsum.vs v8, v4, v20
+# CHECK-INST: vfwredsum.vs v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xc6]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a c6 <unknown>