84 changes: 42 additions & 42 deletions llvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@ define i32 @grev32(i32 %a, i32 %b) nounwind {
; RV32ZBP-NEXT: grev a0, a0, a1
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 %b)
ret i32 %tmp
ret i32 %tmp
}

define i32 @grev32_demandedbits(i32 %a, i32 %b) nounwind {
Expand All @@ -29,7 +29,7 @@ define i32 @grevi32(i32 %a) nounwind {
; RV32ZBP-NEXT: grevi a0, a0, 13
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 13)
ret i32 %tmp
ret i32 %tmp
}

define i32 @revi32(i32 %a) nounwind {
Expand All @@ -38,7 +38,7 @@ define i32 @revi32(i32 %a) nounwind {
; RV32ZBP-NEXT: rev a0, a0
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 31)
ret i32 %tmp
ret i32 %tmp
}

define i32 @rev2i32(i32 %a) nounwind {
Expand All @@ -47,7 +47,7 @@ define i32 @rev2i32(i32 %a) nounwind {
; RV32ZBP-NEXT: rev2 a0, a0
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 30)
ret i32 %tmp
ret i32 %tmp
}

define i32 @rev4i32(i32 %a) nounwind {
Expand All @@ -56,7 +56,7 @@ define i32 @rev4i32(i32 %a) nounwind {
; RV32ZBP-NEXT: rev4 a0, a0
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 28)
ret i32 %tmp
ret i32 %tmp
}

define i32 @rev8i32(i32 %a) nounwind {
Expand All @@ -65,7 +65,7 @@ define i32 @rev8i32(i32 %a) nounwind {
; RV32ZBP-NEXT: rev8 a0, a0
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 24)
ret i32 %tmp
ret i32 %tmp
}

define i32 @rev16i32(i32 %a) nounwind {
Expand All @@ -74,7 +74,7 @@ define i32 @rev16i32(i32 %a) nounwind {
; RV32ZBP-NEXT: rev16 a0, a0
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 16)
ret i32 %tmp
ret i32 %tmp
}

declare i32 @llvm.riscv.gorc.i32(i32 %a, i32 %b)
Expand All @@ -85,7 +85,7 @@ define i32 @gorc32(i32 %a, i32 %b) nounwind {
; RV32ZBP-NEXT: gorc a0, a0, a1
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 %b)
ret i32 %tmp
ret i32 %tmp
}

define i32 @gorc32_demandedbits(i32 %a, i32 %b) nounwind {
Expand All @@ -104,7 +104,7 @@ define i32 @gorci32(i32 %a) nounwind {
; RV32ZBP-NEXT: gorci a0, a0, 13
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 13)
ret i32 %tmp
ret i32 %tmp
}

define i32 @orchi32(i32 %a) nounwind {
Expand All @@ -113,7 +113,7 @@ define i32 @orchi32(i32 %a) nounwind {
; RV32ZBP-NEXT: orc.h a0, a0
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 15)
ret i32 %tmp
ret i32 %tmp
}

define i32 @orc16i32(i32 %a) nounwind {
Expand All @@ -122,7 +122,7 @@ define i32 @orc16i32(i32 %a) nounwind {
; RV32ZBP-NEXT: orc16 a0, a0
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 16)
ret i32 %tmp
ret i32 %tmp
}

define i32 @orc8i32(i32 %a) nounwind {
Expand All @@ -131,7 +131,7 @@ define i32 @orc8i32(i32 %a) nounwind {
; RV32ZBP-NEXT: orc8 a0, a0
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 24)
ret i32 %tmp
ret i32 %tmp
}

define i32 @orc4i32(i32 %a) nounwind {
Expand All @@ -140,7 +140,7 @@ define i32 @orc4i32(i32 %a) nounwind {
; RV32ZBP-NEXT: orc4 a0, a0
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 28)
ret i32 %tmp
ret i32 %tmp
}

define i32 @orc2i32(i32 %a) nounwind {
Expand All @@ -149,7 +149,7 @@ define i32 @orc2i32(i32 %a) nounwind {
; RV32ZBP-NEXT: orc2 a0, a0
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 30)
ret i32 %tmp
ret i32 %tmp
}

define i32 @orci32(i32 %a) nounwind {
Expand All @@ -158,7 +158,7 @@ define i32 @orci32(i32 %a) nounwind {
; RV32ZBP-NEXT: orc a0, a0
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.gorc.i32(i32 %a, i32 31)
ret i32 %tmp
ret i32 %tmp
}

declare i32 @llvm.riscv.shfl.i32(i32 %a, i32 %b)
Expand All @@ -169,7 +169,7 @@ define i32 @shfl32(i32 %a, i32 %b) nounwind {
; RV32ZBP-NEXT: shfl a0, a0, a1
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.shfl.i32(i32 %a, i32 %b)
ret i32 %tmp
ret i32 %tmp
}

define i32 @shfl32_demandedbits(i32 %a, i32 %b) nounwind {
Expand All @@ -188,7 +188,7 @@ define i32 @zipni32(i32 %a) nounwind {
; RV32ZBP-NEXT: zip.n a0, a0
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.shfl.i32(i32 %a, i32 1)
ret i32 %tmp
ret i32 %tmp
}

define i32 @zip2bi32(i32 %a) nounwind {
Expand All @@ -197,7 +197,7 @@ define i32 @zip2bi32(i32 %a) nounwind {
; RV32ZBP-NEXT: zip2.b a0, a0
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.shfl.i32(i32 %a, i32 2)
ret i32 %tmp
ret i32 %tmp
}

define i32 @zipbi32(i32 %a) nounwind {
Expand All @@ -206,7 +206,7 @@ define i32 @zipbi32(i32 %a) nounwind {
; RV32ZBP-NEXT: zip.b a0, a0
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.shfl.i32(i32 %a, i32 3)
ret i32 %tmp
ret i32 %tmp
}

define i32 @zip4hi32(i32 %a) nounwind {
Expand All @@ -215,7 +215,7 @@ define i32 @zip4hi32(i32 %a) nounwind {
; RV32ZBP-NEXT: zip4.h a0, a0
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.shfl.i32(i32 %a, i32 4)
ret i32 %tmp
ret i32 %tmp
}

define i32 @zip2hi32(i32 %a) nounwind {
Expand All @@ -224,7 +224,7 @@ define i32 @zip2hi32(i32 %a) nounwind {
; RV32ZBP-NEXT: zip2.h a0, a0
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.shfl.i32(i32 %a, i32 6)
ret i32 %tmp
ret i32 %tmp
}

define i32 @ziphi32(i32 %a) nounwind {
Expand All @@ -233,7 +233,7 @@ define i32 @ziphi32(i32 %a) nounwind {
; RV32ZBP-NEXT: zip.h a0, a0
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.shfl.i32(i32 %a, i32 7)
ret i32 %tmp
ret i32 %tmp
}

define i32 @shfli32(i32 %a) nounwind {
Expand All @@ -242,7 +242,7 @@ define i32 @shfli32(i32 %a) nounwind {
; RV32ZBP-NEXT: shfli a0, a0, 13
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.shfl.i32(i32 %a, i32 13)
ret i32 %tmp
ret i32 %tmp
}

define i32 @zip4i32(i32 %a) nounwind {
Expand All @@ -251,7 +251,7 @@ define i32 @zip4i32(i32 %a) nounwind {
; RV32ZBP-NEXT: zip4 a0, a0
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.shfl.i32(i32 %a, i32 12)
ret i32 %tmp
ret i32 %tmp
}

define i32 @zip2i32(i32 %a) nounwind {
Expand All @@ -260,7 +260,7 @@ define i32 @zip2i32(i32 %a) nounwind {
; RV32ZBP-NEXT: zip2 a0, a0
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.shfl.i32(i32 %a, i32 14)
ret i32 %tmp
ret i32 %tmp
}

define i32 @zipi32(i32 %a) nounwind {
Expand All @@ -269,7 +269,7 @@ define i32 @zipi32(i32 %a) nounwind {
; RV32ZBP-NEXT: zip a0, a0
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.shfl.i32(i32 %a, i32 15)
ret i32 %tmp
ret i32 %tmp
}

define i32 @zip8i32(i32 %a) nounwind {
Expand All @@ -278,7 +278,7 @@ define i32 @zip8i32(i32 %a) nounwind {
; RV32ZBP-NEXT: zip8 a0, a0
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.shfl.i32(i32 %a, i32 8)
ret i32 %tmp
ret i32 %tmp
}

declare i32 @llvm.riscv.unshfl.i32(i32 %a, i32 %b)
Expand All @@ -289,7 +289,7 @@ define i32 @unshfl32(i32 %a, i32 %b) nounwind {
; RV32ZBP-NEXT: unshfl a0, a0, a1
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.unshfl.i32(i32 %a, i32 %b)
ret i32 %tmp
ret i32 %tmp
}

define i32 @unshfl32_demandedbits(i32 %a, i32 %b) nounwind {
Expand All @@ -308,7 +308,7 @@ define i32 @unzipni32(i32 %a) nounwind {
; RV32ZBP-NEXT: unzip.n a0, a0
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.unshfl.i32(i32 %a, i32 1)
ret i32 %tmp
ret i32 %tmp
}

define i32 @unzip2bi32(i32 %a) nounwind {
Expand All @@ -317,7 +317,7 @@ define i32 @unzip2bi32(i32 %a) nounwind {
; RV32ZBP-NEXT: unzip2.b a0, a0
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.unshfl.i32(i32 %a, i32 2)
ret i32 %tmp
ret i32 %tmp
}

define i32 @unzipbi32(i32 %a) nounwind {
Expand All @@ -326,7 +326,7 @@ define i32 @unzipbi32(i32 %a) nounwind {
; RV32ZBP-NEXT: unzip.b a0, a0
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.unshfl.i32(i32 %a, i32 3)
ret i32 %tmp
ret i32 %tmp
}

define i32 @unzip4hi32(i32 %a) nounwind {
Expand All @@ -335,7 +335,7 @@ define i32 @unzip4hi32(i32 %a) nounwind {
; RV32ZBP-NEXT: unzip4.h a0, a0
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.unshfl.i32(i32 %a, i32 4)
ret i32 %tmp
ret i32 %tmp
}

define i32 @unzip2hi32(i32 %a) nounwind {
Expand All @@ -344,7 +344,7 @@ define i32 @unzip2hi32(i32 %a) nounwind {
; RV32ZBP-NEXT: unzip2.h a0, a0
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.unshfl.i32(i32 %a, i32 6)
ret i32 %tmp
ret i32 %tmp
}

define i32 @unziphi32(i32 %a) nounwind {
Expand All @@ -353,7 +353,7 @@ define i32 @unziphi32(i32 %a) nounwind {
; RV32ZBP-NEXT: unzip.h a0, a0
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.unshfl.i32(i32 %a, i32 7)
ret i32 %tmp
ret i32 %tmp
}

define i32 @unshfli32(i32 %a) nounwind {
Expand All @@ -362,7 +362,7 @@ define i32 @unshfli32(i32 %a) nounwind {
; RV32ZBP-NEXT: unshfli a0, a0, 13
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.unshfl.i32(i32 %a, i32 13)
ret i32 %tmp
ret i32 %tmp
}

define i32 @unzip4i32(i32 %a) nounwind {
Expand All @@ -371,7 +371,7 @@ define i32 @unzip4i32(i32 %a) nounwind {
; RV32ZBP-NEXT: unzip4 a0, a0
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.unshfl.i32(i32 %a, i32 12)
ret i32 %tmp
ret i32 %tmp
}

define i32 @unzip2i32(i32 %a) nounwind {
Expand All @@ -380,7 +380,7 @@ define i32 @unzip2i32(i32 %a) nounwind {
; RV32ZBP-NEXT: unzip2 a0, a0
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.unshfl.i32(i32 %a, i32 14)
ret i32 %tmp
ret i32 %tmp
}

define i32 @unzipi32(i32 %a) nounwind {
Expand All @@ -389,7 +389,7 @@ define i32 @unzipi32(i32 %a) nounwind {
; RV32ZBP-NEXT: unzip a0, a0
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.unshfl.i32(i32 %a, i32 15)
ret i32 %tmp
ret i32 %tmp
}

define i32 @unzip8i32(i32 %a) nounwind {
Expand All @@ -398,7 +398,7 @@ define i32 @unzip8i32(i32 %a) nounwind {
; RV32ZBP-NEXT: unzip8 a0, a0
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.unshfl.i32(i32 %a, i32 8)
ret i32 %tmp
ret i32 %tmp
}

declare i32 @llvm.riscv.xperm.n.i32(i32 %a, i32 %b)
Expand All @@ -409,7 +409,7 @@ define i32 @xpermn32(i32 %a, i32 %b) nounwind {
; RV32ZBP-NEXT: xperm.n a0, a0, a1
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.xperm.n.i32(i32 %a, i32 %b)
ret i32 %tmp
ret i32 %tmp
}

declare i32 @llvm.riscv.xperm.b.i32(i32 %a, i32 %b)
Expand All @@ -420,7 +420,7 @@ define i32 @xpermb32(i32 %a, i32 %b) nounwind {
; RV32ZBP-NEXT: xperm.b a0, a0, a1
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.xperm.b.i32(i32 %a, i32 %b)
ret i32 %tmp
ret i32 %tmp
}

declare i32 @llvm.riscv.xperm.h.i32(i32 %a, i32 %b)
Expand All @@ -431,5 +431,5 @@ define i32 @xpermh32(i32 %a, i32 %b) nounwind {
; RV32ZBP-NEXT: xperm.h a0, a0, a1
; RV32ZBP-NEXT: ret
%tmp = call i32 @llvm.riscv.xperm.h.i32(i32 %a, i32 %b)
ret i32 %tmp
ret i32 %tmp
}
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@ define signext i32 @orcb32(i32 signext %a) nounwind {
; RV64ZBB-NEXT: sext.w a0, a0
; RV64ZBB-NEXT: ret
%tmp = call i32 @llvm.riscv.orc.b.i32(i32 %a)
ret i32 %tmp
ret i32 %tmp
}

declare i64 @llvm.riscv.orc.b.i64(i64)
Expand All @@ -22,5 +22,5 @@ define i64 @orcb64(i64 %a) nounwind {
; RV64ZBB-NEXT: orc.b a0, a0
; RV64ZBB-NEXT: ret
%tmp = call i64 @llvm.riscv.orc.b.i64(i64 %a)
ret i64 %tmp
ret i64 %tmp
}
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/rv64zbc-intrinsic.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -10,5 +10,5 @@ define i64 @clmul64r(i64 %a, i64 %b) nounwind {
; RV64ZBC-NEXT: clmulr a0, a0, a1
; RV64ZBC-NEXT: ret
%tmp = call i64 @llvm.riscv.clmulr.i64(i64 %a, i64 %b)
ret i64 %tmp
ret i64 %tmp
}
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/rv64zbc-zbkc-intrinsic.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@ define i64 @clmul64(i64 %a, i64 %b) nounwind {
; RV64ZBC-ZBKC-NEXT: clmul a0, a0, a1
; RV64ZBC-ZBKC-NEXT: ret
%tmp = call i64 @llvm.riscv.clmul.i64(i64 %a, i64 %b)
ret i64 %tmp
ret i64 %tmp
}

declare i64 @llvm.riscv.clmulh.i64(i64 %a, i64 %b)
Expand All @@ -23,6 +23,6 @@ define i64 @clmul64h(i64 %a, i64 %b) nounwind {
; RV64ZBC-ZBKC-NEXT: clmulh a0, a0, a1
; RV64ZBC-ZBKC-NEXT: ret
%tmp = call i64 @llvm.riscv.clmulh.i64(i64 %a, i64 %b)
ret i64 %tmp
ret i64 %tmp
}

4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/rv64zbf-intrinsic.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@ define signext i32 @bfp32(i32 signext %a, i32 signext %b) nounwind {
; RV64ZBF-NEXT: bfpw a0, a0, a1
; RV64ZBF-NEXT: ret
%tmp = call i32 @llvm.riscv.bfp.i32(i32 %a, i32 %b)
ret i32 %tmp
ret i32 %tmp
}

declare i64 @llvm.riscv.bfp.i64(i64 %a, i64 %b)
Expand All @@ -21,5 +21,5 @@ define i64 @bfp64(i64 %a, i64 %b) nounwind {
; RV64ZBF-NEXT: bfp a0, a0, a1
; RV64ZBF-NEXT: ret
%tmp = call i64 @llvm.riscv.bfp.i64(i64 %a, i64 %b)
ret i64 %tmp
ret i64 %tmp
}
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/rv64zbkx-intrinsic.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@ define i64 @xperm8(i64 %a, i64 %b) nounwind {
; RV64ZBKX-NEXT: xperm8 a0, a0, a1
; RV64ZBKX-NEXT: ret
%tmp = call i64 @llvm.riscv.xperm8.i64(i64 %a, i64 %b)
ret i64 %tmp
ret i64 %tmp
}

declare i64 @llvm.riscv.xperm4.i64(i64 %a, i64 %b)
Expand All @@ -20,5 +20,5 @@ define i64 @xperm4(i64 %a, i64 %b) nounwind {
; RV64ZBKX-NEXT: xperm4 a0, a0, a1
; RV64ZBKX-NEXT: ret
%tmp = call i64 @llvm.riscv.xperm4.i64(i64 %a, i64 %b)
ret i64 %tmp
ret i64 %tmp
}
184 changes: 92 additions & 92 deletions llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll
View file

Large diffs are not rendered by default.