diff --git a/llvm/test/CodeGen/ARM/build-attributes.ll b/llvm/test/CodeGen/ARM/build-attributes.ll
diff --git a/llvm/test/CodeGen/ARM/float-helpers.s b/llvm/test/CodeGen/ARM/float-helpers.s
@@ -12,24 +12,24 @@
 ; floating-point helper functions to always use the base AAPCS (soft-float)
 ; calling convention.
 
-; COM: In this test we cover the following configurations:
-; COM:  CHECK-SOFT -mfloat-abi=soft
-; COM:      * expect no use of floating point instructions
-; COM:      * expect to use __aeabi_ helper function in each function
-; COM:  CHECK-SOFTFP -mfloat-abi=softfp
-; COM:      * all functions use base AAPCS
-; COM:      * floating point instructions permitted, so __aeabi_ helpers only
-; COM:        expected when there is no available instruction.
-; COM:  CHECK-HARDFP-SP -mfloat-abi=hardfp (single precision instructions)
-; COM:      * all non Runtime ABI helper functions use AAPCS VFP
-; COM:      * floating point instructions permitted, so __aeabi_ helpers only
-; COM:        expected when there is no available instruction.
-; COM:  CHECK-HARDFP-DP -mfloat-abi=hardfp (double precision instructions)
-; COM:  CHECK-HARDFP-SPONLY -mfloat-abi=hardfp (double precision but single
-; COM:                       precision only FPU)
-; COM:      * as CHECK-HARDFP-SP, but we split up the double precision helper
-; COM:        functions so we can test a single precision only FPU, which has to use
-; COM:        helper function for all double precision operations.
+; In this test we cover the following configurations:
+; CHECK-SOFT -mfloat-abi=soft
+;     * expect no use of floating point instructions
+;     * expect to use __aeabi_ helper function in each function
+; CHECK-SOFTFP -mfloat-abi=softfp
+;     * all functions use base AAPCS
+;     * floating point instructions permitted, so __aeabi_ helpers only
+;       expected when there is no available instruction.
+; CHECK-HARDFP-SP -mfloat-abi=hardfp (single precision instructions)
+;     * all non Runtime ABI helper functions use AAPCS VFP
+;     * floating point instructions permitted, so __aeabi_ helpers only
+;       expected when there is no available instruction.
+; CHECK-HARDFP-DP -mfloat-abi=hardfp (double precision instructions)
+; CHECK-HARDFP-SPONLY -mfloat-abi=hardfp (double precision but single
+;                      precision only FPU)
+;     * as CHECK-HARDFP-SP, but we split up the double precision helper
+;       functions so we can test a single precision only FPU, which has to use
+;       helper function for all double precision operations.
 
 ; In all cases we must use base AAPCS when calling a helper function from
 ; section 4.1.2.

diff --git a/llvm/test/CodeGen/ARM/select-imm.ll b/llvm/test/CodeGen/ARM/select-imm.ll
@@ -181,7 +181,7 @@ entry:
 define void @t8(i32 %a) {
 entry:
 
-; COM: ARM scheduler emits icmp/zext before both calls, so isn't relevant
+; ARM scheduler emits icmp/zext before both calls, so isn't relevant
 
 ; ARMT2-LABEL: t8:
 ; ARMT2: bl t7
@@ -214,7 +214,7 @@ entry:
 define void @t9(i8* %a, i8 %b) {
 entry:
 
-; COM: ARM scheduler emits icmp/zext before both calls, so isn't relevant
+; ARM scheduler emits icmp/zext before both calls, so isn't relevant
 
 ; ARMT2-LABEL: t9:
 ; ARMT2: bl f

diff --git a/llvm/test/CodeGen/ARM/struct_byval_arm_t1_t2.ll b/llvm/test/CodeGen/ARM/struct_byval_arm_t1_t2.ll
@@ -12,17 +12,17 @@
 ;RUN: cat %t | FileCheck %s --check-prefix=T1POST
 ;RUN: cat %t | FileCheck %s --check-prefix=V8MBASE
 
-; COM: This file contains auto generated tests for the lowering of passing structs
-; COM: byval in the arm backend. We have tests for both packed and unpacked
-; COM: structs at varying alignments. Each test is run for arm, thumb2 and thumb1.
-; COM: We check for the strings in the generated object code using llvm-objdump
-; COM: because it provides better assurance that we are generating instructions
-; COM: for the correct architecture. Otherwise we could accidentally generate an
-; COM: ARM instruction for THUMB1 and wouldn't detect it because the assembly
-; COM: code representation is the same, but the object code would be generated
-; COM: incorrectly. For each test we check for the label, a load instruction of the
-; COM: correct form, a branch if it will be generated with a loop, and the leftover
-; COM: cleanup if the number of bytes does not divide evenly by the store size
+;This file contains auto generated tests for the lowering of passing structs
+;byval in the arm backend. We have tests for both packed and unpacked
+;structs at varying alignments. Each test is run for arm, thumb2 and thumb1.
+;We check for the strings in the generated object code using llvm-objdump
+;because it provides better assurance that we are generating instructions
+;for the correct architecture. Otherwise we could accidentally generate an
+;ARM instruction for THUMB1 and wouldn't detect it because the assembly
+;code representation is the same, but the object code would be generated
+;incorrectly. For each test we check for the label, a load instruction of the
+;correct form, a branch if it will be generated with a loop, and the leftover
+;cleanup if the number of bytes does not divide evenly by the store size
 
 %struct.A = type <{ [ 10 x i32 ] }> ; 40 bytes
 declare void @use_A(%struct.A* byval)

diff --git a/llvm/test/CodeGen/Mips/cconv/arguments-float.ll b/llvm/test/CodeGen/Mips/cconv/arguments-float.ll
@@ -46,14 +46,14 @@ entry:
 }
 
 ; ALL-LABEL: double_args:
-; COM: We won't test the way the global address is calculated in this test. This is
-; COM: just to get the register number for the other checks.
+; We won't test the way the global address is calculated in this test. This is
+; just to get the register number for the other checks.
 ; SYM32-DAG:           addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(doubles)
 ; SYM64-DAG:           daddiu [[R2:\$[0-9]]], ${{[0-9]+}}, %lo(doubles)
 
-; COM: The first four arguments are the same in O32/N32/N64.
-; COM: The first argument is floating point but soft-float is enabled so floating
-; COM: point registers are not used.
+; The first four arguments are the same in O32/N32/N64.
+; The first argument is floating point but soft-float is enabled so floating
+; point registers are not used.
 ; O32-DAG:           sw $4, 8([[R2]])
 ; O32-DAG:           sw $5, 12([[R2]])
 ; NEW-DAG:           sd $4, 8([[R2]])
@@ -62,7 +62,7 @@ entry:
 ; O32-DAG:           sw $7, 20([[R2]])
 ; NEW-DAG:           sd $5, 16([[R2]])
 
-; COM: O32 has run out of argument registers and starts using the stack
+; O32 has run out of argument registers and starts using the stack
 ; O32-DAG:           lw [[R3:\$([0-9]+|gp)]], 16($sp)
 ; O32-DAG:           lw [[R4:\$([0-9]+|gp)]], 20($sp)
 ; O32-DAG:           sw [[R3]], 24([[R2]])
@@ -134,18 +134,18 @@ entry:
 ; SYM32-DAG:           addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(floats)
 ; SYM64-DAG:           daddiu [[R2:\$[0-9]]], ${{[0-9]+}}, %lo(floats)
 
-; COM: The first four arguments are the same in O32/N32/N64.
-; COM: The first argument is floating point but soft-float is enabled so floating
-; COM: point registers are not used.
-; COM: MD00305 and GCC disagree on this one. MD00305 says that floats are treated
-; COM: as 8-byte aligned and occupy two slots on O32. GCC is treating them as 4-byte
-; COM: aligned and occupying one slot. We'll use GCC's definition.
+; The first four arguments are the same in O32/N32/N64.
+; The first argument is floating point but soft-float is enabled so floating
+; point registers are not used.
+; MD00305 and GCC disagree on this one. MD00305 says that floats are treated
+; as 8-byte aligned and occupy two slots on O32. GCC is treating them as 4-byte
+; aligned and occupying one slot. We'll use GCC's definition.
 ; ALL-DAG:           sw $4, 4([[R2]])
 ; ALL-DAG:           sw $5, 8([[R2]])
 ; ALL-DAG:           sw $6, 12([[R2]])
 ; ALL-DAG:           sw $7, 16([[R2]])
 
-; COM: O32 has run out of argument registers and starts using the stack
+; O32 has run out of argument registers and starts using the stack
 ; O32-DAG:           lw [[R3:\$[0-9]+]], 16($sp)
 ; O32-DAG:           sw [[R3]], 20([[R2]])
 ; NEW-DAG:           sw $8, 20([[R2]])
@@ -162,7 +162,7 @@ entry:
 ; O32-DAG:           sw [[R3]], 32([[R2]])
 ; NEW-DAG:           sw $11, 32([[R2]])
 
-; COM: N32/N64 have run out of registers and start using the stack too
+; N32/N64 have run out of registers and start using the stack too
 ; O32-DAG:           lw [[R3:\$[0-9]+]], 32($sp)
 ; O32-DAG:           sw [[R3]], 36([[R2]])
 ; NEW-DAG:           lw [[R3:\$[0-9]+]], 0($sp)
@@ -185,11 +185,11 @@ entry:
 ; SYM32-DAG:           addiu  [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(doubles)
 ; SYM64-DAG:           daddiu [[R2:\$[0-9]]], ${{[0-9]+}}, %lo(doubles)
 
-; COM: The first four arguments are the same in O32/N32/N64.
-; COM: The first argument isn't floating point so floating point registers are not
-; COM: used.
-; COM: The second slot is insufficiently aligned for double on O32 so it is skipped.
-; COM: Also, double occupies two slots on O32 and only one for N32/N64.
+; The first four arguments are the same in O32/N32/N64.
+; The first argument isn't floating point so floating point registers are not
+; used.
+; The second slot is insufficiently aligned for double on O32 so it is skipped.
+; Also, double occupies two slots on O32 and only one for N32/N64.
 ; ALL-DAG:           sb $4, 1([[R1]])
 ; O32-DAG:           sw $6, 8([[R2]])
 ; O32-DAG:           sw $7, 12([[R2]])
@@ -213,11 +213,11 @@ entry:
 ; SYM64-DAG:         daddiu [[R2:\$[0-9]]], ${{[0-9]+}}, %lo(floats)
 
 
-; COM: The first four arguments are the same in O32/N32/N64.
-; COM: The first argument isn't floating point so floating point registers are not
-; COM: used.
-; COM: MD00305 and GCC disagree on this one. MD00305 says that floats are treated
-; COM: as 8-byte aligned and occupy two slots on O32. GCC is treating them as 4-byte
-; COM: aligned and occupying one slot. We'll use GCC's definition.
+; The first four arguments are the same in O32/N32/N64.
+; The first argument isn't floating point so floating point registers are not
+; used.
+; MD00305 and GCC disagree on this one. MD00305 says that floats are treated
+; as 8-byte aligned and occupy two slots on O32. GCC is treating them as 4-byte
+; aligned and occupying one slot. We'll use GCC's definition.
 ; ALL-DAG:           sb $4, 1([[R1]])
 ; ALL-DAG:           sw $5, 4([[R2]])
diff --git a/llvm/test/CodeGen/Mips/cconv/arguments-hard-float-varargs.ll b/llvm/test/CodeGen/Mips/cconv/arguments-hard-float-varargs.ll
@@ -18,14 +18,14 @@
 ; RUN: llc -march=mips64el -relocation-model=static -target-abi n64 < %s \
 ; RUN:   | FileCheck --check-prefixes=ALL,SYM64,N64,NEW,NEWLE %s
 
-; COM: Test the effect of varargs on floating point types in the non-variable part
-; COM: of the argument list as specified by section 2 of the MIPSpro N32 Handbook.
+; Test the effect of varargs on floating point types in the non-variable part
+; of the argument list as specified by section 2 of the MIPSpro N32 Handbook.
 ;
-; COM: N32/N64 are almost identical in this area so many of their checks have been
-; COM: combined into the 'NEW' prefix (the N stands for New).
+; N32/N64 are almost identical in this area so many of their checks have been
+; combined into the 'NEW' prefix (the N stands for New).
 ;
-; COM: On O32, varargs prevents all FPU argument register usage. This contradicts
-; COM: the N32 handbook, but agrees with the SYSV ABI and GCC's behaviour.
+; On O32, varargs prevents all FPU argument register usage. This contradicts
+; the N32 handbook, but agrees with the SYSV ABI and GCC's behaviour.
 
 @floats = global [11 x float] zeroinitializer
 @doubles = global [11 x double] zeroinitializer
@@ -52,8 +52,8 @@ entry:
 ; SYM32-DAG:         addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(doubles)
 ; SYM64-DAG:         daddiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(doubles)
 
-; COM: O32 forbids using floating point registers for the non-variable portion.
-; COM: N32/N64 allow it.
+; O32 forbids using floating point registers for the non-variable portion.
+; N32/N64 allow it.
 ; O32BE-DAG:         mtc1 $5, [[FTMP1:\$f[0-9]*[02468]+]]
 ; O32BE-DAG:         mtc1 $4, [[FTMP2:\$f[0-9]*[13579]+]]
 ; O32LE-DAG:         mtc1 $4, [[FTMP1:\$f[0-9]*[02468]+]]
@@ -72,10 +72,10 @@ entry:
 ; NEW-DAG:           sd $10, 48($sp)
 ; NEW-DAG:           sd $11, 56($sp)
 
-; COM: Get the varargs pointer
-; COM: O32 has 4 bytes padding, 4 bytes for the varargs pointer, and 8 bytes reserved
-; COM: for arguments 1 and 2.
-; COM: N32/N64 has 8 bytes for the varargs pointer, and no reserved area.
+; Get the varargs pointer
+; O32 has 4 bytes padding, 4 bytes for the varargs pointer, and 8 bytes reserved
+; for arguments 1 and 2.
+; N32/N64 has 8 bytes for the varargs pointer, and no reserved area.
 ; O32-DAG:           addiu [[VAPTR:\$[0-9]+]], $sp, 16
 ; O32-DAG:           sw [[VAPTR]], 4($sp)
 ; N32-DAG:           addiu [[VAPTR:\$[0-9]+]], $sp, 8
@@ -133,11 +133,11 @@ entry:
 ; NEW-DAG:           sd $11, 56($sp)
 
 ; Get the varargs pointer
-; COM: O32 has 4 bytes padding, 4 bytes for the varargs pointer, and should have 8
-; COM: bytes reserved for arguments 1 and 2 (the first float arg) but as discussed in
-; COM: arguments-float.ll, GCC doesn't agree with MD00305 and treats floats as 4
-; COM: bytes so we only have 12 bytes total.
-; COM: N32/N64 has 8 bytes for the varargs pointer, and no reserved area.
+; O32 has 4 bytes padding, 4 bytes for the varargs pointer, and should have 8
+; bytes reserved for arguments 1 and 2 (the first float arg) but as discussed in
+; arguments-float.ll, GCC doesn't agree with MD00305 and treats floats as 4
+; bytes so we only have 12 bytes total.
+; N32/N64 has 8 bytes for the varargs pointer, and no reserved area.
 ; O32-DAG:           addiu [[VAPTR:\$[0-9]+]], $sp, 12
 ; O32-DAG:           sw [[VAPTR]], 4($sp)
 ; N32-DAG:           addiu [[VAPTR:\$[0-9]+]], $sp, 8

diff --git a/llvm/test/CodeGen/Mips/cconv/arguments-hard-float.ll b/llvm/test/CodeGen/Mips/cconv/arguments-hard-float.ll
@@ -58,7 +58,7 @@ entry:
 ; O32-DAG:           sdc1 $f14, 16([[R2]])
 ; NEW-DAG:           sdc1 $f13, 16([[R2]])
 
-; COM: O32 has run out of argument registers and starts using the stack
+; O32 has run out of argument registers and starts using the stack
 ; O32-DAG:           ldc1 [[F1:\$f[0-9]+]], 16($sp)
 ; O32-DAG:           sdc1 [[F1]], 24([[R2]])
 ; NEW-DAG:           sdc1 $f14, 24([[R2]])
@@ -121,18 +121,18 @@ entry:
 ; O32-DAG:           swc1 $f14, 8([[R1]])
 ; NEW-DAG:           swc1 $f13, 8([[R1]])
 
-; COM: O32 has run out of argument registers and (in theory) starts using the stack
-; COM: I've yet to find a reference in the documentation about this but GCC uses up
-; COM: the remaining two argument slots in the GPR's first. We'll do the same for
-; COM: compatibility.
+; O32 has run out of argument registers and (in theory) starts using the stack
+; I've yet to find a reference in the documentation about this but GCC uses up
+; the remaining two argument slots in the GPR's first. We'll do the same for
+; compatibility.
 ; O32-DAG:           mtc1 $6, $f0
 ; O32-DAG:           swc1 $f0, 12([[R1]])
 ; NEW-DAG:           swc1 $f14, 12([[R1]])
 ; O32-DAG:           mtc1 $7, $f0
 ; O32-DAG:           swc1 $f0, 16([[R1]])
 ; NEW-DAG:           swc1 $f15, 16([[R1]])
 
-; COM: O32 is definitely out of registers now and switches to the stack.
+; O32 is definitely out of registers now and switches to the stack.
 ; O32-DAG:           lwc1 [[F1:\$f[0-9]+]], 16($sp)
 ; O32-DAG:           swc1 [[F1]], 20([[R1]])
 ; NEW-DAG:           swc1 $f16, 20([[R1]])
@@ -146,7 +146,7 @@ entry:
 ; O32-DAG:           swc1 [[F1]], 32([[R1]])
 ; NEW-DAG:           swc1 $f19, 32([[R1]])
 
-; COM: N32/N64 have run out of registers and start using the stack too
+; N32/N64 have run out of registers and start using the stack too
 ; O32-DAG:           lwc1 [[F1:\$f[0-9]+]], 32($sp)
 ; O32-DAG:           swc1 [[F1]], 36([[R1]])
 ; NEW-DAG:           lwc1 [[F1:\$f[0-9]+]], 0($sp)
@@ -173,10 +173,10 @@ entry:
 ; The first argument is the same in O32/N32/N64.
 ; ALL-DAG:           sb $4, 1([[R1]])
 
-; COM: The first argument isn't floating point so floating point registers are not
-; COM: used in O32, but N32/N64 will still use them.
-; COM: The second slot is insufficiently aligned for double on O32 so it is skipped.
-; COM: Also, double occupies two slots on O32 and only one for N32/N64.
+; The first argument isn't floating point so floating point registers are not
+; used in O32, but N32/N64 will still use them.
+; The second slot is insufficiently aligned for double on O32 so it is skipped.
+; Also, double occupies two slots on O32 and only one for N32/N64.
 ; O32LE-DAG:           mtc1 $6, [[F1:\$f[0-9]*[02468]+]]
 ; O32LE-DAG:           mtc1 $7, [[F2:\$f[0-9]*[13579]+]]
 ; O32BE-DAG:           mtc1 $6, [[F2:\$f[0-9]*[13579]+]]
@@ -204,11 +204,11 @@ entry:
 ; The first argument is the same in O32/N32/N64.
 ; ALL-DAG:           sb $4, 1([[R1]])
 
-; COM: The first argument isn't floating point so floating point registers are not
-; COM: used in O32, but N32/N64 will still use them.
-; COM: MD00305 and GCC disagree on this one. MD00305 says that floats are treated
-; COM: as 8-byte aligned and occupy two slots on O32. GCC is treating them as 4-byte
-; COM: aligned and occupying one slot. We'll use GCC's definition.
+; The first argument isn't floating point so floating point registers are not
+; used in O32, but N32/N64 will still use them.
+; MD00305 and GCC disagree on this one. MD00305 says that floats are treated
+; as 8-byte aligned and occupy two slots on O32. GCC is treating them as 4-byte
+; aligned and occupying one slot. We'll use GCC's definition.
 ; O32-DAG:           mtc1 $5, $f0
 ; O32-DAG:           swc1 $f0, 4([[R2]])
 ; NEW-DAG:           swc1 $f13, 4([[R2]])
diff --git a/llvm/test/CodeGen/Mips/cconv/arguments-varargs.ll b/llvm/test/CodeGen/Mips/cconv/arguments-varargs.ll
diff --git a/llvm/test/CodeGen/Mips/cconv/arguments.ll b/llvm/test/CodeGen/Mips/cconv/arguments.ll
@@ -57,15 +57,15 @@ entry:
 ; SYM32-DAG:           addiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes)
 ; SYM64-DAG:           daddiu [[R1:\$[0-9]+]], ${{[0-9]+}},  %lo(bytes)
 
-; COM: The first four arguments are the same in O32/N32/N64
+; The first four arguments are the same in O32/N32/N64
 ; ALL-DAG:           sb $4, 1([[R1]])
 ; ALL-DAG:           sb $5, 2([[R1]])
 ; ALL-DAG:           sb $6, 3([[R1]])
 ; ALL-DAG:           sb $7, 4([[R1]])
 
-; COM: N32/N64 get an extra four arguments in registers
-; COM: O32 starts loading from the stack. The addresses start at 16 because space is
-; COM: always reserved for the first four arguments.
+; N32/N64 get an extra four arguments in registers
+; O32 starts loading from the stack. The addresses start at 16 because space is
+; always reserved for the first four arguments.
 ; O32-DAG:           lw [[R3:\$[0-9]+]], 16($sp)
 ; O32-DAG:           sb [[R3]], 5([[R1]])
 ; NEW-DAG:           sb $8, 5([[R1]])
@@ -79,9 +79,9 @@ entry:
 ; O32-DAG:           sb [[R3]], 8([[R1]])
 ; NEW-DAG:           sb $11, 8([[R1]])
 
-; COM: O32/N32/N64 are accessing the stack at this point.
-; COM: Unlike O32, N32/N64 do not reserve space for the arguments.
-; COM: increase by 4 for O32 and 8 for N32/N64.
+; O32/N32/N64 are accessing the stack at this point.
+; Unlike O32, N32/N64 do not reserve space for the arguments.
+; increase by 4 for O32 and 8 for N32/N64.
 ; O32-DAG:           lw [[R3:\$[0-9]+]], 32($sp)
 ; O32-DAG:           sb [[R3]], 9([[R1]])
 ; NEW-DAG:           ld [[R3:\$[0-9]+]], 0($sp)
@@ -127,19 +127,19 @@ entry:
 ; The first argument is the same in O32/N32/N64.
 ; ALL-DAG:           sb $4, 1([[R1]])
 
-; COM: The second slot is insufficiently aligned for i64 on O32 so it is skipped.
-; COM: Also, i64 occupies two slots on O32 and only one for N32/N64.
+; The second slot is insufficiently aligned for i64 on O32 so it is skipped.
+; Also, i64 occupies two slots on O32 and only one for N32/N64.
 ; O32-DAG:           sw $6, 8([[R2]])
 ; O32-DAG:           sw $7, 12([[R2]])
 ; NEW-DAG:           sd $5, 8([[R2]])
 
-; COM: N32/N64 get an extra four arguments in registers and still have two left from
-; COM: the first four.
-; COM: O32 starts loading from the stack. The addresses start at 16 because space is
-; COM: always reserved for the first four arguments.
-; COM: It's not clear why O32 uses lbu for this argument, but it's not wrong so we'll
-; COM: accept it for now. The only IR difference is that this argument has
-; COM: anyext from i8 and align 8 on it.
+; N32/N64 get an extra four arguments in registers and still have two left from
+; the first four.
+; O32 starts loading from the stack. The addresses start at 16 because space is
+; always reserved for the first four arguments.
+; It's not clear why O32 uses lbu for this argument, but it's not wrong so we'll
+; accept it for now. The only IR difference is that this argument has
+; anyext from i8 and align 8 on it.
 ; O32-DAG:           lw [[R3:\$[0-9]+]], 16($sp)
 ; O32-DAG:           sb [[R3]], 2([[R1]])
 ; NEW-DAG:           sb $6, 2([[R1]])
@@ -163,9 +163,9 @@ entry:
 ; O32-DAG:           sw [[R3]], 20([[R2]])
 ; NEW-DAG:           sd $11, 16([[R2]])
 
-; COM: O32/N32/N64 are accessing the stack at this point.
-; COM: Unlike O32, N32/N64 do not reserve space for the arguments.
-; COM: increase by 4 for O32 and 8 for N32/N64.
+; O32/N32/N64 are accessing the stack at this point.
+; Unlike O32, N32/N64 do not reserve space for the arguments.
+; increase by 4 for O32 and 8 for N32/N64.
 ; O32-DAG:           lw [[R3:\$[0-9]+]], 48($sp)
 ; O32-DAG:           sb [[R3]], 7([[R1]])
 ; NEW-DAG:           ld [[R3:\$[0-9]+]], 0($sp)

diff --git a/llvm/test/CodeGen/Mips/cconv/return-hard-fp128.ll b/llvm/test/CodeGen/Mips/cconv/return-hard-fp128.ll
@@ -4,8 +4,8 @@
 ; RUN: llc -march=mips64 -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s
 ; RUN: llc -march=mips64el -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s
 
-; COM: Test the fp128 returns for N32/N64 and all byte orders as specified by
-; COM: section 5 of MD00305 (MIPS ABIs Described).
+; Test the fp128 returns for N32/N64 and all byte orders as specified by
+; section 5 of MD00305 (MIPS ABIs Described).
 ;
 ; O32 is not tested because long double is the same as double on O32.
 ;

diff --git a/llvm/test/CodeGen/Mips/cconv/return-hard-struct-f128.ll b/llvm/test/CodeGen/Mips/cconv/return-hard-struct-f128.ll
@@ -4,7 +4,7 @@
 ; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s
 ; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s
 
-; COM: Test return of {fp128} agrees with de-facto N32/N64 ABI.
+; Test return of {fp128} agrees with de-facto N32/N64 ABI.
 
 @struct_fp128 = global {fp128} zeroinitializer
 
@@ -19,9 +19,9 @@ entry:
 ; O32 generates different IR so we don't test it here. It returns the struct
 ; indirectly.
 
-; COM: Contrary to the N32/N64 ABI documentation, a struct containing a long
-; COM: double is returned in $f0, and $f1 instead of the usual $f0, and $f2.
-; COM: This is to match the de facto ABI as implemented by GCC.
+; Contrary to the N32/N64 ABI documentation, a struct containing a long double
+; is returned in $f0, and $f1 instead of the usual $f0, and $f2. This is to
+; match the de facto ABI as implemented by GCC.
 ; N32-DAG:        lui [[R1:\$[0-9]+]], %hi(struct_fp128)
 ; N32-DAG:        ldc1 $f0, %lo(struct_fp128)([[R1]])
 ; N32-DAG:        addiu [[R3:\$[0-9]+]], [[R1]], %lo(struct_fp128)

diff --git a/llvm/test/CodeGen/Mips/countleading.ll b/llvm/test/CodeGen/Mips/countleading.ll
@@ -6,10 +6,10 @@
 ; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck -check-prefixes=ALL,MIPS64-GT-R1 %s
 ; RUN: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck -check-prefixes=ALL,MIPS64-GT-R1 %s
 
-; COM: Prefixes:
-; COM:   ALL      - All
-; COM:   MIPS32-GT-R1 - MIPS64r1 and above (does not include MIPS64's)
-; COM:   MIPS64-GT-R1 - MIPS64r1 and above
+; Prefixes:
+;   ALL      - All
+;   MIPS32-GT-R1 - MIPS64r1 and above (does not include MIPS64's)
+;   MIPS64-GT-R1 - MIPS64r1 and above
 
 define i32 @ctlz_i32(i32 signext %X) nounwind readnone {
 entry:

diff --git a/llvm/test/CodeGen/Mips/divrem.ll b/llvm/test/CodeGen/Mips/divrem.ll
@@ -12,17 +12,17 @@
 ; RUN: llc -march=mips64 -mcpu=mips64r2 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC64,NOCHECK
 ; RUN: llc -march=mips64 -mcpu=mips64r6 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,GPR64,NOCHECK
 
-; COM: FileCheck Prefixes:
-; COM:   ALL - All targets
-; COM:   ACC32 - Accumulator based multiply/divide on 32-bit targets
-; COM:   ACC64 - Same as ACC32 but only for 64-bit targets
-; COM:   GPR32 - GPR based multiply/divide on 32-bit targets
-; COM:   GPR64 - Same as GPR32 but only for 64-bit targets
-; COM:   ACC32-TRAP - Same as TRAP and ACC32 combined
-; COM:   ACC64-TRAP - Same as TRAP and ACC64 combined
-; COM:   GPR32-TRAP - Same as TRAP and GPR32 combined
-; COM:   GPR64-TRAP - Same as TRAP and GPR64 combined
-; COM:   NOCHECK - Division by zero will not be detected
+; FileCheck Prefixes:
+;   ALL - All targets
+;   ACC32 - Accumulator based multiply/divide on 32-bit targets
+;   ACC64 - Same as ACC32 but only for 64-bit targets
+;   GPR32 - GPR based multiply/divide on 32-bit targets
+;   GPR64 - Same as GPR32 but only for 64-bit targets
+;   ACC32-TRAP - Same as TRAP and ACC32 combined
+;   ACC64-TRAP - Same as TRAP and ACC64 combined
+;   GPR32-TRAP - Same as TRAP and GPR32 combined
+;   GPR64-TRAP - Same as TRAP and GPR64 combined
+;   NOCHECK - Division by zero will not be detected
 
 @g0 = common global i32 0, align 4
 @g1 = common global i32 0, align 4

diff --git a/llvm/test/CodeGen/Mips/dynamic-stack-realignment.ll b/llvm/test/CodeGen/Mips/dynamic-stack-realignment.ll
@@ -65,7 +65,7 @@ entry:
 declare void @helper_02(i32, i32, i32, i32,
                         i32, i32, i32, i32, i32*)
 
-; COM: N32/N64 ABIs
+; N32/N64 ABIs
 define void @func_02() {
 entry:
 ; GP64-LABEL: func_02:
@@ -108,7 +108,7 @@ entry:
 
 declare void @helper_03(i32, i32, i32, i32, i32*, i32*)
 
-; COM: O32 ABI
+; O32 ABI
 define void @func_03(i32 %p0, i32 %p1, i32 %p2, i32 %p3, i32* %b) {
 entry:
 ; GP32-LABEL: func_03:
@@ -130,7 +130,7 @@ entry:
 declare void @helper_04(i32, i32, i32, i32,
                         i32, i32, i32, i32, i32*, i32*)
 
-; COM: N32/N64 ABIs
+; N32/N64 ABIs
 define void @func_04(i32 %p0, i32 %p1, i32 %p2, i32 %p3,
                      i32 %p4, i32 %p5, i32 %p6, i32 %p7,
                      i32* %b) {
@@ -153,7 +153,7 @@ entry:
 
 ; Check dynamic stack realignment in functions with variable-sized objects.
 
-; COM: O32 ABI
+; O32 ABI
 define void @func_05(i32 %sz) {
 entry:
 ; GP32-LABEL: func_05:
@@ -194,7 +194,7 @@ entry:
   ret void
 }
 
-; COM: N32/N64 ABIs
+; N32/N64 ABIs
 define void @func_06(i32 %sz) {
 entry:
 ; GP64-LABEL: func_06:
@@ -262,7 +262,7 @@ entry:
   ret void
 }
 
-; COM: N32/N64 ABIs
+; N32/N64 ABIs
 define void @func_08(i32 %p0, i32 %p1, i32 %p2, i32 %p3,
                      i32 %p4, i32 %p5, i32 %p6, i32 %p7,
                      i32 %sz) {

diff --git a/llvm/test/CodeGen/Mips/inlineasm-operand-code.ll b/llvm/test/CodeGen/Mips/inlineasm-operand-code.ll
@@ -5,7 +5,7 @@
 ; RUN: llc -no-integrated-as -march=mips -relocation-model=pic < %s | \
 ; RUN:     FileCheck -check-prefixes=ALL,BE32,GAS %s
 
-; COM: IAS might not print in the same way since it parses the assembly.
+; IAS might not print in the same way since it parses the assembly.
 ; RUN: llc -march=mipsel -relocation-model=pic < %s | \
 ; RUN:     FileCheck -check-prefixes=ALL,LE32,IAS %s
 ; RUN: llc -march=mips -relocation-model=pic < %s | \

diff --git a/llvm/test/CodeGen/Mips/mips64muldiv.ll b/llvm/test/CodeGen/Mips/mips64muldiv.ll
@@ -3,10 +3,10 @@
 ; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck %s -check-prefixes=ALL,ACC
 ; RUN: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck %s -check-prefixes=ALL,GPR
 
-; COM: FileCheck prefixes:
-; COM:  ALL - All targets
-; COM:  ACC - Targets with accumulator based mul/div (i.e. pre-MIPS32r6)
-; COM:  GPR - Targets with register based mul/div (i.e. MIPS32r6)
+; FileCheck prefixes:
+;   ALL - All targets
+;   ACC - Targets with accumulator based mul/div (i.e. pre-MIPS32r6)
+;   GPR - Targets with register based mul/div (i.e. MIPS32r6)
 
 define i64 @m0(i64 %a0, i64 %a1) nounwind readnone {
 entry:

diff --git a/llvm/test/CodeGen/PowerPC/ppc64-crsave.mir b/llvm/test/CodeGen/PowerPC/ppc64-crsave.mir
@@ -11,9 +11,8 @@
 # RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \
 # RUN: FileCheck %s --check-prefixes=CHECK,SAVEALL
 
-# COM: TODO FIXME: We only check the save and restores of the callee saved gpr
-# COM:             for ELF becuase AIX callee saved registers haven't been
-# COM:             properly implemented yet.
+# TODO FIXME: We only check the save and restores of the callee saved gpr for
+# ELF becuase AIX callee saved registers haven't been properly implemented yet.
 
 ---
 name:            CRAllSave
@@ -78,8 +77,8 @@ body:             |
     ; Verify the proper live-ins have been added in the prologue.
     ; CHECK:    liveins: $x3, $x14, $cr2
 
-    ; COM: ELF V2 ABI allows saving only the clobbered cr fields,
-    ; COM: whereas the other ABIs do not.
+    ; ELF V2 ABI allows saving only the clobbered cr fields,
+    ; whereas the other ABIs do not.
     ; SAVEONE:     $x12 = MFOCRF8 killed $cr2
     ; SAVEALL:     $x12 = MFCR8 implicit killed $cr2
 

diff --git a/llvm/test/CodeGen/X86/avx-cast.ll b/llvm/test/CodeGen/X86/avx-cast.ll
@@ -24,7 +24,7 @@ define <4 x double> @castB(<2 x double> %m) nounwind uwtable readnone ssp {
   ret <4 x double> %shuffle.i
 }
 
-; COM: AVX2 is needed for integer types.
+; AVX2 is needed for integer types.
 
 define <4 x i64> @castC(<2 x i64> %m) nounwind uwtable readnone ssp {
 ; AVX-LABEL: castC:

diff --git a/llvm/test/CodeGen/X86/fp-intrinsics.ll b/llvm/test/CodeGen/X86/fp-intrinsics.ll
@@ -919,8 +919,8 @@ entry:
 ; Verify that fptosi(%x) isn't simplified when the rounding mode is
 ; unknown.
 ; Verify that no gross errors happen.
-; COM: FIXME: The SSE/AVX code does not raise an invalid exception for all
-; COM:        value sthat don't fit in i8.
+; FIXME: The SSE/AVX code does not raise an invalid exception for all values
+; that don't fit in i8.
 define i8 @f20s8(double %x) #0 {
 ; X87-LABEL: f20s8:
 ; X87:       # %bb.0: # %entry
@@ -966,8 +966,8 @@ entry:
 ; Verify that fptosi(%x) isn't simplified when the rounding mode is
 ; unknown.
 ; Verify that no gross errors happen.
-; COM: FIXME: The SSE/AVX code does not raise an invalid exception for all
-; COM:        values that don't fit in i16.
+; FIXME: The SSE/AVX code does not raise an invalid exception for all values
+; that don't fit in i16.
 define i16 @f20s16(double %x) #0 {
 ; X87-LABEL: f20s16:
 ; X87:       # %bb.0: # %entry
@@ -1188,11 +1188,11 @@ entry:
   ret i128 %result
 }
 
-; COM: Verify that fptoui(%x) isn't simplified when the rounding mode is
-; COM: unknown.
-; COM: Verify that no gross errors happen.
-; COM: FIXME: The SSE/AVX code does not raise an invalid exception for all values
-; COM:        that don't fit in i8.
+; Verify that fptoui(%x) isn't simplified when the rounding mode is
+; unknown.
+; Verify that no gross errors happen.
+; FIXME: The SSE/AVX code does not raise an invalid exception for all values
+; that don't fit in i8.
 define i8 @f20u8(double %x) #0 {
 ; X87-LABEL: f20u8:
 ; X87:       # %bb.0: # %entry
@@ -1237,8 +1237,8 @@ entry:
 ; Verify that fptoui(%x) isn't simplified when the rounding mode is
 ; unknown.
 ; Verify that no gross errors happen.
-; COM: FIXME: The SSE/AVX code does not raise an invalid exception for all
-; COM:        values that don't fit in i16.
+; FIXME: The SSE/AVX code does not raise an invalid exception for all values
+; that don't fit in i16.
 define i16 @f20u16(double %x) #0 {
 ; X87-LABEL: f20u16:
 ; X87:       # %bb.0: # %entry
@@ -1285,8 +1285,8 @@ entry:
 ; Verify that fptoui(%x) isn't simplified when the rounding mode is
 ; unknown.
 ; Verify that no gross errors happen.
-; COM: FIXME: The X87/SSE/AVX1 code does not raise an invalid exception for all
-; COM:        values that don't fit in i32. The AVX512 code does.
+; FIXME: The X87/SSE/AVX1 code does not raise an invalid exception for all
+; values that don't fit in i32. The AVX512 code does.
 define i32 @f20u(double %x) #0 {
 ; X87-LABEL: f20u:
 ; X87:       # %bb.0: # %entry

diff --git a/llvm/test/CodeGen/X86/splat-for-size.ll b/llvm/test/CodeGen/X86/splat-for-size.ll
@@ -5,7 +5,7 @@
 ; Check constant loads of every 128-bit and 256-bit vector type
 ; for size optimization using splat ops available with AVX and AVX2.
 
-; COM: There is no AVX broadcast from double to 128-bit vector because movddup has been around since SSE3 (grrr).
+; There is no AVX broadcast from double to 128-bit vector because movddup has been around since SSE3 (grrr).
 define <2 x double> @splat_v2f64(<2 x double> %x) #0 {
 ; CHECK-LABEL: splat_v2f64:
 ; CHECK:       # %bb.0:
@@ -88,9 +88,8 @@ define <8 x float> @splat_v8f32_pgso(<8 x float> %x) !prof !14 {
   ret <8 x float> %add
 }
 
-; COM: AVX can't do integer splats, so fake it: use vmovddup to splat 64-bit
-; COM: value. We also generate vmovddup for AVX2 because it's one byte smaller
-; COM: than vpbroadcastq.
+; AVX can't do integer splats, so fake it: use vmovddup to splat 64-bit value.
+; We also generate vmovddup for AVX2 because it's one byte smaller than vpbroadcastq.
 define <2 x i64> @splat_v2i64(<2 x i64> %x) #1 {
 ; AVX-LABEL: splat_v2i64:
 ; AVX:       # %bb.0:
@@ -125,8 +124,8 @@ define <2 x i64> @splat_v2i64_pgso(<2 x i64> %x) !prof !14 {
   ret <2 x i64> %add
 }
 
-; COM: AVX can't do 256-bit integer ops, so we split this into two 128-bit
-; COM: vectors, and then we fake it: use vmovddup to splat 64-bit value.
+; AVX can't do 256-bit integer ops, so we split this into two 128-bit vectors,
+; and then we fake it: use vmovddup to splat 64-bit value.
 define <4 x i64> @splat_v4i64(<4 x i64> %x) #0 {
 ; AVX-LABEL: splat_v4i64:
 ; AVX:       # %bb.0:
@@ -167,7 +166,7 @@ define <4 x i64> @splat_v4i64_pgso(<4 x i64> %x) !prof !14 {
   ret <4 x i64> %add
 }
 
-; COM: AVX can't do integer splats, so fake it: use vbroadcastss to splat 32-bit value.
+; AVX can't do integer splats, so fake it: use vbroadcastss to splat 32-bit value.
 define <4 x i32> @splat_v4i32(<4 x i32> %x) #1 {
 ; AVX-LABEL: splat_v4i32:
 ; AVX:       # %bb.0:
@@ -200,7 +199,7 @@ define <4 x i32> @splat_v4i32_pgso(<4 x i32> %x) !prof !14 {
   ret <4 x i32> %add
 }
 
-; COM: AVX can't do integer splats, so fake it: use vbroadcastss to splat 32-bit value.
+; AVX can't do integer splats, so fake it: use vbroadcastss to splat 32-bit value.
 define <8 x i32> @splat_v8i32(<8 x i32> %x) #0 {
 ; AVX-LABEL: splat_v8i32:
 ; AVX:       # %bb.0:
@@ -239,7 +238,7 @@ define <8 x i32> @splat_v8i32_pgso(<8 x i32> %x) !prof !14 {
   ret <8 x i32> %add
 }
 
-; COM: AVX can't do integer splats, and there's no broadcast fakery for 16-bit. Could use pshuflw, etc?
+; AVX can't do integer splats, and there's no broadcast fakery for 16-bit. Could use pshuflw, etc?
 define <8 x i16> @splat_v8i16(<8 x i16> %x) #1 {
 ; AVX-LABEL: splat_v8i16:
 ; AVX:       # %bb.0:
@@ -270,7 +269,7 @@ define <8 x i16> @splat_v8i16_pgso(<8 x i16> %x) !prof !14 {
   ret <8 x i16> %add
 }
 
-; COM: AVX can't do integer splats, and there's no broadcast fakery for 16-bit. Could use pshuflw, etc?
+; AVX can't do integer splats, and there's no broadcast fakery for 16-bit. Could use pshuflw, etc?
 define <16 x i16> @splat_v16i16(<16 x i16> %x) #0 {
 ; AVX-LABEL: splat_v16i16:
 ; AVX:       # %bb.0:
@@ -309,7 +308,7 @@ define <16 x i16> @splat_v16i16_pgso(<16 x i16> %x) !prof !14 {
   ret <16 x i16> %add
 }
 
-; COM: AVX can't do integer splats, and there's no broadcast fakery for 8-bit. Could use pshufb, etc?
+; AVX can't do integer splats, and there's no broadcast fakery for 8-bit. Could use pshufb, etc?
 define <16 x i8> @splat_v16i8(<16 x i8> %x) #1 {
 ; AVX-LABEL: splat_v16i8:
 ; AVX:       # %bb.0:
@@ -340,7 +339,7 @@ define <16 x i8> @splat_v16i8_pgso(<16 x i8> %x) !prof !14 {
   ret <16 x i8> %add
 }
 
-; COM: AVX can't do integer splats, and there's no broadcast fakery for 8-bit. Could use pshufb, etc?
+; AVX can't do integer splats, and there's no broadcast fakery for 8-bit. Could use pshufb, etc?
 define <32 x i8> @splat_v32i8(<32 x i8> %x) #0 {
 ; AVX-LABEL: splat_v32i8:
 ; AVX:       # %bb.0:
@@ -379,9 +378,9 @@ define <32 x i8> @splat_v32i8_pgso(<32 x i8> %x) !prof !14 {
   ret <32 x i8> %add
 }
 
-; COM: PR23259: Verify that ISel doesn't crash with a 'fatal error in backend'
-; COM: due to a missing AVX pattern to select a v2i64 X86ISD::BROADCAST of a
-; COM: loadi64 with multiple uses.
+; PR23259: Verify that ISel doesn't crash with a 'fatal error in backend'
+; due to a missing AVX pattern to select a v2i64 X86ISD::BROADCAST of a
+; loadi64 with multiple uses.
 
 @A = common global <3 x i64> zeroinitializer, align 32
 

diff --git a/llvm/test/CodeGen/X86/sse-scalar-fp-arith.ll b/llvm/test/CodeGen/X86/sse-scalar-fp-arith.ll
@@ -8,9 +8,9 @@
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,X64,AVX,X64-AVX,AVX1,X64-AVX1
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefixes=CHECK,X64,AVX,X64-AVX,AVX512,X64-AVX512
 
-; COM: Ensure that the backend no longer emits unnecessary vector insert
-; COM: instructions immediately after SSE scalar fp instructions like addss or
-; COM: mulss.
+; Ensure that the backend no longer emits unnecessary vector insert
+; instructions immediately after SSE scalar fp instructions
+; like addss or mulss.
 
 define <4 x float> @test_add_ss(<4 x float> %a, <4 x float> %b) {
 ; SSE-LABEL: test_add_ss:
@@ -635,8 +635,8 @@ define <2 x double> @blend_div_sd(<2 x double> %a, double %b) {
   ret <2 x double> %shuf
 }
 
-; COM: Ensure that the backend selects SSE/AVX scalar fp instructions
-; COM: from a packed fp instruction plus a vector insert.
+; Ensure that the backend selects SSE/AVX scalar fp instructions
+; from a packed fp instruction plus a vector insert.
 
 define <4 x float> @insert_test_add_ss(<4 x float> %a, <4 x float> %b) {
 ; SSE-LABEL: insert_test_add_ss:

diff --git a/llvm/test/CodeGen/X86/vec_shift6.ll b/llvm/test/CodeGen/X86/vec_shift6.ll
@@ -89,9 +89,9 @@ define <4 x i32> @test4(<4 x i32> %a) {
   ret <4 x i32> %shl
 }
 
-; COM: If we have AVX/SSE2 but not AVX2, verify that the following shift is
-; COM: split into two pmullw instructions. With AVX2, the test case below would
-; COM: produce a single vpmullw.
+; If we have AVX/SSE2 but not AVX2, verify that the following shift is split
+; into two pmullw instructions. With AVX2, the test case below would produce
+; a single vpmullw.
 
 define <16 x i16> @test5(<16 x i16> %a) {
 ; SSE-LABEL: test5:
@@ -109,9 +109,9 @@ define <16 x i16> @test5(<16 x i16> %a) {
   ret <16 x i16> %shl
 }
 
-; COM: If we have AVX/SSE4.1 but not AVX2, verify that the following shift is
-; COM: split into two pmulld instructions. With AVX2, the test case below would
-; COM: produce a single vpsllvd instead.
+; If we have AVX/SSE4.1 but not AVX2, verify that the following shift is split
+; into two pmulld instructions. With AVX2, the test case below would produce
+; a single vpsllvd instead.
 
 define <8 x i32> @test6(<8 x i32> %a) {
 ; SSE2-LABEL: test6:
@@ -148,9 +148,9 @@ define <8 x i32> @test6(<8 x i32> %a) {
   ret <8 x i32> %shl
 }
 
-; COM: With AVX2 and AVX512, the test case below should produce a sequence of
-; COM: two vpmullw instructions. On SSE2 instead, we split the shift in four
-; COM: parts and then we convert each part into a pmullw.
+; With AVX2 and AVX512, the test case below should produce a sequence of
+; two vpmullw instructions. On SSE2 instead, we split the shift in four
+; parts and then we convert each part into a pmullw.
 
 define <32 x i16> @test7(<32 x i16> %a) {
 ; SSE-LABEL: test7:
@@ -183,8 +183,8 @@ define <32 x i16> @test7(<32 x i16> %a) {
   ret <32 x i16> %shl
 }
 
-; COM: Similar to test7; the difference is that with AVX512 support we only
-; COM: produce a single vpsllvd/vpsllvq instead of a pair of vpsllvd/vpsllvq.
+; Similar to test7; the difference is that with AVX512 support
+; we only produce a single vpsllvd/vpsllvq instead of a pair of vpsllvd/vpsllvq.
 
 define <16 x i32> @test8(<16 x i32> %a) {
 ; SSE2-LABEL: test8:
@@ -243,8 +243,7 @@ define <16 x i32> @test8(<16 x i32> %a) {
   ret <16 x i32> %shl
 }
 
-; COM: The shift from 'test9' gets shifted separately and blended if we don't
-; COM: have AVX2/AVX512f support.
+; The shift from 'test9' gets shifted separately and blended if we don't have AVX2/AVX512f support.
 
 define <8 x i64> @test9(<8 x i64> %a) {
 ; SSE2-LABEL: test9:

diff --git a/llvm/test/CodeGen/X86/vector-compare-combines.ll b/llvm/test/CodeGen/X86/vector-compare-combines.ll
@@ -2,8 +2,8 @@
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=SSE --check-prefix=SSE42
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1
 
-; COM: If we have SSE/AVX intrinsics in the code, we miss obvious combines
-; COM: unless we do them late on X86-specific nodes.
+; If we have SSE/AVX intrinsics in the code, we miss obvious combines
+; unless we do them late on X86-specific nodes.
 
 declare <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32>, <4 x i32>)
 

diff --git a/llvm/test/CodeGen/X86/vector-narrow-binop.ll b/llvm/test/CodeGen/X86/vector-narrow-binop.ll
@@ -6,9 +6,8 @@
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512 --check-prefix=AVX512BW
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512 --check-prefix=AVX512DQ
 
-; COM: AVX1 has support for 256-bit bitwise logic because the FP variants were
-; COM: included. If using those ops requires extra insert/extract though, it's
-; COM: probably not worth it.
+; AVX1 has support for 256-bit bitwise logic because the FP variants were included.
+; If using those ops requires extra insert/extract though, it's probably not worth it.
 
 define <8 x i32> @PR32790(<8 x i32> %a, <8 x i32> %b, <8 x i32> %c, <8 x i32> %d) {
 ; SSE-LABEL: PR32790:

diff --git a/llvm/test/DebugInfo/COFF/vframe-fpo.ll b/llvm/test/DebugInfo/COFF/vframe-fpo.ll
@@ -49,7 +49,7 @@
 ; ASM:         movl    $2, {{.*}}
 ; ASM:         movl    $3, {{.*}}
 
-; COM: ASM that store-to-push conversion fires.
+; ASM that store-to-push conversion fires.
 ; ASM:         pushl
 ; ASM-NEXT:    pushl
 ; ASM-NEXT:    calll   "?f@@YAXAAH0@Z"

diff --git a/llvm/test/DebugInfo/X86/debug-info-static-member.ll b/llvm/test/DebugInfo/X86/debug-info-static-member.ll
@@ -101,9 +101,9 @@ attributes #1 = { nounwind readnone }
 !32 = !DILocation(line: 21, scope: !26)
 !33 = !DILocation(line: 22, scope: !26)
 
-; COM: PRESENT verifies that static member declarations have these attributes:
-; COM: external, declaration, accessibility, and either DW_AT_linkage_name (for
-; COM: variables) or DW_AT_const_value (for constants).
+; PRESENT verifies that static member declarations have these attributes:
+; external, declaration, accessibility, and either DW_AT_linkage_name
+; (for variables) or DW_AT_const_value (for constants).
 ;
 ; PRESENT:      .debug_info contents:
 ; PRESENT:      DW_TAG_variable
@@ -204,9 +204,9 @@ attributes #1 = { nounwind readnone }
 ; DARWINP-NEXT: DW_AT_location
 ; DARWINP-NEXT: DW_AT_linkage_name {{.*}} "_ZN1C1cE"
 
-; COM: ABSENT verifies that static member declarations do not have either
-; COM: DW_AT_location or DW_AT_data_member_location; also, variables do not
-; COM: have DW_AT_const_value and constants do not have DW_AT_linkage_name.
+; ABSENT verifies that static member declarations do not have either
+; DW_AT_location or DW_AT_data_member_location; also, variables do not
+; have DW_AT_const_value and constants do not have DW_AT_linkage_name.
 ;
 ; ABSENT:      .debug_info contents:
 ; ABSENT:      DW_TAG_member

diff --git a/llvm/test/FileCheck/dump-input-annotations.txt b/llvm/test/FileCheck/dump-input-annotations.txt
@@ -408,11 +408,11 @@
 ; RUN: echo 'CHECK-DAG: def' >> %t.chk
 
 ; Prefixes used here:
-; COM: DAG    = quiet, -v, or -vv
-; COM: DAG-Q  = quiet
-; COM: DAG-V  = -v or -vv (-vv implies -v)
-; COM: DAG-VQ = -v and not -vv
-; COM: DAG-VV = -vv
+; DAG    = quiet, -v, or -vv
+; DAG-Q  = quiet
+; DAG-V  = -v or -vv (-vv implies -v)
+; DAG-VQ = -v and not -vv
+; DAG-VV = -vv
 
 ; RUN: %ProtectFileCheckOutput \
 ; RUN: not FileCheck -dump-input=always -input-file %t.in %t.chk 2>&1 \

diff --git a/llvm/test/FileCheck/var-scope.txt b/llvm/test/FileCheck/var-scope.txt
@@ -1,8 +1,8 @@
-; COM: Test that variables not starting with dollar sign get undefined after a
-; COM: CHECK-LABEL directive iff --enable-var-scope is used.
+; Test that variables not starting with dollar sign get undefined after a
+; CHECK-LABEL directive iff --enable-var-scope is used.
 
-; COM: Reference run: variables remain defined at all time when not using
-; COM: --enable-var-scope option.
+; Reference run: variables remain defined at all time when not using
+; --enable-var-scope option.
 RUN: FileCheck --check-prefixes CHECK,LOCAL3,GLOBAL --input-file %s %s
 
 RUN: FileCheck --check-prefixes CHECK,GLOBAL --enable-var-scope --input-file %s %s

diff --git a/llvm/test/MC/AsmParser/expr-shr.s b/llvm/test/MC/AsmParser/expr-shr.s
@@ -6,7 +6,7 @@
 
 // CHECK: .quad 3
 
-// COM: MSVC does AShr.
+// MSVC does AShr.
 // MSVC: .quad -1
 
 .quad (~0 >> 62)
diff --git a/llvm/test/MC/Mips/relocation-n64.s b/llvm/test/MC/Mips/relocation-n64.s
@@ -11,14 +11,14 @@
 // Test that we produce the correct relocation.
 // FIXME: move more relocation only tests here.
 
-// COM: Check prefixes:
-// COM: RELOC - Check the relocation in the object.
-// COM: FIXUP - Check the fixup on the instruction.
-// COM: ENCBE - Check the big-endian encoding on the instruction.
-// COM: ENCLE - Check the little-endian encoding on the instruction.
-// COM: ????? - Placeholder. Relocation is defined but the way of generating it is
-// COM:         unknown.
-// COM: FIXME - Placeholder. Generation method is known but doesn't work.
+// Check prefixes:
+// RELOC - Check the relocation in the object.
+// FIXUP - Check the fixup on the instruction.
+// ENCBE - Check the big-endian encoding on the instruction.
+// ENCLE - Check the little-endian encoding on the instruction.
+// ????? - Placeholder. Relocation is defined but the way of generating it is
+//         unknown.
+// FIXME - Placeholder. Generation method is known but doesn't work.
 
 // DATA-LABEL: Name: .text
 // DATA:       SectionData (

diff --git a/llvm/test/MC/Mips/relocation.s b/llvm/test/MC/Mips/relocation.s
@@ -11,14 +11,14 @@
 // Test that we produce the correct relocation.
 // FIXME: move more relocation only tests here.
 
-// COM: Check prefixes:
-// COM: RELOC - Check the relocation in the object.
-// COM: FIXUP - Check the fixup on the instruction.
-// COM: ENCBE - Check the big-endian encoding on the instruction.
-// COM: ENCLE - Check the little-endian encoding on the instruction.
-// COM: ????? - Placeholder. Relocation is defined but the way of generating it is
-// COM:         unknown.
-// COM: FIXME - Placeholder. Generation method is known but doesn't work.
+// Check prefixes:
+// RELOC - Check the relocation in the object.
+// FIXUP - Check the fixup on the instruction.
+// ENCBE - Check the big-endian encoding on the instruction.
+// ENCLE - Check the little-endian encoding on the instruction.
+// ????? - Placeholder. Relocation is defined but the way of generating it is
+//         unknown.
+// FIXME - Placeholder. Generation method is known but doesn't work.
 
 // RELOC-LABEL: .rel.text {
 // DATA-LABEL: Name: .text

diff --git a/llvm/test/MC/RISCV/compressed-relocations.s b/llvm/test/MC/RISCV/compressed-relocations.s
@@ -5,10 +5,10 @@
 # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+relax < %s \
 # RUN:     | llvm-readobj -r | FileCheck -check-prefix=RELOC %s
 
-# COM: Check prefixes:
-# COM: RELOC - Check the relocation in the object.
-# COM: FIXUP - Check the fixup on the instruction.
-# COM: INSTR - Check the instruction is handled properly by the ASMPrinter
+# Check prefixes:
+# RELOC - Check the relocation in the object.
+# FIXUP - Check the fixup on the instruction.
+# INSTR - Check the instruction is handled properly by the ASMPrinter
 c.jal foo
 # A compressed jump (c.j) to an unresolved symbol will be relaxed to a (jal).
 # RELOC: R_RISCV_JAL

diff --git a/llvm/test/MC/RISCV/relocations.s b/llvm/test/MC/RISCV/relocations.s
@@ -3,10 +3,10 @@
 # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c < %s \
 # RUN:     | llvm-readobj -r | FileCheck -check-prefix=RELOC %s
 
-# COM: Check prefixes:
-# COM: RELOC - Check the relocation in the object.
-# COM: FIXUP - Check the fixup on the instruction.
-# COM: INSTR - Check the instruction is handled properly by the ASMPrinter
+# Check prefixes:
+# RELOC - Check the relocation in the object.
+# FIXUP - Check the fixup on the instruction.
+# INSTR - Check the instruction is handled properly by the ASMPrinter
 
 .long foo
 # RELOC: R_RISCV_32 foo

diff --git a/llvm/test/MC/RISCV/rv32b-aliases-valid.s b/llvm/test/MC/RISCV/rv32b-aliases-valid.s
@@ -9,11 +9,11 @@
 # RUN:     | llvm-objdump -d -r --mattr=+experimental-b - \
 # RUN:     | FileCheck -check-prefixes=CHECK-S-OBJ %s
 
-# COM: The following check prefixes are used in this test:
-# COM: CHECK-S-OBJ            Match both the .s and objdumped object output with
-# COM:                        aliases enabled
-# COM: CHECK-S-OBJ-NOALIAS    Match both the .s and objdumped object output with
-# COM:                        aliases disabled
+# The following check prefixes are used in this test:
+# CHECK-S-OBJ            Match both the .s and objdumped object output with
+#                        aliases enabled
+# CHECK-S-OBJ-NOALIAS    Match both the .s and objdumped object output with
+#                        aliases disabled
 
 # CHECK-S-OBJ-NOALIAS: andi t0, t1, 255
 # CHECK-S-OBJ: zext.b t0, t1

diff --git a/llvm/test/MC/RISCV/rv64b-aliases-valid.s b/llvm/test/MC/RISCV/rv64b-aliases-valid.s
@@ -9,11 +9,11 @@
 # RUN:     | llvm-objdump -d -r --mattr=+experimental-b - \
 # RUN:     | FileCheck -check-prefixes=CHECK-S-OBJ %s
 
-# COM: The following check prefixes are used in this test:
-# COM: CHECK-S-OBJ            Match both the .s and objdumped object output with
-# COM:                        aliases enabled
-# COM: CHECK-S-OBJ-NOALIAS    Match both the .s and objdumped object output with
-# COM:                        aliases disabled
+# The following check prefixes are used in this test:
+# CHECK-S-OBJ            Match both the .s and objdumped object output with
+#                        aliases enabled
+# CHECK-S-OBJ-NOALIAS    Match both the .s and objdumped object output with
+#                        aliases disabled
 
 # CHECK-S-OBJ-NOALIAS: andi t0, t1, 255
 # CHECK-S-OBJ: zext.b t0, t1

diff --git a/llvm/test/MC/RISCV/rva-aliases-valid.s b/llvm/test/MC/RISCV/rva-aliases-valid.s
@@ -19,15 +19,15 @@
 # RUN:     | llvm-objdump -d --mattr=+a - \
 # RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-S-OBJ %s
 
-# COM: The following check prefixes are used in this test:
-# COM: CHECK-S                 Match the .s output with aliases enabled
-# COM: CHECK-S-NOALIAS         Match the .s output with aliases disabled
-# COM: CHECK-OBJ               Match the objdumped object output with aliases enabled
-# COM: CHECK-OBJ-NOALIAS       Match the objdumped object output with aliases enabled
-# COM: CHECK-S-OBJ             Match both the .s and objdumped object output with
-# COM:                         aliases enabled
-# COM: CHECK-S-OBJ-NOALIAS     Match both the .s and objdumped object output with
-# COM:                         aliases disabled
+# The following check prefixes are used in this test:
+# CHECK-S                 Match the .s output with aliases enabled
+# CHECK-S-NOALIAS         Match the .s output with aliases disabled
+# CHECK-OBJ               Match the objdumped object output with aliases enabled
+# CHECK-OBJ-NOALIAS       Match the objdumped object output with aliases enabled
+# CHECK-S-OBJ             Match both the .s and objdumped object output with
+#                         aliases enabled
+# CHECK-S-OBJ-NOALIAS     Match both the .s and objdumped object output with
+#                         aliases disabled
 
 # The below tests for lr.w, sc.w and amo*.w, using `0(reg)` are actually
 # implemented using a custom parser, but we test them as if they're aliases.

diff --git a/llvm/test/MC/RISCV/rvi-aliases-valid.s b/llvm/test/MC/RISCV/rvi-aliases-valid.s
@@ -19,15 +19,15 @@
 # RUN:     | llvm-objdump -d -r - \
 # RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-S-OBJ %s
 
-# COM: The following check prefixes are used in this test:
-# COM: CHECK-S                 Match the .s output with aliases enabled
-# COM: CHECK-S-NOALIAS         Match the .s output with aliases disabled
-# COM: CHECK-OBJ               Match the objdumped object output with aliases enabled
-# COM: CHECK-OBJ-NOALIAS       Match the objdumped object output with aliases enabled
-# COM: CHECK-S-OBJ             Match both the .s and objdumped object output with
-# COM:                         aliases enabled
-# COM: CHECK-S-OBJ-NOALIAS     Match both the .s and objdumped object output with
-# COM:                         aliases disabled
+# The following check prefixes are used in this test:
+# CHECK-S                 Match the .s output with aliases enabled
+# CHECK-S-NOALIAS         Match the .s output with aliases disabled
+# CHECK-OBJ               Match the objdumped object output with aliases enabled
+# CHECK-OBJ-NOALIAS       Match the objdumped object output with aliases enabled
+# CHECK-S-OBJ             Match both the .s and objdumped object output with
+#                         aliases enabled
+# CHECK-S-OBJ-NOALIAS     Match both the .s and objdumped object output with
+#                         aliases disabled
 
 # TODO la
 # TODO lb lh lw

diff --git a/llvm/test/Transforms/InstCombine/double-float-shrink-2.ll b/llvm/test/Transforms/InstCombine/double-float-shrink-2.ll
@@ -95,8 +95,8 @@ define float @test_shrink_libcall_trunc(float %C) {
   ret float %F
 }
 
-; COM: This is replaced with the intrinsic, which does the right thing on CHECK
-; COM: platforms.
+; This is replaced with the intrinsic, which does the right thing on
+; CHECK platforms.
 define float @test_shrink_libcall_fabs(float %C) {
 ; CHECK-LABEL: @test_shrink_libcall_fabs(
 ; CHECK-NEXT:    [[F:%.*]] = call float @llvm.fabs.f32(float [[C:%.*]])

diff --git a/llvm/test/Transforms/LoopFusion/cannot_fuse.ll b/llvm/test/Transforms/LoopFusion/cannot_fuse.ll
@@ -3,7 +3,7 @@
 
 @B = common global [1024 x i32] zeroinitializer, align 16
 
-; Check that the two candidates for fusion are placed into separate candidate
+; CHECK that the two candidates for fusion are placed into separate candidate
 ; sets because they are not control flow equivalent.
 
 ; CHECK: Performing Loop Fusion on function non_cfe

diff --git a/llvm/test/tools/llvm-objdump/ELF/dynamic-section-machine-specific.test b/llvm/test/tools/llvm-objdump/ELF/dynamic-section-machine-specific.test
@@ -1,6 +1,6 @@
 ## In this test we test how machine-specific dynamic tags are dumped.
 
-## COM: Case 1: Test that hexagon machine-specific tags can be dumped.
+## Case 1: Test that hexagon machine-specific tags can be dumped.
 # RUN: yaml2obj --docnum=1 -o %t.hex %s
 # RUN: llvm-objdump -p %t.hex | FileCheck %s --check-prefix=HEXAGON
 
@@ -35,8 +35,8 @@ ProgramHeaders:
     Sections:
       - Section: .dynamic
 
-## COM: Case 2: Test that MIPS machine-specific tags can be dumped.
-## COM:         MIPS has a few long tag names. Show that we indent columns properly.
+## Case 2: Test that MIPS machine-specific tags can be dumped.
+##         MIPS has a few long tag names. Show that we indent columns properly.
 # RUN: yaml2obj --docnum=2 -o %t.mips %s
 # RUN: llvm-objdump -p %t.mips | FileCheck %s  --strict-whitespace --match-full-lines --check-prefix=MIPS
 
@@ -197,7 +197,7 @@ ProgramHeaders:
     Sections:
       - Section: .dynamic
 
-## COM: Case 3: Test that PPC machine-specific tags can be dumped.
+## Case 3: Test that PPC machine-specific tags can be dumped.
 # RUN: yaml2obj --docnum=3 -o %t.ppc %s
 # RUN: llvm-objdump -p %t.ppc | FileCheck %s --check-prefix=PPC
 
@@ -229,7 +229,7 @@ ProgramHeaders:
     Sections:
       - Section: .dynamic
 
-## COM: Case 4: Test that PPC64 machine-specific tags can be dumped.
+## Case 4: Test that PPC64 machine-specific tags can be dumped.
 # RUN: yaml2obj --docnum=4 -o %t.ppc64 %s
 # RUN: llvm-objdump -p %t.ppc64 | FileCheck %s --check-prefix=PPC64
 
@@ -258,7 +258,7 @@ ProgramHeaders:
     Sections:
       - Section: .dynamic
 
-## COM: Case 5: Test that AARCH64 machine-specific tags can be dumped.
+## Case 5: Test that AARCH64 machine-specific tags can be dumped.
 # RUN: yaml2obj --docnum=5 -o %t.aarch64 %s
 # RUN: llvm-objdump -p %t.aarch64 | FileCheck %s --check-prefix=AARCH64
 

diff --git a/llvm/test/tools/llvm-readobj/ELF/RISCV/section-types.test b/llvm/test/tools/llvm-readobj/ELF/RISCV/section-types.test
@@ -1,5 +1,5 @@
-## COM: Show that all RISCV specific section types are properly printed for both
-## COM: LLVM and GNU styles.
+## Show that all RISCV specific section types are properly printed for both
+## LLVM and GNU styles.
 
 # RUN: yaml2obj %s -o %t-riscv.o
 # RUN: llvm-readobj --section-headers %t-riscv.o | FileCheck %s --check-prefix=LLVM

diff --git a/llvm/test/tools/llvm-readobj/ELF/section-types.test b/llvm/test/tools/llvm-readobj/ELF/section-types.test
@@ -1,5 +1,5 @@
-# COM: Show that all regular section types are properly printed for both LLVM and
-# COM: GNU styles.
+# Show that all regular section types are properly printed for both LLVM and
+# GNU styles.
 
 # RUN: yaml2obj %s -o %t-basic.o
 # RUN: llvm-readobj --section-headers %t-basic.o | FileCheck %s --check-prefix=LLVM

diff --git a/llvm/test/tools/llvm-readobj/ELF/symbol-binding.test b/llvm/test/tools/llvm-readobj/ELF/symbol-binding.test
@@ -1,5 +1,5 @@
-# COM: Show that llvm-readobj can print symbol bindings correctly for both LLVM and
-# COM: GNU styles, including for symbol bindings that are not recognised.
+# Show that llvm-readobj can print symbol bindings correctly for both LLVM and
+# GNU styles, including for symbol bindings that are not recognised.
 
 # RUN: yaml2obj %s -o %t
 # RUN: llvm-readobj --symbols --dyn-symbols %t | FileCheck %s --check-prefix=LLVM