@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+xsfvcp \
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+xsfvcp,+zvfh \
; RUN: -verify-machineinstrs | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+xsfvcp \
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+xsfvcp,+zvfh \
; RUN: -verify-machineinstrs | FileCheck %s
define void @test_sf_vc_x_se_e8mf8 (i8 zeroext %rs1 , iXLen %vl ) {
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@@ -1563,3 +1563,393 @@ entry:
}
declare <vscale x 8 x i64 > @llvm.riscv.sf.vc.v.i.nxv8i64.iXLen.iXLen.iXLen (iXLen, iXLen, iXLen, iXLen)
define <vscale x 1 x half > @test_f_sf_vc_v_i_se_e16mf4 (iXLen %vl ) {
; CHECK-LABEL: test_f_sf_vc_v_i_se_e16mf4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 10
; CHECK-NEXT: ret
entry:
%0 = tail call <vscale x 1 x half > @llvm.riscv.sf.vc.v.i.se.nxv1f16.iXLen.iXLen.iXLen (iXLen 3 , iXLen 31 , iXLen 10 , iXLen %vl )
ret <vscale x 1 x half > %0
}
declare <vscale x 1 x half > @llvm.riscv.sf.vc.v.i.se.nxv1f16.iXLen.iXLen.iXLen (iXLen, iXLen, iXLen, iXLen)
define <vscale x 2 x half > @test_f_sf_vc_v_i_se_e16mf2 (iXLen %vl ) {
; CHECK-LABEL: test_f_sf_vc_v_i_se_e16mf2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 10
; CHECK-NEXT: ret
entry:
%0 = tail call <vscale x 2 x half > @llvm.riscv.sf.vc.v.i.se.nxv2f16.iXLen.iXLen.iXLen (iXLen 3 , iXLen 31 , iXLen 10 , iXLen %vl )
ret <vscale x 2 x half > %0
}
declare <vscale x 2 x half > @llvm.riscv.sf.vc.v.i.se.nxv2f16.iXLen.iXLen.iXLen (iXLen, iXLen, iXLen, iXLen)
define <vscale x 4 x half > @test_f_sf_vc_v_i_se_e16m1 (iXLen %vl ) {
; CHECK-LABEL: test_f_sf_vc_v_i_se_e16m1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 10
; CHECK-NEXT: ret
entry:
%0 = tail call <vscale x 4 x half > @llvm.riscv.sf.vc.v.i.se.nxv4f16.iXLen.iXLen.iXLen (iXLen 3 , iXLen 31 , iXLen 10 , iXLen %vl )
ret <vscale x 4 x half > %0
}
declare <vscale x 4 x half > @llvm.riscv.sf.vc.v.i.se.nxv4f16.iXLen.iXLen.iXLen (iXLen, iXLen, iXLen, iXLen)
define <vscale x 8 x half > @test_f_sf_vc_v_i_se_e16m2 (iXLen %vl ) {
; CHECK-LABEL: test_f_sf_vc_v_i_se_e16m2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 10
; CHECK-NEXT: ret
entry:
%0 = tail call <vscale x 8 x half > @llvm.riscv.sf.vc.v.i.se.nxv8f16.iXLen.iXLen.iXLen (iXLen 3 , iXLen 31 , iXLen 10 , iXLen %vl )
ret <vscale x 8 x half > %0
}
declare <vscale x 8 x half > @llvm.riscv.sf.vc.v.i.se.nxv8f16.iXLen.iXLen.iXLen (iXLen, iXLen, iXLen, iXLen)
define <vscale x 16 x half > @test_f_sf_vc_v_i_se_e16m4 (iXLen %vl ) {
; CHECK-LABEL: test_f_sf_vc_v_i_se_e16m4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 10
; CHECK-NEXT: ret
entry:
%0 = tail call <vscale x 16 x half > @llvm.riscv.sf.vc.v.i.se.nxv16f16.iXLen.iXLen.iXLen (iXLen 3 , iXLen 31 , iXLen 10 , iXLen %vl )
ret <vscale x 16 x half > %0
}
declare <vscale x 16 x half > @llvm.riscv.sf.vc.v.i.se.nxv16f16.iXLen.iXLen.iXLen (iXLen, iXLen, iXLen, iXLen)
define <vscale x 32 x half > @test_f_sf_vc_v_i_se_e16m8 (iXLen %vl ) {
; CHECK-LABEL: test_f_sf_vc_v_i_se_e16m8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 10
; CHECK-NEXT: ret
entry:
%0 = tail call <vscale x 32 x half > @llvm.riscv.sf.vc.v.i.se.nxv32f16.iXLen.iXLen.iXLen (iXLen 3 , iXLen 31 , iXLen 10 , iXLen %vl )
ret <vscale x 32 x half > %0
}
declare <vscale x 32 x half > @llvm.riscv.sf.vc.v.i.se.nxv32f16.iXLen.iXLen.iXLen (iXLen, iXLen, iXLen, iXLen)
define <vscale x 1 x float > @test_f_sf_vc_v_i_se_e32mf2 (iXLen %vl ) {
; CHECK-LABEL: test_f_sf_vc_v_i_se_e32mf2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 10
; CHECK-NEXT: ret
entry:
%0 = tail call <vscale x 1 x float > @llvm.riscv.sf.vc.v.i.se.nxv1f32.iXLen.iXLen.iXLen (iXLen 3 , iXLen 31 , iXLen 10 , iXLen %vl )
ret <vscale x 1 x float > %0
}
declare <vscale x 1 x float > @llvm.riscv.sf.vc.v.i.se.nxv1f32.iXLen.iXLen.iXLen (iXLen, iXLen, iXLen, iXLen)
define <vscale x 2 x float > @test_f_sf_vc_v_i_se_e32m1 (iXLen %vl ) {
; CHECK-LABEL: test_f_sf_vc_v_i_se_e32m1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 10
; CHECK-NEXT: ret
entry:
%0 = tail call <vscale x 2 x float > @llvm.riscv.sf.vc.v.i.se.nxv2f32.iXLen.iXLen.iXLen (iXLen 3 , iXLen 31 , iXLen 10 , iXLen %vl )
ret <vscale x 2 x float > %0
}
declare <vscale x 2 x float > @llvm.riscv.sf.vc.v.i.se.nxv2f32.iXLen.iXLen.iXLen (iXLen, iXLen, iXLen, iXLen)
define <vscale x 4 x float > @test_f_sf_vc_v_i_se_e32m2 (iXLen %vl ) {
; CHECK-LABEL: test_f_sf_vc_v_i_se_e32m2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 10
; CHECK-NEXT: ret
entry:
%0 = tail call <vscale x 4 x float > @llvm.riscv.sf.vc.v.i.se.nxv4f32.iXLen.iXLen.iXLen (iXLen 3 , iXLen 31 , iXLen 10 , iXLen %vl )
ret <vscale x 4 x float > %0
}
declare <vscale x 4 x float > @llvm.riscv.sf.vc.v.i.se.nxv4f32.iXLen.iXLen.iXLen (iXLen, iXLen, iXLen, iXLen)
define <vscale x 8 x float > @test_f_sf_vc_v_i_se_e32m4 (iXLen %vl ) {
; CHECK-LABEL: test_f_sf_vc_v_i_se_e32m4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 10
; CHECK-NEXT: ret
entry:
%0 = tail call <vscale x 8 x float > @llvm.riscv.sf.vc.v.i.se.nxv8f32.iXLen.iXLen.iXLen (iXLen 3 , iXLen 31 , iXLen 10 , iXLen %vl )
ret <vscale x 8 x float > %0
}
declare <vscale x 8 x float > @llvm.riscv.sf.vc.v.i.se.nxv8f32.iXLen.iXLen.iXLen (iXLen, iXLen, iXLen, iXLen)
define <vscale x 16 x float > @test_f_sf_vc_v_i_se_e32m8 (iXLen %vl ) {
; CHECK-LABEL: test_f_sf_vc_v_i_se_e32m8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 10
; CHECK-NEXT: ret
entry:
%0 = tail call <vscale x 16 x float > @llvm.riscv.sf.vc.v.i.se.nxv16f32.iXLen.iXLen.iXLen (iXLen 3 , iXLen 31 , iXLen 10 , iXLen %vl )
ret <vscale x 16 x float > %0
}
declare <vscale x 16 x float > @llvm.riscv.sf.vc.v.i.se.nxv16f32.iXLen.iXLen.iXLen (iXLen, iXLen, iXLen, iXLen)
define <vscale x 1 x double > @test_f_sf_vc_v_i_se_e64m1 (iXLen %vl ) {
; CHECK-LABEL: test_f_sf_vc_v_i_se_e64m1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 10
; CHECK-NEXT: ret
entry:
%0 = tail call <vscale x 1 x double > @llvm.riscv.sf.vc.v.i.se.nxv1f64.iXLen.iXLen.iXLen (iXLen 3 , iXLen 31 , iXLen 10 , iXLen %vl )
ret <vscale x 1 x double > %0
}
declare <vscale x 1 x double > @llvm.riscv.sf.vc.v.i.se.nxv1f64.iXLen.iXLen.iXLen (iXLen, iXLen, iXLen, iXLen)
define <vscale x 2 x double > @test_f_sf_vc_v_i_se_e64m2 (iXLen %vl ) {
; CHECK-LABEL: test_f_sf_vc_v_i_se_e64m2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 10
; CHECK-NEXT: ret
entry:
%0 = tail call <vscale x 2 x double > @llvm.riscv.sf.vc.v.i.se.nxv2f64.iXLen.iXLen.iXLen (iXLen 3 , iXLen 31 , iXLen 10 , iXLen %vl )
ret <vscale x 2 x double > %0
}
declare <vscale x 2 x double > @llvm.riscv.sf.vc.v.i.se.nxv2f64.iXLen.iXLen.iXLen (iXLen, iXLen, iXLen, iXLen)
define <vscale x 4 x double > @test_f_sf_vc_v_i_se_e64m4 (iXLen %vl ) {
; CHECK-LABEL: test_f_sf_vc_v_i_se_e64m4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 10
; CHECK-NEXT: ret
entry:
%0 = tail call <vscale x 4 x double > @llvm.riscv.sf.vc.v.i.se.nxv4f64.iXLen.iXLen.iXLen (iXLen 3 , iXLen 31 , iXLen 10 , iXLen %vl )
ret <vscale x 4 x double > %0
}
declare <vscale x 4 x double > @llvm.riscv.sf.vc.v.i.se.nxv4f64.iXLen.iXLen.iXLen (iXLen, iXLen, iXLen, iXLen)
define <vscale x 8 x double > @test_f_sf_vc_v_i_se_e64m8 (iXLen %vl ) {
; CHECK-LABEL: test_f_sf_vc_v_i_se_e64m8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 10
; CHECK-NEXT: ret
entry:
%0 = tail call <vscale x 8 x double > @llvm.riscv.sf.vc.v.i.se.nxv8f64.iXLen.iXLen.iXLen (iXLen 3 , iXLen 31 , iXLen 10 , iXLen %vl )
ret <vscale x 8 x double > %0
}
declare <vscale x 8 x double > @llvm.riscv.sf.vc.v.i.se.nxv8f64.iXLen.iXLen.iXLen (iXLen, iXLen, iXLen, iXLen)
define <vscale x 1 x half > @test_f_sf_vc_v_i_e16mf4 (iXLen %vl ) {
; CHECK-LABEL: test_f_sf_vc_v_i_e16mf4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 10
; CHECK-NEXT: ret
entry:
%0 = tail call <vscale x 1 x half > @llvm.riscv.sf.vc.v.i.nxv1f16.iXLen.iXLen.iXLen (iXLen 3 , iXLen 31 , iXLen 10 , iXLen %vl )
ret <vscale x 1 x half > %0
}
declare <vscale x 1 x half > @llvm.riscv.sf.vc.v.i.nxv1f16.iXLen.iXLen.iXLen (iXLen, iXLen, iXLen, iXLen)
define <vscale x 2 x half > @test_f_sf_vc_v_i_e16mf2 (iXLen %vl ) {
; CHECK-LABEL: test_f_sf_vc_v_i_e16mf2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 10
; CHECK-NEXT: ret
entry:
%0 = tail call <vscale x 2 x half > @llvm.riscv.sf.vc.v.i.nxv2f16.iXLen.iXLen.iXLen (iXLen 3 , iXLen 31 , iXLen 10 , iXLen %vl )
ret <vscale x 2 x half > %0
}
declare <vscale x 2 x half > @llvm.riscv.sf.vc.v.i.nxv2f16.iXLen.iXLen.iXLen (iXLen, iXLen, iXLen, iXLen)
define <vscale x 4 x half > @test_f_sf_vc_v_i_e16m1 (iXLen %vl ) {
; CHECK-LABEL: test_f_sf_vc_v_i_e16m1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 10
; CHECK-NEXT: ret
entry:
%0 = tail call <vscale x 4 x half > @llvm.riscv.sf.vc.v.i.nxv4f16.iXLen.iXLen.iXLen (iXLen 3 , iXLen 31 , iXLen 10 , iXLen %vl )
ret <vscale x 4 x half > %0
}
declare <vscale x 4 x half > @llvm.riscv.sf.vc.v.i.nxv4f16.iXLen.iXLen.iXLen (iXLen, iXLen, iXLen, iXLen)
define <vscale x 8 x half > @test_f_sf_vc_v_i_e16m2 (iXLen %vl ) {
; CHECK-LABEL: test_f_sf_vc_v_i_e16m2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 10
; CHECK-NEXT: ret
entry:
%0 = tail call <vscale x 8 x half > @llvm.riscv.sf.vc.v.i.nxv8f16.iXLen.iXLen.iXLen (iXLen 3 , iXLen 31 , iXLen 10 , iXLen %vl )
ret <vscale x 8 x half > %0
}
declare <vscale x 8 x half > @llvm.riscv.sf.vc.v.i.nxv8f16.iXLen.iXLen.iXLen (iXLen, iXLen, iXLen, iXLen)
define <vscale x 16 x half > @test_f_sf_vc_v_i_e16m4 (iXLen %vl ) {
; CHECK-LABEL: test_f_sf_vc_v_i_e16m4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 10
; CHECK-NEXT: ret
entry:
%0 = tail call <vscale x 16 x half > @llvm.riscv.sf.vc.v.i.nxv16f16.iXLen.iXLen.iXLen (iXLen 3 , iXLen 31 , iXLen 10 , iXLen %vl )
ret <vscale x 16 x half > %0
}
declare <vscale x 16 x half > @llvm.riscv.sf.vc.v.i.nxv16f16.iXLen.iXLen.iXLen (iXLen, iXLen, iXLen, iXLen)
define <vscale x 32 x half > @test_f_sf_vc_v_i_e16m8 (iXLen %vl ) {
; CHECK-LABEL: test_f_sf_vc_v_i_e16m8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 10
; CHECK-NEXT: ret
entry:
%0 = tail call <vscale x 32 x half > @llvm.riscv.sf.vc.v.i.nxv32f16.iXLen.iXLen.iXLen (iXLen 3 , iXLen 31 , iXLen 10 , iXLen %vl )
ret <vscale x 32 x half > %0
}
declare <vscale x 32 x half > @llvm.riscv.sf.vc.v.i.nxv32f16.iXLen.iXLen.iXLen (iXLen, iXLen, iXLen, iXLen)
define <vscale x 1 x float > @test_f_sf_vc_v_i_e32mf2 (iXLen %vl ) {
; CHECK-LABEL: test_f_sf_vc_v_i_e32mf2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 10
; CHECK-NEXT: ret
entry:
%0 = tail call <vscale x 1 x float > @llvm.riscv.sf.vc.v.i.nxv1f32.iXLen.iXLen.iXLen (iXLen 3 , iXLen 31 , iXLen 10 , iXLen %vl )
ret <vscale x 1 x float > %0
}
declare <vscale x 1 x float > @llvm.riscv.sf.vc.v.i.nxv1f32.iXLen.iXLen.iXLen (iXLen, iXLen, iXLen, iXLen)
define <vscale x 2 x float > @test_f_sf_vc_v_i_e32m1 (iXLen %vl ) {
; CHECK-LABEL: test_f_sf_vc_v_i_e32m1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 10
; CHECK-NEXT: ret
entry:
%0 = tail call <vscale x 2 x float > @llvm.riscv.sf.vc.v.i.nxv2f32.iXLen.iXLen.iXLen (iXLen 3 , iXLen 31 , iXLen 10 , iXLen %vl )
ret <vscale x 2 x float > %0
}
declare <vscale x 2 x float > @llvm.riscv.sf.vc.v.i.nxv2f32.iXLen.iXLen.iXLen (iXLen, iXLen, iXLen, iXLen)
define <vscale x 4 x float > @test_f_sf_vc_v_i_e32m2 (iXLen %vl ) {
; CHECK-LABEL: test_f_sf_vc_v_i_e32m2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 10
; CHECK-NEXT: ret
entry:
%0 = tail call <vscale x 4 x float > @llvm.riscv.sf.vc.v.i.nxv4f32.iXLen.iXLen.iXLen (iXLen 3 , iXLen 31 , iXLen 10 , iXLen %vl )
ret <vscale x 4 x float > %0
}
declare <vscale x 4 x float > @llvm.riscv.sf.vc.v.i.nxv4f32.iXLen.iXLen.iXLen (iXLen, iXLen, iXLen, iXLen)
define <vscale x 8 x float > @test_f_sf_vc_v_i_e32m4 (iXLen %vl ) {
; CHECK-LABEL: test_f_sf_vc_v_i_e32m4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 10
; CHECK-NEXT: ret
entry:
%0 = tail call <vscale x 8 x float > @llvm.riscv.sf.vc.v.i.nxv8f32.iXLen.iXLen.iXLen (iXLen 3 , iXLen 31 , iXLen 10 , iXLen %vl )
ret <vscale x 8 x float > %0
}
declare <vscale x 8 x float > @llvm.riscv.sf.vc.v.i.nxv8f32.iXLen.iXLen.iXLen (iXLen, iXLen, iXLen, iXLen)
define <vscale x 16 x float > @test_f_sf_vc_v_i_e32m8 (iXLen %vl ) {
; CHECK-LABEL: test_f_sf_vc_v_i_e32m8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 10
; CHECK-NEXT: ret
entry:
%0 = tail call <vscale x 16 x float > @llvm.riscv.sf.vc.v.i.nxv16f32.iXLen.iXLen.iXLen (iXLen 3 , iXLen 31 , iXLen 10 , iXLen %vl )
ret <vscale x 16 x float > %0
}
declare <vscale x 16 x float > @llvm.riscv.sf.vc.v.i.nxv16f32.iXLen.iXLen.iXLen (iXLen, iXLen, iXLen, iXLen)
define <vscale x 1 x double > @test_f_sf_vc_v_i_e64m1 (iXLen %vl ) {
; CHECK-LABEL: test_f_sf_vc_v_i_e64m1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 10
; CHECK-NEXT: ret
entry:
%0 = tail call <vscale x 1 x double > @llvm.riscv.sf.vc.v.i.nxv1f64.iXLen.iXLen.iXLen (iXLen 3 , iXLen 31 , iXLen 10 , iXLen %vl )
ret <vscale x 1 x double > %0
}
declare <vscale x 1 x double > @llvm.riscv.sf.vc.v.i.nxv1f64.iXLen.iXLen.iXLen (iXLen, iXLen, iXLen, iXLen)
define <vscale x 2 x double > @test_f_sf_vc_v_i_e64m2 (iXLen %vl ) {
; CHECK-LABEL: test_f_sf_vc_v_i_e64m2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 10
; CHECK-NEXT: ret
entry:
%0 = tail call <vscale x 2 x double > @llvm.riscv.sf.vc.v.i.nxv2f64.iXLen.iXLen.iXLen (iXLen 3 , iXLen 31 , iXLen 10 , iXLen %vl )
ret <vscale x 2 x double > %0
}
declare <vscale x 2 x double > @llvm.riscv.sf.vc.v.i.nxv2f64.iXLen.iXLen.iXLen (iXLen, iXLen, iXLen, iXLen)
define <vscale x 4 x double > @test_f_sf_vc_v_i_e64m4 (iXLen %vl ) {
; CHECK-LABEL: test_f_sf_vc_v_i_e64m4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 10
; CHECK-NEXT: ret
entry:
%0 = tail call <vscale x 4 x double > @llvm.riscv.sf.vc.v.i.nxv4f64.iXLen.iXLen.iXLen (iXLen 3 , iXLen 31 , iXLen 10 , iXLen %vl )
ret <vscale x 4 x double > %0
}
declare <vscale x 4 x double > @llvm.riscv.sf.vc.v.i.nxv4f64.iXLen.iXLen.iXLen (iXLen, iXLen, iXLen, iXLen)
define <vscale x 8 x double > @test_f_sf_vc_v_i_e64m8 (iXLen %vl ) {
; CHECK-LABEL: test_f_sf_vc_v_i_e64m8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 10
; CHECK-NEXT: ret
entry:
%0 = tail call <vscale x 8 x double > @llvm.riscv.sf.vc.v.i.nxv8f64.iXLen.iXLen.iXLen (iXLen 3 , iXLen 31 , iXLen 10 , iXLen %vl )
ret <vscale x 8 x double > %0
}
declare <vscale x 8 x double > @llvm.riscv.sf.vc.v.i.nxv8f64.iXLen.iXLen.iXLen (iXLen, iXLen, iXLen, iXLen)