217 changes: 217 additions & 0 deletions llvm/test/CodeGen/RISCV/atomic-load-store.ll
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IA %s

define i8 @atomic_load_i8_unordered(i8 *%a) nounwind {
; RV32I-LABEL: atomic_load_i8_unordered:
Expand All @@ -12,6 +14,11 @@ define i8 @atomic_load_i8_unordered(i8 *%a) nounwind {
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomic_load_i8_unordered:
; RV32IA: # %bb.0:
; RV32IA-NEXT: lb a0, 0(a0)
; RV32IA-NEXT: ret
%1 = load atomic i8, i8* %a unordered, align 1
ret i8 %1
}
Expand All @@ -26,6 +33,11 @@ define i8 @atomic_load_i8_monotonic(i8 *%a) nounwind {
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomic_load_i8_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: lb a0, 0(a0)
; RV32IA-NEXT: ret
%1 = load atomic i8, i8* %a monotonic, align 1
ret i8 %1
}
Expand All @@ -40,6 +52,12 @@ define i8 @atomic_load_i8_acquire(i8 *%a) nounwind {
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomic_load_i8_acquire:
; RV32IA: # %bb.0:
; RV32IA-NEXT: lb a0, 0(a0)
; RV32IA-NEXT: fence r, rw
; RV32IA-NEXT: ret
%1 = load atomic i8, i8* %a acquire, align 1
ret i8 %1
}
Expand All @@ -54,6 +72,13 @@ define i8 @atomic_load_i8_seq_cst(i8 *%a) nounwind {
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomic_load_i8_seq_cst:
; RV32IA: # %bb.0:
; RV32IA-NEXT: fence rw, rw
; RV32IA-NEXT: lb a0, 0(a0)
; RV32IA-NEXT: fence r, rw
; RV32IA-NEXT: ret
%1 = load atomic i8, i8* %a seq_cst, align 1
ret i8 %1
}
Expand All @@ -68,6 +93,11 @@ define i16 @atomic_load_i16_unordered(i16 *%a) nounwind {
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomic_load_i16_unordered:
; RV32IA: # %bb.0:
; RV32IA-NEXT: lh a0, 0(a0)
; RV32IA-NEXT: ret
%1 = load atomic i16, i16* %a unordered, align 2
ret i16 %1
}
Expand All @@ -82,6 +112,11 @@ define i16 @atomic_load_i16_monotonic(i16 *%a) nounwind {
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomic_load_i16_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: lh a0, 0(a0)
; RV32IA-NEXT: ret
%1 = load atomic i16, i16* %a monotonic, align 2
ret i16 %1
}
Expand All @@ -96,6 +131,12 @@ define i16 @atomic_load_i16_acquire(i16 *%a) nounwind {
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomic_load_i16_acquire:
; RV32IA: # %bb.0:
; RV32IA-NEXT: lh a0, 0(a0)
; RV32IA-NEXT: fence r, rw
; RV32IA-NEXT: ret
%1 = load atomic i16, i16* %a acquire, align 2
ret i16 %1
}
Expand All @@ -110,6 +151,13 @@ define i16 @atomic_load_i16_seq_cst(i16 *%a) nounwind {
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomic_load_i16_seq_cst:
; RV32IA: # %bb.0:
; RV32IA-NEXT: fence rw, rw
; RV32IA-NEXT: lh a0, 0(a0)
; RV32IA-NEXT: fence r, rw
; RV32IA-NEXT: ret
%1 = load atomic i16, i16* %a seq_cst, align 2
ret i16 %1
}
Expand All @@ -124,6 +172,11 @@ define i32 @atomic_load_i32_unordered(i32 *%a) nounwind {
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomic_load_i32_unordered:
; RV32IA: # %bb.0:
; RV32IA-NEXT: lw a0, 0(a0)
; RV32IA-NEXT: ret
%1 = load atomic i32, i32* %a unordered, align 4
ret i32 %1
}
Expand All @@ -138,6 +191,11 @@ define i32 @atomic_load_i32_monotonic(i32 *%a) nounwind {
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomic_load_i32_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: lw a0, 0(a0)
; RV32IA-NEXT: ret
%1 = load atomic i32, i32* %a monotonic, align 4
ret i32 %1
}
Expand All @@ -152,6 +210,12 @@ define i32 @atomic_load_i32_acquire(i32 *%a) nounwind {
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomic_load_i32_acquire:
; RV32IA: # %bb.0:
; RV32IA-NEXT: lw a0, 0(a0)
; RV32IA-NEXT: fence r, rw
; RV32IA-NEXT: ret
%1 = load atomic i32, i32* %a acquire, align 4
ret i32 %1
}
Expand All @@ -166,6 +230,13 @@ define i32 @atomic_load_i32_seq_cst(i32 *%a) nounwind {
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomic_load_i32_seq_cst:
; RV32IA: # %bb.0:
; RV32IA-NEXT: fence rw, rw
; RV32IA-NEXT: lw a0, 0(a0)
; RV32IA-NEXT: fence r, rw
; RV32IA-NEXT: ret
%1 = load atomic i32, i32* %a seq_cst, align 4
ret i32 %1
}
Expand All @@ -180,6 +251,16 @@ define i64 @atomic_load_i64_unordered(i64 *%a) nounwind {
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomic_load_i64_unordered:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp)
; RV32IA-NEXT: mv a1, zero
; RV32IA-NEXT: call __atomic_load_8
; RV32IA-NEXT: lw ra, 12(sp)
; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret
%1 = load atomic i64, i64* %a unordered, align 8
ret i64 %1
}
Expand All @@ -194,6 +275,16 @@ define i64 @atomic_load_i64_monotonic(i64 *%a) nounwind {
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomic_load_i64_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp)
; RV32IA-NEXT: mv a1, zero
; RV32IA-NEXT: call __atomic_load_8
; RV32IA-NEXT: lw ra, 12(sp)
; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret
%1 = load atomic i64, i64* %a monotonic, align 8
ret i64 %1
}
Expand All @@ -208,6 +299,16 @@ define i64 @atomic_load_i64_acquire(i64 *%a) nounwind {
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomic_load_i64_acquire:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp)
; RV32IA-NEXT: addi a1, zero, 2
; RV32IA-NEXT: call __atomic_load_8
; RV32IA-NEXT: lw ra, 12(sp)
; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret
%1 = load atomic i64, i64* %a acquire, align 8
ret i64 %1
}
Expand All @@ -222,6 +323,16 @@ define i64 @atomic_load_i64_seq_cst(i64 *%a) nounwind {
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomic_load_i64_seq_cst:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp)
; RV32IA-NEXT: addi a1, zero, 5
; RV32IA-NEXT: call __atomic_load_8
; RV32IA-NEXT: lw ra, 12(sp)
; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret
%1 = load atomic i64, i64* %a seq_cst, align 8
ret i64 %1
}
Expand All @@ -236,6 +347,11 @@ define void @atomic_store_i8_unordered(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomic_store_i8_unordered:
; RV32IA: # %bb.0:
; RV32IA-NEXT: sb a0, 0(a1)
; RV32IA-NEXT: ret
store atomic i8 %b, i8* %a unordered, align 1
ret void
}
Expand All @@ -250,6 +366,11 @@ define void @atomic_store_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomic_store_i8_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: sb a0, 0(a1)
; RV32IA-NEXT: ret
store atomic i8 %b, i8* %a monotonic, align 1
ret void
}
Expand All @@ -264,6 +385,12 @@ define void @atomic_store_i8_release(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomic_store_i8_release:
; RV32IA: # %bb.0:
; RV32IA-NEXT: fence rw, w
; RV32IA-NEXT: sb a0, 0(a1)
; RV32IA-NEXT: ret
store atomic i8 %b, i8* %a release, align 1
ret void
}
Expand All @@ -278,6 +405,12 @@ define void @atomic_store_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomic_store_i8_seq_cst:
; RV32IA: # %bb.0:
; RV32IA-NEXT: fence rw, w
; RV32IA-NEXT: sb a0, 0(a1)
; RV32IA-NEXT: ret
store atomic i8 %b, i8* %a seq_cst, align 1
ret void
}
Expand All @@ -292,6 +425,11 @@ define void @atomic_store_i16_unordered(i16 *%a, i16 %b) nounwind {
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomic_store_i16_unordered:
; RV32IA: # %bb.0:
; RV32IA-NEXT: sh a0, 0(a1)
; RV32IA-NEXT: ret
store atomic i16 %b, i16* %a unordered, align 2
ret void
}
Expand All @@ -306,6 +444,11 @@ define void @atomic_store_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomic_store_i16_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: sh a0, 0(a1)
; RV32IA-NEXT: ret
store atomic i16 %b, i16* %a monotonic, align 2
ret void
}
Expand All @@ -320,6 +463,12 @@ define void @atomic_store_i16_release(i16 *%a, i16 %b) nounwind {
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomic_store_i16_release:
; RV32IA: # %bb.0:
; RV32IA-NEXT: fence rw, w
; RV32IA-NEXT: sh a0, 0(a1)
; RV32IA-NEXT: ret
store atomic i16 %b, i16* %a release, align 2
ret void
}
Expand All @@ -334,6 +483,12 @@ define void @atomic_store_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomic_store_i16_seq_cst:
; RV32IA: # %bb.0:
; RV32IA-NEXT: fence rw, w
; RV32IA-NEXT: sh a0, 0(a1)
; RV32IA-NEXT: ret
store atomic i16 %b, i16* %a seq_cst, align 2
ret void
}
Expand All @@ -348,6 +503,11 @@ define void @atomic_store_i32_unordered(i32 *%a, i32 %b) nounwind {
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomic_store_i32_unordered:
; RV32IA: # %bb.0:
; RV32IA-NEXT: sw a0, 0(a1)
; RV32IA-NEXT: ret
store atomic i32 %b, i32* %a unordered, align 4
ret void
}
Expand All @@ -362,6 +522,11 @@ define void @atomic_store_i32_monotonic(i32 *%a, i32 %b) nounwind {
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomic_store_i32_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: sw a0, 0(a1)
; RV32IA-NEXT: ret
store atomic i32 %b, i32* %a monotonic, align 4
ret void
}
Expand All @@ -376,6 +541,12 @@ define void @atomic_store_i32_release(i32 *%a, i32 %b) nounwind {
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomic_store_i32_release:
; RV32IA: # %bb.0:
; RV32IA-NEXT: fence rw, w
; RV32IA-NEXT: sw a0, 0(a1)
; RV32IA-NEXT: ret
store atomic i32 %b, i32* %a release, align 4
ret void
}
Expand All @@ -390,6 +561,12 @@ define void @atomic_store_i32_seq_cst(i32 *%a, i32 %b) nounwind {
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomic_store_i32_seq_cst:
; RV32IA: # %bb.0:
; RV32IA-NEXT: fence rw, w
; RV32IA-NEXT: sw a0, 0(a1)
; RV32IA-NEXT: ret
store atomic i32 %b, i32* %a seq_cst, align 4
ret void
}
Expand All @@ -404,6 +581,16 @@ define void @atomic_store_i64_unordered(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomic_store_i64_unordered:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp)
; RV32IA-NEXT: mv a3, zero
; RV32IA-NEXT: call __atomic_store_8
; RV32IA-NEXT: lw ra, 12(sp)
; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret
store atomic i64 %b, i64* %a unordered, align 8
ret void
}
Expand All @@ -418,6 +605,16 @@ define void @atomic_store_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomic_store_i64_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp)
; RV32IA-NEXT: mv a3, zero
; RV32IA-NEXT: call __atomic_store_8
; RV32IA-NEXT: lw ra, 12(sp)
; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret
store atomic i64 %b, i64* %a monotonic, align 8
ret void
}
Expand All @@ -432,6 +629,16 @@ define void @atomic_store_i64_release(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomic_store_i64_release:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp)
; RV32IA-NEXT: addi a3, zero, 3
; RV32IA-NEXT: call __atomic_store_8
; RV32IA-NEXT: lw ra, 12(sp)
; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret
store atomic i64 %b, i64* %a release, align 8
ret void
}
Expand All @@ -446,6 +653,16 @@ define void @atomic_store_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomic_store_i64_seq_cst:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp)
; RV32IA-NEXT: addi a3, zero, 5
; RV32IA-NEXT: call __atomic_store_8
; RV32IA-NEXT: lw ra, 12(sp)
; RV32IA-NEXT: addi sp, sp, 16
; RV32IA-NEXT: ret
store atomic i64 %b, i64* %a seq_cst, align 8
ret void
}