diff --git a/llvm/test/CodeGen/X86/add.ll b/llvm/test/CodeGen/X86/add.ll
diff --git a/llvm/test/CodeGen/X86/viabs.ll b/llvm/test/CodeGen/X86/viabs.ll
@@ -1,11 +1,11 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2     | FileCheck %s --check-prefixes=SSE,SSE2
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ssse3    | FileCheck %s --check-prefixes=SSE,SSSE3
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.1   | FileCheck %s --check-prefixes=SSE,SSE41
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx      | FileCheck %s --check-prefixes=AVX,AVX1
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2     | FileCheck %s --check-prefixes=AVX,AVX2
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512vl --show-mc-encoding | FileCheck %s --check-prefixes=AVX,AVX512,AVX512F,AVX512VL
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512vl,+avx512bw --show-mc-encoding | FileCheck %s --check-prefixes=AVX,AVX512,AVX512BW
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2     | FileCheck %s --check-prefix=SSE2
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ssse3    | FileCheck %s --check-prefix=SSSE3
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.1   | FileCheck %s --check-prefix=SSE41
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx      | FileCheck %s --check-prefix=AVX1
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2     | FileCheck %s --check-prefix=AVX2
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512vl --show-mc-encoding | FileCheck %s --check-prefixes=AVX512,AVX512F
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512vl,+avx512bw --show-mc-encoding | FileCheck %s --check-prefixes=AVX512,AVX512BW
 
 define <4 x i32> @test_abs_gt_v4i32(<4 x i32> %a) nounwind {
 ; SSE2-LABEL: test_abs_gt_v4i32:

diff --git a/llvm/test/CodeGen/X86/vp2intersect_multiple_pairs.ll b/llvm/test/CodeGen/X86/vp2intersect_multiple_pairs.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512vp2intersect -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,X86
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vp2intersect -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,X64
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512vp2intersect -verify-machineinstrs | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vp2intersect -verify-machineinstrs | FileCheck %s --check-prefix=X64
 
 ; Test with more than four live mask pairs
 

diff --git a/llvm/test/CodeGen/X86/vshift-1.ll b/llvm/test/CodeGen/X86/vshift-1.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,X86
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,X64
+; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64
 
 ; test vector shifts converted to proper SSE2 vector shifts when the shift
 ; amounts are the same.

diff --git a/llvm/test/CodeGen/X86/vshift-2.ll b/llvm/test/CodeGen/X86/vshift-2.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,X86
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,X64
+; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64
 
 ; test vector shifts converted to proper SSE2 vector shifts when the shift
 ; amounts are the same.

diff --git a/llvm/test/CodeGen/X86/vshift-3.ll b/llvm/test/CodeGen/X86/vshift-3.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,X86
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,X64
+; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64
 
 ; test vector shifts converted to proper SSE2 vector shifts when the shift
 ; amounts are the same.

diff --git a/llvm/test/CodeGen/X86/vshift-4.ll b/llvm/test/CodeGen/X86/vshift-4.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,X86
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,X64
+; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64
 
 ; test vector shifts converted to proper SSE2 vector shifts when the shift
 ; amounts are the same when using a shuffle splat.

diff --git a/llvm/test/CodeGen/X86/vshift-5.ll b/llvm/test/CodeGen/X86/vshift-5.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,X86
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,X64
+; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64
 
 ; When loading the shift amount from memory, avoid generating the splat.
 

diff --git a/llvm/test/CodeGen/X86/vshift-6.ll b/llvm/test/CodeGen/X86/vshift-6.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,X86
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,X64
+; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64
 
 ; This test makes sure that the compiler does not crash with an
 ; assertion failure when trying to fold a vector shift left

diff --git a/llvm/test/CodeGen/X86/widen_arith-4.ll b/llvm/test/CodeGen/X86/widen_arith-4.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,SSE2
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefixes=CHECK,SSE41
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=SSE41
 
 ; Widen a v5i16 to v8i16 to do a vector sub and multiple
 

diff --git a/llvm/test/CodeGen/X86/widen_bitops-0.ll b/llvm/test/CodeGen/X86/widen_bitops-0.ll
diff --git a/llvm/test/CodeGen/X86/widen_bitops-1.ll b/llvm/test/CodeGen/X86/widen_bitops-1.ll
@@ -1,23 +1,23 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=X32-SSE --check-prefix=X32-SSE42
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=X64-SSE --check-prefix=X64-SSE42
+; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=X64
 
 ;
 ; AND/XOR/OR i32 as v4i8
 ;
 
 define i32 @and_i32_as_v4i8(i32 %a, i32 %b) nounwind {
-; X32-SSE-LABEL: and_i32_as_v4i8:
-; X32-SSE:       # %bb.0:
-; X32-SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-SSE-NEXT:    andl {{[0-9]+}}(%esp), %eax
-; X32-SSE-NEXT:    retl
-;
-; X64-SSE-LABEL: and_i32_as_v4i8:
-; X64-SSE:       # %bb.0:
-; X64-SSE-NEXT:    movl %edi, %eax
-; X64-SSE-NEXT:    andl %esi, %eax
-; X64-SSE-NEXT:    retq
+; X86-LABEL: and_i32_as_v4i8:
+; X86:       # %bb.0:
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    retl
+;
+; X64-LABEL: and_i32_as_v4i8:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andl %esi, %eax
+; X64-NEXT:    retq
   %1 = bitcast i32 %a to <4 x i8>
   %2 = bitcast i32 %b to <4 x i8>
   %3 = and <4 x i8> %1, %2
@@ -26,17 +26,17 @@ define i32 @and_i32_as_v4i8(i32 %a, i32 %b) nounwind {
 }
 
 define i32 @xor_i32_as_v4i8(i32 %a, i32 %b) nounwind {
-; X32-SSE-LABEL: xor_i32_as_v4i8:
-; X32-SSE:       # %bb.0:
-; X32-SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-SSE-NEXT:    xorl {{[0-9]+}}(%esp), %eax
-; X32-SSE-NEXT:    retl
-;
-; X64-SSE-LABEL: xor_i32_as_v4i8:
-; X64-SSE:       # %bb.0:
-; X64-SSE-NEXT:    movl %edi, %eax
-; X64-SSE-NEXT:    xorl %esi, %eax
-; X64-SSE-NEXT:    retq
+; X86-LABEL: xor_i32_as_v4i8:
+; X86:       # %bb.0:
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    xorl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    retl
+;
+; X64-LABEL: xor_i32_as_v4i8:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    xorl %esi, %eax
+; X64-NEXT:    retq
   %1 = bitcast i32 %a to <4 x i8>
   %2 = bitcast i32 %b to <4 x i8>
   %3 = xor <4 x i8> %1, %2
@@ -45,17 +45,17 @@ define i32 @xor_i32_as_v4i8(i32 %a, i32 %b) nounwind {
 }
 
 define i32 @or_i32_as_v4i8(i32 %a, i32 %b) nounwind {
-; X32-SSE-LABEL: or_i32_as_v4i8:
-; X32-SSE:       # %bb.0:
-; X32-SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-SSE-NEXT:    orl {{[0-9]+}}(%esp), %eax
-; X32-SSE-NEXT:    retl
-;
-; X64-SSE-LABEL: or_i32_as_v4i8:
-; X64-SSE:       # %bb.0:
-; X64-SSE-NEXT:    movl %edi, %eax
-; X64-SSE-NEXT:    orl %esi, %eax
-; X64-SSE-NEXT:    retq
+; X86-LABEL: or_i32_as_v4i8:
+; X86:       # %bb.0:
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    orl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    retl
+;
+; X64-LABEL: or_i32_as_v4i8:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    orl %esi, %eax
+; X64-NEXT:    retq
   %1 = bitcast i32 %a to <4 x i8>
   %2 = bitcast i32 %b to <4 x i8>
   %3 = or <4 x i8> %1, %2
@@ -68,17 +68,17 @@ define i32 @or_i32_as_v4i8(i32 %a, i32 %b) nounwind {
 ;
 
 define i32 @and_i32_as_v8i4(i32 %a, i32 %b) nounwind {
-; X32-SSE-LABEL: and_i32_as_v8i4:
-; X32-SSE:       # %bb.0:
-; X32-SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-SSE-NEXT:    andl {{[0-9]+}}(%esp), %eax
-; X32-SSE-NEXT:    retl
-;
-; X64-SSE-LABEL: and_i32_as_v8i4:
-; X64-SSE:       # %bb.0:
-; X64-SSE-NEXT:    movl %edi, %eax
-; X64-SSE-NEXT:    andl %esi, %eax
-; X64-SSE-NEXT:    retq
+; X86-LABEL: and_i32_as_v8i4:
+; X86:       # %bb.0:
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    retl
+;
+; X64-LABEL: and_i32_as_v8i4:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    andl %esi, %eax
+; X64-NEXT:    retq
   %1 = bitcast i32 %a to <8 x i4>
   %2 = bitcast i32 %b to <8 x i4>
   %3 = and <8 x i4> %1, %2
@@ -87,17 +87,17 @@ define i32 @and_i32_as_v8i4(i32 %a, i32 %b) nounwind {
 }
 
 define i32 @xor_i32_as_v8i4(i32 %a, i32 %b) nounwind {
-; X32-SSE-LABEL: xor_i32_as_v8i4:
-; X32-SSE:       # %bb.0:
-; X32-SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-SSE-NEXT:    xorl {{[0-9]+}}(%esp), %eax
-; X32-SSE-NEXT:    retl
-;
-; X64-SSE-LABEL: xor_i32_as_v8i4:
-; X64-SSE:       # %bb.0:
-; X64-SSE-NEXT:    movl %edi, %eax
-; X64-SSE-NEXT:    xorl %esi, %eax
-; X64-SSE-NEXT:    retq
+; X86-LABEL: xor_i32_as_v8i4:
+; X86:       # %bb.0:
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    xorl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    retl
+;
+; X64-LABEL: xor_i32_as_v8i4:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    xorl %esi, %eax
+; X64-NEXT:    retq
   %1 = bitcast i32 %a to <8 x i4>
   %2 = bitcast i32 %b to <8 x i4>
   %3 = xor <8 x i4> %1, %2
@@ -106,17 +106,17 @@ define i32 @xor_i32_as_v8i4(i32 %a, i32 %b) nounwind {
 }
 
 define i32 @or_i32_as_v8i4(i32 %a, i32 %b) nounwind {
-; X32-SSE-LABEL: or_i32_as_v8i4:
-; X32-SSE:       # %bb.0:
-; X32-SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-SSE-NEXT:    orl {{[0-9]+}}(%esp), %eax
-; X32-SSE-NEXT:    retl
-;
-; X64-SSE-LABEL: or_i32_as_v8i4:
-; X64-SSE:       # %bb.0:
-; X64-SSE-NEXT:    movl %edi, %eax
-; X64-SSE-NEXT:    orl %esi, %eax
-; X64-SSE-NEXT:    retq
+; X86-LABEL: or_i32_as_v8i4:
+; X86:       # %bb.0:
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    orl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    retl
+;
+; X64-LABEL: or_i32_as_v8i4:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    orl %esi, %eax
+; X64-NEXT:    retq
   %1 = bitcast i32 %a to <8 x i4>
   %2 = bitcast i32 %b to <8 x i4>
   %3 = or <8 x i4> %1, %2
@@ -129,15 +129,15 @@ define i32 @or_i32_as_v8i4(i32 %a, i32 %b) nounwind {
 ;
 
 define <4 x i8> @and_v4i8_as_i32(<4 x i8> %a, <4 x i8> %b) nounwind {
-; X32-SSE-LABEL: and_v4i8_as_i32:
-; X32-SSE:       # %bb.0:
-; X32-SSE-NEXT:    andps %xmm1, %xmm0
-; X32-SSE-NEXT:    retl
-;
-; X64-SSE-LABEL: and_v4i8_as_i32:
-; X64-SSE:       # %bb.0:
-; X64-SSE-NEXT:    andps %xmm1, %xmm0
-; X64-SSE-NEXT:    retq
+; X86-LABEL: and_v4i8_as_i32:
+; X86:       # %bb.0:
+; X86-NEXT:    andps %xmm1, %xmm0
+; X86-NEXT:    retl
+;
+; X64-LABEL: and_v4i8_as_i32:
+; X64:       # %bb.0:
+; X64-NEXT:    andps %xmm1, %xmm0
+; X64-NEXT:    retq
   %1 = bitcast <4 x i8> %a to i32
   %2 = bitcast <4 x i8> %b to i32
   %3 = and i32 %1, %2
@@ -146,15 +146,15 @@ define <4 x i8> @and_v4i8_as_i32(<4 x i8> %a, <4 x i8> %b) nounwind {
 }
 
 define <4 x i8> @xor_v4i8_as_i32(<4 x i8> %a, <4 x i8> %b) nounwind {
-; X32-SSE-LABEL: xor_v4i8_as_i32:
-; X32-SSE:       # %bb.0:
-; X32-SSE-NEXT:    xorps %xmm1, %xmm0
-; X32-SSE-NEXT:    retl
-;
-; X64-SSE-LABEL: xor_v4i8_as_i32:
-; X64-SSE:       # %bb.0:
-; X64-SSE-NEXT:    xorps %xmm1, %xmm0
-; X64-SSE-NEXT:    retq
+; X86-LABEL: xor_v4i8_as_i32:
+; X86:       # %bb.0:
+; X86-NEXT:    xorps %xmm1, %xmm0
+; X86-NEXT:    retl
+;
+; X64-LABEL: xor_v4i8_as_i32:
+; X64:       # %bb.0:
+; X64-NEXT:    xorps %xmm1, %xmm0
+; X64-NEXT:    retq
   %1 = bitcast <4 x i8> %a to i32
   %2 = bitcast <4 x i8> %b to i32
   %3 = xor i32 %1, %2
@@ -163,15 +163,15 @@ define <4 x i8> @xor_v4i8_as_i32(<4 x i8> %a, <4 x i8> %b) nounwind {
 }
 
 define <4 x i8> @or_v4i8_as_i32(<4 x i8> %a, <4 x i8> %b) nounwind {
-; X32-SSE-LABEL: or_v4i8_as_i32:
-; X32-SSE:       # %bb.0:
-; X32-SSE-NEXT:    orps %xmm1, %xmm0
-; X32-SSE-NEXT:    retl
-;
-; X64-SSE-LABEL: or_v4i8_as_i32:
-; X64-SSE:       # %bb.0:
-; X64-SSE-NEXT:    orps %xmm1, %xmm0
-; X64-SSE-NEXT:    retq
+; X86-LABEL: or_v4i8_as_i32:
+; X86:       # %bb.0:
+; X86-NEXT:    orps %xmm1, %xmm0
+; X86-NEXT:    retl
+;
+; X64-LABEL: or_v4i8_as_i32:
+; X64:       # %bb.0:
+; X64-NEXT:    orps %xmm1, %xmm0
+; X64-NEXT:    retq
   %1 = bitcast <4 x i8> %a to i32
   %2 = bitcast <4 x i8> %b to i32
   %3 = or i32 %1, %2
@@ -184,15 +184,15 @@ define <4 x i8> @or_v4i8_as_i32(<4 x i8> %a, <4 x i8> %b) nounwind {
 ;
 
 define <8 x i4> @and_v8i4_as_i32(<8 x i4> %a, <8 x i4> %b) nounwind {
-; X32-SSE-LABEL: and_v8i4_as_i32:
-; X32-SSE:       # %bb.0:
-; X32-SSE-NEXT:    andps %xmm1, %xmm0
-; X32-SSE-NEXT:    retl
-;
-; X64-SSE-LABEL: and_v8i4_as_i32:
-; X64-SSE:       # %bb.0:
-; X64-SSE-NEXT:    andps %xmm1, %xmm0
-; X64-SSE-NEXT:    retq
+; X86-LABEL: and_v8i4_as_i32:
+; X86:       # %bb.0:
+; X86-NEXT:    andps %xmm1, %xmm0
+; X86-NEXT:    retl
+;
+; X64-LABEL: and_v8i4_as_i32:
+; X64:       # %bb.0:
+; X64-NEXT:    andps %xmm1, %xmm0
+; X64-NEXT:    retq
   %1 = bitcast <8 x i4> %a to i32
   %2 = bitcast <8 x i4> %b to i32
   %3 = and i32 %1, %2
@@ -201,15 +201,15 @@ define <8 x i4> @and_v8i4_as_i32(<8 x i4> %a, <8 x i4> %b) nounwind {
 }
 
 define <8 x i4> @xor_v8i4_as_i32(<8 x i4> %a, <8 x i4> %b) nounwind {
-; X32-SSE-LABEL: xor_v8i4_as_i32:
-; X32-SSE:       # %bb.0:
-; X32-SSE-NEXT:    xorps %xmm1, %xmm0
-; X32-SSE-NEXT:    retl
-;
-; X64-SSE-LABEL: xor_v8i4_as_i32:
-; X64-SSE:       # %bb.0:
-; X64-SSE-NEXT:    xorps %xmm1, %xmm0
-; X64-SSE-NEXT:    retq
+; X86-LABEL: xor_v8i4_as_i32:
+; X86:       # %bb.0:
+; X86-NEXT:    xorps %xmm1, %xmm0
+; X86-NEXT:    retl
+;
+; X64-LABEL: xor_v8i4_as_i32:
+; X64:       # %bb.0:
+; X64-NEXT:    xorps %xmm1, %xmm0
+; X64-NEXT:    retq
   %1 = bitcast <8 x i4> %a to i32
   %2 = bitcast <8 x i4> %b to i32
   %3 = xor i32 %1, %2
@@ -218,15 +218,15 @@ define <8 x i4> @xor_v8i4_as_i32(<8 x i4> %a, <8 x i4> %b) nounwind {
 }
 
 define <8 x i4> @or_v8i4_as_i32(<8 x i4> %a, <8 x i4> %b) nounwind {
-; X32-SSE-LABEL: or_v8i4_as_i32:
-; X32-SSE:       # %bb.0:
-; X32-SSE-NEXT:    orps %xmm1, %xmm0
-; X32-SSE-NEXT:    retl
-;
-; X64-SSE-LABEL: or_v8i4_as_i32:
-; X64-SSE:       # %bb.0:
-; X64-SSE-NEXT:    orps %xmm1, %xmm0
-; X64-SSE-NEXT:    retq
+; X86-LABEL: or_v8i4_as_i32:
+; X86:       # %bb.0:
+; X86-NEXT:    orps %xmm1, %xmm0
+; X86-NEXT:    retl
+;
+; X64-LABEL: or_v8i4_as_i32:
+; X64:       # %bb.0:
+; X64-NEXT:    orps %xmm1, %xmm0
+; X64-NEXT:    retq
   %1 = bitcast <8 x i4> %a to i32
   %2 = bitcast <8 x i4> %b to i32
   %3 = or i32 %1, %2

diff --git a/llvm/test/CodeGen/X86/widen_conv-3.ll b/llvm/test/CodeGen/X86/widen_conv-3.ll
@@ -1,8 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X86 --check-prefix=X86-SSE2
-; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=X86 --check-prefix=X86-SSE42
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64 --check-prefix=X64-SSE2
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=X64 --check-prefix=X64-SSE42
+; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X86-SSE2
+; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=X86-SSE42
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64-SSE2
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=X64-SSE42
 
 ; sign to float v2i16 to v2f32
 

diff --git a/llvm/test/CodeGen/X86/widen_conv-4.ll b/llvm/test/CodeGen/X86/widen_conv-4.ll
@@ -1,8 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X86 --check-prefix=X86-SSE2
-; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=X86 --check-prefix=X86-SSE42
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64 --check-prefix=X64-SSE2
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=X64 --check-prefix=X64-SSE42
+; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X86-SSE2
+; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=X86-SSE42
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64-SSE2
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=X64-SSE42
 
 ; unsigned to float v7i16 to v7f32
 

diff --git a/llvm/test/CodeGen/X86/widen_load-3.ll b/llvm/test/CodeGen/X86/widen_load-3.ll
@@ -1,10 +1,10 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i686-linux -mattr=+sse4.2 | FileCheck %s --check-prefix=X86 --check-prefix=X86-SSE
-; RUN: llc < %s -mtriple=i686-linux -mattr=+avx    | FileCheck %s --check-prefix=X86 --check-prefix=X86-AVX --check-prefix=X86-AVX1
-; RUN: llc < %s -mtriple=i686-linux -mattr=+avx2   | FileCheck %s --check-prefix=X86 --check-prefix=X86-AVX --check-prefix=X86-AVX2
-; RUN: llc < %s -mtriple=x86_64-linux -mattr=+sse4.2 | FileCheck %s --check-prefix=X64 --check-prefix=X64-SSE
-; RUN: llc < %s -mtriple=x86_64-linux -mattr=+avx    | FileCheck %s --check-prefix=X64 --check-prefix=X64-AVX --check-prefix=X64-AVX1
-; RUN: llc < %s -mtriple=x86_64-linux -mattr=+avx2   | FileCheck %s --check-prefix=X64 --check-prefix=X64-AVX --check-prefix=X64-AVX2
+; RUN: llc < %s -mtriple=i686-linux -mattr=+sse4.2 | FileCheck %s --check-prefix=X86-SSE
+; RUN: llc < %s -mtriple=i686-linux -mattr=+avx    | FileCheck %s --check-prefix=X86-AVX
+; RUN: llc < %s -mtriple=i686-linux -mattr=+avx2   | FileCheck %s --check-prefix=X86-AVX
+; RUN: llc < %s -mtriple=x86_64-linux -mattr=+sse4.2 | FileCheck %s --check-prefix=X64-SSE
+; RUN: llc < %s -mtriple=x86_64-linux -mattr=+avx    | FileCheck %s --check-prefix=X64-AVX
+; RUN: llc < %s -mtriple=x86_64-linux -mattr=+avx2   | FileCheck %s --check-prefix=X64-AVX
 
 ; PR27708
 

diff --git a/llvm/test/CodeGen/X86/widen_mul.ll b/llvm/test/CodeGen/X86/widen_mul.ll
@@ -1,9 +1,9 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=SSE --check-prefix=SSE2
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE --check-prefix=SSE41
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=AVX --check-prefix=AVX512 --check-prefix=AVX512F
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefix=AVX --check-prefix=AVX512 --check-prefix=AVX512BW
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=AVX
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefix=AVX
 
 ; Test multiplies of various narrow types.
 

diff --git a/llvm/test/CodeGen/X86/widened-broadcast.ll b/llvm/test/CodeGen/X86/widened-broadcast.ll
@@ -3,7 +3,7 @@
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=SSE --check-prefix=SSE42
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=AVX --check-prefix=AVX512 --check-prefix=AVX512F
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=AVX --check-prefix=AVX512
 
 ; Widened shuffle broadcast loads
 

diff --git a/llvm/test/CodeGen/X86/win64_frame.ll b/llvm/test/CodeGen/X86/win64_frame.ll
diff --git a/llvm/test/CodeGen/X86/xaluo128.ll b/llvm/test/CodeGen/X86/xaluo128.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=x86_64-darwin-unknown < %s | FileCheck %s --check-prefix=SDAG --check-prefix=X64
-; RUN: llc -mtriple=i686-darwin-unknown < %s | FileCheck %s --check-prefix=SDAG --check-prefix=X86
+; RUN: llc -mtriple=x86_64-darwin-unknown < %s | FileCheck %s --check-prefix=X64
+; RUN: llc -mtriple=i686-darwin-unknown < %s | FileCheck %s --check-prefix=X86
 
 define zeroext i1 @saddoi128(i128 %v1, i128 %v2, i128* %res) nounwind {
 ; X64-LABEL: saddoi128:

diff --git a/llvm/test/CodeGen/X86/xmulo.ll b/llvm/test/CodeGen/X86/xmulo.ll
@@ -1,60 +1,38 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -disable-peephole -mtriple=x86_64-darwin-unknown < %s | FileCheck %s --check-prefix=SDAG
-; RUN: llc -disable-peephole -mtriple=x86_64-darwin-unknown -fast-isel -fast-isel-abort=1 < %s | FileCheck %s --check-prefix=FAST
-; RUN: llc -disable-peephole -mtriple=x86_64-darwin-unknown -mcpu=knl < %s | FileCheck %s --check-prefix=SDAG --check-prefix=KNL
+; RUN: llc -disable-peephole -mtriple=x86_64-darwin-unknown < %s | FileCheck %s --check-prefixes=CHECK,SDAG
+; RUN: llc -disable-peephole -mtriple=x86_64-darwin-unknown -fast-isel -fast-isel-abort=1 < %s | FileCheck %s --check-prefixes=CHECK,FAST
+; RUN: llc -disable-peephole -mtriple=x86_64-darwin-unknown -mcpu=knl < %s | FileCheck %s --check-prefixes=CHECK,SDAG
 
 define {i64, i1} @t1() nounwind {
-; SDAG-LABEL: t1:
-; SDAG:       ## %bb.0:
-; SDAG-NEXT:    movl $8, %ecx
-; SDAG-NEXT:    movl $9, %eax
-; SDAG-NEXT:    mulq %rcx
-; SDAG-NEXT:    seto %dl
-; SDAG-NEXT:    retq
-;
-; FAST-LABEL: t1:
-; FAST:       ## %bb.0:
-; FAST-NEXT:    movl $8, %ecx
-; FAST-NEXT:    movl $9, %eax
-; FAST-NEXT:    mulq %rcx
-; FAST-NEXT:    seto %dl
-; FAST-NEXT:    retq
+; CHECK-LABEL: t1:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    movl $8, %ecx
+; CHECK-NEXT:    movl $9, %eax
+; CHECK-NEXT:    mulq %rcx
+; CHECK-NEXT:    seto %dl
+; CHECK-NEXT:    retq
   %1 = call {i64, i1} @llvm.umul.with.overflow.i64(i64 9, i64 8)
   ret {i64, i1} %1
 }
 
 define {i64, i1} @t2() nounwind {
-; SDAG-LABEL: t2:
-; SDAG:       ## %bb.0:
-; SDAG-NEXT:    xorl %eax, %eax
-; SDAG-NEXT:    xorl %edx, %edx
-; SDAG-NEXT:    retq
-;
-; FAST-LABEL: t2:
-; FAST:       ## %bb.0:
-; FAST-NEXT:    xorl %eax, %eax
-; FAST-NEXT:    xorl %edx, %edx
-; FAST-NEXT:    retq
+; CHECK-LABEL: t2:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    xorl %eax, %eax
+; CHECK-NEXT:    xorl %edx, %edx
+; CHECK-NEXT:    retq
   %1 = call {i64, i1} @llvm.umul.with.overflow.i64(i64 9, i64 0)
   ret {i64, i1} %1
 }
 
 define {i64, i1} @t3() nounwind {
-; SDAG-LABEL: t3:
-; SDAG:       ## %bb.0:
-; SDAG-NEXT:    movq $-1, %rcx
-; SDAG-NEXT:    movl $9, %eax
-; SDAG-NEXT:    mulq %rcx
-; SDAG-NEXT:    seto %dl
-; SDAG-NEXT:    retq
-;
-; FAST-LABEL: t3:
-; FAST:       ## %bb.0:
-; FAST-NEXT:    movq $-1, %rcx
-; FAST-NEXT:    movl $9, %eax
-; FAST-NEXT:    mulq %rcx
-; FAST-NEXT:    seto %dl
-; FAST-NEXT:    retq
+; CHECK-LABEL: t3:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    movq $-1, %rcx
+; CHECK-NEXT:    movl $9, %eax
+; CHECK-NEXT:    mulq %rcx
+; CHECK-NEXT:    seto %dl
+; CHECK-NEXT:    retq
   %1 = call {i64, i1} @llvm.umul.with.overflow.i64(i64 9, i64 -1)
   ret {i64, i1} %1
 }
@@ -276,87 +254,55 @@ define zeroext i1 @umuloi64(i64 %v1, i64 %v2, i64* %res) {
 ; Check the use of the overflow bit in combination with a select instruction.
 ;
 define i32 @smuloselecti32(i32 %v1, i32 %v2) {
-; SDAG-LABEL: smuloselecti32:
-; SDAG:       ## %bb.0:
-; SDAG-NEXT:    movl %esi, %eax
-; SDAG-NEXT:    movl %edi, %ecx
-; SDAG-NEXT:    imull %esi, %ecx
-; SDAG-NEXT:    cmovol %edi, %eax
-; SDAG-NEXT:    retq
-;
-; FAST-LABEL: smuloselecti32:
-; FAST:       ## %bb.0:
-; FAST-NEXT:    movl %esi, %eax
-; FAST-NEXT:    movl %edi, %ecx
-; FAST-NEXT:    imull %esi, %ecx
-; FAST-NEXT:    cmovol %edi, %eax
-; FAST-NEXT:    retq
+; CHECK-LABEL: smuloselecti32:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    movl %esi, %eax
+; CHECK-NEXT:    movl %edi, %ecx
+; CHECK-NEXT:    imull %esi, %ecx
+; CHECK-NEXT:    cmovol %edi, %eax
+; CHECK-NEXT:    retq
   %t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
   %obit = extractvalue {i32, i1} %t, 1
   %ret = select i1 %obit, i32 %v1, i32 %v2
   ret i32 %ret
 }
 
 define i64 @smuloselecti64(i64 %v1, i64 %v2) {
-; SDAG-LABEL: smuloselecti64:
-; SDAG:       ## %bb.0:
-; SDAG-NEXT:    movq %rsi, %rax
-; SDAG-NEXT:    movq %rdi, %rcx
-; SDAG-NEXT:    imulq %rsi, %rcx
-; SDAG-NEXT:    cmovoq %rdi, %rax
-; SDAG-NEXT:    retq
-;
-; FAST-LABEL: smuloselecti64:
-; FAST:       ## %bb.0:
-; FAST-NEXT:    movq %rsi, %rax
-; FAST-NEXT:    movq %rdi, %rcx
-; FAST-NEXT:    imulq %rsi, %rcx
-; FAST-NEXT:    cmovoq %rdi, %rax
-; FAST-NEXT:    retq
+; CHECK-LABEL: smuloselecti64:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    movq %rsi, %rax
+; CHECK-NEXT:    movq %rdi, %rcx
+; CHECK-NEXT:    imulq %rsi, %rcx
+; CHECK-NEXT:    cmovoq %rdi, %rax
+; CHECK-NEXT:    retq
   %t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
   %obit = extractvalue {i64, i1} %t, 1
   %ret = select i1 %obit, i64 %v1, i64 %v2
   ret i64 %ret
 }
 
 define i32 @umuloselecti32(i32 %v1, i32 %v2) {
-; SDAG-LABEL: umuloselecti32:
-; SDAG:       ## %bb.0:
-; SDAG-NEXT:    movl %edi, %eax
-; SDAG-NEXT:    mull %esi
-; SDAG-NEXT:    cmovol %edi, %esi
-; SDAG-NEXT:    movl %esi, %eax
-; SDAG-NEXT:    retq
-;
-; FAST-LABEL: umuloselecti32:
-; FAST:       ## %bb.0:
-; FAST-NEXT:    movl %edi, %eax
-; FAST-NEXT:    mull %esi
-; FAST-NEXT:    cmovol %edi, %esi
-; FAST-NEXT:    movl %esi, %eax
-; FAST-NEXT:    retq
+; CHECK-LABEL: umuloselecti32:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    mull %esi
+; CHECK-NEXT:    cmovol %edi, %esi
+; CHECK-NEXT:    movl %esi, %eax
+; CHECK-NEXT:    retq
   %t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
   %obit = extractvalue {i32, i1} %t, 1
   %ret = select i1 %obit, i32 %v1, i32 %v2
   ret i32 %ret
 }
 
 define i64 @umuloselecti64(i64 %v1, i64 %v2) {
-; SDAG-LABEL: umuloselecti64:
-; SDAG:       ## %bb.0:
-; SDAG-NEXT:    movq %rdi, %rax
-; SDAG-NEXT:    mulq %rsi
-; SDAG-NEXT:    cmovoq %rdi, %rsi
-; SDAG-NEXT:    movq %rsi, %rax
-; SDAG-NEXT:    retq
-;
-; FAST-LABEL: umuloselecti64:
-; FAST:       ## %bb.0:
-; FAST-NEXT:    movq %rdi, %rax
-; FAST-NEXT:    mulq %rsi
-; FAST-NEXT:    cmovoq %rdi, %rsi
-; FAST-NEXT:    movq %rsi, %rax
-; FAST-NEXT:    retq
+; CHECK-LABEL: umuloselecti64:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    movq %rdi, %rax
+; CHECK-NEXT:    mulq %rsi
+; CHECK-NEXT:    cmovoq %rdi, %rsi
+; CHECK-NEXT:    movq %rsi, %rax
+; CHECK-NEXT:    retq
   %t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
   %obit = extractvalue {i64, i1} %t, 1
   %ret = select i1 %obit, i64 %v1, i64 %v2
@@ -695,23 +641,14 @@ continue:
 }
 
 define i1 @bug27873(i64 %c1, i1 %c2) {
-; SDAG-LABEL: bug27873:
-; SDAG:       ## %bb.0:
-; SDAG-NEXT:    movq %rdi, %rax
-; SDAG-NEXT:    movl $160, %ecx
-; SDAG-NEXT:    mulq %rcx
-; SDAG-NEXT:    seto %al
-; SDAG-NEXT:    orb %sil, %al
-; SDAG-NEXT:    retq
-;
-; FAST-LABEL: bug27873:
-; FAST:       ## %bb.0:
-; FAST-NEXT:    movq %rdi, %rax
-; FAST-NEXT:    movl $160, %ecx
-; FAST-NEXT:    mulq %rcx
-; FAST-NEXT:    seto %al
-; FAST-NEXT:    orb %sil, %al
-; FAST-NEXT:    retq
+; CHECK-LABEL: bug27873:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    movq %rdi, %rax
+; CHECK-NEXT:    movl $160, %ecx
+; CHECK-NEXT:    mulq %rcx
+; CHECK-NEXT:    seto %al
+; CHECK-NEXT:    orb %sil, %al
+; CHECK-NEXT:    retq
   %mul = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %c1, i64 160)
   %mul.overflow = extractvalue { i64, i1 } %mul, 1
   %x1 = or i1 %c2, %mul.overflow

diff --git a/llvm/test/CodeGen/X86/xop-intrinsics-fast-isel.ll b/llvm/test/CodeGen/X86/xop-intrinsics-fast-isel.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -fast-isel -mtriple=i686-unknown-unknown -mattr=+avx,+fma4,+xop | FileCheck %s --check-prefixes=CHECK,X86
-; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+avx,+fma4,+xop | FileCheck %s --check-prefixes=CHECK,X64
+; RUN: llc < %s -fast-isel -mtriple=i686-unknown-unknown -mattr=+avx,+fma4,+xop | FileCheck %s
+; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+avx,+fma4,+xop | FileCheck %s
 
 ; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/xop-builtins.c
 

diff --git a/llvm/test/CodeGen/X86/xor-icmp.ll b/llvm/test/CodeGen/X86/xor-icmp.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i686-unknown   | FileCheck %s --check-prefixes=CHECK,X86
-; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s --check-prefixes=CHECK,X64
+; RUN: llc < %s -mtriple=i686-unknown   | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s --check-prefix=X64
 ; rdar://7367229
 
 define i32 @t(i32 %a, i32 %b) nounwind ssp {

diff --git a/llvm/test/CodeGen/X86/xor.ll b/llvm/test/CodeGen/X86/xor.ll
@@ -1,7 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,X86
-; RUN: llc < %s -mtriple=x86_64-linux -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,X64,X64-LIN
-; RUN: llc < %s -mtriple=x86_64-win32 -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,X64,X64-WIN
+; RUN: llc < %s -mtriple=x86_64-linux -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,X64-LIN
+; RUN: llc < %s -mtriple=x86_64-win32 -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,X64-WIN
 
 ; Though it is undefined, we want xor undef,undef to produce zero.
 define <4 x i32> @test1() nounwind {