134 changes: 66 additions & 68 deletions llvm/lib/CodeGen/Passes.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -235,8 +235,8 @@ TargetPassConfig::~TargetPassConfig() {
// registers all common codegen passes.
TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm)
: ImmutablePass(ID), PM(&pm), StartAfter(nullptr), StopAfter(nullptr),
Started(true), Stopped(false), TM(tm), Impl(nullptr), Initialized(false),
DisableVerify(false),
Started(true), Stopped(false), AddingMachinePasses(false), TM(tm),
Impl(nullptr), Initialized(false), DisableVerify(false),
EnableTailMerge(true) {

Impl = new PassConfigImpl();
Expand Down Expand Up @@ -304,7 +304,7 @@ IdentifyingPassPtr TargetPassConfig::getPassSubstitution(AnalysisID ID) const {
/// a later pass or that it should stop after an earlier pass, then do not add
/// the pass. Finally, compare the current pass against the StartAfter
/// and StopAfter options and change the Started/Stopped flags accordingly.
void TargetPassConfig::addPass(Pass *P) {
void TargetPassConfig::addPass(Pass *P, bool verifyAfter, bool printAfter) {
assert(!Initialized && "PassConfig is immutable");

// Cache the Pass ID here in case the pass manager finds this pass is
Expand All @@ -313,10 +313,21 @@ void TargetPassConfig::addPass(Pass *P) {
// and shouldn't reference it.
AnalysisID PassID = P->getPassID();

if (Started && !Stopped)
if (Started && !Stopped) {
std::string Banner;
// Construct banner message before PM->add() as that may delete the pass.
if (AddingMachinePasses && (printAfter || verifyAfter))
Banner = std::string("After ") + std::string(P->getPassName());
PM->add(P);
else
if (AddingMachinePasses) {
if (printAfter)
addPrintPass(Banner);
if (verifyAfter)
addVerifyPass(Banner);
}
} else {
delete P;
}
if (StopAfter == PassID)
Stopped = true;
if (StartAfter == PassID)
Expand All @@ -330,7 +341,8 @@ void TargetPassConfig::addPass(Pass *P) {
///
/// addPass cannot return a pointer to the pass instance because is internal the
/// PassManager and the instance we create here may already be freed.
AnalysisID TargetPassConfig::addPass(AnalysisID PassID) {
AnalysisID TargetPassConfig::addPass(AnalysisID PassID, bool verifyAfter,
bool printAfter) {
IdentifyingPassPtr TargetID = getPassSubstitution(PassID);
IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID);
if (!FinalPtr.isValid())
Expand All @@ -345,7 +357,7 @@ AnalysisID TargetPassConfig::addPass(AnalysisID PassID) {
llvm_unreachable("Pass ID not registered");
}
AnalysisID FinalID = P->getPassID();
addPass(P); // Ends the lifetime of P.
addPass(P, verifyAfter, printAfter); // Ends the lifetime of P.

// Add the passes after the pass P if there is any.
for (SmallVectorImpl<std::pair<AnalysisID, IdentifyingPassPtr> >::iterator
Expand All @@ -360,18 +372,25 @@ AnalysisID TargetPassConfig::addPass(AnalysisID PassID) {
NP = Pass::createPass((*I).second.getID());
assert(NP && "Pass ID not registered");
}
addPass(NP);
addPass(NP, false, false);
}
}
return FinalID;
}

void TargetPassConfig::printAndVerify(const char *Banner) {
void TargetPassConfig::printAndVerify(const std::string &Banner) {
addPrintPass(Banner);
addVerifyPass(Banner);
}

void TargetPassConfig::addPrintPass(const std::string &Banner) {
if (TM->shouldPrintMachineCode())
addPass(createMachineFunctionPrinterPass(dbgs(), Banner));
PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
}

void TargetPassConfig::addVerifyPass(const std::string &Banner) {
if (VerifyMachineCode)
addPass(createMachineVerifierPass(Banner));
PM->add(createMachineVerifierPass(Banner));
}

/// Add common target configurable passes that perform LLVM IR to IR transforms
Expand Down Expand Up @@ -491,6 +510,8 @@ void TargetPassConfig::addISelPrepare() {
/// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
/// before/after any target-independent pass. But it's currently overkill.
void TargetPassConfig::addMachinePasses() {
AddingMachinePasses = true;

// Insert a machine instr printer pass after the specified pass.
// If -print-machineinstrs specified, print machineinstrs after all passes.
if (StringRef(PrintMachineInstrs.getValue()).equals(""))
Expand All @@ -510,21 +531,19 @@ void TargetPassConfig::addMachinePasses() {
printAndVerify("After Instruction Selection");

// Expand pseudo-instructions emitted by ISel.
if (addPass(&ExpandISelPseudosID))
printAndVerify("After ExpandISelPseudos");
addPass(&ExpandISelPseudosID);

// Add passes that optimize machine instructions in SSA form.
if (getOptLevel() != CodeGenOpt::None) {
addMachineSSAOptimization();
} else {
// If the target requests it, assign local variables to stack slots relative
// to one another and simplify frame index references where possible.
addPass(&LocalStackSlotAllocationID);
addPass(&LocalStackSlotAllocationID, false);
}

// Run pre-ra passes.
if (addPreRegAlloc())
printAndVerify("After PreRegAlloc passes");
addPreRegAlloc();

// Run register allocation and passes that are tightly coupled with it,
// including phi elimination and scheduling.
Expand All @@ -534,91 +553,82 @@ void TargetPassConfig::addMachinePasses() {
addFastRegAlloc(createRegAllocPass(false));

// Run post-ra passes.
if (addPostRegAlloc())
printAndVerify("After PostRegAlloc passes");
addPostRegAlloc();

// Insert prolog/epilog code. Eliminate abstract frame index references...
addPass(&PrologEpilogCodeInserterID);
printAndVerify("After PrologEpilogCodeInserter");

/// Add passes that optimize machine instructions after register allocation.
if (getOptLevel() != CodeGenOpt::None)
addMachineLateOptimization();

// Expand pseudo instructions before second scheduling pass.
addPass(&ExpandPostRAPseudosID);
printAndVerify("After ExpandPostRAPseudos");

// Run pre-sched2 passes.
if (addPreSched2())
printAndVerify("After PreSched2 passes");
addPreSched2();

// Second pass scheduler.
if (getOptLevel() != CodeGenOpt::None) {
if (MISchedPostRA)
addPass(&PostMachineSchedulerID);
else
addPass(&PostRASchedulerID);
printAndVerify("After PostRAScheduler");
}

// GC
if (addGCPasses()) {
if (PrintGCInfo)
addPass(createGCInfoPrinter(dbgs()));
addPass(createGCInfoPrinter(dbgs()), false, false);
}

// Basic block placement.
if (getOptLevel() != CodeGenOpt::None)
addBlockPlacement();

if (addPreEmitPass())
printAndVerify("After PreEmit passes");
addPreEmitPass();

addPass(&StackMapLivenessID, false);

addPass(&StackMapLivenessID);
AddingMachinePasses = false;
}

/// Add passes that optimize machine instructions in SSA form.
void TargetPassConfig::addMachineSSAOptimization() {
// Pre-ra tail duplication.
if (addPass(&EarlyTailDuplicateID))
printAndVerify("After Pre-RegAlloc TailDuplicate");
addPass(&EarlyTailDuplicateID);

// Optimize PHIs before DCE: removing dead PHI cycles may make more
// instructions dead.
addPass(&OptimizePHIsID);
addPass(&OptimizePHIsID, false);

// This pass merges large allocas. StackSlotColoring is a different pass
// which merges spill slots.
addPass(&StackColoringID);
addPass(&StackColoringID, false);

// If the target requests it, assign local variables to stack slots relative
// to one another and simplify frame index references where possible.
addPass(&LocalStackSlotAllocationID);
addPass(&LocalStackSlotAllocationID, false);

// With optimization, dead code should already be eliminated. However
// there is one known exception: lowered code for arguments that are only
// used by tail calls, where the tail calls reuse the incoming stack
// arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
addPass(&DeadMachineInstructionElimID);
printAndVerify("After codegen DCE pass");

// Allow targets to insert passes that improve instruction level parallelism,
// like if-conversion. Such passes will typically need dominator trees and
// loop info, just like LICM and CSE below.
if (addILPOpts())
printAndVerify("After ILP optimizations");
addILPOpts();

addPass(&MachineLICMID);
addPass(&MachineCSEID);
addPass(&MachineLICMID, false);
addPass(&MachineCSEID, false);
addPass(&MachineSinkingID);
printAndVerify("After Machine LICM, CSE and Sinking passes");

addPass(&PeepholeOptimizerID);
addPass(&PeepholeOptimizerID, false);
// Clean-up the dead code that may have been generated by peephole
// rewriting.
addPass(&DeadMachineInstructionElimID);
printAndVerify("After codegen peephole optimization pass");
}

//===---------------------------------------------------------------------===//
Expand Down Expand Up @@ -701,54 +711,48 @@ bool TargetPassConfig::usingDefaultRegAlloc() const {
/// Add the minimum set of target-independent passes that are required for
/// register allocation. No coalescing or scheduling.
void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
addPass(&PHIEliminationID);
addPass(&TwoAddressInstructionPassID);
addPass(&PHIEliminationID, false);
addPass(&TwoAddressInstructionPassID, false);

addPass(RegAllocPass);
printAndVerify("After Register Allocation");
}

/// Add standard target-independent passes that are tightly coupled with
/// optimized register allocation, including coalescing, machine instruction
/// scheduling, and register allocation itself.
void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
addPass(&ProcessImplicitDefsID);
addPass(&ProcessImplicitDefsID, false);

// LiveVariables currently requires pure SSA form.
//
// FIXME: Once TwoAddressInstruction pass no longer uses kill flags,
// LiveVariables can be removed completely, and LiveIntervals can be directly
// computed. (We still either need to regenerate kill flags after regalloc, or
// preferably fix the scavenger to not depend on them).
addPass(&LiveVariablesID);
addPass(&LiveVariablesID, false);

// Edge splitting is smarter with machine loop info.
addPass(&MachineLoopInfoID);
addPass(&PHIEliminationID);
addPass(&MachineLoopInfoID, false);
addPass(&PHIEliminationID, false);

// Eventually, we want to run LiveIntervals before PHI elimination.
if (EarlyLiveIntervals)
addPass(&LiveIntervalsID);
addPass(&LiveIntervalsID, false);

addPass(&TwoAddressInstructionPassID);
addPass(&TwoAddressInstructionPassID, false);
addPass(&RegisterCoalescerID);
printAndVerify("After Register Coalescing");

// PreRA instruction scheduling.
if (addPass(&MachineSchedulerID))
printAndVerify("After Machine Scheduling");
addPass(&MachineSchedulerID);

// Add the selected register allocation pass.
addPass(RegAllocPass);
printAndVerify("After Register Allocation, before rewriter");

// Allow targets to change the register assignments before rewriting.
if (addPreRewrite())
printAndVerify("After pre-rewrite passes");
addPreRewrite();

// Finally rewrite virtual registers.
addPass(&VirtRegRewriterID);
printAndVerify("After Virtual Register Rewriter");

// Perform stack slot coloring and post-ra machine LICM.
//
Expand All @@ -760,8 +764,6 @@ void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
//
// FIXME: can this move into MachineLateOptimization?
addPass(&PostRAMachineLICMID);

printAndVerify("After StackSlotColoring and postra Machine LICM");
}

//===---------------------------------------------------------------------===//
Expand All @@ -771,34 +773,30 @@ void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
/// Add passes that optimize machine instructions after register allocation.
void TargetPassConfig::addMachineLateOptimization() {
// Branch folding must be run after regalloc and prolog/epilog insertion.
if (addPass(&BranchFolderPassID))
printAndVerify("After BranchFolding");
addPass(&BranchFolderPassID);

// Tail duplication.
// Note that duplicating tail just increases code size and degrades
// performance for targets that require Structured Control Flow.
// In addition it can also make CFG irreducible. Thus we disable it.
if (!TM->requiresStructuredCFG() && addPass(&TailDuplicateID))
printAndVerify("After TailDuplicate");
if (!TM->requiresStructuredCFG())
addPass(&TailDuplicateID);

// Copy propagation.
if (addPass(&MachineCopyPropagationID))
printAndVerify("After copy propagation pass");
addPass(&MachineCopyPropagationID);
}

/// Add standard GC passes.
bool TargetPassConfig::addGCPasses() {
addPass(&GCMachineCodeAnalysisID);
addPass(&GCMachineCodeAnalysisID, false);
return true;
}

/// Add standard basic block placement passes.
void TargetPassConfig::addBlockPlacement() {
if (addPass(&MachineBlockPlacementID)) {
if (addPass(&MachineBlockPlacementID, false)) {
// Run a separate pass to collect block placement statistics.
if (EnableBlockPlacementStats)
addPass(&MachineBlockPlacementStatsID);

printAndVerify("After machine block placement.");
}
}
30 changes: 13 additions & 17 deletions llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -181,10 +181,10 @@ class AArch64PassConfig : public TargetPassConfig {
bool addPreISel() override;
bool addInstSelector() override;
bool addILPOpts() override;
bool addPreRegAlloc() override;
bool addPostRegAlloc() override;
bool addPreSched2() override;
bool addPreEmitPass() override;
void addPreRegAlloc() override;
void addPostRegAlloc() override;
void addPreSched2() override;
void addPreEmitPass() override;
};
} // namespace

Expand Down Expand Up @@ -267,47 +267,43 @@ bool AArch64PassConfig::addILPOpts() {
return true;
}

bool AArch64PassConfig::addPreRegAlloc() {
void AArch64PassConfig::addPreRegAlloc() {
// Use AdvSIMD scalar instructions whenever profitable.
if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
addPass(createAArch64AdvSIMDScalar());
addPass(createAArch64AdvSIMDScalar(), false);
// The AdvSIMD pass may produce copies that can be rewritten to
// be register coaleascer friendly.
addPass(&PeepholeOptimizerID);
}
return true;
}

bool AArch64PassConfig::addPostRegAlloc() {
void AArch64PassConfig::addPostRegAlloc() {
// Change dead register definitions to refer to the zero register.
if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
addPass(createAArch64DeadRegisterDefinitions());
addPass(createAArch64DeadRegisterDefinitions(), false);
if (TM->getOptLevel() != CodeGenOpt::None &&
(TM->getSubtarget<AArch64Subtarget>().isCortexA53() ||
TM->getSubtarget<AArch64Subtarget>().isCortexA57()) &&
usingDefaultRegAlloc())
// Improve performance for some FP/SIMD code for A57.
addPass(createAArch64A57FPLoadBalancing());
return true;
}

bool AArch64PassConfig::addPreSched2() {
void AArch64PassConfig::addPreSched2() {
// Expand some pseudo instructions to allow proper scheduling.
addPass(createAArch64ExpandPseudoPass());
addPass(createAArch64ExpandPseudoPass(), false);
// Use load/store pair instructions when possible.
if (TM->getOptLevel() != CodeGenOpt::None && EnableLoadStoreOpt)
addPass(createAArch64LoadStoreOptimizationPass());
return true;
}

bool AArch64PassConfig::addPreEmitPass() {
void AArch64PassConfig::addPreEmitPass() {
if (EnableA53Fix835769)
addPass(createAArch64A53Fix835769());
addPass(createAArch64A53Fix835769(), false);
// Relax conditional branch instructions if they're otherwise out of
// range of their destination.
addPass(createAArch64BranchRelaxation());
addPass(createAArch64BranchRelaxation(), false);
if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
TM->getSubtarget<AArch64Subtarget>().isTargetMachO())
addPass(createAArch64CollectLOHPass());
return true;
}
38 changes: 16 additions & 22 deletions llvm/lib/Target/ARM/ARMTargetMachine.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -197,9 +197,9 @@ class ARMPassConfig : public TargetPassConfig {
void addIRPasses() override;
bool addPreISel() override;
bool addInstSelector() override;
bool addPreRegAlloc() override;
bool addPreSched2() override;
bool addPreEmitPass() override;
void addPreRegAlloc() override;
void addPreSched2() override;
void addPreEmitPass() override;
};
} // namespace

Expand Down Expand Up @@ -241,59 +241,53 @@ bool ARMPassConfig::addInstSelector() {
return false;
}

bool ARMPassConfig::addPreRegAlloc() {
void ARMPassConfig::addPreRegAlloc() {
if (getOptLevel() != CodeGenOpt::None)
addPass(createARMLoadStoreOptimizationPass(true));
addPass(createARMLoadStoreOptimizationPass(true), false);
if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA9())
addPass(createMLxExpansionPass());
addPass(createMLxExpansionPass(), false);
// Since the A15SDOptimizer pass can insert VDUP instructions, it can only be
// enabled when NEON is available.
if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA15() &&
getARMSubtarget().hasNEON() && !DisableA15SDOptimization) {
addPass(createA15SDOptimizerPass());
}
return true;
}

bool ARMPassConfig::addPreSched2() {
void ARMPassConfig::addPreSched2() {
if (getOptLevel() != CodeGenOpt::None) {
addPass(createARMLoadStoreOptimizationPass());
printAndVerify("After ARM load / store optimizer");
addPass(createARMLoadStoreOptimizationPass(), false);

if (getARMSubtarget().hasNEON())
addPass(createExecutionDependencyFixPass(&ARM::DPRRegClass));
addPass(createExecutionDependencyFixPass(&ARM::DPRRegClass), false);
}

// Expand some pseudo instructions into multiple instructions to allow
// proper scheduling.
addPass(createARMExpandPseudoPass());
addPass(createARMExpandPseudoPass(), false);

if (getOptLevel() != CodeGenOpt::None) {
if (!getARMSubtarget().isThumb1Only()) {
// in v8, IfConversion depends on Thumb instruction widths
if (getARMSubtarget().restrictIT() &&
!getARMSubtarget().prefers32BitThumb())
addPass(createThumb2SizeReductionPass());
addPass(&IfConverterID);
addPass(createThumb2SizeReductionPass(), false);
addPass(&IfConverterID, false);
}
}
if (getARMSubtarget().isThumb2())
addPass(createThumb2ITBlockPass());

return true;
}

bool ARMPassConfig::addPreEmitPass() {
void ARMPassConfig::addPreEmitPass() {
if (getARMSubtarget().isThumb2()) {
if (!getARMSubtarget().prefers32BitThumb())
addPass(createThumb2SizeReductionPass());
addPass(createThumb2SizeReductionPass(), false);

// Constant island pass work on unbundled instructions.
addPass(&UnpackMachineBundlesID);
addPass(&UnpackMachineBundlesID, false);
}

addPass(createARMOptimizeBarriersPass());
addPass(createARMOptimizeBarriersPass(), false);
addPass(createARMConstantIslandPass());

return true;
}
40 changes: 17 additions & 23 deletions llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -103,10 +103,10 @@ class HexagonPassConfig : public TargetPassConfig {
}

bool addInstSelector() override;
bool addPreRegAlloc() override;
bool addPostRegAlloc() override;
bool addPreSched2() override;
bool addPreEmitPass() override;
void addPreRegAlloc() override;
void addPostRegAlloc() override;
void addPreSched2() override;
void addPreEmitPass() override;
};
} // namespace

Expand All @@ -131,51 +131,45 @@ bool HexagonPassConfig::addInstSelector() {
return false;
}

bool HexagonPassConfig::addPreRegAlloc() {
void HexagonPassConfig::addPreRegAlloc() {
if (getOptLevel() != CodeGenOpt::None)
if (!DisableHardwareLoops)
addPass(createHexagonHardwareLoops());
return false;
addPass(createHexagonHardwareLoops(), false);
}

bool HexagonPassConfig::addPostRegAlloc() {
void HexagonPassConfig::addPostRegAlloc() {
const HexagonTargetMachine &TM = getHexagonTargetMachine();
if (getOptLevel() != CodeGenOpt::None)
if (!DisableHexagonCFGOpt)
addPass(createHexagonCFGOptimizer(TM));
return false;
addPass(createHexagonCFGOptimizer(TM), false);
}

bool HexagonPassConfig::addPreSched2() {
void HexagonPassConfig::addPreSched2() {
const HexagonTargetMachine &TM = getHexagonTargetMachine();

addPass(createHexagonCopyToCombine());
addPass(createHexagonCopyToCombine(), false);
if (getOptLevel() != CodeGenOpt::None)
addPass(&IfConverterID);
addPass(&IfConverterID, false);
addPass(createHexagonSplitConst32AndConst64(TM));
printAndVerify("After hexagon split const32/64 pass");
return true;
}

bool HexagonPassConfig::addPreEmitPass() {
void HexagonPassConfig::addPreEmitPass() {
const HexagonTargetMachine &TM = getHexagonTargetMachine();
bool NoOpt = (getOptLevel() == CodeGenOpt::None);

if (!NoOpt)
addPass(createHexagonNewValueJump());
addPass(createHexagonNewValueJump(), false);

// Expand Spill code for predicate registers.
addPass(createHexagonExpandPredSpillCode(TM));
addPass(createHexagonExpandPredSpillCode(TM), false);

// Split up TFRcondsets into conditional transfers.
addPass(createHexagonSplitTFRCondSets(TM));
addPass(createHexagonSplitTFRCondSets(TM), false);

// Create Packets.
if (!NoOpt) {
if (!DisableHardwareLoops)
addPass(createHexagonFixupHwLoops());
addPass(createHexagonPacketizer());
addPass(createHexagonFixupHwLoops(), false);
addPass(createHexagonPacketizer(), false);
}

return false;
}
7 changes: 3 additions & 4 deletions llvm/lib/Target/MSP430/MSP430TargetMachine.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -50,7 +50,7 @@ class MSP430PassConfig : public TargetPassConfig {
}

bool addInstSelector() override;
bool addPreEmitPass() override;
void addPreEmitPass() override;
};
} // namespace

Expand All @@ -64,8 +64,7 @@ bool MSP430PassConfig::addInstSelector() {
return false;
}

bool MSP430PassConfig::addPreEmitPass() {
void MSP430PassConfig::addPreEmitPass() {
// Must run branch selection immediately preceding the asm printer.
addPass(createMSP430BranchSelectionPass());
return false;
addPass(createMSP430BranchSelectionPass(), false);
}
19 changes: 7 additions & 12 deletions llvm/lib/Target/Mips/MipsTargetMachine.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -170,9 +170,9 @@ class MipsPassConfig : public TargetPassConfig {
void addIRPasses() override;
bool addInstSelector() override;
void addMachineSSAOptimization() override;
bool addPreEmitPass() override;
void addPreEmitPass() override;

bool addPreRegAlloc() override;
void addPreRegAlloc() override;

};
} // namespace
Expand Down Expand Up @@ -203,13 +203,9 @@ void MipsPassConfig::addMachineSSAOptimization() {
TargetPassConfig::addMachineSSAOptimization();
}

bool MipsPassConfig::addPreRegAlloc() {
if (getOptLevel() == CodeGenOpt::None) {
void MipsPassConfig::addPreRegAlloc() {
if (getOptLevel() == CodeGenOpt::None)
addPass(createMipsOptimizePICCallPass(getMipsTargetMachine()));
return true;
}
else
return false;
}

void MipsTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
Expand All @@ -228,10 +224,9 @@ void MipsTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
// Implemented by targets that want to run passes immediately before
// machine code is emitted. return true if -print-machineinstrs should
// print out the code after the passes.
bool MipsPassConfig::addPreEmitPass() {
void MipsPassConfig::addPreEmitPass() {
MipsTargetMachine &TM = getMipsTargetMachine();
addPass(createMipsDelaySlotFillerPass(TM));
addPass(createMipsLongBranchPass(TM));
addPass(createMipsDelaySlotFillerPass(TM), false);
addPass(createMipsLongBranchPass(TM), false);
addPass(createMipsConstantIslandPass(TM));
return true;
}
9 changes: 3 additions & 6 deletions llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -110,8 +110,7 @@ class NVPTXPassConfig : public TargetPassConfig {

void addIRPasses() override;
bool addInstSelector() override;
bool addPreRegAlloc() override;
bool addPostRegAlloc() override;
void addPostRegAlloc() override;
void addMachineSSAOptimization() override;

FunctionPass *createTargetRegisterAllocator(bool) override;
Expand Down Expand Up @@ -183,10 +182,8 @@ bool NVPTXPassConfig::addInstSelector() {
return false;
}

bool NVPTXPassConfig::addPreRegAlloc() { return false; }
bool NVPTXPassConfig::addPostRegAlloc() {
addPass(createNVPTXPrologEpilogPass());
return false;
void NVPTXPassConfig::addPostRegAlloc() {
addPass(createNVPTXPrologEpilogPass(), false);
}

FunctionPass *NVPTXPassConfig::createTargetRegisterAllocator(bool) {
Expand Down
22 changes: 9 additions & 13 deletions llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -162,9 +162,9 @@ class PPCPassConfig : public TargetPassConfig {
bool addPreISel() override;
bool addILPOpts() override;
bool addInstSelector() override;
bool addPreRegAlloc() override;
bool addPreSched2() override;
bool addPreEmitPass() override;
void addPreRegAlloc() override;
void addPreSched2() override;
void addPreEmitPass() override;
};
} // namespace

Expand Down Expand Up @@ -216,28 +216,24 @@ bool PPCPassConfig::addInstSelector() {
return false;
}

bool PPCPassConfig::addPreRegAlloc() {
void PPCPassConfig::addPreRegAlloc() {
initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
&PPCVSXFMAMutateID);
return false;
}

bool PPCPassConfig::addPreSched2() {
addPass(createPPCVSXCopyCleanupPass());
void PPCPassConfig::addPreSched2() {
addPass(createPPCVSXCopyCleanupPass(), false);

if (getOptLevel() != CodeGenOpt::None)
addPass(&IfConverterID);

return true;
}

bool PPCPassConfig::addPreEmitPass() {
void PPCPassConfig::addPreEmitPass() {
if (getOptLevel() != CodeGenOpt::None)
addPass(createPPCEarlyReturnPass());
addPass(createPPCEarlyReturnPass(), false);
// Must run branch selection immediately preceding the asm printer.
addPass(createPPCBranchSelectionPass());
return false;
addPass(createPPCBranchSelectionPass(), false);
}

void PPCTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
Expand Down
47 changes: 21 additions & 26 deletions llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -87,10 +87,10 @@ class AMDGPUPassConfig : public TargetPassConfig {
void addCodeGenPrepare() override;
bool addPreISel() override;
bool addInstSelector() override;
bool addPreRegAlloc() override;
bool addPostRegAlloc() override;
bool addPreSched2() override;
bool addPreEmitPass() override;
void addPreRegAlloc() override;
void addPostRegAlloc() override;
void addPreSched2() override;
void addPreEmitPass() override;
};
} // End of anonymous namespace

Expand Down Expand Up @@ -163,7 +163,7 @@ bool AMDGPUPassConfig::addInstSelector() {
return false;
}

bool AMDGPUPassConfig::addPreRegAlloc() {
void AMDGPUPassConfig::addPreRegAlloc() {
const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();

if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
Expand All @@ -179,47 +179,42 @@ bool AMDGPUPassConfig::addPreRegAlloc() {
insertPass(&MachineSchedulerID, &SILoadStoreOptimizerID);
}

addPass(createSIShrinkInstructionsPass());
addPass(createSIFixSGPRLiveRangesPass());
addPass(createSIShrinkInstructionsPass(), false);
addPass(createSIFixSGPRLiveRangesPass(), false);
}
return false;
}

bool AMDGPUPassConfig::addPostRegAlloc() {
void AMDGPUPassConfig::addPostRegAlloc() {
const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();

if (ST.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) {
addPass(createSIShrinkInstructionsPass());
addPass(createSIShrinkInstructionsPass(), false);
}
return false;
}

bool AMDGPUPassConfig::addPreSched2() {
void AMDGPUPassConfig::addPreSched2() {
const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();

if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
addPass(createR600EmitClauseMarkers());
addPass(createR600EmitClauseMarkers(), false);
if (ST.isIfCvtEnabled())
addPass(&IfConverterID);
addPass(&IfConverterID, false);
if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
addPass(createR600ClauseMergePass(*TM));
addPass(createR600ClauseMergePass(*TM), false);
if (ST.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
addPass(createSIInsertWaits(*TM));
addPass(createSIInsertWaits(*TM), false);
}
return false;
}

bool AMDGPUPassConfig::addPreEmitPass() {
void AMDGPUPassConfig::addPreEmitPass() {
const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
addPass(createAMDGPUCFGStructurizerPass());
addPass(createR600ExpandSpecialInstrsPass(*TM));
addPass(&FinalizeMachineBundlesID);
addPass(createR600Packetizer(*TM));
addPass(createR600ControlFlowFinalizer(*TM));
addPass(createAMDGPUCFGStructurizerPass(), false);
addPass(createR600ExpandSpecialInstrsPass(*TM), false);
addPass(&FinalizeMachineBundlesID, false);
addPass(createR600Packetizer(*TM), false);
addPass(createR600ControlFlowFinalizer(*TM), false);
} else {
addPass(createSILowerControlFlowPass(*TM));
addPass(createSILowerControlFlowPass(*TM), false);
}

return false;
}
8 changes: 2 additions & 6 deletions llvm/lib/Target/Sparc/SparcTargetMachine.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -53,7 +53,7 @@ class SparcPassConfig : public TargetPassConfig {

void addIRPasses() override;
bool addInstSelector() override;
bool addPreEmitPass() override;
void addPreEmitPass() override;
};
} // namespace

Expand All @@ -72,12 +72,8 @@ bool SparcPassConfig::addInstSelector() {
return false;
}

/// addPreEmitPass - This pass may be implemented by targets that want to run
/// passes immediately before machine code is emitted. This should return
/// true if -print-machineinstrs should print out the code after the passes.
bool SparcPassConfig::addPreEmitPass(){
void SparcPassConfig::addPreEmitPass(){
addPass(createSparcDelaySlotFillerPass(getSparcTargetMachine()));
return true;
}

void SparcV8TargetMachine::anchor() { }
Expand Down
14 changes: 6 additions & 8 deletions llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -46,8 +46,8 @@ class SystemZPassConfig : public TargetPassConfig {

void addIRPasses() override;
bool addInstSelector() override;
bool addPreSched2() override;
bool addPreEmitPass() override;
void addPreSched2() override;
void addPreEmitPass() override;
};
} // end anonymous namespace

Expand All @@ -60,14 +60,13 @@ bool SystemZPassConfig::addInstSelector() {
return false;
}

bool SystemZPassConfig::addPreSched2() {
void SystemZPassConfig::addPreSched2() {
if (getOptLevel() != CodeGenOpt::None &&
getSystemZTargetMachine().getSubtargetImpl()->hasLoadStoreOnCond())
addPass(&IfConverterID);
return true;
}

bool SystemZPassConfig::addPreEmitPass() {
void SystemZPassConfig::addPreEmitPass() {
// We eliminate comparisons here rather than earlier because some
// transformations can change the set of available CC values and we
// generally want those transformations to have priority. This is
Expand All @@ -92,11 +91,10 @@ bool SystemZPassConfig::addPreEmitPass() {
// between the comparison and the branch, but it isn't clear whether
// preventing that would be a win or not.
if (getOptLevel() != CodeGenOpt::None)
addPass(createSystemZElimComparePass(getSystemZTargetMachine()));
addPass(createSystemZElimComparePass(getSystemZTargetMachine()), false);
if (getOptLevel() != CodeGenOpt::None)
addPass(createSystemZShortenInstPass(getSystemZTargetMachine()));
addPass(createSystemZShortenInstPass(getSystemZTargetMachine()), false);
addPass(createSystemZLongBranchPass(getSystemZTargetMachine()));
return true;
}

TargetPassConfig *SystemZTargetMachine::createPassConfig(PassManagerBase &PM) {
Expand Down
32 changes: 9 additions & 23 deletions llvm/lib/Target/X86/X86TargetMachine.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -154,9 +154,8 @@ class X86PassConfig : public TargetPassConfig {
void addIRPasses() override;
bool addInstSelector() override;
bool addILPOpts() override;
bool addPreRegAlloc() override;
bool addPostRegAlloc() override;
bool addPreEmitPass() override;
void addPostRegAlloc() override;
void addPreEmitPass() override;
};
} // namespace

Expand Down Expand Up @@ -188,32 +187,19 @@ bool X86PassConfig::addILPOpts() {
return true;
}

bool X86PassConfig::addPreRegAlloc() {
return false; // -print-machineinstr shouldn't print after this.
}

bool X86PassConfig::addPostRegAlloc() {
void X86PassConfig::addPostRegAlloc() {
addPass(createX86FloatingPointStackifierPass());
return true; // -print-machineinstr should print after this.
}

bool X86PassConfig::addPreEmitPass() {
bool ShouldPrint = false;
if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2()) {
addPass(createExecutionDependencyFixPass(&X86::VR128RegClass));
ShouldPrint = true;
}
void X86PassConfig::addPreEmitPass() {
if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2())
addPass(createExecutionDependencyFixPass(&X86::VR128RegClass), false);

if (UseVZeroUpper) {
addPass(createX86IssueVZeroUpperPass());
ShouldPrint = true;
}
if (UseVZeroUpper)
addPass(createX86IssueVZeroUpperPass(), false);

if (getOptLevel() != CodeGenOpt::None) {
addPass(createX86PadShortFunctions());
addPass(createX86PadShortFunctions(), false);
addPass(createX86FixupLEAs());
ShouldPrint = true;
}

return ShouldPrint;
}
7 changes: 3 additions & 4 deletions llvm/lib/Target/XCore/XCoreTargetMachine.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -48,7 +48,7 @@ class XCorePassConfig : public TargetPassConfig {
void addIRPasses() override;
bool addPreISel() override;
bool addInstSelector() override;
bool addPreEmitPass() override;
void addPreEmitPass() override;
};
} // namespace

Expand All @@ -72,9 +72,8 @@ bool XCorePassConfig::addInstSelector() {
return false;
}

bool XCorePassConfig::addPreEmitPass() {
addPass(createXCoreFrameToArgsOffsetEliminationPass());
return false;
void XCorePassConfig::addPreEmitPass() {
addPass(createXCoreFrameToArgsOffsetEliminationPass(), false);
}

// Force static initialization.
Expand Down