1,500 changes: 640 additions & 860 deletions llvm/test/CodeGen/CSKY/atomic-rmw.ll
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6 changes: 3 additions & 3 deletions llvm/test/CodeGen/CSKY/base-i.ll
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -csky-no-aliases -mattr=+e2 -mattr=+2e3 < %s -mtriple=csky | FileCheck %s
; RUN: llc -verify-machineinstrs -csky-no-aliases -mattr=+btst16 < %s -mtriple=csky | FileCheck %s --check-prefix=GENERIC
; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky | FileCheck %s --check-prefix=GENERIC

define i32 @addRR(i32 %x, i32 %y) {
; CHECK-LABEL: addRR:
Expand Down Expand Up @@ -279,9 +279,9 @@ define i64 @SUB_LONG(i64 %x, i64 %y) {
; CHECK-NEXT: setc32
; CHECK-NEXT: subc32 a0, a2, a0
; CHECK-NEXT: mvcv16 a2
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: mvcv16 a2
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: subc32 a1, a3, a1
; CHECK-NEXT: rts16
;
Expand Down
124 changes: 62 additions & 62 deletions llvm/test/CodeGen/CSKY/br.ll
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -mattr=+2e3 | FileCheck %s
; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -mattr=+btst16 | FileCheck %s --check-prefix=GENERIC
; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky | FileCheck %s --check-prefix=GENERIC

;EQ
define i32 @brRR_eq(i32 %x, i32 %y) {
Expand Down Expand Up @@ -1390,15 +1390,15 @@ define i64 @brRR_i64_ugt(i64 %x, i64 %y) {
; CHECK-NEXT: mvc32 a0
; CHECK-NEXT: st16.w a0, (sp, 8)
; CHECK-NEXT: ld16.w a0, (sp, 4)
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: mvc32 a0
; CHECK-NEXT: ld16.w a1, (sp, 12)
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w a2, (sp, 8)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: bt32 .LBB35_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
Expand Down Expand Up @@ -1473,9 +1473,9 @@ define i64 @brRI_i64_ugt(i64 %x) {
; CHECK-NEXT: mvcv16 a0
; CHECK-NEXT: movi16 a1, 0
; CHECK-NEXT: ld16.w a2, (sp, 4)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: bt32 .LBB36_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
Expand Down Expand Up @@ -1580,9 +1580,9 @@ define i64 @brRR_i64_uge(i64 %x, i64 %y) {
; CHECK-NEXT: cmphs16 a2, a0
; CHECK-NEXT: mvcv16 a0
; CHECK-NEXT: ld16.w a2, (sp, 4)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: bt32 .LBB38_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
Expand Down Expand Up @@ -1650,9 +1650,9 @@ define i64 @brRI_i64_uge(i64 %x) {
; CHECK-NEXT: mvcv16 a0
; CHECK-NEXT: movi16 a1, 0
; CHECK-NEXT: ld16.w a2, (sp, 4)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: bt32 .LBB39_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
Expand Down Expand Up @@ -1717,15 +1717,15 @@ define i64 @brRR_i64_ult(i64 %x, i64 %y) {
; CHECK-NEXT: mvc32 a0
; CHECK-NEXT: st16.w a0, (sp, 8)
; CHECK-NEXT: ld16.w a0, (sp, 4)
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: mvc32 a0
; CHECK-NEXT: ld16.w a1, (sp, 12)
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w a2, (sp, 8)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: bt32 .LBB40_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
Expand Down Expand Up @@ -1796,7 +1796,7 @@ define i64 @brRI_i64_ult(i64 %x) {
; CHECK-NEXT: cmpnei16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: bt32 .LBB41_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
Expand Down Expand Up @@ -1861,9 +1861,9 @@ define i64 @brRR_i64_ule(i64 %x, i64 %y) {
; CHECK-NEXT: cmphs16 a0, a2
; CHECK-NEXT: mvcv16 a0
; CHECK-NEXT: ld16.w a2, (sp, 4)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: bt32 .LBB42_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
Expand Down Expand Up @@ -1927,7 +1927,7 @@ define i64 @brRI_i64_ule(i64 %x) {
; CHECK-NEXT: cmpnei16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: bt32 .LBB43_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
Expand Down Expand Up @@ -2034,12 +2034,12 @@ define i64 @brRR_i64_sgt(i64 %x, i64 %y) {
; CHECK-NEXT: cmplt16 a1, a3
; CHECK-NEXT: mvcv16 a0
; CHECK-NEXT: ld16.w a1, (sp, 4)
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w a2, (sp, 8)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a0, a1
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: bt32 .LBB45_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
Expand Down Expand Up @@ -2106,12 +2106,12 @@ define i64 @brRI_i64_sgt(i64 %x) {
; CHECK-NEXT: cmphsi16 a0, 11
; CHECK-NEXT: mvcv16 a0
; CHECK-NEXT: ld16.w a1, (sp, 4)
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w a2, (sp, 8)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: bt32 .LBB46_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
Expand Down Expand Up @@ -2179,12 +2179,12 @@ define i64 @brR0_i64_sgt(i64 %x) {
; CHECK-NEXT: cmpnei16 a0, 0
; CHECK-NEXT: mvcv16 a0
; CHECK-NEXT: ld16.w a1, (sp, 4)
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w a2, (sp, 8)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: bt32 .LBB47_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
Expand Down Expand Up @@ -2252,12 +2252,12 @@ define i64 @brRR_i64_sge(i64 %x, i64 %y) {
; CHECK-NEXT: cmphs16 a2, a0
; CHECK-NEXT: mvcv16 a0
; CHECK-NEXT: ld16.w a1, (sp, 4)
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w a2, (sp, 8)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: bt32 .LBB48_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
Expand Down Expand Up @@ -2329,12 +2329,12 @@ define i64 @brRI_i64_sge(i64 %x) {
; CHECK-NEXT: cmphsi16 a0, 10
; CHECK-NEXT: mvcv16 a0
; CHECK-NEXT: ld16.w a1, (sp, 4)
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w a2, (sp, 8)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: bt32 .LBB49_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
Expand Down Expand Up @@ -2443,12 +2443,12 @@ define i64 @brRR_i64_slt(i64 %x, i64 %y) {
; CHECK-NEXT: cmplt16 a3, a1
; CHECK-NEXT: mvcv16 a0
; CHECK-NEXT: ld16.w a1, (sp, 4)
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w a2, (sp, 8)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a0, a1
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: bt32 .LBB51_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
Expand Down Expand Up @@ -2516,12 +2516,12 @@ define i64 @brRI_i64_slt(i64 %x) {
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: st16.w a1, (sp, 4)
; CHECK-NEXT: ld16.w a1, (sp, 8)
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w a2, (sp, 4)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: bt32 .LBB52_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
Expand Down Expand Up @@ -2640,12 +2640,12 @@ define i64 @brRR_i64_sle(i64 %x, i64 %y) {
; CHECK-NEXT: cmphs16 a0, a2
; CHECK-NEXT: mvcv16 a0
; CHECK-NEXT: ld16.w a1, (sp, 4)
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w a2, (sp, 8)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: bt32 .LBB54_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
Expand Down Expand Up @@ -2718,12 +2718,12 @@ define i64 @brRI_i64_sle(i64 %x) {
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: st16.w a1, (sp, 4)
; CHECK-NEXT: ld16.w a1, (sp, 8)
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w a2, (sp, 4)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: bt32 .LBB55_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
Expand Down Expand Up @@ -2793,15 +2793,15 @@ define i64 @brR0_i64_sle(i64 %x) {
; CHECK-NEXT: mvc32 a0
; CHECK-NEXT: st16.w a0, (sp, 8)
; CHECK-NEXT: ld16.w a0, (sp, 4)
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: mvc32 a0
; CHECK-NEXT: ld16.w a1, (sp, 12)
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w a2, (sp, 8)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: bt32 .LBB56_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
Expand Down Expand Up @@ -5500,7 +5500,7 @@ define i1 @brRI_i1_eq(i1 %x) {
; CHECK-LABEL: brRI_i1_eq:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: andi32 a0, a0, 1
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: bf32 .LBB117_2
; CHECK-NEXT: # %bb.1: # %label2
; CHECK-NEXT: movi16 a0, 0
Expand Down Expand Up @@ -5539,7 +5539,7 @@ define i1 @brR0_i1_eq(i1 %x) {
; CHECK-LABEL: brR0_i1_eq:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: andi32 a0, a0, 1
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: bf32 .LBB118_2
; CHECK-NEXT: # %bb.1: # %label2
; CHECK-NEXT: movi16 a0, 0
Expand Down Expand Up @@ -5864,7 +5864,7 @@ define i1 @brRI_i1_uge(i1 %x) {
; CHECK-LABEL: brRI_i1_uge:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movi16 a0, 0
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: bt32 .LBB126_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
Expand Down Expand Up @@ -5948,7 +5948,7 @@ define i1 @brRI_i1_ult(i1 %x) {
; CHECK-LABEL: brRI_i1_ult:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movi16 a0, 1
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: bt32 .LBB128_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
Expand Down Expand Up @@ -6033,7 +6033,7 @@ define i1 @brRI_i1_ule(i1 %x) {
; CHECK-LABEL: brRI_i1_ule:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: andi32 a0, a0, 1
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: bt32 .LBB130_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
Expand Down Expand Up @@ -6074,7 +6074,7 @@ define i1 @brR0_i1_ule(i1 %x) {
; CHECK-LABEL: brR0_i1_ule:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: andi32 a0, a0, 1
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: bt32 .LBB131_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
Expand Down Expand Up @@ -6160,7 +6160,7 @@ define i1 @brRI_i1_sgt(i1 %x) {
; CHECK-LABEL: brRI_i1_sgt:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movi16 a0, 1
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: bt32 .LBB133_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
Expand Down Expand Up @@ -6200,7 +6200,7 @@ define i1 @brR0_i1_sgt(i1 %x) {
; CHECK-LABEL: brR0_i1_sgt:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movi16 a0, 1
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: bt32 .LBB134_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
Expand Down Expand Up @@ -6285,7 +6285,7 @@ define i1 @brRI_i1_sge(i1 %x) {
; CHECK-LABEL: brRI_i1_sge:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: andi32 a0, a0, 1
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: bt32 .LBB136_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
Expand Down Expand Up @@ -6326,7 +6326,7 @@ define i1 @brR0_i1_sge(i1 %x) {
; CHECK-LABEL: brR0_i1_sge:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: andi32 a0, a0, 1
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: bt32 .LBB137_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
Expand Down Expand Up @@ -6537,7 +6537,7 @@ define i1 @brRI_i1_sle(i1 %x) {
; CHECK-LABEL: brRI_i1_sle:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movi16 a0, 0
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: bt32 .LBB142_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
Expand Down Expand Up @@ -6577,7 +6577,7 @@ define i1 @brR0_i1_sle(i1 %x) {
; CHECK-LABEL: brR0_i1_sle:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movi16 a0, 0
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: bt32 .LBB143_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
Expand Down
54 changes: 27 additions & 27 deletions llvm/test/CodeGen/CSKY/cmp-i.ll
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -mattr=+2e3 | FileCheck %s
; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -mattr=+btst16 | FileCheck %s --check-prefix=GENERIC
; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky | FileCheck %s --check-prefix=GENERIC

;eq
define i1 @icmpRR_eq(i32 %x, i32 %y) {
Expand Down Expand Up @@ -687,7 +687,7 @@ define i1 @ICMP_LONG_ugt(i64 %x, i64 %y) {
; CHECK-NEXT: cmphs16 a0, a2
; CHECK-NEXT: mvcv16 a0
; CHECK-NEXT: ld16.w a2, (sp, 4)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: addi16 sp, sp, 8
Expand Down Expand Up @@ -1016,13 +1016,13 @@ define i1 @ICMP_LONG_uge(i64 %x, i64 %y) {
; CHECK-NEXT: mvc32 a0
; CHECK-NEXT: st16.w a0, (sp, 8)
; CHECK-NEXT: ld16.w a0, (sp, 4)
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w a0, (sp, 12)
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: mvc32 a0
; CHECK-NEXT: ld16.w a2, (sp, 8)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a0, a1
; CHECK-NEXT: addi16 sp, sp, 16
; CHECK-NEXT: rts16
Expand Down Expand Up @@ -1345,7 +1345,7 @@ define i1 @ICMP_LONG_ult(i64 %x, i64 %y) {
; CHECK-NEXT: cmphs16 a2, a0
; CHECK-NEXT: mvcv16 a0
; CHECK-NEXT: ld16.w a2, (sp, 4)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: addi16 sp, sp, 8
Expand Down Expand Up @@ -1658,13 +1658,13 @@ define i1 @ICMP_LONG_ule(i64 %x, i64 %y) {
; CHECK-NEXT: mvc32 a0
; CHECK-NEXT: st16.w a0, (sp, 8)
; CHECK-NEXT: ld16.w a0, (sp, 4)
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w a0, (sp, 12)
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: mvc32 a0
; CHECK-NEXT: ld16.w a2, (sp, 8)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a0, a1
; CHECK-NEXT: addi16 sp, sp, 16
; CHECK-NEXT: rts16
Expand Down Expand Up @@ -1718,7 +1718,7 @@ define i1 @ICMP_LONG_I_ule(i64 %x) {
; CHECK-NEXT: mvcv16 a1
; CHECK-NEXT: movi16 a0, 0
; CHECK-NEXT: ld16.w a2, (sp, 4)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a0, a1
; CHECK-NEXT: addi16 sp, sp, 8
; CHECK-NEXT: rts16
Expand Down Expand Up @@ -2007,10 +2007,10 @@ define i1 @ICMP_LONG_sgt(i64 %x, i64 %y) {
; CHECK-NEXT: cmphs16 a0, a2
; CHECK-NEXT: mvcv16 a1
; CHECK-NEXT: ld16.w a0, (sp, 4)
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: mvc32 a0
; CHECK-NEXT: ld16.w a2, (sp, 8)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a0, a1
; CHECK-NEXT: addi16 sp, sp, 12
; CHECK-NEXT: rts16
Expand Down Expand Up @@ -2061,10 +2061,10 @@ define i1 @ICMP_LONG_I_sgt(i64 %x) {
; CHECK-NEXT: mvc32 a0
; CHECK-NEXT: st16.w a0, (sp, 4)
; CHECK-NEXT: ld16.w a0, (sp, 8)
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: mvc32 a0
; CHECK-NEXT: ld16.w a1, (sp, 4)
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: movf32 a0, a2
; CHECK-NEXT: addi16 sp, sp, 12
; CHECK-NEXT: rts16
Expand Down Expand Up @@ -2340,10 +2340,10 @@ define i1 @ICMP_LONG_sge(i64 %x, i64 %y) {
; CHECK-NEXT: cmplt16 a3, a1
; CHECK-NEXT: mvcv16 a0
; CHECK-NEXT: ld16.w a1, (sp, 4)
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w a2, (sp, 8)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a0, a1
; CHECK-NEXT: addi16 sp, sp, 12
; CHECK-NEXT: rts16
Expand Down Expand Up @@ -2389,13 +2389,13 @@ define i1 @ICMP_LONG_I_sge(i64 %x) {
; CHECK-NEXT: mvc32 a0
; CHECK-NEXT: st16.w a0, (sp, 8)
; CHECK-NEXT: ld16.w a0, (sp, 4)
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w a0, (sp, 12)
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: mvc32 a0
; CHECK-NEXT: ld16.w a2, (sp, 8)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a0, a1
; CHECK-NEXT: addi16 sp, sp, 16
; CHECK-NEXT: rts16
Expand Down Expand Up @@ -2671,10 +2671,10 @@ define i1 @ICMP_LONG_slt(i64 %x, i64 %y) {
; CHECK-NEXT: cmphs16 a2, a0
; CHECK-NEXT: mvcv16 a1
; CHECK-NEXT: ld16.w a0, (sp, 4)
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: mvc32 a0
; CHECK-NEXT: ld16.w a2, (sp, 8)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a0, a1
; CHECK-NEXT: addi16 sp, sp, 12
; CHECK-NEXT: rts16
Expand Down Expand Up @@ -2724,10 +2724,10 @@ define i1 @ICMP_LONG_I_slt(i64 %x) {
; CHECK-NEXT: cmpnei16 a0, 0
; CHECK-NEXT: mvcv16 a1
; CHECK-NEXT: ld16.w a0, (sp, 4)
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: mvc32 a0
; CHECK-NEXT: ld16.w a2, (sp, 8)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a0, a1
; CHECK-NEXT: addi16 sp, sp, 12
; CHECK-NEXT: rts16
Expand Down Expand Up @@ -2998,10 +2998,10 @@ define i1 @ICMP_LONG_sle(i64 %x, i64 %y) {
; CHECK-NEXT: cmplt16 a1, a3
; CHECK-NEXT: mvcv16 a0
; CHECK-NEXT: ld16.w a1, (sp, 4)
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w a2, (sp, 8)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a0, a1
; CHECK-NEXT: addi16 sp, sp, 12
; CHECK-NEXT: rts16
Expand Down Expand Up @@ -3046,10 +3046,10 @@ define i1 @ICMP_LONG_I_sle(i64 %x) {
; CHECK-NEXT: cmphsi16 a0, 2
; CHECK-NEXT: mvcv16 a1
; CHECK-NEXT: ld16.w a0, (sp, 4)
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: mvc32 a0
; CHECK-NEXT: ld16.w a2, (sp, 8)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a0, a1
; CHECK-NEXT: addi16 sp, sp, 12
; CHECK-NEXT: rts16
Expand Down
96 changes: 48 additions & 48 deletions llvm/test/CodeGen/CSKY/fpu/br-d.ll
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96 changes: 48 additions & 48 deletions llvm/test/CodeGen/CSKY/fpu/br-f.ll
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11 changes: 5 additions & 6 deletions llvm/test/CodeGen/CSKY/fpu/select.ll
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Original file line number Diff line number Diff line change
@@ -1,12 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -mattr=+2e3,+hard-float,+fpuv2_sf,+fpuv2_df -float-abi=hard | FileCheck %s
; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -mattr=+2e3,+hard-float,+fpuv3_sf,+fpuv3_df -float-abi=hard | FileCheck %s --check-prefix=CHECK-DF3
; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -mattr=+btst16,+hard-float,+fpuv2_sf,+fpuv2_df -float-abi=hard | FileCheck %s --check-prefix=GENERIC
; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -mattr=+hard-float,+fpuv2_sf,+fpuv2_df -float-abi=hard | FileCheck %s --check-prefix=GENERIC

define float @selectRR_eq_float(i1 %x, float %n, float %m) {
; CHECK-LABEL: selectRR_eq_float:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: bt32 .LBB0_2
; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: fmovs vr1, vr0
Expand All @@ -16,7 +16,7 @@ define float @selectRR_eq_float(i1 %x, float %n, float %m) {
;
; CHECK-DF3-LABEL: selectRR_eq_float:
; CHECK-DF3: # %bb.0: # %entry
; CHECK-DF3-NEXT: btsti32 a0, 0
; CHECK-DF3-NEXT: btsti16 a0, 0
; CHECK-DF3-NEXT: fsel.32 vr0, vr1, vr0
; CHECK-DF3-NEXT: rts16
;
Expand All @@ -41,7 +41,7 @@ entry:
define double @selectRR_eq_double(i1 %x, double %n, double %m) {
; CHECK-LABEL: selectRR_eq_double:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: bt32 .LBB1_2
; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: fmovd vr1, vr0
Expand All @@ -51,7 +51,7 @@ define double @selectRR_eq_double(i1 %x, double %n, double %m) {
;
; CHECK-DF3-LABEL: selectRR_eq_double:
; CHECK-DF3: # %bb.0: # %entry
; CHECK-DF3-NEXT: btsti32 a0, 0
; CHECK-DF3-NEXT: btsti16 a0, 0
; CHECK-DF3-NEXT: fsel.64 vr0, vr1, vr0
; CHECK-DF3-NEXT: rts16
;
Expand All @@ -72,4 +72,3 @@ entry:
%ret = select i1 %x, double %m, double %n
ret double %ret
}

278 changes: 139 additions & 139 deletions llvm/test/CodeGen/CSKY/select.ll
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