75 changes: 27 additions & 48 deletions llvm/test/CodeGen/RISCV/xventanacondops.ll
View file
Original file line number Diff line number Diff line change
@@ -1,30 +1,27 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops < %s | FileCheck %s

define i64 @zero1(i64 %rs1, i1 %rc) {
define i64 @zero1(i64 %rs1, i1 zeroext %rc) {
; CHECK-LABEL: zero1:
; CHECK: # %bb.0:
; CHECK-NEXT: andi a1, a1, 1
; CHECK-NEXT: vt.maskc a0, a0, a1
; CHECK-NEXT: ret
%sel = select i1 %rc, i64 %rs1, i64 0
ret i64 %sel
}

define i64 @zero2(i64 %rs1, i1 %rc) {
define i64 @zero2(i64 %rs1, i1 zeroext %rc) {
; CHECK-LABEL: zero2:
; CHECK: # %bb.0:
; CHECK-NEXT: andi a1, a1, 1
; CHECK-NEXT: vt.maskcn a0, a0, a1
; CHECK-NEXT: ret
%sel = select i1 %rc, i64 0, i64 %rs1
ret i64 %sel
}

define i64 @add1(i1 %rc, i64 %rs1, i64 %rs2) {
define i64 @add1(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
; CHECK-LABEL: add1:
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: vt.maskc a0, a2, a0
; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: ret
Expand All @@ -33,10 +30,9 @@ define i64 @add1(i1 %rc, i64 %rs1, i64 %rs2) {
ret i64 %sel
}

define i64 @add2(i1 %rc, i64 %rs1, i64 %rs2) {
define i64 @add2(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
; CHECK-LABEL: add2:
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: vt.maskc a0, a1, a0
; CHECK-NEXT: add a0, a2, a0
; CHECK-NEXT: ret
Expand All @@ -45,10 +41,9 @@ define i64 @add2(i1 %rc, i64 %rs1, i64 %rs2) {
ret i64 %sel
}

define i64 @add3(i1 %rc, i64 %rs1, i64 %rs2) {
define i64 @add3(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
; CHECK-LABEL: add3:
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: vt.maskcn a0, a2, a0
; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: ret
Expand All @@ -57,10 +52,9 @@ define i64 @add3(i1 %rc, i64 %rs1, i64 %rs2) {
ret i64 %sel
}

define i64 @add4(i1 %rc, i64 %rs1, i64 %rs2) {
define i64 @add4(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
; CHECK-LABEL: add4:
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: vt.maskcn a0, a1, a0
; CHECK-NEXT: add a0, a2, a0
; CHECK-NEXT: ret
Expand All @@ -69,10 +63,9 @@ define i64 @add4(i1 %rc, i64 %rs1, i64 %rs2) {
ret i64 %sel
}

define i64 @sub1(i1 %rc, i64 %rs1, i64 %rs2) {
define i64 @sub1(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
; CHECK-LABEL: sub1:
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: vt.maskc a0, a2, a0
; CHECK-NEXT: sub a0, a1, a0
; CHECK-NEXT: ret
Expand All @@ -81,10 +74,9 @@ define i64 @sub1(i1 %rc, i64 %rs1, i64 %rs2) {
ret i64 %sel
}

define i64 @sub2(i1 %rc, i64 %rs1, i64 %rs2) {
define i64 @sub2(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
; CHECK-LABEL: sub2:
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: vt.maskcn a0, a2, a0
; CHECK-NEXT: sub a0, a1, a0
; CHECK-NEXT: ret
Expand All @@ -93,10 +85,9 @@ define i64 @sub2(i1 %rc, i64 %rs1, i64 %rs2) {
ret i64 %sel
}

define i64 @or1(i1 %rc, i64 %rs1, i64 %rs2) {
define i64 @or1(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
; CHECK-LABEL: or1:
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: vt.maskc a0, a2, a0
; CHECK-NEXT: or a0, a1, a0
; CHECK-NEXT: ret
Expand All @@ -105,10 +96,9 @@ define i64 @or1(i1 %rc, i64 %rs1, i64 %rs2) {
ret i64 %sel
}

define i64 @or2(i1 %rc, i64 %rs1, i64 %rs2) {
define i64 @or2(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
; CHECK-LABEL: or2:
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: vt.maskc a0, a1, a0
; CHECK-NEXT: or a0, a2, a0
; CHECK-NEXT: ret
Expand All @@ -117,10 +107,9 @@ define i64 @or2(i1 %rc, i64 %rs1, i64 %rs2) {
ret i64 %sel
}

define i64 @or3(i1 %rc, i64 %rs1, i64 %rs2) {
define i64 @or3(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
; CHECK-LABEL: or3:
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: vt.maskcn a0, a2, a0
; CHECK-NEXT: or a0, a1, a0
; CHECK-NEXT: ret
Expand All @@ -129,10 +118,9 @@ define i64 @or3(i1 %rc, i64 %rs1, i64 %rs2) {
ret i64 %sel
}

define i64 @or4(i1 %rc, i64 %rs1, i64 %rs2) {
define i64 @or4(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
; CHECK-LABEL: or4:
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: vt.maskcn a0, a1, a0
; CHECK-NEXT: or a0, a2, a0
; CHECK-NEXT: ret
Expand All @@ -141,10 +129,9 @@ define i64 @or4(i1 %rc, i64 %rs1, i64 %rs2) {
ret i64 %sel
}

define i64 @xor1(i1 %rc, i64 %rs1, i64 %rs2) {
define i64 @xor1(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
; CHECK-LABEL: xor1:
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: vt.maskc a0, a2, a0
; CHECK-NEXT: xor a0, a1, a0
; CHECK-NEXT: ret
Expand All @@ -153,10 +140,9 @@ define i64 @xor1(i1 %rc, i64 %rs1, i64 %rs2) {
ret i64 %sel
}

define i64 @xor2(i1 %rc, i64 %rs1, i64 %rs2) {
define i64 @xor2(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
; CHECK-LABEL: xor2:
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: vt.maskc a0, a1, a0
; CHECK-NEXT: xor a0, a2, a0
; CHECK-NEXT: ret
Expand All @@ -165,10 +151,9 @@ define i64 @xor2(i1 %rc, i64 %rs1, i64 %rs2) {
ret i64 %sel
}

define i64 @xor3(i1 %rc, i64 %rs1, i64 %rs2) {
define i64 @xor3(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
; CHECK-LABEL: xor3:
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: vt.maskcn a0, a2, a0
; CHECK-NEXT: xor a0, a1, a0
; CHECK-NEXT: ret
Expand All @@ -177,10 +162,9 @@ define i64 @xor3(i1 %rc, i64 %rs1, i64 %rs2) {
ret i64 %sel
}

define i64 @xor4(i1 %rc, i64 %rs1, i64 %rs2) {
define i64 @xor4(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
; CHECK-LABEL: xor4:
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: vt.maskcn a0, a1, a0
; CHECK-NEXT: xor a0, a2, a0
; CHECK-NEXT: ret
Expand All @@ -189,62 +173,57 @@ define i64 @xor4(i1 %rc, i64 %rs1, i64 %rs2) {
ret i64 %sel
}

define i64 @and1(i1 %rc, i64 %rs1, i64 %rs2) {
define i64 @and1(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
; CHECK-LABEL: and1:
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: and a2, a1, a2
; CHECK-NEXT: vt.maskcn a0, a1, a0
; CHECK-NEXT: or a0, a2, a0
; CHECK-NEXT: and a1, a1, a2
; CHECK-NEXT: or a0, a1, a0
; CHECK-NEXT: ret
%and = and i64 %rs1, %rs2
%sel = select i1 %rc, i64 %and, i64 %rs1
ret i64 %sel
}

define i64 @and2(i1 %rc, i64 %rs1, i64 %rs2) {
define i64 @and2(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
; CHECK-LABEL: and2:
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: and a1, a2, a1
; CHECK-NEXT: vt.maskcn a0, a2, a0
; CHECK-NEXT: and a1, a2, a1
; CHECK-NEXT: or a0, a1, a0
; CHECK-NEXT: ret
%and = and i64 %rs1, %rs2
%sel = select i1 %rc, i64 %and, i64 %rs2
ret i64 %sel
}

define i64 @and3(i1 %rc, i64 %rs1, i64 %rs2) {
define i64 @and3(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
; CHECK-LABEL: and3:
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: and a2, a1, a2
; CHECK-NEXT: vt.maskc a0, a1, a0
; CHECK-NEXT: or a0, a2, a0
; CHECK-NEXT: and a1, a1, a2
; CHECK-NEXT: or a0, a1, a0
; CHECK-NEXT: ret
%and = and i64 %rs1, %rs2
%sel = select i1 %rc, i64 %rs1, i64 %and
ret i64 %sel
}

define i64 @and4(i1 %rc, i64 %rs1, i64 %rs2) {
define i64 @and4(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
; CHECK-LABEL: and4:
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: and a1, a2, a1
; CHECK-NEXT: vt.maskc a0, a2, a0
; CHECK-NEXT: and a1, a2, a1
; CHECK-NEXT: or a0, a1, a0
; CHECK-NEXT: ret
%and = and i64 %rs1, %rs2
%sel = select i1 %rc, i64 %rs2, i64 %and
ret i64 %sel
}

define i64 @basic(i1 %rc, i64 %rs1, i64 %rs2) {
define i64 @basic(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
; CHECK-LABEL: basic:
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: vt.maskcn a2, a2, a0
; CHECK-NEXT: vt.maskc a0, a1, a0
; CHECK-NEXT: or a0, a0, a2
Expand Down