205 changes: 71 additions & 134 deletions llvm/lib/Target/ARM/ARMISelLowering.cpp
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4 changes: 1 addition & 3 deletions llvm/lib/Target/ARM/ARMISelLowering.h
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Original file line number Diff line number Diff line change
Expand Up @@ -978,13 +978,11 @@ class VectorType;
bool isUnsupportedFloatingType(EVT VT) const;

SDValue getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal, SDValue TrueVal,
SDValue ARMcc, SDValue CCR, SDValue Cmp,
SelectionDAG &DAG) const;
SDValue ARMcc, SDValue Flags, SelectionDAG &DAG) const;
SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
SDValue &ARMcc, SelectionDAG &DAG, const SDLoc &dl) const;
SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
const SDLoc &dl, bool Signaling = false) const;
SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;

SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;

Expand Down
13 changes: 3 additions & 10 deletions llvm/lib/Target/ARM/ARMInstrFormats.td
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Original file line number Diff line number Diff line change
Expand Up @@ -167,16 +167,6 @@ def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm),
let DecoderMethod = "DecodePredicateOperand";
}

// Selectable predicate operand for CMOV instructions. We can't use a normal
// predicate because the default values interfere with instruction selection. In
// all other respects it is identical though: pseudo-instruction expansion
// relies on the MachineOperands being compatible.
def cmovpred : Operand<i32>, PredicateOp,
ComplexPattern<i32, 2, "SelectCMOVPred"> {
let MIOperandInfo = (ops i32imm, i32imm);
let PrintMethod = "printPredicateOperand";
}

// Conditional code result for instructions whose 's' bit is set, e.g. subs.
def CCOutOperand : AsmOperandClass {
let Name = "CCOut";
Expand Down Expand Up @@ -1134,6 +1124,9 @@ class ARMV5MOPat<dag pattern, dag result> : Pat<pattern, result> {
class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
list<Predicate> Predicates = [IsARM, HasV6];
}
class ARMV6T2Pat<dag pattern, dag result> : Pat<pattern, result> {
list<Predicate> Predicates = [IsARM, HasV6T2];
}
class VFPPat<dag pattern, dag result> : Pat<pattern, result> {
list<Predicate> Predicates = [HasVFP2];
}
Expand Down
148 changes: 84 additions & 64 deletions llvm/lib/Target/ARM/ARMInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -14,6 +14,9 @@
// ARM specific DAG Nodes.
//

/// Value type used for "condition code" operands.
defvar CondCodeVT = i32;

/// Value type used for "flags" operands / results (either CPSR or FPSCR_NZCV).
defvar FlagsVT = i32;

Expand All @@ -29,12 +32,19 @@ def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;

def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;

def SDT_ARMCMov : SDTypeProfile<1, 3,
[SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
SDTCisVT<3, i32>]>;
def SDT_ARMCMov : SDTypeProfile<1, 4, [
/* any */ // result
SDTCisSameAs<1, 0>, // value on false
SDTCisSameAs<2, 0>, // value on true
SDTCisVT<3, CondCodeVT>, // condition code
SDTCisVT<4, FlagsVT>, // in flags
]>;

def SDT_ARMBrcond : SDTypeProfile<0, 2,
[SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
def SDT_ARMBrcond : SDTypeProfile<0, 2, [
SDTCisVT<0, OtherVT>, // target basic block
SDTCisVT<1, CondCodeVT>, // condition code
SDTCisVT<2, FlagsVT>, // in flags
]>;

def SDT_ARMBrJT : SDTypeProfile<0, 2,
[SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
Expand All @@ -53,7 +63,11 @@ def SDT_ARMAnd : SDTypeProfile<1, 2,
[SDTCisVT<0, i32>, SDTCisVT<1, i32>,
SDTCisVT<2, i32>]>;

def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
def SDT_ARMCmp : SDTypeProfile<1, 2, [
SDTCisVT<0, FlagsVT>, // out flags
SDTCisInt<1>, // lhs
SDTCisSameAs<2, 1> // rhs
]>;

def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
Expand Down Expand Up @@ -124,15 +138,17 @@ def ARMSmlaldx : SDNode<"ARMISD::SMLALDX", SDT_LongMac>;
def ARMSmlsld : SDNode<"ARMISD::SMLSLD", SDT_LongMac>;
def ARMSmlsldx : SDNode<"ARMISD::SMLSLDX", SDT_LongMac>;

def SDT_ARMCSel : SDTypeProfile<1, 3,
[SDTCisSameAs<0, 1>,
SDTCisSameAs<0, 2>,
SDTCisInt<3>,
SDTCisVT<3, i32>]>;
def SDT_ARMCSel : SDTypeProfile<1, 4, [
/* any */ // result
SDTCisSameAs<1, 0>, // lhs
SDTCisSameAs<2, 0>, // rhs
SDTCisVT<3, CondCodeVT>, // condition code
SDTCisVT<3, FlagsVT> // in flags
]>;

def ARMcsinv : SDNode<"ARMISD::CSINV", SDT_ARMCSel, [SDNPOptInGlue]>;
def ARMcsneg : SDNode<"ARMISD::CSNEG", SDT_ARMCSel, [SDNPOptInGlue]>;
def ARMcsinc : SDNode<"ARMISD::CSINC", SDT_ARMCSel, [SDNPOptInGlue]>;
def ARMcsinv : SDNode<"ARMISD::CSINV", SDT_ARMCSel>;
def ARMcsneg : SDNode<"ARMISD::CSNEG", SDT_ARMCSel>;
def ARMcsinc : SDNode<"ARMISD::CSINC", SDT_ARMCSel>;

def SDT_MulHSR : SDTypeProfile<1, 3, [SDTCisVT<0,i32>,
SDTCisSameAs<0, 1>,
Expand Down Expand Up @@ -173,15 +189,13 @@ def ARMseretglue : SDNode<"ARMISD::SERET_GLUE", SDTNone,
[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
def ARMintretglue : SDNode<"ARMISD::INTRET_GLUE", SDT_ARMcall,
[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
[SDNPInGlue]>;
def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov>;

def ARMssat : SDNode<"ARMISD::SSAT", SDTIntSatNoShOp, []>;

def ARMusat : SDNode<"ARMISD::USAT", SDTIntSatNoShOp, []>;

def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
[SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond, [SDNPHasChain]>;

def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
[SDNPHasChain]>;
Expand All @@ -191,14 +205,11 @@ def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
[SDNPHasChain]>;

def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
[SDNPOutGlue]>;
def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp>;

def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp,
[SDNPOutGlue]>;
def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp>;

def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
[SDNPOutGlue, SDNPCommutative]>;
def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp, [SDNPCommutative]>;

def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;

Expand Down Expand Up @@ -1776,7 +1787,7 @@ multiclass AI1_cmp_irs<bits<4> opcod, string opc,
string rrDecoderMethod = ""> {
def ri : AI1<opcod, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, iii,
opc, "\t$Rn, $imm",
[(opnode GPR:$Rn, mod_imm:$imm)]>,
[(set CPSR, (opnode GPR:$Rn, mod_imm:$imm))]>,
Sched<[WriteCMP, ReadALU]> {
bits<4> Rn;
bits<12> imm;
Expand All @@ -1790,7 +1801,7 @@ multiclass AI1_cmp_irs<bits<4> opcod, string opc,
}
def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
opc, "\t$Rn, $Rm",
[(opnode GPR:$Rn, GPR:$Rm)]>,
[(set CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
Sched<[WriteCMP, ReadALU, ReadALU]> {
bits<4> Rn;
bits<4> Rm;
Expand All @@ -1808,7 +1819,7 @@ multiclass AI1_cmp_irs<bits<4> opcod, string opc,
def rsi : AI1<opcod, (outs),
(ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
opc, "\t$Rn, $shift",
[(opnode GPR:$Rn, so_reg_imm:$shift)]>,
[(set CPSR, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
Sched<[WriteCMPsi, ReadALU]> {
bits<4> Rn;
bits<12> shift;
Expand All @@ -1825,7 +1836,7 @@ multiclass AI1_cmp_irs<bits<4> opcod, string opc,
def rsr : AI1<opcod, (outs),
(ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
opc, "\t$Rn, $shift",
[(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>,
[(set CPSR, (opnode GPRnopc:$Rn, so_reg_reg:$shift))]>,
Sched<[WriteCMPsr, ReadALU]> {
bits<4> Rn;
bits<12> shift;
Expand Down Expand Up @@ -4943,7 +4954,7 @@ def : ARMPat<(ARMcmpZ so_reg_reg:$rhs, 0),
let isCompare = 1, Defs = [CPSR] in {
def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, IIC_iCMPi,
"cmn", "\t$Rn, $imm",
[(ARMcmn GPR:$Rn, mod_imm:$imm)]>,
[(set CPSR, (ARMcmn GPR:$Rn, mod_imm:$imm))]>,
Sched<[WriteCMP, ReadALU]> {
bits<4> Rn;
bits<12> imm;
Expand All @@ -4959,8 +4970,8 @@ def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, IIC_iCMPi,
// CMN register-register/shift
def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
"cmn", "\t$Rn, $Rm",
[(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
[(set CPSR, (BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
GPR:$Rn, GPR:$Rm))]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
bits<4> Rn;
bits<4> Rm;
let isCommutable = 1;
Expand All @@ -4977,8 +4988,8 @@ def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
def CMNzrsi : AI1<0b1011, (outs),
(ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
"cmn", "\t$Rn, $shift",
[(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
GPR:$Rn, so_reg_imm:$shift)]>,
[(set CPSR, (BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
GPR:$Rn, so_reg_imm:$shift))]>,
Sched<[WriteCMPsi, ReadALU]> {
bits<4> Rn;
bits<12> shift;
Expand All @@ -4996,8 +5007,8 @@ def CMNzrsi : AI1<0b1011, (outs),
def CMNzrsr : AI1<0b1011, (outs),
(ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr,
"cmn", "\t$Rn, $shift",
[(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
GPRnopc:$Rn, so_reg_reg:$shift)]>,
[(set CPSR, (BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
GPRnopc:$Rn, so_reg_reg:$shift))]>,
Sched<[WriteCMPsr, ReadALU]> {
bits<4> Rn;
bits<12> shift;
Expand Down Expand Up @@ -5052,65 +5063,74 @@ let hasSideEffects = 0 in {

let isCommutable = 1, isSelect = 1 in
def MOVCCr : ARMPseudoInst<(outs GPR:$Rd),
(ins GPR:$false, GPR:$Rm, cmovpred:$p),
4, IIC_iCMOVr,
[(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm,
cmovpred:$p))]>,
(ins GPR:$false, GPR:$Rm, pred:$p),
4, IIC_iCMOVr, []>,
RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;

def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
(ins GPR:$false, so_reg_imm:$shift, cmovpred:$p),
4, IIC_iCMOVsr,
[(set GPR:$Rd,
(ARMcmov GPR:$false, so_reg_imm:$shift,
cmovpred:$p))]>,
(ins GPR:$false, so_reg_imm:$shift, pred:$p),
4, IIC_iCMOVsr, []>,
RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
(ins GPR:$false, so_reg_reg:$shift, cmovpred:$p),
4, IIC_iCMOVsr,
[(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
cmovpred:$p))]>,
(ins GPR:$false, so_reg_reg:$shift, pred:$p),
4, IIC_iCMOVsr, []>,
RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;


let isMoveImm = 1 in
def MOVCCi16
: ARMPseudoInst<(outs GPR:$Rd),
(ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p),
4, IIC_iMOVi,
[(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm,
cmovpred:$p))]>,
(ins GPR:$false, imm0_65535_expr:$imm, pred:$p),
4, IIC_iMOVi, []>,
RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
Sched<[WriteALU]>;

let isMoveImm = 1 in
def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
(ins GPR:$false, mod_imm:$imm, cmovpred:$p),
4, IIC_iCMOVi,
[(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm:$imm,
cmovpred:$p))]>,
(ins GPR:$false, mod_imm:$imm, pred:$p),
4, IIC_iCMOVi, []>,
RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;

// Two instruction predicate mov immediate.
let isMoveImm = 1 in
def MOVCCi32imm
: ARMPseudoInst<(outs GPR:$Rd),
(ins GPR:$false, i32imm:$src, cmovpred:$p),
8, IIC_iCMOVix2,
[(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src,
cmovpred:$p))]>,
(ins GPR:$false, i32imm:$src, pred:$p),
8, IIC_iCMOVix2, []>,
RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;

let isMoveImm = 1 in
def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
(ins GPR:$false, mod_imm:$imm, cmovpred:$p),
4, IIC_iCMOVi,
[(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm_not:$imm,
cmovpred:$p))]>,
(ins GPR:$false, mod_imm:$imm, pred:$p),
4, IIC_iCMOVi, []>,
RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;

} // hasSideEffects

// The following patterns have to be defined out-of-line because the number
// of instruction operands does not match the number of SDNode operands
// (`pred` counts as one operand).

def : ARMPat<(ARMcmov i32:$false, i32:$Rm, imm:$cc, CPSR),
(MOVCCr $false, $Rm, imm:$cc, CPSR)>;

def : ARMPat<(ARMcmov i32:$false, so_reg_imm:$shift, imm:$cc, CPSR),
(MOVCCsi $false, so_reg_imm:$shift, imm:$cc, CPSR)>;

def : ARMPat<(ARMcmov i32:$false, so_reg_reg:$shift, imm:$cc, CPSR),
(MOVCCsr $false, so_reg_reg:$shift, imm:$cc, CPSR)>;

def : ARMV6T2Pat<(ARMcmov i32:$false, imm0_65535:$imm, imm:$cc, CPSR),
(MOVCCi16 $false, imm0_65535:$imm, imm:$cc, CPSR)>;

def : ARMPat<(ARMcmov i32:$false, mod_imm:$imm, imm:$cc, CPSR),
(MOVCCi $false, mod_imm:$imm, imm:$cc, CPSR)>;

def : ARMPat<(ARMcmov i32:$false, mod_imm_not:$imm, imm:$cc, CPSR),
(MVNCCi $false, mod_imm_not:$imm, imm:$cc, CPSR)>;

def : ARMV6T2Pat<(ARMcmov i32:$false, imm:$src, imm:$cc, CPSR),
(MOVCCi32imm $false, imm:$src, imm:$cc, CPSR)>;

//===----------------------------------------------------------------------===//
// Atomic operations intrinsics
Expand Down
22 changes: 12 additions & 10 deletions llvm/lib/Target/ARM/ARMInstrThumb.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -23,8 +23,7 @@ def imm_sr_XFORM: SDNodeXForm<imm, [{
return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), SDLoc(N), MVT::i32);
}]>;
def ThumbSRImmAsmOperand: ImmAsmOperand<1,32> { let Name = "ImmThumbSR"; }
def imm_sr : Operand<i32>, PatLeaf<(imm), [{
uint64_t Imm = N->getZExtValue();
def imm_sr : Operand<i32>, ImmLeaf<i32, [{
return Imm > 0 && Imm <= 32;
}], imm_sr_XFORM> {
let PrintMethod = "printThumbSRImm";
Expand Down Expand Up @@ -1108,21 +1107,22 @@ let isCompare = 1, Defs = [CPSR] in {
// T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs),
// IIC_iCMPr,
// "cmn", "\t$lhs, $rhs",
// [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
// [(set CPSR, (ARMcmp tGPR:$lhs, (ineg tGPR:$rhs)))]>;

def tCMNz : // A8.6.33
T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),
IIC_iCMPr,
"cmn", "\t$Rn, $Rm",
[(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>, Sched<[WriteCMP]>;
[(set CPSR, (ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm)))]>,
Sched<[WriteCMP]>;

} // isCompare = 1, Defs = [CPSR]

// CMP immediate
let isCompare = 1, Defs = [CPSR] in {
def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi,
"cmp", "\t$Rn, $imm8",
[(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>,
[(set CPSR, (ARMcmp tGPR:$Rn, imm0_255:$imm8))]>,
T1General<{1,0,1,?,?}>, Sched<[WriteCMP]> {
// A8.6.35
bits<3> Rn;
Expand All @@ -1136,7 +1136,7 @@ def tCMPr : // A8.6.36 T1
T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm),
IIC_iCMPr,
"cmp", "\t$Rn, $Rm",
[(ARMcmp tGPR:$Rn, tGPR:$Rm)]>, Sched<[WriteCMP]>;
[(set CPSR, (ARMcmp tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteCMP]>;

def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,
"cmp", "\t$Rn, $Rm", []>,
Expand Down Expand Up @@ -1423,7 +1423,7 @@ let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
def tTST : // A8.6.230
T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,
"tst", "\t$Rn, $Rm",
[(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>,
[(set CPSR, (ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0))]>,
Sched<[WriteALU]>;

// A8.8.247 UDF - Undefined (Encoding T1)
Expand Down Expand Up @@ -1466,9 +1466,11 @@ def tUXTH : // A8.6.264
// Expanded after instruction selection into a branch sequence.
let usesCustomInserter = 1 in // Expanded after instruction selection.
def tMOVCCr_pseudo :
PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, cmovpred:$p),
NoItinerary,
[(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, cmovpred:$p))]>;
PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$p),
NoItinerary, []>;

def : Pat<(ARMcmov tGPR:$false, tGPR:$true, imm:$cc, CPSR),
(tMOVCCr_pseudo $false, $true, imm:$cc, CPSR)>;

// tLEApcrel - Load a pc-relative address into a register without offending the
// assembler.
Expand Down
152 changes: 87 additions & 65 deletions llvm/lib/Target/ARM/ARMInstrThumb2.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1144,7 +1144,8 @@ let isCompare = 1, Defs = [CPSR] in {
def ri : T2OneRegCmpImm<
(outs), (ins LHSGPR:$Rn, t2_so_imm:$imm), iii,
opc, ".w\t$Rn, $imm",
[(opnode LHSGPR:$Rn, t2_so_imm:$imm)]>, Sched<[WriteCMP]> {
[(set CPSR, (opnode LHSGPR:$Rn, t2_so_imm:$imm))]>,
Sched<[WriteCMP]> {
let Inst{31-27} = 0b11110;
let Inst{25} = 0;
let Inst{24-21} = opcod;
Expand All @@ -1156,7 +1157,8 @@ let isCompare = 1, Defs = [CPSR] in {
def rr : T2TwoRegCmp<
(outs), (ins LHSGPR:$Rn, rGPR:$Rm), iir,
opc, ".w\t$Rn, $Rm",
[(opnode LHSGPR:$Rn, rGPR:$Rm)]>, Sched<[WriteCMP]> {
[(set CPSR, (opnode LHSGPR:$Rn, rGPR:$Rm))]>,
Sched<[WriteCMP]> {
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
let Inst{24-21} = opcod;
Expand All @@ -1170,7 +1172,7 @@ let isCompare = 1, Defs = [CPSR] in {
def rs : T2OneRegCmpShiftedReg<
(outs), (ins LHSGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
opc, ".w\t$Rn, $ShiftedRm",
[(opnode LHSGPR:$Rn, t2_so_reg:$ShiftedRm)]>,
[(set CPSR, (opnode LHSGPR:$Rn, t2_so_reg:$ShiftedRm))]>,
Sched<[WriteCMPsi]> {
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
Expand Down Expand Up @@ -3477,7 +3479,7 @@ let isCompare = 1, Defs = [CPSR] in {
def t2CMNri : T2OneRegCmpImm<
(outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iCMPi,
"cmn", ".w\t$Rn, $imm",
[(ARMcmn GPRnopc:$Rn, (ineg t2_so_imm:$imm))]>,
[(set CPSR, (ARMcmn GPRnopc:$Rn, (ineg t2_so_imm:$imm)))]>,
Sched<[WriteCMP, ReadALU]> {
let Inst{31-27} = 0b11110;
let Inst{25} = 0;
Expand All @@ -3490,8 +3492,9 @@ let isCompare = 1, Defs = [CPSR] in {
def t2CMNzrr : T2TwoRegCmp<
(outs), (ins GPRnopc:$Rn, rGPR:$Rm), IIC_iCMPr,
"cmn", ".w\t$Rn, $Rm",
[(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
GPRnopc:$Rn, rGPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
[(set CPSR, (BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
GPRnopc:$Rn, rGPR:$Rm))]>,
Sched<[WriteCMP, ReadALU, ReadALU]> {
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
let Inst{24-21} = 0b1000;
Expand All @@ -3505,8 +3508,8 @@ let isCompare = 1, Defs = [CPSR] in {
def t2CMNzrs : T2OneRegCmpShiftedReg<
(outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), IIC_iCMPsi,
"cmn", ".w\t$Rn, $ShiftedRm",
[(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]>,
[(set CPSR, (BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]>,
Sched<[WriteCMPsi, ReadALU, ReadALU]> {
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
Expand Down Expand Up @@ -3542,67 +3545,84 @@ let hasSideEffects = 0 in {

let isCommutable = 1, isSelect = 1 in
def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd),
(ins rGPR:$false, rGPR:$Rm, cmovpred:$p),
4, IIC_iCMOVr,
[(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm,
cmovpred:$p))]>,
(ins rGPR:$false, rGPR:$Rm, pred:$p),
4, IIC_iCMOVr, []>,
RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;

let isMoveImm = 1 in
def t2MOVCCi
: t2PseudoInst<(outs rGPR:$Rd),
(ins rGPR:$false, t2_so_imm:$imm, cmovpred:$p),
4, IIC_iCMOVi,
[(set rGPR:$Rd, (ARMcmov rGPR:$false,t2_so_imm:$imm,
cmovpred:$p))]>,
(ins rGPR:$false, t2_so_imm:$imm, pred:$p),
4, IIC_iCMOVi, []>,
RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;

let isCodeGenOnly = 1 in {
let isMoveImm = 1 in
def t2MOVCCi16
: t2PseudoInst<(outs rGPR:$Rd),
(ins rGPR:$false, imm0_65535_expr:$imm, cmovpred:$p),
4, IIC_iCMOVi,
[(set rGPR:$Rd, (ARMcmov rGPR:$false, imm0_65535:$imm,
cmovpred:$p))]>,
(ins rGPR:$false, imm0_65535_expr:$imm, pred:$p),
4, IIC_iCMOVi, []>,
RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;

let isMoveImm = 1 in
def t2MVNCCi
: t2PseudoInst<(outs rGPR:$Rd),
(ins rGPR:$false, t2_so_imm:$imm, cmovpred:$p),
4, IIC_iCMOVi,
[(set rGPR:$Rd,
(ARMcmov rGPR:$false, t2_so_imm_not:$imm,
cmovpred:$p))]>,
(ins rGPR:$false, t2_so_imm:$imm, pred:$p),
4, IIC_iCMOVi, []>,
RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;

class MOVCCShPseudo<SDPatternOperator opnode, Operand ty>
class MOVCCShPseudo
: t2PseudoInst<(outs rGPR:$Rd),
(ins rGPR:$false, rGPR:$Rm, i32imm:$imm, cmovpred:$p),
4, IIC_iCMOVsi,
[(set rGPR:$Rd, (ARMcmov rGPR:$false,
(opnode rGPR:$Rm, (i32 ty:$imm)),
cmovpred:$p))]>,
(ins rGPR:$false, rGPR:$Rm, i32imm:$imm, pred:$p),
4, IIC_iCMOVsi, []>,
RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;

def t2MOVCClsl : MOVCCShPseudo<shl, imm0_31>;
def t2MOVCClsr : MOVCCShPseudo<srl, imm_sr>;
def t2MOVCCasr : MOVCCShPseudo<sra, imm_sr>;
def t2MOVCCror : MOVCCShPseudo<rotr, imm0_31>;
def t2MOVCClsl : MOVCCShPseudo;
def t2MOVCClsr : MOVCCShPseudo;
def t2MOVCCasr : MOVCCShPseudo;
def t2MOVCCror : MOVCCShPseudo;

let isMoveImm = 1 in
def t2MOVCCi32imm
: t2PseudoInst<(outs rGPR:$dst),
(ins rGPR:$false, i32imm:$src, cmovpred:$p),
8, IIC_iCMOVix2,
[(set rGPR:$dst, (ARMcmov rGPR:$false, imm:$src,
cmovpred:$p))]>,
(ins rGPR:$false, i32imm:$src, pred:$p),
8, IIC_iCMOVix2, []>,
RegConstraint<"$false = $dst">;
} // isCodeGenOnly = 1

} // hasSideEffects

// The following patterns have to be defined out-of-line because the number
// of instruction operands does not match the number of SDNode operands
// (`pred` counts as one operand).

def : T2Pat<(ARMcmov i32:$false, i32:$Rm, imm:$cc, CPSR),
(t2MOVCCr $false, $Rm, imm:$cc, CPSR)>;

def : T2Pat<(ARMcmov i32:$false, t2_so_imm:$imm, imm:$cc, CPSR),
(t2MOVCCi $false, t2_so_imm:$imm, imm:$cc, CPSR)>;

def : T2Pat<(ARMcmov i32:$false, imm0_65535:$imm, imm:$cc, CPSR),
(t2MOVCCi16 $false, imm0_65535:$imm, imm:$cc, CPSR)>;

def : T2Pat<(ARMcmov i32:$false, t2_so_imm_not:$imm, imm:$cc, CPSR),
(t2MVNCCi $false, t2_so_imm_not:$imm, imm:$cc, CPSR)>;

def : T2Pat<(ARMcmov i32:$false, (shl i32:$Rm, imm0_31:$imm), imm:$cc, CPSR),
(t2MOVCClsl $false, $Rm, imm0_31:$imm, imm:$cc, CPSR)>;

def : T2Pat<(ARMcmov i32:$false, (srl i32:$Rm, imm_sr:$imm), imm:$cc, CPSR),
(t2MOVCClsr $false, $Rm, imm_sr:$imm, imm:$cc, CPSR)>;

def : T2Pat<(ARMcmov i32:$false, (sra i32:$Rm, imm_sr:$imm), imm:$cc, CPSR),
(t2MOVCCasr $false, $Rm, imm_sr:$imm, imm:$cc, CPSR)>;

def : T2Pat<(ARMcmov i32:$false, (rotr i32:$Rm, imm0_31:$imm), imm:$cc, CPSR),
(t2MOVCCror $false, $Rm, imm0_31:$imm, imm:$cc, CPSR)>;

def : T2Pat<(ARMcmov i32:$false, imm:$src, imm:$cc, CPSR),
(t2MOVCCi32imm $false, imm:$src, imm:$cc, CPSR)>;

//===----------------------------------------------------------------------===//
// Atomic operations intrinsics
//
Expand Down Expand Up @@ -5706,51 +5726,53 @@ def t2CSINC : CS<"csinc", 0b1001>;
def t2CSINV : CS<"csinv", 0b1010>;
def t2CSNEG : CS<"csneg", 0b1011>;

def ARMcsinc_su : PatFrag<(ops node:$lhs, node:$rhs, node:$cond),
(ARMcsinc node:$lhs, node:$rhs, node:$cond), [{
def ARMcsinc_su
: PatFrag<(ops node:$lhs, node:$rhs, node:$cc, node:$flags),
(ARMcsinc node:$lhs, node:$rhs, node:$cc, node:$flags), [{
return N->hasOneUse();
}]>;

let Predicates = [HasV8_1MMainline] in {
multiclass CSPats<SDNode Node, Instruction Insn> {
def : T2Pat<(Node GPRwithZR:$tval, GPRwithZR:$fval, imm0_31:$imm),
(Insn GPRwithZR:$tval, GPRwithZR:$fval, imm0_31:$imm)>;
def : T2Pat<(Node (i32 0), GPRwithZR:$fval, imm0_31:$imm),
(Insn ZR, GPRwithZR:$fval, imm0_31:$imm)>;
def : T2Pat<(Node GPRwithZR:$tval, (i32 0), imm0_31:$imm),
(Insn GPRwithZR:$tval, ZR, imm0_31:$imm)>;
def : T2Pat<(Node (i32 0), (i32 0), imm0_31:$imm),
(Insn ZR, ZR, imm0_31:$imm)>;
def : T2Pat<(Node GPRwithZR:$tval, GPRwithZR:$fval, imm:$cc, CPSR),
(Insn GPRwithZR:$tval, GPRwithZR:$fval, imm:$cc)>;
def : T2Pat<(Node (i32 0), GPRwithZR:$fval, imm:$cc, CPSR),
(Insn ZR, GPRwithZR:$fval, imm:$cc)>;
def : T2Pat<(Node GPRwithZR:$tval, (i32 0), imm:$cc, CPSR),
(Insn GPRwithZR:$tval, ZR, imm:$cc)>;
def : T2Pat<(Node (i32 0), (i32 0), imm:$cc, CPSR),
(Insn ZR, ZR, imm:$cc)>;
}

defm : CSPats<ARMcsinc, t2CSINC>;
defm : CSPats<ARMcsinv, t2CSINV>;
defm : CSPats<ARMcsneg, t2CSNEG>;

def : T2Pat<(ARMcmov (i32 1), (i32 0), cmovpred:$imm),
(t2CSINC ZR, ZR, imm0_31:$imm)>;
def : T2Pat<(ARMcmov (i32 -1), (i32 0), cmovpred:$imm),
(t2CSINV ZR, ZR, imm0_31:$imm)>;
def : T2Pat<(ARMcmov (i32 0), (i32 1), cmovpred:$imm),
(t2CSINC ZR, ZR, (inv_cond_XFORM imm:$imm))>;
def : T2Pat<(ARMcmov (i32 0), (i32 -1), cmovpred:$imm),
(t2CSINV ZR, ZR, (inv_cond_XFORM imm:$imm))>;
def : T2Pat<(ARMcmov (i32 1), (i32 0), imm:$cc, CPSR),
(t2CSINC ZR, ZR, imm:$cc)>;
def : T2Pat<(ARMcmov (i32 -1), (i32 0), imm:$cc, CPSR),
(t2CSINV ZR, ZR, imm:$cc)>;
def : T2Pat<(ARMcmov (i32 0), (i32 1), imm:$cc, CPSR),
(t2CSINC ZR, ZR, (inv_cond_XFORM imm:$cc))>;
def : T2Pat<(ARMcmov (i32 0), (i32 -1), imm:$cc, CPSR),
(t2CSINV ZR, ZR, (inv_cond_XFORM imm:$cc))>;

multiclass ModifiedV8_1CSEL<Instruction Insn, dag modvalue> {
def : T2Pat<(ARMcmov modvalue, GPRwithZR:$tval, cmovpred:$imm),
(Insn GPRwithZR:$tval, GPRwithZR:$fval, imm0_31:$imm)>;
def : T2Pat<(ARMcmov GPRwithZR:$tval, modvalue, cmovpred:$imm),
def : T2Pat<(ARMcmov modvalue, GPRwithZR:$tval, imm:$cc, CPSR),
(Insn GPRwithZR:$tval, GPRwithZR:$fval, imm:$cc)>;
def : T2Pat<(ARMcmov GPRwithZR:$tval, modvalue, imm:$cc, CPSR),
(Insn GPRwithZR:$tval, GPRwithZR:$fval,
(i32 (inv_cond_XFORM imm:$imm)))>;
(i32 (inv_cond_XFORM imm:$cc)))>;
}
defm : ModifiedV8_1CSEL<t2CSINC, (add rGPR:$fval, 1)>;
defm : ModifiedV8_1CSEL<t2CSINV, (xor rGPR:$fval, -1)>;
defm : ModifiedV8_1CSEL<t2CSNEG, (sub 0, rGPR:$fval)>;

def : T2Pat<(ARMcmov (topbitsallzero32:$Rn), (i32 1), cmovpred:$imm),
(t2CSINC $Rn, ZR, (inv_cond_XFORM imm:$imm))>;
def : T2Pat<(and (topbitsallzero32:$Rn), (ARMcsinc_su (i32 0), (i32 0), cmovpred:$imm)),
(t2CSEL ZR, $Rn, $imm)>;
def : T2Pat<(ARMcmov (topbitsallzero32:$Rn), (i32 1), imm:$cc, CPSR),
(t2CSINC $Rn, ZR, (inv_cond_XFORM imm:$cc))>;
def : T2Pat<(and (topbitsallzero32:$Rn),
(ARMcsinc_su (i32 0), (i32 0), imm:$cc, CPSR)),
(t2CSEL ZR, $Rn, imm:$cc)>;
}

// CS aliases.
Expand Down
52 changes: 32 additions & 20 deletions llvm/lib/Target/ARM/ARMInstrVFP.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -34,10 +34,10 @@ def arm_cmpfpe : SDNode<"ARMISD::CMPFPE", SDT_CMPFP>;
def arm_cmpfpe0 : SDNode<"ARMISD::CMPFPEw0", SDT_CMPFP0>;

def arm_fmstat : SDNode<"ARMISD::FMSTAT",
SDTypeProfile<0, 1, [
SDTCisVT<0, FlagsVT> // in flags
]>,
[SDNPOutGlue] // TODO: Change Glue to a normal result.
SDTypeProfile<1, 1, [
SDTCisVT<0, FlagsVT>, // out flags
SDTCisVT<1, FlagsVT> // in flags
]>
>;

def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>;
Expand Down Expand Up @@ -562,19 +562,21 @@ multiclass vsel_inst<string op, bits<2> opc, int CC> {
def H : AHbInp<0b11100, opc, 0,
(outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm),
NoItinerary, !strconcat("vsel", op, ".f16\t$Sd, $Sn, $Sm"),
[(set (f16 HPR:$Sd), (ARMcmov (f16 HPR:$Sm), (f16 HPR:$Sn), CC))]>,
[(set (f16 HPR:$Sd),
(ARMcmov (f16 HPR:$Sm), (f16 HPR:$Sn), CC, CPSR))]>,
Requires<[HasFullFP16]>;

def S : ASbInp<0b11100, opc, 0,
(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
NoItinerary, !strconcat("vsel", op, ".f32\t$Sd, $Sn, $Sm"),
[(set SPR:$Sd, (ARMcmov SPR:$Sm, SPR:$Sn, CC))]>,
[(set SPR:$Sd, (ARMcmov SPR:$Sm, SPR:$Sn, CC, CPSR))]>,
Requires<[HasFPARMv8]>;

def D : ADbInp<0b11100, opc, 0,
(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
NoItinerary, !strconcat("vsel", op, ".f64\t$Dd, $Dn, $Dm"),
[(set DPR:$Dd, (ARMcmov (f64 DPR:$Dm), (f64 DPR:$Dn), CC))]>,
[(set DPR:$Dd,
(ARMcmov (f64 DPR:$Dm), (f64 DPR:$Dn), CC, CPSR))]>,
Requires<[HasFPARMv8, HasDPVFP]>;
}
}
Expand Down Expand Up @@ -2461,25 +2463,35 @@ def : Pat<(fneg (f16 (fma (fneg (f16 HPR:$Sn)), (f16 HPR:$Sm), (f16 HPR:$Sdin)))
//

let hasSideEffects = 0 in {
def VMOVDcc : PseudoInst<(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm, cmovpred:$p),
IIC_fpUNA64,
[(set (f64 DPR:$Dd),
(ARMcmov DPR:$Dn, DPR:$Dm, cmovpred:$p))]>,
def VMOVDcc : PseudoInst<(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm, pred:$p),
IIC_fpUNA64, []>,
RegConstraint<"$Dn = $Dd">, Requires<[HasFPRegs64]>;

def VMOVScc : PseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, cmovpred:$p),
IIC_fpUNA32,
[(set (f32 SPR:$Sd),
(ARMcmov SPR:$Sn, SPR:$Sm, cmovpred:$p))]>,
def VMOVScc : PseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, pred:$p),
IIC_fpUNA32, []>,
RegConstraint<"$Sn = $Sd">, Requires<[HasFPRegs]>;

def VMOVHcc : PseudoInst<(outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm, cmovpred:$p),
IIC_fpUNA16,
[(set (f16 HPR:$Sd),
(ARMcmov (f16 HPR:$Sn), (f16 HPR:$Sm), cmovpred:$p))]>,
def VMOVHcc : PseudoInst<(outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm, pred:$p),
IIC_fpUNA16, []>,
RegConstraint<"$Sd = $Sn">, Requires<[HasFPRegs]>;
} // hasSideEffects

// The following patterns have to be defined out-of-line because the number
// of instruction operands does not match the number of SDNode operands
// (`pred` counts as one operand).

def : Pat<(ARMcmov f64:$Dn, f64:$Dm, imm:$cc, CPSR),
(VMOVDcc $Dn, $Dm, imm:$cc, CPSR)>,
Requires<[HasFPRegs64]>;

def : Pat<(ARMcmov f32:$Sn, f32:$Sm, imm:$cc, CPSR),
(VMOVScc $Sn, $Sm, imm:$cc, CPSR)>,
Requires<[HasFPRegs]>;

def : Pat<(ARMcmov f16:$Sn, f16:$Sm, imm:$cc, CPSR),
(VMOVHcc $Sn, $Sm, imm:$cc, CPSR)>,
Requires<[HasFPRegs]>; // FIXME: Shouldn't this be HasFPRegs16?

//===----------------------------------------------------------------------===//
// Move from VFP System Register to ARM core register.
//
Expand Down Expand Up @@ -2510,7 +2522,7 @@ let DecoderMethod = "DecodeForVMRSandVMSR" in {
Rt = 0b1111 /* apsr_nzcv */ in
def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins),
"vmrs", "\tAPSR_nzcv, fpscr",
[(arm_fmstat FPSCR_NZCV)]>;
[(set CPSR, (arm_fmstat FPSCR_NZCV))]>;

// Application level FPSCR -> GPR
let hasSideEffects = 1, Uses = [FPSCR], Predicates = [HasFPRegs] in
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/ARM/add-like-or.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -29,8 +29,8 @@ define i32 @test_add_i3(i1 %tst, i32 %a, i32 %b) {
; CHECK-T2: @ %bb.0:
; CHECK-T2-NEXT: .save {r4, lr}
; CHECK-T2-NEXT: push {r4, lr}
; CHECK-T2-NEXT: lsls r0, r0, #31
; CHECK-T2-NEXT: bic r4, r2, #3
; CHECK-T2-NEXT: lsls r0, r0, #31
; CHECK-T2-NEXT: it ne
; CHECK-T2-NEXT: bicne r4, r1, #6
; CHECK-T2-NEXT: mov r0, r4
Expand Down Expand Up @@ -144,12 +144,12 @@ define i32 @test_add_i12(i32 %a, i32 %b, i1 %tst) {
;
; CHECK-A-LABEL: test_add_i12:
; CHECK-A: @ %bb.0:
; CHECK-A-NEXT: bfc r1, #0, #13
; CHECK-A-NEXT: bfc r0, #0, #12
; CHECK-A-NEXT: bfc r1, #0, #13
; CHECK-A-NEXT: tst r2, #1
; CHECK-A-NEXT: moveq r0, r1
; CHECK-A-NEXT: movw r1, #854
; CHECK-A-NEXT: orr r0, r0, r1
; CHECK-A-NEXT: movne r1, r0
; CHECK-A-NEXT: movw r0, #854
; CHECK-A-NEXT: orr r0, r1, r0
; CHECK-A-NEXT: bx lr
%tmp = and i32 %a, -4096
%tmp1 = and i32 %b, -8192
Expand Down
46 changes: 46 additions & 0 deletions llvm/test/CodeGen/ARM/and-cmpz-to-shift.ll
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,46 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=thumbv6m %s -o - | FileCheck %s --check-prefix=T1
; RUN: llc -mtriple=thumbv7m %s -o - | FileCheck %s --check-prefix=T2

define void @test(i32 %x, i32 %a, i32 %b, i32 %c, i32 %d, ptr %p1, ptr %p2) {
; T1-LABEL: test:
; T1: @ %bb.0:
; T1-NEXT: push {r4, lr}
; T1-NEXT: movs r4, #1
; T1-NEXT: lsls r4, r4, #24
; T1-NEXT: tst r0, r4
; T1-NEXT: beq .LBB0_2
; T1-NEXT: @ %bb.1:
; T1-NEXT: mov r1, r2
; T1-NEXT: .LBB0_2:
; T1-NEXT: ldr r0, [sp, #12]
; T1-NEXT: str r1, [r0]
; T1-NEXT: beq .LBB0_4
; T1-NEXT: @ %bb.3:
; T1-NEXT: ldr r3, [sp, #8]
; T1-NEXT: .LBB0_4:
; T1-NEXT: ldr r0, [sp, #16]
; T1-NEXT: str r3, [r0]
; T1-NEXT: pop {r4, pc}
;
; T2-LABEL: test:
; T2: @ %bb.0:
; T2-NEXT: tst.w r0, #16777216
; T2-NEXT: ldr r0, [sp, #4]
; T2-NEXT: it ne
; T2-NEXT: movne r1, r2
; T2-NEXT: str r1, [r0]
; T2-NEXT: ldr r1, [sp, #8]
; T2-NEXT: ldr r0, [sp]
; T2-NEXT: it eq
; T2-NEXT: moveq r0, r3
; T2-NEXT: str r0, [r1]
; T2-NEXT: bx lr
%and = and i32 %x, u0x1000000
%cmp = icmp eq i32 %and, 0
%sel1 = select i1 %cmp, i32 %a, i32 %b
%sel2 = select i1 %cmp, i32 %c, i32 %d
store i32 %sel1, ptr %p1, align 4
store i32 %sel2, ptr %p2, align 4
ret void
}
94 changes: 51 additions & 43 deletions llvm/test/CodeGen/ARM/arm-shrink-wrapping.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1965,32 +1965,34 @@ define float @debug_info(float %gamma, float %slopeLimit, i1 %or.cond, double %t
; ARM-ENABLE-NEXT: @ %bb.1: @ %bb3
; ARM-ENABLE-NEXT: push {r4, r7, lr}
; ARM-ENABLE-NEXT: add r7, sp, #4
; ARM-ENABLE-NEXT: sub r4, sp, #16
; ARM-ENABLE-NEXT: sub r4, sp, #24
; ARM-ENABLE-NEXT: bfc r4, #0, #4
; ARM-ENABLE-NEXT: mov sp, r4
; ARM-ENABLE-NEXT: ldr r1, [r7, #8]
; ARM-ENABLE-NEXT: vmov.f64 d16, #1.000000e+00
; ARM-ENABLE-NEXT: mov r2, r3
; ARM-ENABLE-NEXT: vst1.64 {d8, d9}, [r4:128]
; ARM-ENABLE-NEXT: vmov d9, r3, r1
; ARM-ENABLE-NEXT: vmov s16, r0
; ARM-ENABLE-NEXT: mov r0, r3
; ARM-ENABLE-NEXT: vmov d9, r3, r1
; ARM-ENABLE-NEXT: mov r3, r1
; ARM-ENABLE-NEXT: vstr d10, [r4, #16]
; ARM-ENABLE-NEXT: vadd.f64 d10, d9, d16
; ARM-ENABLE-NEXT: bl _pow
; ARM-ENABLE-NEXT: vmov.f32 s0, #1.000000e+00
; ARM-ENABLE-NEXT: mov r4, sp
; ARM-ENABLE-NEXT: vmov.f64 d16, #1.000000e+00
; ARM-ENABLE-NEXT: vadd.f64 d16, d9, d16
; ARM-ENABLE-NEXT: vmov.f64 d17, d9
; ARM-ENABLE-NEXT: vmov d16, r0, r1
; ARM-ENABLE-NEXT: vcmp.f32 s16, s0
; ARM-ENABLE-NEXT: vmrs APSR_nzcv, fpscr
; ARM-ENABLE-NEXT: vmov d17, r0, r1
; ARM-ENABLE-NEXT: vmov.f64 d18, d9
; ARM-ENABLE-NEXT: vadd.f64 d17, d17, d17
; ARM-ENABLE-NEXT: vmovgt.f64 d18, d16
; ARM-ENABLE-NEXT: vcmp.f64 d18, d9
; ARM-ENABLE-NEXT: vadd.f64 d16, d16, d16
; ARM-ENABLE-NEXT: vmovgt.f64 d17, d10
; ARM-ENABLE-NEXT: vcmp.f64 d17, d9
; ARM-ENABLE-NEXT: vmrs APSR_nzcv, fpscr
; ARM-ENABLE-NEXT: vmovne.f64 d9, d17
; ARM-ENABLE-NEXT: vmovne.f64 d9, d16
; ARM-ENABLE-NEXT: vcvt.f32.f64 s0, d9
; ARM-ENABLE-NEXT: vld1.64 {d8, d9}, [r4:128]
; ARM-ENABLE-NEXT: vldr d10, [r4, #16]
; ARM-ENABLE-NEXT: sub sp, r7, #4
; ARM-ENABLE-NEXT: pop {r4, r7, lr}
; ARM-ENABLE-NEXT: vmov r0, s0
Expand All @@ -2012,32 +2014,33 @@ define float @debug_info(float %gamma, float %slopeLimit, i1 %or.cond, double %t
; ARM-DISABLE-NEXT: @ %bb.0: @ %bb
; ARM-DISABLE-NEXT: push {r4, r7, lr}
; ARM-DISABLE-NEXT: add r7, sp, #4
; ARM-DISABLE-NEXT: sub r4, sp, #16
; ARM-DISABLE-NEXT: sub r4, sp, #24
; ARM-DISABLE-NEXT: bfc r4, #0, #4
; ARM-DISABLE-NEXT: mov sp, r4
; ARM-DISABLE-NEXT: tst r2, #1
; ARM-DISABLE-NEXT: vst1.64 {d8, d9}, [r4:128]
; ARM-DISABLE-NEXT: vstr d10, [r4, #16]
; ARM-DISABLE-NEXT: beq LBB12_2
; ARM-DISABLE-NEXT: @ %bb.1: @ %bb3
; ARM-DISABLE-NEXT: ldr r1, [r7, #8]
; ARM-DISABLE-NEXT: vmov s16, r0
; ARM-DISABLE-NEXT: mov r0, r3
; ARM-DISABLE-NEXT: vmov.f64 d16, #1.000000e+00
; ARM-DISABLE-NEXT: mov r2, r3
; ARM-DISABLE-NEXT: vmov d9, r3, r1
; ARM-DISABLE-NEXT: vmov s16, r0
; ARM-DISABLE-NEXT: mov r0, r3
; ARM-DISABLE-NEXT: mov r3, r1
; ARM-DISABLE-NEXT: vadd.f64 d10, d9, d16
; ARM-DISABLE-NEXT: bl _pow
; ARM-DISABLE-NEXT: vmov.f32 s0, #1.000000e+00
; ARM-DISABLE-NEXT: vmov.f64 d16, #1.000000e+00
; ARM-DISABLE-NEXT: vadd.f64 d16, d9, d16
; ARM-DISABLE-NEXT: vmov.f64 d17, d9
; ARM-DISABLE-NEXT: vmov d16, r0, r1
; ARM-DISABLE-NEXT: vcmp.f32 s16, s0
; ARM-DISABLE-NEXT: vmrs APSR_nzcv, fpscr
; ARM-DISABLE-NEXT: vmov d17, r0, r1
; ARM-DISABLE-NEXT: vmov.f64 d18, d9
; ARM-DISABLE-NEXT: vadd.f64 d17, d17, d17
; ARM-DISABLE-NEXT: vmovgt.f64 d18, d16
; ARM-DISABLE-NEXT: vcmp.f64 d18, d9
; ARM-DISABLE-NEXT: vadd.f64 d16, d16, d16
; ARM-DISABLE-NEXT: vmovgt.f64 d17, d10
; ARM-DISABLE-NEXT: vcmp.f64 d17, d9
; ARM-DISABLE-NEXT: vmrs APSR_nzcv, fpscr
; ARM-DISABLE-NEXT: vmovne.f64 d9, d17
; ARM-DISABLE-NEXT: vmovne.f64 d9, d16
; ARM-DISABLE-NEXT: vcvt.f32.f64 s0, d9
; ARM-DISABLE-NEXT: b LBB12_3
; ARM-DISABLE-NEXT: LBB12_2:
Expand All @@ -2046,6 +2049,7 @@ define float @debug_info(float %gamma, float %slopeLimit, i1 %or.cond, double %t
; ARM-DISABLE-NEXT: mov r4, sp
; ARM-DISABLE-NEXT: vld1.64 {d8, d9}, [r4:128]
; ARM-DISABLE-NEXT: vmov r0, s0
; ARM-DISABLE-NEXT: vldr d10, [r4, #16]
; ARM-DISABLE-NEXT: sub sp, r7, #4
; ARM-DISABLE-NEXT: pop {r4, r7, pc}
; ARM-DISABLE-NEXT: .p2align 2
Expand All @@ -2064,34 +2068,36 @@ define float @debug_info(float %gamma, float %slopeLimit, i1 %or.cond, double %t
; THUMB-ENABLE-NEXT: @ %bb.1: @ %bb3
; THUMB-ENABLE-NEXT: push {r4, r7, lr}
; THUMB-ENABLE-NEXT: add r7, sp, #4
; THUMB-ENABLE-NEXT: sub.w r4, sp, #16
; THUMB-ENABLE-NEXT: sub.w r4, sp, #24
; THUMB-ENABLE-NEXT: bfc r4, #0, #4
; THUMB-ENABLE-NEXT: mov sp, r4
; THUMB-ENABLE-NEXT: ldr r1, [r7, #8]
; THUMB-ENABLE-NEXT: vmov.f64 d16, #1.000000e+00
; THUMB-ENABLE-NEXT: mov r2, r3
; THUMB-ENABLE-NEXT: vst1.64 {d8, d9}, [r4:128]
; THUMB-ENABLE-NEXT: vmov d9, r3, r1
; THUMB-ENABLE-NEXT: vmov s16, r0
; THUMB-ENABLE-NEXT: mov r0, r3
; THUMB-ENABLE-NEXT: vmov d9, r3, r1
; THUMB-ENABLE-NEXT: mov r3, r1
; THUMB-ENABLE-NEXT: vstr d10, [r4, #16]
; THUMB-ENABLE-NEXT: vadd.f64 d10, d9, d16
; THUMB-ENABLE-NEXT: bl _pow
; THUMB-ENABLE-NEXT: vmov.f32 s0, #1.000000e+00
; THUMB-ENABLE-NEXT: mov r4, sp
; THUMB-ENABLE-NEXT: vmov.f64 d16, #1.000000e+00
; THUMB-ENABLE-NEXT: vmov.f64 d18, d9
; THUMB-ENABLE-NEXT: vmov.f64 d17, d9
; THUMB-ENABLE-NEXT: vmov d16, r0, r1
; THUMB-ENABLE-NEXT: vcmp.f32 s16, s0
; THUMB-ENABLE-NEXT: vadd.f64 d16, d9, d16
; THUMB-ENABLE-NEXT: vmrs APSR_nzcv, fpscr
; THUMB-ENABLE-NEXT: it gt
; THUMB-ENABLE-NEXT: vmovgt.f64 d18, d16
; THUMB-ENABLE-NEXT: vcmp.f64 d18, d9
; THUMB-ENABLE-NEXT: vmov d17, r0, r1
; THUMB-ENABLE-NEXT: vmovgt.f64 d17, d10
; THUMB-ENABLE-NEXT: vcmp.f64 d17, d9
; THUMB-ENABLE-NEXT: vadd.f64 d16, d16, d16
; THUMB-ENABLE-NEXT: vmrs APSR_nzcv, fpscr
; THUMB-ENABLE-NEXT: vadd.f64 d17, d17, d17
; THUMB-ENABLE-NEXT: it ne
; THUMB-ENABLE-NEXT: vmovne.f64 d9, d17
; THUMB-ENABLE-NEXT: vmovne.f64 d9, d16
; THUMB-ENABLE-NEXT: vcvt.f32.f64 s0, d9
; THUMB-ENABLE-NEXT: vld1.64 {d8, d9}, [r4:128]
; THUMB-ENABLE-NEXT: vldr d10, [r4, #16]
; THUMB-ENABLE-NEXT: subs r4, r7, #4
; THUMB-ENABLE-NEXT: mov sp, r4
; THUMB-ENABLE-NEXT: pop.w {r4, r7, lr}
Expand All @@ -2114,43 +2120,45 @@ define float @debug_info(float %gamma, float %slopeLimit, i1 %or.cond, double %t
; THUMB-DISABLE-NEXT: @ %bb.0: @ %bb
; THUMB-DISABLE-NEXT: push {r4, r7, lr}
; THUMB-DISABLE-NEXT: add r7, sp, #4
; THUMB-DISABLE-NEXT: sub.w r4, sp, #16
; THUMB-DISABLE-NEXT: sub.w r4, sp, #24
; THUMB-DISABLE-NEXT: bfc r4, #0, #4
; THUMB-DISABLE-NEXT: mov sp, r4
; THUMB-DISABLE-NEXT: lsls r1, r2, #31
; THUMB-DISABLE-NEXT: vst1.64 {d8, d9}, [r4:128]
; THUMB-DISABLE-NEXT: vstr d10, [r4, #16]
; THUMB-DISABLE-NEXT: beq LBB12_2
; THUMB-DISABLE-NEXT: @ %bb.1: @ %bb3
; THUMB-DISABLE-NEXT: ldr r1, [r7, #8]
; THUMB-DISABLE-NEXT: vmov s16, r0
; THUMB-DISABLE-NEXT: mov r0, r3
; THUMB-DISABLE-NEXT: vmov.f64 d16, #1.000000e+00
; THUMB-DISABLE-NEXT: mov r2, r3
; THUMB-DISABLE-NEXT: vmov d9, r3, r1
; THUMB-DISABLE-NEXT: vmov s16, r0
; THUMB-DISABLE-NEXT: mov r0, r3
; THUMB-DISABLE-NEXT: mov r3, r1
; THUMB-DISABLE-NEXT: vadd.f64 d10, d9, d16
; THUMB-DISABLE-NEXT: bl _pow
; THUMB-DISABLE-NEXT: vmov.f32 s0, #1.000000e+00
; THUMB-DISABLE-NEXT: vmov.f64 d16, #1.000000e+00
; THUMB-DISABLE-NEXT: vmov.f64 d18, d9
; THUMB-DISABLE-NEXT: vmov.f64 d17, d9
; THUMB-DISABLE-NEXT: vmov d16, r0, r1
; THUMB-DISABLE-NEXT: vcmp.f32 s16, s0
; THUMB-DISABLE-NEXT: vadd.f64 d16, d9, d16
; THUMB-DISABLE-NEXT: vmrs APSR_nzcv, fpscr
; THUMB-DISABLE-NEXT: it gt
; THUMB-DISABLE-NEXT: vmovgt.f64 d18, d16
; THUMB-DISABLE-NEXT: vcmp.f64 d18, d9
; THUMB-DISABLE-NEXT: vmov d17, r0, r1
; THUMB-DISABLE-NEXT: vmovgt.f64 d17, d10
; THUMB-DISABLE-NEXT: vcmp.f64 d17, d9
; THUMB-DISABLE-NEXT: vadd.f64 d16, d16, d16
; THUMB-DISABLE-NEXT: vmrs APSR_nzcv, fpscr
; THUMB-DISABLE-NEXT: vadd.f64 d17, d17, d17
; THUMB-DISABLE-NEXT: it ne
; THUMB-DISABLE-NEXT: vmovne.f64 d9, d17
; THUMB-DISABLE-NEXT: vmovne.f64 d9, d16
; THUMB-DISABLE-NEXT: vcvt.f32.f64 s0, d9
; THUMB-DISABLE-NEXT: b LBB12_3
; THUMB-DISABLE-NEXT: LBB12_2:
; THUMB-DISABLE-NEXT: vldr s0, LCPI12_0
; THUMB-DISABLE-NEXT: LBB12_3: @ %bb13
; THUMB-DISABLE-NEXT: mov r4, sp
; THUMB-DISABLE-NEXT: vld1.64 {d8, d9}, [r4:128]
; THUMB-DISABLE-NEXT: subs r4, r7, #4
; THUMB-DISABLE-NEXT: vmov r0, s0
; THUMB-DISABLE-NEXT: vldr d10, [r4, #16]
; THUMB-DISABLE-NEXT: subs r4, r7, #4
; THUMB-DISABLE-NEXT: mov sp, r4
; THUMB-DISABLE-NEXT: pop {r4, r7, pc}
; THUMB-DISABLE-NEXT: .p2align 2
Expand Down
60 changes: 20 additions & 40 deletions llvm/test/CodeGen/ARM/atomic-64bit.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -278,12 +278,9 @@ define i64 @test10(ptr %ptr, i64 %val) {
; CHECK-BE: subs {{[^,]+}}, r2, [[REG2]]
; CHECK-LE: sbcs {{[^,]+}}, r2, [[REG2]]
; CHECK-BE: sbcs {{[^,]+}}, r1, [[REG1]]
; CHECK: mov [[CMP:[a-z0-9]+]], #0
; CHECK: movwge [[CMP]], #1
; CHECK: cmp [[CMP]], #0
; CHECK: movne [[OUT_HI]], [[REG2]]
; CHECK: movge [[OUT_HI]], [[REG2]]
; CHECK: mov [[OUT_LO:[a-z0-9]+]], r1
; CHECK: movne [[OUT_LO]], [[REG1]]
; CHECK: movge [[OUT_LO]], [[REG1]]
; CHECK: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]]
; CHECK: cmp
; CHECK: bne
Expand All @@ -297,12 +294,10 @@ define i64 @test10(ptr %ptr, i64 %val) {
; CHECK-THUMB-BE: subs.w {{[^,]+}}, r3, [[REG2]]
; CHECK-THUMB-LE: sbcs.w {{[^,]+}}, r3, [[REG2]]
; CHECK-THUMB-BE: sbcs.w {{[^,]+}}, r2, [[REG1]]
; CHECK-THUMB: mov.w [[CMP:[a-z0-9]+]], #0
; CHECK-THUMB: movge.w [[CMP]], #1
; CHECK-THUMB: cmp.w [[CMP]], #0
; CHECK-THUMB: mov [[OUT_HI:[a-z0-9]+]], r3
; CHECK-THUMB: movne [[OUT_HI]], [[REG2]]
; CHECK-THUMB: movne [[OUT_LO]], [[REG1]]
; CHECK-THUMB: itt ge
; CHECK-THUMB: movge [[OUT_HI]], [[REG2]]
; CHECK-THUMB: movge [[OUT_LO]], [[REG1]]
; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]]
; CHECK-THUMB: cmp
; CHECK-THUMB: bne
Expand All @@ -323,12 +318,9 @@ define i64 @test11(ptr %ptr, i64 %val) {
; CHECK-BE: subs {{[^,]+}}, r2, [[REG2]]
; CHECK-LE: sbcs {{[^,]+}}, r2, [[REG2]]
; CHECK-BE: sbcs {{[^,]+}}, r1, [[REG1]]
; CHECK: mov [[CMP:[a-z0-9]+]], #0
; CHECK: movwhs [[CMP]], #1
; CHECK: cmp [[CMP]], #0
; CHECK: movne [[OUT_HI]], [[REG2]]
; CHECK: movhs [[OUT_HI]], [[REG2]]
; CHECK: mov [[OUT_LO:[a-z0-9]+]], r1
; CHECK: movne [[OUT_LO]], [[REG1]]
; CHECK: movhs [[OUT_LO]], [[REG1]]
; CHECK: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]]
; CHECK: cmp
; CHECK: bne
Expand All @@ -342,12 +334,10 @@ define i64 @test11(ptr %ptr, i64 %val) {
; CHECK-THUMB-BE: subs.w {{[^,]+}}, r3, [[REG2]]
; CHECK-THUMB-LE: sbcs.w {{[^,]+}}, r3, [[REG2]]
; CHECK-THUMB-BE: sbcs.w {{[^,]+}}, r2, [[REG1]]
; CHECK-THUMB: mov.w [[CMP:[a-z0-9]+]], #0
; CHECK-THUMB: movhs.w [[CMP]], #1
; CHECK-THUMB: cmp.w [[CMP]], #0
; CHECK-THUMB: mov [[OUT_HI:[a-z0-9]+]], r3
; CHECK-THUMB: movne [[OUT_HI]], [[REG2]]
; CHECK-THUMB: movne [[OUT_LO]], [[REG1]]
; CHECK-THUMB: itt hs
; CHECK-THUMB: movhs [[OUT_HI]], [[REG2]]
; CHECK-THUMB: movhs [[OUT_LO]], [[REG1]]
; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]]
; CHECK-THUMB: cmp
; CHECK-THUMB: bne
Expand All @@ -368,12 +358,9 @@ define i64 @test12(ptr %ptr, i64 %val) {
; CHECK-BE: subs {{[^,]+}}, r2, [[REG2]]
; CHECK-LE: sbcs {{[^,]+}}, r2, [[REG2]]
; CHECK-BE: sbcs {{[^,]+}}, r1, [[REG1]]
; CHECK: mov [[CMP:[a-z0-9]+]], #0
; CHECK: movwlt [[CMP]], #1
; CHECK: cmp [[CMP]], #0
; CHECK: movne [[OUT_HI]], [[REG2]]
; CHECK: movlt [[OUT_HI]], [[REG2]]
; CHECK: mov [[OUT_LO:[a-z0-9]+]], r1
; CHECK: movne [[OUT_LO]], [[REG1]]
; CHECK: movlt [[OUT_LO]], [[REG1]]
; CHECK: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]]
; CHECK: cmp
; CHECK: bne
Expand All @@ -387,12 +374,10 @@ define i64 @test12(ptr %ptr, i64 %val) {
; CHECK-THUMB-BE: subs.w {{[^,]+}}, r3, [[REG2]]
; CHECK-THUMB-LE: sbcs.w {{[^,]+}}, r3, [[REG2]]
; CHECK-THUMB-BE: sbcs.w {{[^,]+}}, r2, [[REG1]]
; CHECK-THUMB: mov.w [[CMP:[a-z0-9]+]], #0
; CHECK-THUMB: movlt.w [[CMP]], #1
; CHECK-THUMB: cmp.w [[CMP]], #0
; CHECK-THUMB: mov [[OUT_HI:[a-z0-9]+]], r3
; CHECK-THUMB: movne [[OUT_HI]], [[REG2]]
; CHECK-THUMB: movne [[OUT_LO]], [[REG1]]
; CHECK-THUMB: itt lt
; CHECK-THUMB: movlt [[OUT_HI]], [[REG2]]
; CHECK-THUMB: movlt [[OUT_LO]], [[REG1]]
; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]]
; CHECK-THUMB: cmp
; CHECK-THUMB: bne
Expand All @@ -413,12 +398,9 @@ define i64 @test13(ptr %ptr, i64 %val) {
; CHECK-BE: subs {{[^,]+}}, r2, [[REG2]]
; CHECK-LE: sbcs {{[^,]+}}, r2, [[REG2]]
; CHECK-BE: sbcs {{[^,]+}}, r1, [[REG1]]
; CHECK: mov [[CMP:[a-z0-9]+]], #0
; CHECK: movwlo [[CMP]], #1
; CHECK: cmp [[CMP]], #0
; CHECK: movne [[OUT_HI]], [[REG2]]
; CHECK: movlo [[OUT_HI]], [[REG2]]
; CHECK: mov [[OUT_LO:[a-z0-9]+]], r1
; CHECK: movne [[OUT_LO]], [[REG1]]
; CHECK: movlo [[OUT_LO]], [[REG1]]
; CHECK: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]]
; CHECK: cmp
; CHECK: bne
Expand All @@ -432,12 +414,10 @@ define i64 @test13(ptr %ptr, i64 %val) {
; CHECK-THUMB-BE: subs.w {{[^,]+}}, r3, [[REG2]]
; CHECK-THUMB-LE: sbcs.w {{[^,]+}}, r3, [[REG2]]
; CHECK-THUMB-BE: sbcs.w {{[^,]+}}, r2, [[REG1]]
; CHECK-THUMB: mov.w [[CMP:[a-z0-9]+]], #0
; CHECK-THUMB: movlo.w [[CMP]], #1
; CHECK-THUMB: cmp.w [[CMP]], #0
; CHECK-THUMB: mov [[OUT_HI:[a-z0-9]+]], r3
; CHECK-THUMB: movne [[OUT_HI]], [[REG2]]
; CHECK-THUMB: movne [[OUT_LO]], [[REG1]]
; CHECK-THUMB: itt lo
; CHECK-THUMB: movlo [[OUT_HI]], [[REG2]]
; CHECK-THUMB: movlo [[OUT_LO]], [[REG1]]
; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]]
; CHECK-THUMB: cmp
; CHECK-THUMB: bne
Expand Down
28 changes: 8 additions & 20 deletions llvm/test/CodeGen/ARM/atomic-ops-v8.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -672,12 +672,9 @@ define void @test_atomic_load_min_i64(i64 %offset) nounwind {
; CHECK-ARM-LE: sbcs {{[^,]+}}, r1, [[OLD2]]
; CHECK-ARM-BE: subs {{[^,]+}}, r1, [[OLD2]]
; CHECK-ARM-BE: sbcs {{[^,]+}}, r0, [[OLD1]]
; CHECK-ARM: mov [[CMP:r[0-9]+|lr]], #0
; CHECK-ARM: movwge [[CMP:r[0-9]+|lr]], #1
; CHECK-ARM: cmp [[CMP:r[0-9]+|lr]], #0
; CHECK-ARM: movne [[MINHI]], [[OLD2]]
; CHECK-ARM: movge [[MINHI]], [[OLD2]]
; CHECK-ARM: mov [[MINLO:r[0-9]+]], r0
; CHECK-ARM: movne [[MINLO]], [[OLD1]]
; CHECK-ARM: movge [[MINLO]], [[OLD1]]
; CHECK-ARM: stlexd [[STATUS:r[0-9]+]], [[MINLO]], [[MINHI]], [r[[ADDR]]]
; CHECK-THUMB: stlexd [[STATUS:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]
; CHECK-NEXT: cmp [[STATUS]], #0
Expand Down Expand Up @@ -785,12 +782,9 @@ define void @test_atomic_load_max_i64(i64 %offset) nounwind {
; CHECK-ARM-LE: sbcs {{[^,]+}}, r1, [[OLD2]]
; CHECK-ARM-BE: subs {{[^,]+}}, r1, [[OLD2]]
; CHECK-ARM-BE: sbcs {{[^,]+}}, r0, [[OLD1]]
; CHECK-ARM: mov [[CMP:r[0-9]+|lr]], #0
; CHECK-ARM: movwlt [[CMP:r[0-9]+|lr]], #1
; CHECK-ARM: cmp [[CMP:r[0-9]+|lr]], #0
; CHECK-ARM: movne [[MINHI]], [[OLD2]]
; CHECK-ARM: movlt [[MINHI]], [[OLD2]]
; CHECK-ARM: mov [[MINLO:r[0-9]+]], r0
; CHECK-ARM: movne [[MINLO]], [[OLD1]]
; CHECK-ARM: movlt [[MINLO]], [[OLD1]]
; CHECK-ARM: strexd [[STATUS:r[0-9]+]], [[MINLO]], [[MINHI]], [r[[ADDR]]]
; CHECK-THUMB: strexd [[STATUS:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]
; CHECK-NEXT: cmp [[STATUS]], #0
Expand Down Expand Up @@ -898,12 +892,9 @@ define void @test_atomic_load_umin_i64(i64 %offset) nounwind {
; CHECK-ARM-LE: sbcs {{[^,]+}}, r1, [[OLD2]]
; CHECK-ARM-BE: subs {{[^,]+}}, r1, [[OLD2]]
; CHECK-ARM-BE: sbcs {{[^,]+}}, r0, [[OLD1]]
; CHECK-ARM: mov [[CMP:r[0-9]+|lr]], #0
; CHECK-ARM: movwhs [[CMP:r[0-9]+|lr]], #1
; CHECK-ARM: cmp [[CMP:r[0-9]+|lr]], #0
; CHECK-ARM: movne [[MINHI]], [[OLD2]]
; CHECK-ARM: movhs [[MINHI]], [[OLD2]]
; CHECK-ARM: mov [[MINLO:r[0-9]+]], r0
; CHECK-ARM: movne [[MINLO]], [[OLD1]]
; CHECK-ARM: movhs [[MINLO]], [[OLD1]]
; CHECK-ARM: stlexd [[STATUS:r[0-9]+]], [[MINLO]], [[MINHI]], [r[[ADDR]]]
; CHECK-THUMB: stlexd [[STATUS:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]
; CHECK-NEXT: cmp [[STATUS]], #0
Expand Down Expand Up @@ -1011,12 +1002,9 @@ define void @test_atomic_load_umax_i64(i64 %offset) nounwind {
; CHECK-ARM-LE: sbcs {{[^,]+}}, r1, [[OLD2]]
; CHECK-ARM-BE: subs {{[^,]+}}, r1, [[OLD2]]
; CHECK-ARM-BE: sbcs {{[^,]+}}, r0, [[OLD1]]
; CHECK-ARM: mov [[CMP:r[0-9]+|lr]], #0
; CHECK-ARM: movwlo [[CMP:r[0-9]+|lr]], #1
; CHECK-ARM: cmp [[CMP:r[0-9]+|lr]], #0
; CHECK-ARM: movne [[MINHI]], [[OLD2]]
; CHECK-ARM: movlo [[MINHI]], [[OLD2]]
; CHECK-ARM: mov [[MINLO:r[0-9]+]], r0
; CHECK-ARM: movne [[MINLO]], [[OLD1]]
; CHECK-ARM: movlo [[MINLO]], [[OLD1]]
; CHECK-ARM: stlexd [[STATUS:r[0-9]+]], [[MINLO]], [[MINHI]], [r[[ADDR]]]
; CHECK-THUMB: stlexd [[STATUS:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]
; CHECK-NEXT: cmp [[STATUS]], #0
Expand Down
28 changes: 12 additions & 16 deletions llvm/test/CodeGen/ARM/atomicrmw-cond-sub-clamp.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -68,27 +68,23 @@ define i32 @atomicrmw_usub_cond_i32(ptr %ptr, i32 %val) {
define i64 @atomicrmw_usub_cond_i64(ptr %ptr, i64 %val) {
; CHECK-LABEL: atomicrmw_usub_cond_i64:
; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r6, r7, r11, lr}
; CHECK-NEXT: push {r4, r5, r6, r7, r11, lr}
; CHECK-NEXT: .save {r4, r5, r11, lr}
; CHECK-NEXT: push {r4, r5, r11, lr}
; CHECK-NEXT: mov r12, r0
; CHECK-NEXT: dmb ish
; CHECK-NEXT: .LBB3_1: @ %atomicrmw.start
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldrexd r4, r5, [r0]
; CHECK-NEXT: mov r1, #0
; CHECK-NEXT: subs r6, r4, r2
; CHECK-NEXT: sbcs r7, r5, r3
; CHECK-NEXT: movwhs r1, #1
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: moveq r7, r5
; CHECK-NEXT: moveq r6, r4
; CHECK-NEXT: strexd r1, r6, r7, [r0]
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: ldrexd r0, r1, [r12]
; CHECK-NEXT: subs r4, r0, r2
; CHECK-NEXT: sbcs r5, r1, r3
; CHECK-NEXT: movlo r5, r1
; CHECK-NEXT: movlo r4, r0
; CHECK-NEXT: strexd lr, r4, r5, [r12]
; CHECK-NEXT: cmp lr, #0
; CHECK-NEXT: bne .LBB3_1
; CHECK-NEXT: @ %bb.2: @ %atomicrmw.end
; CHECK-NEXT: mov r0, r4
; CHECK-NEXT: mov r1, r5
; CHECK-NEXT: dmb ish
; CHECK-NEXT: pop {r4, r5, r6, r7, r11, pc}
; CHECK-NEXT: pop {r4, r5, r11, pc}
%result = atomicrmw usub_cond ptr %ptr, i64 %val seq_cst
ret i64 %result
}
Expand Down Expand Up @@ -164,7 +160,7 @@ define i64 @atomicrmw_usub_sat_i64(ptr %ptr, i64 %val) {
; CHECK-NEXT: subs r6, r4, r2
; CHECK-NEXT: sbcs r7, r5, r3
; CHECK-NEXT: adc r1, r12, #0
; CHECK-NEXT: eors r1, r1, #1
; CHECK-NEXT: teq r1, #1
; CHECK-NEXT: movwne r7, #0
; CHECK-NEXT: movwne r6, #0
; CHECK-NEXT: strexd r1, r6, r7, [r0]
Expand Down
34 changes: 15 additions & 19 deletions llvm/test/CodeGen/ARM/atomicrmw-uinc-udec-wrap.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -69,29 +69,25 @@ define i32 @atomicrmw_uinc_wrap_i32(ptr %ptr, i32 %val) {
define i64 @atomicrmw_uinc_wrap_i64(ptr %ptr, i64 %val) {
; CHECK-LABEL: atomicrmw_uinc_wrap_i64:
; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r6, r7, r11, lr}
; CHECK-NEXT: push {r4, r5, r6, r7, r11, lr}
; CHECK-NEXT: .save {r4, r6, r7, lr}
; CHECK-NEXT: push {r4, r6, r7, lr}
; CHECK-NEXT: mov r12, r0
; CHECK-NEXT: dmb ish
; CHECK-NEXT: .LBB3_1: @ %atomicrmw.start
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldrexd r4, r5, [r0]
; CHECK-NEXT: adds r6, r4, #1
; CHECK-NEXT: adc r7, r5, #0
; CHECK-NEXT: subs r1, r4, r2
; CHECK-NEXT: sbcs r1, r5, r3
; CHECK-NEXT: mov r1, #0
; CHECK-NEXT: movwhs r1, #1
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: movwne r7, #0
; CHECK-NEXT: movwne r6, #0
; CHECK-NEXT: strexd r1, r6, r7, [r0]
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: ldrexd r0, r1, [r12]
; CHECK-NEXT: adds r6, r0, #1
; CHECK-NEXT: adc r7, r1, #0
; CHECK-NEXT: subs r4, r0, r2
; CHECK-NEXT: sbcs r4, r1, r3
; CHECK-NEXT: movwhs r7, #0
; CHECK-NEXT: movwhs r6, #0
; CHECK-NEXT: strexd r4, r6, r7, [r12]
; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: bne .LBB3_1
; CHECK-NEXT: @ %bb.2: @ %atomicrmw.end
; CHECK-NEXT: mov r0, r4
; CHECK-NEXT: mov r1, r5
; CHECK-NEXT: dmb ish
; CHECK-NEXT: pop {r4, r5, r6, r7, r11, pc}
; CHECK-NEXT: pop {r4, r6, r7, pc}
%result = atomicrmw uinc_wrap ptr %ptr, i64 %val seq_cst
ret i64 %result
}
Expand All @@ -102,8 +98,8 @@ define i8 @atomicrmw_udec_wrap_i8(ptr %ptr, i8 %val) {
; CHECK-NEXT: dmb ish
; CHECK-NEXT: .LBB4_1: @ %atomicrmw.start
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: uxtb r3, r1
; CHECK-NEXT: ldrexb r12, [r0]
; CHECK-NEXT: uxtb r3, r1
; CHECK-NEXT: cmp r12, r3
; CHECK-NEXT: mov r3, r1
; CHECK-NEXT: subls r3, r12, #1
Expand All @@ -126,8 +122,8 @@ define i16 @atomicrmw_udec_wrap_i16(ptr %ptr, i16 %val) {
; CHECK-NEXT: dmb ish
; CHECK-NEXT: .LBB5_1: @ %atomicrmw.start
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: uxth r3, r1
; CHECK-NEXT: ldrexh r12, [r0]
; CHECK-NEXT: uxth r3, r1
; CHECK-NEXT: cmp r12, r3
; CHECK-NEXT: mov r3, r1
; CHECK-NEXT: subls r3, r12, #1
Expand Down
124 changes: 56 additions & 68 deletions llvm/test/CodeGen/ARM/atomicrmw_exclusive_monitor_ints.ll
View file

Large diffs are not rendered by default.

9 changes: 5 additions & 4 deletions llvm/test/CodeGen/ARM/bfi.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -204,10 +204,11 @@ define i32 @f12(i32 %x, i32 %y) {
define i32 @f13(i32 %x, i32 %y) {
; CHECK-LABEL: f13:
; CHECK: @ %bb.0:
; CHECK-NEXT: and r2, r0, #4
; CHECK-NEXT: bic r0, r1, #255
; CHECK-NEXT: cmp r2, #42
; CHECK-NEXT: orrne r0, r0, #16
; CHECK-NEXT: and r0, r0, #4
; CHECK-NEXT: bic r1, r1, #255
; CHECK-NEXT: cmp r0, #42
; CHECK-NEXT: orrne r1, r1, #16
; CHECK-NEXT: mov r0, r1
; CHECK-NEXT: bx lr
%y2 = and i32 %y, 4294967040 ; 0xFFFFFF00
%and = and i32 %x, 4
Expand Down
108 changes: 54 additions & 54 deletions llvm/test/CodeGen/ARM/cmov_fp16.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,12 +5,12 @@
define i32 @test_ne(i32 %x, i32 %y, i32 %a, i32 %b) {
; CHECK-LABEL: test_ne:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov s0, r1
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: cmp r2, r3
; CHECK-NEXT: vmov s2, r0
; CHECK-NEXT: vmov s2, r1
; CHECK-NEXT: vcvt.f16.u32 s0, s0
; CHECK-NEXT: vcvt.f16.u32 s2, s2
; CHECK-NEXT: vseleq.f16 s0, s0, s2
; CHECK-NEXT: vseleq.f16 s0, s2, s0
; CHECK-NEXT: vmov.f16 r0, s0
; CHECK-NEXT: bx lr
entry:
Expand All @@ -26,12 +26,12 @@ entry:
define i32 @test_eq(i32 %x, i32 %y, i32 %a, i32 %b) {
; CHECK-LABEL: test_eq:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vmov s0, r1
; CHECK-NEXT: cmp r2, r3
; CHECK-NEXT: vmov s2, r1
; CHECK-NEXT: vmov s2, r0
; CHECK-NEXT: vcvt.f16.u32 s0, s0
; CHECK-NEXT: vcvt.f16.u32 s2, s2
; CHECK-NEXT: vseleq.f16 s0, s0, s2
; CHECK-NEXT: vseleq.f16 s0, s2, s0
; CHECK-NEXT: vmov.f16 r0, s0
; CHECK-NEXT: bx lr
entry:
Expand All @@ -47,12 +47,12 @@ entry:
define i32 @test_gt(i32 %x, i32 %y, i32 %a, i32 %b) {
; CHECK-LABEL: test_gt:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vmov s0, r1
; CHECK-NEXT: cmp r2, r3
; CHECK-NEXT: vmov s2, r1
; CHECK-NEXT: vmov s2, r0
; CHECK-NEXT: vcvt.f16.u32 s0, s0
; CHECK-NEXT: vcvt.f16.u32 s2, s2
; CHECK-NEXT: vselgt.f16 s0, s0, s2
; CHECK-NEXT: vselgt.f16 s0, s2, s0
; CHECK-NEXT: vmov.f16 r0, s0
; CHECK-NEXT: bx lr
entry:
Expand All @@ -68,12 +68,12 @@ entry:
define i32 @test_ge(i32 %x, i32 %y, i32 %a, i32 %b) {
; CHECK-LABEL: test_ge:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vmov s0, r1
; CHECK-NEXT: cmp r2, r3
; CHECK-NEXT: vmov s2, r1
; CHECK-NEXT: vmov s2, r0
; CHECK-NEXT: vcvt.f16.u32 s0, s0
; CHECK-NEXT: vcvt.f16.u32 s2, s2
; CHECK-NEXT: vselge.f16 s0, s0, s2
; CHECK-NEXT: vselge.f16 s0, s2, s0
; CHECK-NEXT: vmov.f16 r0, s0
; CHECK-NEXT: bx lr
entry:
Expand All @@ -89,12 +89,12 @@ entry:
define i32 @test_lt(i32 %x, i32 %y, i32 %a, i32 %b) {
; CHECK-LABEL: test_lt:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov s0, r1
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: cmp r2, r3
; CHECK-NEXT: vmov s2, r0
; CHECK-NEXT: vmov s2, r1
; CHECK-NEXT: vcvt.f16.u32 s0, s0
; CHECK-NEXT: vcvt.f16.u32 s2, s2
; CHECK-NEXT: vselge.f16 s0, s0, s2
; CHECK-NEXT: vselge.f16 s0, s2, s0
; CHECK-NEXT: vmov.f16 r0, s0
; CHECK-NEXT: bx lr
entry:
Expand All @@ -110,12 +110,12 @@ entry:
define i32 @test_le(i32 %x, i32 %y, i32 %a, i32 %b) {
; CHECK-LABEL: test_le:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov s0, r1
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: cmp r2, r3
; CHECK-NEXT: vmov s2, r0
; CHECK-NEXT: vmov s2, r1
; CHECK-NEXT: vcvt.f16.u32 s0, s0
; CHECK-NEXT: vcvt.f16.u32 s2, s2
; CHECK-NEXT: vselgt.f16 s0, s0, s2
; CHECK-NEXT: vselgt.f16 s0, s2, s0
; CHECK-NEXT: vmov.f16 r0, s0
; CHECK-NEXT: bx lr
entry:
Expand All @@ -131,25 +131,25 @@ entry:
define i32 @test_hi(i32 %x, i32 %y, i32 %a, i32 %b) {
; CHECK-THUMB-LABEL: test_hi:
; CHECK-THUMB: @ %bb.0: @ %entry
; CHECK-THUMB-NEXT: vmov s0, r1
; CHECK-THUMB-NEXT: vmov s2, r1
; CHECK-THUMB-NEXT: cmp r2, r3
; CHECK-THUMB-NEXT: vmov s2, r0
; CHECK-THUMB-NEXT: vcvt.f16.u32 s0, s0
; CHECK-THUMB-NEXT: vmov s0, r0
; CHECK-THUMB-NEXT: vcvt.f16.u32 s2, s2
; CHECK-THUMB-NEXT: vcvt.f16.u32 s0, s0
; CHECK-THUMB-NEXT: it hi
; CHECK-THUMB-NEXT: vmovhi.f32 s0, s2
; CHECK-THUMB-NEXT: vmov.f16 r0, s0
; CHECK-THUMB-NEXT: vmovhi.f32 s2, s0
; CHECK-THUMB-NEXT: vmov.f16 r0, s2
; CHECK-THUMB-NEXT: bx lr
;
; CHECK-ARM-LABEL: test_hi:
; CHECK-ARM: @ %bb.0: @ %entry
; CHECK-ARM-NEXT: vmov s0, r1
; CHECK-ARM-NEXT: vmov s0, r0
; CHECK-ARM-NEXT: cmp r2, r3
; CHECK-ARM-NEXT: vmov s2, r0
; CHECK-ARM-NEXT: vmov s2, r1
; CHECK-ARM-NEXT: vcvt.f16.u32 s0, s0
; CHECK-ARM-NEXT: vcvt.f16.u32 s2, s2
; CHECK-ARM-NEXT: vmovhi.f32 s0, s2
; CHECK-ARM-NEXT: vmov.f16 r0, s0
; CHECK-ARM-NEXT: vmovhi.f32 s2, s0
; CHECK-ARM-NEXT: vmov.f16 r0, s2
; CHECK-ARM-NEXT: bx lr
entry:
%x.half = uitofp i32 %x to half
Expand All @@ -164,25 +164,25 @@ entry:
define i32 @test_hs(i32 %x, i32 %y, i32 %a, i32 %b) {
; CHECK-THUMB-LABEL: test_hs:
; CHECK-THUMB: @ %bb.0: @ %entry
; CHECK-THUMB-NEXT: vmov s0, r1
; CHECK-THUMB-NEXT: vmov s2, r1
; CHECK-THUMB-NEXT: cmp r2, r3
; CHECK-THUMB-NEXT: vmov s2, r0
; CHECK-THUMB-NEXT: vcvt.f16.u32 s0, s0
; CHECK-THUMB-NEXT: vmov s0, r0
; CHECK-THUMB-NEXT: vcvt.f16.u32 s2, s2
; CHECK-THUMB-NEXT: vcvt.f16.u32 s0, s0
; CHECK-THUMB-NEXT: it hs
; CHECK-THUMB-NEXT: vmovhs.f32 s0, s2
; CHECK-THUMB-NEXT: vmov.f16 r0, s0
; CHECK-THUMB-NEXT: vmovhs.f32 s2, s0
; CHECK-THUMB-NEXT: vmov.f16 r0, s2
; CHECK-THUMB-NEXT: bx lr
;
; CHECK-ARM-LABEL: test_hs:
; CHECK-ARM: @ %bb.0: @ %entry
; CHECK-ARM-NEXT: vmov s0, r1
; CHECK-ARM-NEXT: vmov s0, r0
; CHECK-ARM-NEXT: cmp r2, r3
; CHECK-ARM-NEXT: vmov s2, r0
; CHECK-ARM-NEXT: vmov s2, r1
; CHECK-ARM-NEXT: vcvt.f16.u32 s0, s0
; CHECK-ARM-NEXT: vcvt.f16.u32 s2, s2
; CHECK-ARM-NEXT: vmovhs.f32 s0, s2
; CHECK-ARM-NEXT: vmov.f16 r0, s0
; CHECK-ARM-NEXT: vmovhs.f32 s2, s0
; CHECK-ARM-NEXT: vmov.f16 r0, s2
; CHECK-ARM-NEXT: bx lr
entry:
%x.half = uitofp i32 %x to half
Expand All @@ -197,25 +197,25 @@ entry:
define i32 @test_lo(i32 %x, i32 %y, i32 %a, i32 %b) {
; CHECK-THUMB-LABEL: test_lo:
; CHECK-THUMB: @ %bb.0: @ %entry
; CHECK-THUMB-NEXT: vmov s0, r1
; CHECK-THUMB-NEXT: vmov s2, r1
; CHECK-THUMB-NEXT: cmp r2, r3
; CHECK-THUMB-NEXT: vmov s2, r0
; CHECK-THUMB-NEXT: vcvt.f16.u32 s0, s0
; CHECK-THUMB-NEXT: vmov s0, r0
; CHECK-THUMB-NEXT: vcvt.f16.u32 s2, s2
; CHECK-THUMB-NEXT: vcvt.f16.u32 s0, s0
; CHECK-THUMB-NEXT: it lo
; CHECK-THUMB-NEXT: vmovlo.f32 s0, s2
; CHECK-THUMB-NEXT: vmov.f16 r0, s0
; CHECK-THUMB-NEXT: vmovlo.f32 s2, s0
; CHECK-THUMB-NEXT: vmov.f16 r0, s2
; CHECK-THUMB-NEXT: bx lr
;
; CHECK-ARM-LABEL: test_lo:
; CHECK-ARM: @ %bb.0: @ %entry
; CHECK-ARM-NEXT: vmov s0, r1
; CHECK-ARM-NEXT: vmov s0, r0
; CHECK-ARM-NEXT: cmp r2, r3
; CHECK-ARM-NEXT: vmov s2, r0
; CHECK-ARM-NEXT: vmov s2, r1
; CHECK-ARM-NEXT: vcvt.f16.u32 s0, s0
; CHECK-ARM-NEXT: vcvt.f16.u32 s2, s2
; CHECK-ARM-NEXT: vmovlo.f32 s0, s2
; CHECK-ARM-NEXT: vmov.f16 r0, s0
; CHECK-ARM-NEXT: vmovlo.f32 s2, s0
; CHECK-ARM-NEXT: vmov.f16 r0, s2
; CHECK-ARM-NEXT: bx lr
entry:
%x.half = uitofp i32 %x to half
Expand All @@ -230,25 +230,25 @@ entry:
define i32 @test_ls(i32 %x, i32 %y, i32 %a, i32 %b) {
; CHECK-THUMB-LABEL: test_ls:
; CHECK-THUMB: @ %bb.0: @ %entry
; CHECK-THUMB-NEXT: vmov s0, r1
; CHECK-THUMB-NEXT: vmov s2, r1
; CHECK-THUMB-NEXT: cmp r2, r3
; CHECK-THUMB-NEXT: vmov s2, r0
; CHECK-THUMB-NEXT: vcvt.f16.u32 s0, s0
; CHECK-THUMB-NEXT: vmov s0, r0
; CHECK-THUMB-NEXT: vcvt.f16.u32 s2, s2
; CHECK-THUMB-NEXT: vcvt.f16.u32 s0, s0
; CHECK-THUMB-NEXT: it ls
; CHECK-THUMB-NEXT: vmovls.f32 s0, s2
; CHECK-THUMB-NEXT: vmov.f16 r0, s0
; CHECK-THUMB-NEXT: vmovls.f32 s2, s0
; CHECK-THUMB-NEXT: vmov.f16 r0, s2
; CHECK-THUMB-NEXT: bx lr
;
; CHECK-ARM-LABEL: test_ls:
; CHECK-ARM: @ %bb.0: @ %entry
; CHECK-ARM-NEXT: vmov s0, r1
; CHECK-ARM-NEXT: vmov s0, r0
; CHECK-ARM-NEXT: cmp r2, r3
; CHECK-ARM-NEXT: vmov s2, r0
; CHECK-ARM-NEXT: vmov s2, r1
; CHECK-ARM-NEXT: vcvt.f16.u32 s0, s0
; CHECK-ARM-NEXT: vcvt.f16.u32 s2, s2
; CHECK-ARM-NEXT: vmovls.f32 s0, s2
; CHECK-ARM-NEXT: vmov.f16 r0, s0
; CHECK-ARM-NEXT: vmovls.f32 s2, s0
; CHECK-ARM-NEXT: vmov.f16 r0, s2
; CHECK-ARM-NEXT: bx lr
entry:
%x.half = uitofp i32 %x to half
Expand Down
4 changes: 3 additions & 1 deletion llvm/test/CodeGen/ARM/cse-call.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,9 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
; CHECK-T1: cmp

; CHECK: S_trimzeros
; CHECK: cmp
; CHECK-T1: S_trimzeros
; CHECK-NOT: moveq
; CHECK-T1-NOT: beq
; CHECK: strlen

@F_floatmul.man1 = external global [200 x i8], align 1
Expand Down
204 changes: 98 additions & 106 deletions llvm/test/CodeGen/ARM/cttz.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -223,42 +223,39 @@ define i64 @test_i64(i64 %a) {
; CHECK-6M: @ %bb.0:
; CHECK-6M-NEXT: .save {r4, r5, r7, lr}
; CHECK-6M-NEXT: push {r4, r5, r7, lr}
; CHECK-6M-NEXT: mov r2, r0
; CHECK-6M-NEXT: ldr r5, .LCPI3_0
; CHECK-6M-NEXT: adr r4, .LCPI3_1
; CHECK-6M-NEXT: movs r3, #32
; CHECK-6M-NEXT: cmp r0, #0
; CHECK-6M-NEXT: mov r2, r3
; CHECK-6M-NEXT: bne .LBB3_5
; CHECK-6M-NEXT: @ %bb.1:
; CHECK-6M-NEXT: adr r3, .LCPI3_1
; CHECK-6M-NEXT: movs r0, #32
; CHECK-6M-NEXT: cmp r1, #0
; CHECK-6M-NEXT: bne .LBB3_6
; CHECK-6M-NEXT: mov r4, r0
; CHECK-6M-NEXT: beq .LBB3_2
; CHECK-6M-NEXT: @ %bb.1:
; CHECK-6M-NEXT: rsbs r4, r1, #0
; CHECK-6M-NEXT: ands r4, r1
; CHECK-6M-NEXT: muls r4, r5, r4
; CHECK-6M-NEXT: lsrs r1, r4, #27
; CHECK-6M-NEXT: ldrb r4, [r3, r1]
; CHECK-6M-NEXT: .LBB3_2:
; CHECK-6M-NEXT: cmp r0, #0
; CHECK-6M-NEXT: bne .LBB3_4
; CHECK-6M-NEXT: .LBB3_3:
; CHECK-6M-NEXT: adds r3, #32
; CHECK-6M-NEXT: mov r2, r3
; CHECK-6M-NEXT: adds r4, #32
; CHECK-6M-NEXT: rsbs r1, r2, #0
; CHECK-6M-NEXT: ands r1, r2
; CHECK-6M-NEXT: muls r5, r1, r5
; CHECK-6M-NEXT: lsrs r1, r5, #27
; CHECK-6M-NEXT: cmp r2, #0
; CHECK-6M-NEXT: bne .LBB3_5
; CHECK-6M-NEXT: @ %bb.3:
; CHECK-6M-NEXT: beq .LBB3_6
; CHECK-6M-NEXT: .LBB3_4:
; CHECK-6M-NEXT: movs r1, #0
; CHECK-6M-NEXT: mov r0, r2
; CHECK-6M-NEXT: pop {r4, r5, r7, pc}
; CHECK-6M-NEXT: .LBB3_5:
; CHECK-6M-NEXT: rsbs r2, r0, #0
; CHECK-6M-NEXT: ands r2, r0
; CHECK-6M-NEXT: muls r2, r5, r2
; CHECK-6M-NEXT: lsrs r2, r2, #27
; CHECK-6M-NEXT: ldrb r2, [r4, r2]
; CHECK-6M-NEXT: cmp r1, #0
; CHECK-6M-NEXT: beq .LBB3_2
; CHECK-6M-NEXT: ldrb r0, [r3, r1]
; CHECK-6M-NEXT: bne .LBB3_4
; CHECK-6M-NEXT: .LBB3_6:
; CHECK-6M-NEXT: rsbs r3, r1, #0
; CHECK-6M-NEXT: ands r3, r1
; CHECK-6M-NEXT: muls r5, r3, r5
; CHECK-6M-NEXT: lsrs r1, r5, #27
; CHECK-6M-NEXT: ldrb r3, [r4, r1]
; CHECK-6M-NEXT: cmp r0, #0
; CHECK-6M-NEXT: beq .LBB3_3
; CHECK-6M-NEXT: b .LBB3_4
; CHECK-6M-NEXT: mov r0, r4
; CHECK-6M-NEXT: movs r1, #0
; CHECK-6M-NEXT: pop {r4, r5, r7, pc}
; CHECK-6M-NEXT: .p2align 2
; CHECK-6M-NEXT: @ %bb.7:
; CHECK-6M-NEXT: .LCPI3_0:
Expand All @@ -270,40 +267,39 @@ define i64 @test_i64(i64 %a) {
; CHECK-8MBASE: @ %bb.0:
; CHECK-8MBASE-NEXT: .save {r4, r5, r7, lr}
; CHECK-8MBASE-NEXT: push {r4, r5, r7, lr}
; CHECK-8MBASE-NEXT: mov r2, r0
; CHECK-8MBASE-NEXT: movw r5, #46385
; CHECK-8MBASE-NEXT: movt r5, #1916
; CHECK-8MBASE-NEXT: adr r4, .LCPI3_0
; CHECK-8MBASE-NEXT: movs r3, #32
; CHECK-8MBASE-NEXT: mov r2, r3
; CHECK-8MBASE-NEXT: cbnz r0, .LBB3_5
; CHECK-8MBASE-NEXT: adr r3, .LCPI3_0
; CHECK-8MBASE-NEXT: movs r0, #32
; CHECK-8MBASE-NEXT: mov r4, r0
; CHECK-8MBASE-NEXT: cbz r1, .LBB3_2
; CHECK-8MBASE-NEXT: @ %bb.1:
; CHECK-8MBASE-NEXT: cbnz r1, .LBB3_6
; CHECK-8MBASE-NEXT: rsbs r4, r1, #0
; CHECK-8MBASE-NEXT: ands r4, r1
; CHECK-8MBASE-NEXT: muls r4, r5, r4
; CHECK-8MBASE-NEXT: lsrs r1, r4, #27
; CHECK-8MBASE-NEXT: ldrb r4, [r3, r1]
; CHECK-8MBASE-NEXT: .LBB3_2:
; CHECK-8MBASE-NEXT: cbnz r0, .LBB3_4
; CHECK-8MBASE-NEXT: .LBB3_3:
; CHECK-8MBASE-NEXT: adds r3, #32
; CHECK-8MBASE-NEXT: mov r2, r3
; CHECK-8MBASE-NEXT: adds r4, #32
; CHECK-8MBASE-NEXT: rsbs r1, r2, #0
; CHECK-8MBASE-NEXT: ands r1, r2
; CHECK-8MBASE-NEXT: muls r5, r1, r5
; CHECK-8MBASE-NEXT: lsrs r1, r5, #27
; CHECK-8MBASE-NEXT: cmp r2, #0
; CHECK-8MBASE-NEXT: bne .LBB3_5
; CHECK-8MBASE-NEXT: @ %bb.3:
; CHECK-8MBASE-NEXT: beq .LBB3_6
; CHECK-8MBASE-NEXT: .LBB3_4:
; CHECK-8MBASE-NEXT: movs r1, #0
; CHECK-8MBASE-NEXT: mov r0, r2
; CHECK-8MBASE-NEXT: pop {r4, r5, r7, pc}
; CHECK-8MBASE-NEXT: .LBB3_5:
; CHECK-8MBASE-NEXT: rsbs r2, r0, #0
; CHECK-8MBASE-NEXT: ands r2, r0
; CHECK-8MBASE-NEXT: muls r2, r5, r2
; CHECK-8MBASE-NEXT: lsrs r2, r2, #27
; CHECK-8MBASE-NEXT: ldrb r2, [r4, r2]
; CHECK-8MBASE-NEXT: cmp r1, #0
; CHECK-8MBASE-NEXT: beq .LBB3_2
; CHECK-8MBASE-NEXT: ldrb r0, [r3, r1]
; CHECK-8MBASE-NEXT: bne .LBB3_4
; CHECK-8MBASE-NEXT: .LBB3_6:
; CHECK-8MBASE-NEXT: rsbs r3, r1, #0
; CHECK-8MBASE-NEXT: ands r3, r1
; CHECK-8MBASE-NEXT: muls r5, r3, r5
; CHECK-8MBASE-NEXT: lsrs r1, r5, #27
; CHECK-8MBASE-NEXT: ldrb r3, [r4, r1]
; CHECK-8MBASE-NEXT: cmp r0, #0
; CHECK-8MBASE-NEXT: beq .LBB3_3
; CHECK-8MBASE-NEXT: b .LBB3_4
; CHECK-8MBASE-NEXT: mov r0, r4
; CHECK-8MBASE-NEXT: movs r1, #0
; CHECK-8MBASE-NEXT: pop {r4, r5, r7, pc}
; CHECK-8MBASE-NEXT: .p2align 2
; CHECK-8MBASE-NEXT: @ %bb.7:
; CHECK-8MBASE-NEXT: .LCPI3_0:
Expand Down Expand Up @@ -494,42 +490,39 @@ define i64 @test_i64_zero_undef(i64 %a) {
; CHECK-6M: @ %bb.0:
; CHECK-6M-NEXT: .save {r4, r5, r7, lr}
; CHECK-6M-NEXT: push {r4, r5, r7, lr}
; CHECK-6M-NEXT: mov r2, r0
; CHECK-6M-NEXT: ldr r5, .LCPI7_0
; CHECK-6M-NEXT: adr r4, .LCPI7_1
; CHECK-6M-NEXT: movs r3, #32
; CHECK-6M-NEXT: cmp r0, #0
; CHECK-6M-NEXT: mov r2, r3
; CHECK-6M-NEXT: bne .LBB7_5
; CHECK-6M-NEXT: @ %bb.1:
; CHECK-6M-NEXT: adr r3, .LCPI7_1
; CHECK-6M-NEXT: movs r0, #32
; CHECK-6M-NEXT: cmp r1, #0
; CHECK-6M-NEXT: bne .LBB7_6
; CHECK-6M-NEXT: mov r4, r0
; CHECK-6M-NEXT: beq .LBB7_2
; CHECK-6M-NEXT: @ %bb.1:
; CHECK-6M-NEXT: rsbs r4, r1, #0
; CHECK-6M-NEXT: ands r4, r1
; CHECK-6M-NEXT: muls r4, r5, r4
; CHECK-6M-NEXT: lsrs r1, r4, #27
; CHECK-6M-NEXT: ldrb r4, [r3, r1]
; CHECK-6M-NEXT: .LBB7_2:
; CHECK-6M-NEXT: cmp r0, #0
; CHECK-6M-NEXT: bne .LBB7_4
; CHECK-6M-NEXT: .LBB7_3:
; CHECK-6M-NEXT: adds r3, #32
; CHECK-6M-NEXT: mov r2, r3
; CHECK-6M-NEXT: adds r4, #32
; CHECK-6M-NEXT: rsbs r1, r2, #0
; CHECK-6M-NEXT: ands r1, r2
; CHECK-6M-NEXT: muls r5, r1, r5
; CHECK-6M-NEXT: lsrs r1, r5, #27
; CHECK-6M-NEXT: cmp r2, #0
; CHECK-6M-NEXT: bne .LBB7_5
; CHECK-6M-NEXT: @ %bb.3:
; CHECK-6M-NEXT: beq .LBB7_6
; CHECK-6M-NEXT: .LBB7_4:
; CHECK-6M-NEXT: movs r1, #0
; CHECK-6M-NEXT: mov r0, r2
; CHECK-6M-NEXT: pop {r4, r5, r7, pc}
; CHECK-6M-NEXT: .LBB7_5:
; CHECK-6M-NEXT: rsbs r2, r0, #0
; CHECK-6M-NEXT: ands r2, r0
; CHECK-6M-NEXT: muls r2, r5, r2
; CHECK-6M-NEXT: lsrs r2, r2, #27
; CHECK-6M-NEXT: ldrb r2, [r4, r2]
; CHECK-6M-NEXT: cmp r1, #0
; CHECK-6M-NEXT: beq .LBB7_2
; CHECK-6M-NEXT: ldrb r0, [r3, r1]
; CHECK-6M-NEXT: bne .LBB7_4
; CHECK-6M-NEXT: .LBB7_6:
; CHECK-6M-NEXT: rsbs r3, r1, #0
; CHECK-6M-NEXT: ands r3, r1
; CHECK-6M-NEXT: muls r5, r3, r5
; CHECK-6M-NEXT: lsrs r1, r5, #27
; CHECK-6M-NEXT: ldrb r3, [r4, r1]
; CHECK-6M-NEXT: cmp r0, #0
; CHECK-6M-NEXT: beq .LBB7_3
; CHECK-6M-NEXT: b .LBB7_4
; CHECK-6M-NEXT: mov r0, r4
; CHECK-6M-NEXT: movs r1, #0
; CHECK-6M-NEXT: pop {r4, r5, r7, pc}
; CHECK-6M-NEXT: .p2align 2
; CHECK-6M-NEXT: @ %bb.7:
; CHECK-6M-NEXT: .LCPI7_0:
Expand All @@ -541,40 +534,39 @@ define i64 @test_i64_zero_undef(i64 %a) {
; CHECK-8MBASE: @ %bb.0:
; CHECK-8MBASE-NEXT: .save {r4, r5, r7, lr}
; CHECK-8MBASE-NEXT: push {r4, r5, r7, lr}
; CHECK-8MBASE-NEXT: mov r2, r0
; CHECK-8MBASE-NEXT: movw r5, #46385
; CHECK-8MBASE-NEXT: movt r5, #1916
; CHECK-8MBASE-NEXT: adr r4, .LCPI7_0
; CHECK-8MBASE-NEXT: movs r3, #32
; CHECK-8MBASE-NEXT: mov r2, r3
; CHECK-8MBASE-NEXT: cbnz r0, .LBB7_5
; CHECK-8MBASE-NEXT: adr r3, .LCPI7_0
; CHECK-8MBASE-NEXT: movs r0, #32
; CHECK-8MBASE-NEXT: mov r4, r0
; CHECK-8MBASE-NEXT: cbz r1, .LBB7_2
; CHECK-8MBASE-NEXT: @ %bb.1:
; CHECK-8MBASE-NEXT: cbnz r1, .LBB7_6
; CHECK-8MBASE-NEXT: rsbs r4, r1, #0
; CHECK-8MBASE-NEXT: ands r4, r1
; CHECK-8MBASE-NEXT: muls r4, r5, r4
; CHECK-8MBASE-NEXT: lsrs r1, r4, #27
; CHECK-8MBASE-NEXT: ldrb r4, [r3, r1]
; CHECK-8MBASE-NEXT: .LBB7_2:
; CHECK-8MBASE-NEXT: cbnz r0, .LBB7_4
; CHECK-8MBASE-NEXT: .LBB7_3:
; CHECK-8MBASE-NEXT: adds r3, #32
; CHECK-8MBASE-NEXT: mov r2, r3
; CHECK-8MBASE-NEXT: adds r4, #32
; CHECK-8MBASE-NEXT: rsbs r1, r2, #0
; CHECK-8MBASE-NEXT: ands r1, r2
; CHECK-8MBASE-NEXT: muls r5, r1, r5
; CHECK-8MBASE-NEXT: lsrs r1, r5, #27
; CHECK-8MBASE-NEXT: cmp r2, #0
; CHECK-8MBASE-NEXT: bne .LBB7_5
; CHECK-8MBASE-NEXT: @ %bb.3:
; CHECK-8MBASE-NEXT: beq .LBB7_6
; CHECK-8MBASE-NEXT: .LBB7_4:
; CHECK-8MBASE-NEXT: movs r1, #0
; CHECK-8MBASE-NEXT: mov r0, r2
; CHECK-8MBASE-NEXT: pop {r4, r5, r7, pc}
; CHECK-8MBASE-NEXT: .LBB7_5:
; CHECK-8MBASE-NEXT: rsbs r2, r0, #0
; CHECK-8MBASE-NEXT: ands r2, r0
; CHECK-8MBASE-NEXT: muls r2, r5, r2
; CHECK-8MBASE-NEXT: lsrs r2, r2, #27
; CHECK-8MBASE-NEXT: ldrb r2, [r4, r2]
; CHECK-8MBASE-NEXT: cmp r1, #0
; CHECK-8MBASE-NEXT: beq .LBB7_2
; CHECK-8MBASE-NEXT: ldrb r0, [r3, r1]
; CHECK-8MBASE-NEXT: bne .LBB7_4
; CHECK-8MBASE-NEXT: .LBB7_6:
; CHECK-8MBASE-NEXT: rsbs r3, r1, #0
; CHECK-8MBASE-NEXT: ands r3, r1
; CHECK-8MBASE-NEXT: muls r5, r3, r5
; CHECK-8MBASE-NEXT: lsrs r1, r5, #27
; CHECK-8MBASE-NEXT: ldrb r3, [r4, r1]
; CHECK-8MBASE-NEXT: cmp r0, #0
; CHECK-8MBASE-NEXT: beq .LBB7_3
; CHECK-8MBASE-NEXT: b .LBB7_4
; CHECK-8MBASE-NEXT: mov r0, r4
; CHECK-8MBASE-NEXT: movs r1, #0
; CHECK-8MBASE-NEXT: pop {r4, r5, r7, pc}
; CHECK-8MBASE-NEXT: .p2align 2
; CHECK-8MBASE-NEXT: @ %bb.7:
; CHECK-8MBASE-NEXT: .LCPI7_0:
Expand Down
20 changes: 10 additions & 10 deletions llvm/test/CodeGen/ARM/fadd-select-fneg-combine.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,12 +4,12 @@
define float @fadd_select_fneg_fneg_f32(i32 %arg0, float %x, float %y, float %z) {
; CHECK-LABEL: fadd_select_fneg_fneg_f32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov s0, r3
; CHECK-NEXT: vmov s0, r2
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: vmov s2, r2
; CHECK-NEXT: vmov s4, r1
; CHECK-NEXT: vseleq.f32 s2, s4, s2
; CHECK-NEXT: vsub.f32 s0, s0, s2
; CHECK-NEXT: vmov s2, r3
; CHECK-NEXT: vseleq.f32 s0, s4, s0
; CHECK-NEXT: vsub.f32 s0, s2, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bx lr
%cmp = icmp eq i32 %arg0, 0
Expand Down Expand Up @@ -248,10 +248,10 @@ define half @fadd_select_fsub_select_f16(i32 %arg0, half %x, half %y, half %z) {
define half @fadd_select_fneg_negk_f16(i32 %arg0, half %x, half %y) {
; CHECK-LABEL: fadd_select_fneg_negk_f16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.f16 s0, r1
; CHECK-NEXT: vmov.f16 s2, #4.000000e+00
; CHECK-NEXT: vmov.f16 s0, #4.000000e+00
; CHECK-NEXT: vmov.f16 s2, r1
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: vseleq.f16 s0, s0, s2
; CHECK-NEXT: vseleq.f16 s0, s2, s0
; CHECK-NEXT: vmov.f16 s2, r2
; CHECK-NEXT: vsub.f16 s0, s2, s0
; CHECK-NEXT: vmov r0, s0
Expand All @@ -266,10 +266,10 @@ define half @fadd_select_fneg_negk_f16(i32 %arg0, half %x, half %y) {
define half @fadd_select_fneg_posk_f16(i32 %arg0, half %x, half %y) {
; CHECK-LABEL: fadd_select_fneg_posk_f16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.f16 s0, r1
; CHECK-NEXT: vmov.f16 s2, #-4.000000e+00
; CHECK-NEXT: vmov.f16 s0, #-4.000000e+00
; CHECK-NEXT: vmov.f16 s2, r1
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: vseleq.f16 s0, s0, s2
; CHECK-NEXT: vseleq.f16 s0, s2, s0
; CHECK-NEXT: vmov.f16 s2, r2
; CHECK-NEXT: vsub.f16 s0, s2, s0
; CHECK-NEXT: vmov r0, s0
Expand Down
20 changes: 10 additions & 10 deletions llvm/test/CodeGen/ARM/fcmp-xo.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -69,12 +69,12 @@ define arm_aapcs_vfpcc float @float128(float %a0) local_unnamed_addr {
define arm_aapcs_vfpcc double @double1(double %a0) local_unnamed_addr {
; CHECK-LABEL: double1:
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.f64 d18, #1.000000e+00
; CHECK-NEXT: vcmp.f64 d18, d0
; CHECK-NEXT: vmov.f64 d16, #1.000000e+00
; CHECK-NEXT: vcmp.f64 d16, d0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov.f64 d16, #5.000000e-01
; CHECK-NEXT: vmov.f64 d17, #-5.000000e-01
; CHECK-NEXT: vselgt.f64 d0, d17, d16
; CHECK-NEXT: vmov.f64 d17, #5.000000e-01
; CHECK-NEXT: vmov.f64 d18, #-5.000000e-01
; CHECK-NEXT: vselgt.f64 d0, d18, d17
; CHECK-NEXT: bx lr
%1 = fcmp nsz olt double %a0, 1.000000e+00
%2 = select i1 %1, double -5.000000e-01, double 5.000000e-01
Expand All @@ -87,12 +87,12 @@ define arm_aapcs_vfpcc double @double128(double %a0) local_unnamed_addr {
; CHECK-NEXT: movs r0, #0
; CHECK-NEXT: movs r1, #0
; CHECK-NEXT: movt r0, #16480
; CHECK-NEXT: vmov.f64 d16, #5.000000e-01
; CHECK-NEXT: vmov d18, r1, r0
; CHECK-NEXT: vcmp.f64 d18, d0
; CHECK-NEXT: vmov.f64 d17, #5.000000e-01
; CHECK-NEXT: vmov d16, r1, r0
; CHECK-NEXT: vcmp.f64 d16, d0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov.f64 d17, #-5.000000e-01
; CHECK-NEXT: vselgt.f64 d0, d17, d16
; CHECK-NEXT: vmov.f64 d18, #-5.000000e-01
; CHECK-NEXT: vselgt.f64 d0, d18, d17
; CHECK-NEXT: bx lr
%1 = fcmp nsz olt double %a0, 128.000000e+00
%2 = select i1 %1, double -5.000000e-01, double 5.000000e-01
Expand Down
1,744 changes: 694 additions & 1,050 deletions llvm/test/CodeGen/ARM/fpclamptosat.ll
View file

Large diffs are not rendered by default.

3,204 changes: 1,564 additions & 1,640 deletions llvm/test/CodeGen/ARM/fpclamptosat_vec.ll
View file

Large diffs are not rendered by default.

44 changes: 32 additions & 12 deletions llvm/test/CodeGen/ARM/fpscr-multi-use.ll
View file
Original file line number Diff line number Diff line change
@@ -1,31 +1,51 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=armv7 %s -o - | FileCheck %s
; RUN: llc -mtriple=thumbv7 %s -o - | FileCheck --check-prefix=THUMB %s

declare double @fn()

define void @test(ptr %p, ptr %res) nounwind {
; CHECK-LABEL: test:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: push {r4, lr}
; CHECK-NEXT: vpush {d8}
; CHECK-NEXT: vldr d8, [r0]
; CHECK-NEXT: push {r4, r5, r11, lr}
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: mov r4, r1
; CHECK-NEXT: vcmp.f64 d8, #0
; CHECK-NEXT: vcmp.f64 d16, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vneg.f64 d16, d8
; CHECK-NEXT: vmov.f64 d17, d8
; CHECK-NEXT: vmovne.f64 d17, d16
; CHECK-NEXT: vstr d17, [r1]
; CHECK-NEXT: mrs r5, apsr
; CHECK-NEXT: vneg.f64 d17, d16
; CHECK-NEXT: vmovne.f64 d16, d17
; CHECK-NEXT: vstr d16, [r1]
; CHECK-NEXT: bl fn
; CHECK-NEXT: vcmp.f64 d8, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov d16, r0, r1
; CHECK-NEXT: eor r1, r1, #-2147483648
; CHECK-NEXT: msr APSR_nzcvq, r5
; CHECK-NEXT: vmov d17, r0, r1
; CHECK-NEXT: vmovne.f64 d16, d17
; CHECK-NEXT: vstr d16, [r4]
; CHECK-NEXT: vpop {d8}
; CHECK-NEXT: pop {r4, pc}
; CHECK-NEXT: pop {r4, r5, r11, pc}
;
; THUMB-LABEL: test:
; THUMB: @ %bb.0: @ %entry
; THUMB-NEXT: push {r4, r5, r7, lr}
; THUMB-NEXT: vldr d16, [r0]
; THUMB-NEXT: mov r4, r1
; THUMB-NEXT: vcmp.f64 d16, #0
; THUMB-NEXT: vmrs APSR_nzcv, fpscr
; THUMB-NEXT: mrs r5, apsr
; THUMB-NEXT: vneg.f64 d17, d16
; THUMB-NEXT: it ne
; THUMB-NEXT: vmovne.f64 d16, d17
; THUMB-NEXT: vstr d16, [r1]
; THUMB-NEXT: bl fn
; THUMB-NEXT: vmov d16, r0, r1
; THUMB-NEXT: eor r1, r1, #-2147483648
; THUMB-NEXT: msr APSR_nzcvq, r5
; THUMB-NEXT: vmov d17, r0, r1
; THUMB-NEXT: it ne
; THUMB-NEXT: vmovne.f64 d16, d17
; THUMB-NEXT: vstr d16, [r4]
; THUMB-NEXT: pop {r4, r5, r7, pc}
entry:
%x = load double, ptr %p
%cmp = fcmp une double %x, 0.000000e+00
Expand Down
157 changes: 77 additions & 80 deletions llvm/test/CodeGen/ARM/fptoi-sat-store.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -75,64 +75,62 @@ define void @test_signed_i32_f64(ptr %d, double %f) nounwind {
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, r5, r6, r7, lr}
; SOFT-NEXT: push {r4, r5, r6, r7, lr}
; SOFT-NEXT: .pad #12
; SOFT-NEXT: sub sp, #12
; SOFT-NEXT: mov r5, r3
; SOFT-NEXT: mov r6, r2
; SOFT-NEXT: str r0, [sp, #8] @ 4-byte Spill
; SOFT-NEXT: ldr r2, .LCPI1_0
; SOFT-NEXT: ldr r3, .LCPI1_1
; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: bl __aeabi_dcmpgt
; SOFT-NEXT: str r0, [sp, #4] @ 4-byte Spill
; SOFT-NEXT: movs r7, #0
; SOFT-NEXT: ldr r3, .LCPI1_2
; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: mov r2, r7
; SOFT-NEXT: .pad #4
; SOFT-NEXT: sub sp, #4
; SOFT-NEXT: mov r6, r3
; SOFT-NEXT: mov r7, r2
; SOFT-NEXT: str r0, [sp] @ 4-byte Spill
; SOFT-NEXT: movs r5, #0
; SOFT-NEXT: ldr r3, .LCPI1_0
; SOFT-NEXT: mov r0, r2
; SOFT-NEXT: mov r1, r6
; SOFT-NEXT: mov r2, r5
; SOFT-NEXT: bl __aeabi_dcmpge
; SOFT-NEXT: mov r4, r0
; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: mov r1, r6
; SOFT-NEXT: bl __aeabi_d2iz
; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: bne .LBB1_2
; SOFT-NEXT: beq .LBB1_2
; SOFT-NEXT: @ %bb.1:
; SOFT-NEXT: movs r0, #1
; SOFT-NEXT: lsls r0, r0, #31
; SOFT-NEXT: .LBB1_2:
; SOFT-NEXT: ldr r1, [sp, #4] @ 4-byte Reload
; SOFT-NEXT: cmp r1, #0
; SOFT-NEXT: bne .LBB1_4
; SOFT-NEXT: @ %bb.3:
; SOFT-NEXT: mov r4, r0
; SOFT-NEXT: b .LBB1_5
; SOFT-NEXT: .LBB1_4:
; SOFT-NEXT: b .LBB1_3
; SOFT-NEXT: .LBB1_2:
; SOFT-NEXT: movs r0, #1
; SOFT-NEXT: lsls r4, r0, #31
; SOFT-NEXT: .LBB1_3:
; SOFT-NEXT: ldr r2, .LCPI1_1
; SOFT-NEXT: ldr r3, .LCPI1_2
; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: mov r1, r6
; SOFT-NEXT: bl __aeabi_dcmpgt
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: beq .LBB1_5
; SOFT-NEXT: @ %bb.4:
; SOFT-NEXT: ldr r4, .LCPI1_3
; SOFT-NEXT: .LBB1_5:
; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: mov r2, r6
; SOFT-NEXT: mov r3, r5
; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: mov r1, r6
; SOFT-NEXT: mov r2, r7
; SOFT-NEXT: mov r3, r6
; SOFT-NEXT: bl __aeabi_dcmpun
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB1_7
; SOFT-NEXT: @ %bb.6:
; SOFT-NEXT: mov r7, r4
; SOFT-NEXT: mov r5, r4
; SOFT-NEXT: .LBB1_7:
; SOFT-NEXT: ldr r0, [sp, #8] @ 4-byte Reload
; SOFT-NEXT: str r7, [r0]
; SOFT-NEXT: add sp, #12
; SOFT-NEXT: ldr r0, [sp] @ 4-byte Reload
; SOFT-NEXT: str r5, [r0]
; SOFT-NEXT: add sp, #4
; SOFT-NEXT: pop {r4, r5, r6, r7, pc}
; SOFT-NEXT: .p2align 2
; SOFT-NEXT: @ %bb.8:
; SOFT-NEXT: .LCPI1_0:
; SOFT-NEXT: .long 4290772992 @ 0xffc00000
; SOFT-NEXT: .long 3252682752 @ 0xc1e00000
; SOFT-NEXT: .LCPI1_1:
; SOFT-NEXT: .long 1105199103 @ 0x41dfffff
; SOFT-NEXT: .long 4290772992 @ 0xffc00000
; SOFT-NEXT: .LCPI1_2:
; SOFT-NEXT: .long 3252682752 @ 0xc1e00000
; SOFT-NEXT: .long 1105199103 @ 0x41dfffff
; SOFT-NEXT: .LCPI1_3:
; SOFT-NEXT: .long 2147483647 @ 0x7fffffff
;
Expand Down Expand Up @@ -161,31 +159,31 @@ define void @test_unsigned_i32_f32(ptr %d, float %f) nounwind {
; SOFT-NEXT: push {r4, r5, r6, r7, lr}
; SOFT-NEXT: .pad #4
; SOFT-NEXT: sub sp, #4
; SOFT-NEXT: mov r7, r1
; SOFT-NEXT: mov r6, r1
; SOFT-NEXT: str r0, [sp] @ 4-byte Spill
; SOFT-NEXT: ldr r1, .LCPI2_0
; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: bl __aeabi_fcmpgt
; SOFT-NEXT: mov r6, r0
; SOFT-NEXT: movs r5, #0
; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: mov r0, r1
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: bl __aeabi_fcmpge
; SOFT-NEXT: mov r4, r0
; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: mov r7, r0
; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: bl __aeabi_f2uiz
; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: mov r4, r0
; SOFT-NEXT: cmp r7, #0
; SOFT-NEXT: bne .LBB2_2
; SOFT-NEXT: @ %bb.1:
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: mov r4, r7
; SOFT-NEXT: .LBB2_2:
; SOFT-NEXT: cmp r6, #0
; SOFT-NEXT: ldr r1, .LCPI2_0
; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: bl __aeabi_fcmpgt
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: beq .LBB2_4
; SOFT-NEXT: @ %bb.3:
; SOFT-NEXT: mvns r0, r5
; SOFT-NEXT: mvns r4, r5
; SOFT-NEXT: .LBB2_4:
; SOFT-NEXT: ldr r1, [sp] @ 4-byte Reload
; SOFT-NEXT: str r0, [r1]
; SOFT-NEXT: ldr r0, [sp] @ 4-byte Reload
; SOFT-NEXT: str r4, [r0]
; SOFT-NEXT: add sp, #4
; SOFT-NEXT: pop {r4, r5, r6, r7, pc}
; SOFT-NEXT: .p2align 2
Expand All @@ -209,41 +207,40 @@ define void @test_unsigned_i32_f64(ptr %d, double %f) nounwind {
; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, r5, r6, r7, lr}
; SOFT-NEXT: push {r4, r5, r6, r7, lr}
; SOFT-NEXT: .pad #12
; SOFT-NEXT: sub sp, #12
; SOFT-NEXT: mov r5, r3
; SOFT-NEXT: mov r4, r2
; SOFT-NEXT: str r0, [sp, #8] @ 4-byte Spill
; SOFT-NEXT: ldr r2, .LCPI3_0
; SOFT-NEXT: ldr r3, .LCPI3_1
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: bl __aeabi_dcmpgt
; SOFT-NEXT: str r0, [sp, #4] @ 4-byte Spill
; SOFT-NEXT: movs r6, #0
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: mov r2, r6
; SOFT-NEXT: mov r3, r6
; SOFT-NEXT: .pad #4
; SOFT-NEXT: sub sp, #4
; SOFT-NEXT: mov r6, r3
; SOFT-NEXT: mov r7, r2
; SOFT-NEXT: str r0, [sp] @ 4-byte Spill
; SOFT-NEXT: movs r5, #0
; SOFT-NEXT: mov r0, r2
; SOFT-NEXT: mov r1, r3
; SOFT-NEXT: mov r2, r5
; SOFT-NEXT: mov r3, r5
; SOFT-NEXT: bl __aeabi_dcmpge
; SOFT-NEXT: mov r7, r0
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: mov r4, r0
; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: mov r1, r6
; SOFT-NEXT: bl __aeabi_d2uiz
; SOFT-NEXT: cmp r7, #0
; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: bne .LBB3_2
; SOFT-NEXT: @ %bb.1:
; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: .LBB3_2:
; SOFT-NEXT: ldr r1, [sp, #4] @ 4-byte Reload
; SOFT-NEXT: cmp r1, #0
; SOFT-NEXT: mov r4, r0
; SOFT-NEXT: ldr r2, .LCPI3_0
; SOFT-NEXT: ldr r3, .LCPI3_1
; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: mov r1, r6
; SOFT-NEXT: bl __aeabi_dcmpgt
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: beq .LBB3_4
; SOFT-NEXT: @ %bb.3:
; SOFT-NEXT: mvns r0, r6
; SOFT-NEXT: mvns r4, r5
; SOFT-NEXT: .LBB3_4:
; SOFT-NEXT: ldr r1, [sp, #8] @ 4-byte Reload
; SOFT-NEXT: str r0, [r1]
; SOFT-NEXT: add sp, #12
; SOFT-NEXT: ldr r0, [sp] @ 4-byte Reload
; SOFT-NEXT: str r4, [r0]
; SOFT-NEXT: add sp, #4
; SOFT-NEXT: pop {r4, r5, r6, r7, pc}
; SOFT-NEXT: .p2align 2
; SOFT-NEXT: @ %bb.5:
Expand Down
1,660 changes: 797 additions & 863 deletions llvm/test/CodeGen/ARM/fptosi-sat-scalar.ll
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1,476 changes: 695 additions & 781 deletions llvm/test/CodeGen/ARM/fptoui-sat-scalar.ll
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8 changes: 4 additions & 4 deletions llvm/test/CodeGen/ARM/funnel-shift-rot.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -71,12 +71,12 @@ define i64 @rotl_i64(i64 %x, i64 %z) {
; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, lr}
; CHECK-NEXT: push {r4, lr}
; CHECK-NEXT: ands r3, r2, #32
; CHECK-NEXT: and r12, r2, #31
; CHECK-NEXT: tst r2, #32
; CHECK-NEXT: mov r3, r0
; CHECK-NEXT: mov r4, #31
; CHECK-NEXT: and r12, r2, #31
; CHECK-NEXT: movne r3, r1
; CHECK-NEXT: movne r1, r0
; CHECK-NEXT: mov r4, #31
; CHECK-NEXT: bic r2, r4, r2
; CHECK-NEXT: lsl lr, r3, r12
; CHECK-NEXT: lsr r0, r1, #1
Expand Down Expand Up @@ -206,7 +206,7 @@ define i32 @rotr_i32(i32 %x, i32 %z) {
define i64 @rotr_i64(i64 %x, i64 %z) {
; CHECK-LABEL: rotr_i64:
; CHECK: @ %bb.0:
; CHECK-NEXT: ands r3, r2, #32
; CHECK-NEXT: tst r2, #32
; CHECK-NEXT: mov r3, r1
; CHECK-NEXT: moveq r3, r0
; CHECK-NEXT: moveq r0, r1
Expand Down
144 changes: 70 additions & 74 deletions llvm/test/CodeGen/ARM/funnel-shift.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -47,69 +47,67 @@ declare i37 @llvm.fshl.i37(i37, i37, i37)
define i37 @fshl_i37(i37 %x, i37 %y, i37 %z) {
; SCALAR-LABEL: fshl_i37:
; SCALAR: @ %bb.0:
; SCALAR-NEXT: .save {r4, r5, r6, r7, r8, r9, r11, lr}
; SCALAR-NEXT: push {r4, r5, r6, r7, r8, r9, r11, lr}
; SCALAR-NEXT: .save {r4, r5, r6, r7, r8, lr}
; SCALAR-NEXT: push {r4, r5, r6, r7, r8, lr}
; SCALAR-NEXT: mov r8, r0
; SCALAR-NEXT: ldr r0, [sp, #36]
; SCALAR-NEXT: ldr r0, [sp, #28]
; SCALAR-NEXT: mov r4, r1
; SCALAR-NEXT: mov r6, r3
; SCALAR-NEXT: mov r5, r3
; SCALAR-NEXT: and r1, r0, #31
; SCALAR-NEXT: ldr r0, [sp, #32]
; SCALAR-NEXT: mov r9, r2
; SCALAR-NEXT: ldr r0, [sp, #24]
; SCALAR-NEXT: mov r6, r2
; SCALAR-NEXT: mov r2, #37
; SCALAR-NEXT: mov r3, #0
; SCALAR-NEXT: bl __aeabi_uldivmod
; SCALAR-NEXT: lsl r1, r6, #27
; SCALAR-NEXT: ands r0, r2, #32
; SCALAR-NEXT: orr r1, r1, r9, lsr #5
; SCALAR-NEXT: mov r3, r8
; SCALAR-NEXT: and r6, r2, #31
; SCALAR-NEXT: lsl r0, r5, #27
; SCALAR-NEXT: tst r2, #32
; SCALAR-NEXT: orr r0, r0, r6, lsr #5
; SCALAR-NEXT: mov r1, r8
; SCALAR-NEXT: and r3, r2, #31
; SCALAR-NEXT: mov r7, #31
; SCALAR-NEXT: movne r3, r1
; SCALAR-NEXT: cmp r0, #0
; SCALAR-NEXT: lslne r1, r9, #27
; SCALAR-NEXT: movne r1, r0
; SCALAR-NEXT: lslne r0, r6, #27
; SCALAR-NEXT: bic r2, r7, r2
; SCALAR-NEXT: lsl r5, r1, r3
; SCALAR-NEXT: lsr r0, r0, #1
; SCALAR-NEXT: movne r4, r8
; SCALAR-NEXT: lsl r5, r3, r6
; SCALAR-NEXT: lsr r0, r1, #1
; SCALAR-NEXT: lsl r1, r4, r6
; SCALAR-NEXT: lsr r3, r3, #1
; SCALAR-NEXT: lsr r1, r1, #1
; SCALAR-NEXT: lsl r3, r4, r3
; SCALAR-NEXT: orr r0, r5, r0, lsr r2
; SCALAR-NEXT: orr r1, r1, r3, lsr r2
; SCALAR-NEXT: pop {r4, r5, r6, r7, r8, r9, r11, pc}
; SCALAR-NEXT: orr r1, r3, r1, lsr r2
; SCALAR-NEXT: pop {r4, r5, r6, r7, r8, pc}
;
; NEON-LABEL: fshl_i37:
; NEON: @ %bb.0:
; NEON-NEXT: .save {r4, r5, r6, r7, r11, lr}
; NEON-NEXT: push {r4, r5, r6, r7, r11, lr}
; NEON-NEXT: .save {r4, r5, r6, r7, r8, lr}
; NEON-NEXT: push {r4, r5, r6, r7, r8, lr}
; NEON-NEXT: mov r4, r1
; NEON-NEXT: ldr r1, [sp, #28]
; NEON-NEXT: mov r6, r0
; NEON-NEXT: mov r8, r0
; NEON-NEXT: ldr r0, [sp, #24]
; NEON-NEXT: and r1, r1, #31
; NEON-NEXT: mov r5, r3
; NEON-NEXT: mov r7, r2
; NEON-NEXT: mov r6, r2
; NEON-NEXT: mov r2, #37
; NEON-NEXT: mov r3, #0
; NEON-NEXT: bl __aeabi_uldivmod
; NEON-NEXT: mov r0, #31
; NEON-NEXT: bic r1, r0, r2
; NEON-NEXT: lsl r0, r5, #27
; NEON-NEXT: ands r12, r2, #32
; NEON-NEXT: orr r0, r0, r7, lsr #5
; NEON-NEXT: mov r5, r6
; NEON-NEXT: and r2, r2, #31
; NEON-NEXT: movne r5, r0
; NEON-NEXT: lslne r0, r7, #27
; NEON-NEXT: cmp r12, #0
; NEON-NEXT: lsl r3, r5, r2
; NEON-NEXT: tst r2, #32
; NEON-NEXT: orr r0, r0, r6, lsr #5
; NEON-NEXT: mov r1, r8
; NEON-NEXT: and r3, r2, #31
; NEON-NEXT: mov r7, #31
; NEON-NEXT: movne r1, r0
; NEON-NEXT: lslne r0, r6, #27
; NEON-NEXT: bic r2, r7, r2
; NEON-NEXT: lsl r5, r1, r3
; NEON-NEXT: lsr r0, r0, #1
; NEON-NEXT: movne r4, r6
; NEON-NEXT: orr r0, r3, r0, lsr r1
; NEON-NEXT: lsr r3, r5, #1
; NEON-NEXT: lsl r2, r4, r2
; NEON-NEXT: orr r1, r2, r3, lsr r1
; NEON-NEXT: pop {r4, r5, r6, r7, r11, pc}
; NEON-NEXT: movne r4, r8
; NEON-NEXT: lsr r1, r1, #1
; NEON-NEXT: lsl r3, r4, r3
; NEON-NEXT: orr r0, r5, r0, lsr r2
; NEON-NEXT: orr r1, r3, r1, lsr r2
; NEON-NEXT: pop {r4, r5, r6, r7, r8, pc}
%f = call i37 @llvm.fshl.i37(i37 %x, i37 %y, i37 %z)
ret i37 %f
}
Expand Down Expand Up @@ -237,71 +235,69 @@ declare i37 @llvm.fshr.i37(i37, i37, i37)
define i37 @fshr_i37(i37 %x, i37 %y, i37 %z) {
; SCALAR-LABEL: fshr_i37:
; SCALAR: @ %bb.0:
; SCALAR-NEXT: .save {r4, r5, r6, r7, r8, lr}
; SCALAR-NEXT: push {r4, r5, r6, r7, r8, lr}
; SCALAR-NEXT: mov r8, r0
; SCALAR-NEXT: .save {r4, r5, r6, r7, r11, lr}
; SCALAR-NEXT: push {r4, r5, r6, r7, r11, lr}
; SCALAR-NEXT: mov r5, r0
; SCALAR-NEXT: ldr r0, [sp, #28]
; SCALAR-NEXT: mov r4, r1
; SCALAR-NEXT: mov r5, r3
; SCALAR-NEXT: mov r6, r3
; SCALAR-NEXT: and r1, r0, #31
; SCALAR-NEXT: ldr r0, [sp, #24]
; SCALAR-NEXT: mov r7, r2
; SCALAR-NEXT: mov r2, #37
; SCALAR-NEXT: mov r3, #0
; SCALAR-NEXT: bl __aeabi_uldivmod
; SCALAR-NEXT: lsl r3, r5, #27
; SCALAR-NEXT: add r0, r2, #27
; SCALAR-NEXT: orr r3, r3, r7, lsr #5
; SCALAR-NEXT: ands r2, r0, #32
; SCALAR-NEXT: mov r5, r8
; SCALAR-NEXT: lsl r2, r6, #27
; SCALAR-NEXT: orr r2, r2, r7, lsr #5
; SCALAR-NEXT: mov r1, #31
; SCALAR-NEXT: moveq r5, r3
; SCALAR-NEXT: lsleq r3, r7, #27
; SCALAR-NEXT: cmp r2, #0
; SCALAR-NEXT: tst r0, #32
; SCALAR-NEXT: mov r3, r5
; SCALAR-NEXT: moveq r3, r2
; SCALAR-NEXT: lsleq r2, r7, #27
; SCALAR-NEXT: bic r1, r1, r0
; SCALAR-NEXT: moveq r4, r8
; SCALAR-NEXT: lsl r6, r5, #1
; SCALAR-NEXT: and r7, r0, #31
; SCALAR-NEXT: lsl r2, r4, #1
; SCALAR-NEXT: lsl r6, r3, #1
; SCALAR-NEXT: moveq r4, r5
; SCALAR-NEXT: lsl r6, r6, r1
; SCALAR-NEXT: orr r0, r6, r2, lsr r7
; SCALAR-NEXT: lsl r2, r4, #1
; SCALAR-NEXT: lsl r1, r2, r1
; SCALAR-NEXT: orr r0, r6, r3, lsr r7
; SCALAR-NEXT: orr r1, r1, r5, lsr r7
; SCALAR-NEXT: pop {r4, r5, r6, r7, r8, pc}
; SCALAR-NEXT: orr r1, r1, r3, lsr r7
; SCALAR-NEXT: pop {r4, r5, r6, r7, r11, pc}
;
; NEON-LABEL: fshr_i37:
; NEON: @ %bb.0:
; NEON-NEXT: .save {r4, r5, r6, r7, r8, lr}
; NEON-NEXT: push {r4, r5, r6, r7, r8, lr}
; NEON-NEXT: .save {r4, r5, r6, r7, r11, lr}
; NEON-NEXT: push {r4, r5, r6, r7, r11, lr}
; NEON-NEXT: mov r4, r1
; NEON-NEXT: ldr r1, [sp, #28]
; NEON-NEXT: mov r8, r0
; NEON-NEXT: mov r5, r0
; NEON-NEXT: ldr r0, [sp, #24]
; NEON-NEXT: and r1, r1, #31
; NEON-NEXT: mov r5, r3
; NEON-NEXT: mov r6, r3
; NEON-NEXT: mov r7, r2
; NEON-NEXT: mov r2, #37
; NEON-NEXT: mov r3, #0
; NEON-NEXT: bl __aeabi_uldivmod
; NEON-NEXT: lsl r3, r5, #27
; NEON-NEXT: add r0, r2, #27
; NEON-NEXT: orr r3, r3, r7, lsr #5
; NEON-NEXT: ands r2, r0, #32
; NEON-NEXT: mov r5, r8
; NEON-NEXT: lsl r2, r6, #27
; NEON-NEXT: orr r2, r2, r7, lsr #5
; NEON-NEXT: mov r1, #31
; NEON-NEXT: moveq r5, r3
; NEON-NEXT: lsleq r3, r7, #27
; NEON-NEXT: cmp r2, #0
; NEON-NEXT: tst r0, #32
; NEON-NEXT: mov r3, r5
; NEON-NEXT: moveq r3, r2
; NEON-NEXT: lsleq r2, r7, #27
; NEON-NEXT: bic r1, r1, r0
; NEON-NEXT: moveq r4, r8
; NEON-NEXT: lsl r6, r5, #1
; NEON-NEXT: and r7, r0, #31
; NEON-NEXT: lsl r2, r4, #1
; NEON-NEXT: lsl r6, r3, #1
; NEON-NEXT: moveq r4, r5
; NEON-NEXT: lsl r6, r6, r1
; NEON-NEXT: orr r0, r6, r2, lsr r7
; NEON-NEXT: lsl r2, r4, #1
; NEON-NEXT: lsl r1, r2, r1
; NEON-NEXT: orr r0, r6, r3, lsr r7
; NEON-NEXT: orr r1, r1, r5, lsr r7
; NEON-NEXT: pop {r4, r5, r6, r7, r8, pc}
; NEON-NEXT: orr r1, r1, r3, lsr r7
; NEON-NEXT: pop {r4, r5, r6, r7, r11, pc}
%f = call i37 @llvm.fshr.i37(i37 %x, i37 %y, i37 %z)
ret i37 %f
}
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/ARM/ifcvt1.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,10 +13,10 @@ define i32 @t1(i32 %a, i32 %b) {
;
; SWIFT-LABEL: t1:
; SWIFT: @ %bb.0: @ %common.ret
; SWIFT-NEXT: mov r2, #1
; SWIFT-NEXT: cmp r0, #0
; SWIFT-NEXT: mvneq r2, #0
; SWIFT-NEXT: add r0, r1, r2
; SWIFT-NEXT: mov r0, #1
; SWIFT-NEXT: mvneq r0, #0
; SWIFT-NEXT: add r0, r1, r0
; SWIFT-NEXT: bx lr
%tmp2 = icmp eq i32 %a, 0
br i1 %tmp2, label %cond_false, label %cond_true
Expand Down
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