133 changes: 0 additions & 133 deletions llvm/test/CodeGen/RISCV/alu32.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11,14 +11,7 @@
define i32 @addi(i32 %a) nounwind {
; RV32I-LABEL: addi:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: addi a0, a0, 1
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = add i32 %a, 1
ret i32 %1
Expand All @@ -27,14 +20,7 @@ define i32 @addi(i32 %a) nounwind {
define i32 @slti(i32 %a) nounwind {
; RV32I-LABEL: slti:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: slti a0, a0, 2
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = icmp slt i32 %a, 2
%2 = zext i1 %1 to i32
Expand All @@ -44,14 +30,7 @@ define i32 @slti(i32 %a) nounwind {
define i32 @sltiu(i32 %a) nounwind {
; RV32I-LABEL: sltiu:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: sltiu a0, a0, 3
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = icmp ult i32 %a, 3
%2 = zext i1 %1 to i32
Expand All @@ -61,14 +40,7 @@ define i32 @sltiu(i32 %a) nounwind {
define i32 @xori(i32 %a) nounwind {
; RV32I-LABEL: xori:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: xori a0, a0, 4
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = xor i32 %a, 4
ret i32 %1
Expand All @@ -77,14 +49,7 @@ define i32 @xori(i32 %a) nounwind {
define i32 @ori(i32 %a) nounwind {
; RV32I-LABEL: ori:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: ori a0, a0, 5
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = or i32 %a, 5
ret i32 %1
Expand All @@ -93,14 +58,7 @@ define i32 @ori(i32 %a) nounwind {
define i32 @andi(i32 %a) nounwind {
; RV32I-LABEL: andi:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: andi a0, a0, 6
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = and i32 %a, 6
ret i32 %1
Expand All @@ -109,14 +67,7 @@ define i32 @andi(i32 %a) nounwind {
define i32 @slli(i32 %a) nounwind {
; RV32I-LABEL: slli:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: slli a0, a0, 7
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = shl i32 %a, 7
ret i32 %1
Expand All @@ -125,14 +76,7 @@ define i32 @slli(i32 %a) nounwind {
define i32 @srli(i32 %a) nounwind {
; RV32I-LABEL: srli:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: srli a0, a0, 8
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = lshr i32 %a, 8
ret i32 %1
Expand All @@ -141,14 +85,7 @@ define i32 @srli(i32 %a) nounwind {
define i32 @srai(i32 %a) nounwind {
; RV32I-LABEL: srai:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: srai a0, a0, 9
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = ashr i32 %a, 9
ret i32 %1
Expand All @@ -159,14 +96,7 @@ define i32 @srai(i32 %a) nounwind {
define i32 @add(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: add:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = add i32 %a, %b
ret i32 %1
Expand All @@ -175,14 +105,7 @@ define i32 @add(i32 %a, i32 %b) nounwind {
define i32 @sub(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: sub:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = sub i32 %a, %b
ret i32 %1
Expand All @@ -191,14 +114,7 @@ define i32 @sub(i32 %a, i32 %b) nounwind {
define i32 @sll(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: sll:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: sll a0, a0, a1
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
Expand All @@ -207,14 +123,7 @@ define i32 @sll(i32 %a, i32 %b) nounwind {
define i32 @slt(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: slt:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: slt a0, a0, a1
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = icmp slt i32 %a, %b
%2 = zext i1 %1 to i32
Expand All @@ -224,14 +133,7 @@ define i32 @slt(i32 %a, i32 %b) nounwind {
define i32 @sltu(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: sltu:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: sltu a0, a0, a1
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = icmp ult i32 %a, %b
%2 = zext i1 %1 to i32
Expand All @@ -241,14 +143,7 @@ define i32 @sltu(i32 %a, i32 %b) nounwind {
define i32 @xor(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: xor:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = xor i32 %a, %b
ret i32 %1
Expand All @@ -257,14 +152,7 @@ define i32 @xor(i32 %a, i32 %b) nounwind {
define i32 @srl(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: srl:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: srl a0, a0, a1
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
Expand All @@ -273,14 +161,7 @@ define i32 @srl(i32 %a, i32 %b) nounwind {
define i32 @sra(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: sra:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: sra a0, a0, a1
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
Expand All @@ -289,14 +170,7 @@ define i32 @sra(i32 %a, i32 %b) nounwind {
define i32 @or(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: or:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = or i32 %a, %b
ret i32 %1
Expand All @@ -305,14 +179,7 @@ define i32 @or(i32 %a, i32 %b) nounwind {
define i32 @and(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: and:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = and i32 %a, %b
ret i32 %1
Expand Down
6 changes: 0 additions & 6 deletions llvm/test/CodeGen/RISCV/analyze-branch.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -17,16 +17,13 @@ define void @test_bcc_fallthrough_taken(i32 %in) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: addi a1, zero, 42
; RV32I-NEXT: bne a0, a1, .LBB0_3
; RV32I-NEXT: # %bb.1: # %true
; RV32I-NEXT: lui a0, %hi(test_true)
; RV32I-NEXT: addi a0, a0, %lo(test_true)
; RV32I-NEXT: .LBB0_2: # %true
; RV32I-NEXT: jalr a0
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand Down Expand Up @@ -55,16 +52,13 @@ define void @test_bcc_fallthrough_nottaken(i32 %in) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: addi a1, zero, 42
; RV32I-NEXT: beq a0, a1, .LBB1_3
; RV32I-NEXT: # %bb.1: # %false
; RV32I-NEXT: lui a0, %hi(test_false)
; RV32I-NEXT: addi a0, a0, %lo(test_false)
; RV32I-NEXT: .LBB1_2: # %true
; RV32I-NEXT: jalr a0
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand Down
7 changes: 0 additions & 7 deletions llvm/test/CodeGen/RISCV/bare-select.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,19 +5,12 @@
define i32 @bare_select(i1 %a, i32 %b, i32 %c) {
; RV32I-LABEL: bare_select:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: bnez a0, .LBB0_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a1, a2
; RV32I-NEXT: .LBB0_2:
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = select i1 %a, i32 %b, i32 %c
ret i32 %1
Expand Down
3 changes: 0 additions & 3 deletions llvm/test/CodeGen/RISCV/blockaddress.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9,8 +9,6 @@ define void @test_blockaddress() nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a0, %hi(addr)
; RV32I-NEXT: addi a0, a0, %lo(addr)
; RV32I-NEXT: lui a1, %hi(.Ltmp0)
Expand All @@ -20,7 +18,6 @@ define void @test_blockaddress() nounwind {
; RV32I-NEXT: jr a0
; RV32I-NEXT: .Ltmp0: # Block address taken
; RV32I-NEXT: .LBB0_1: # %block
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand Down
20 changes: 3 additions & 17 deletions llvm/test/CodeGen/RISCV/branch-relaxation.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,10 +6,6 @@
define void @relax_bcc(i1 %a) {
; CHECK-LABEL: relax_bcc:
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw ra, 12(sp)
; CHECK-NEXT: sw s0, 8(sp)
; CHECK-NEXT: addi s0, sp, 16
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: bnez a0, .LBB0_1
; CHECK-NEXT: j .LBB0_2
Expand All @@ -18,9 +14,6 @@ define void @relax_bcc(i1 %a) {
; CHECK-NEXT: .space 4096
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB0_2: # %tail
; CHECK-NEXT: lw s0, 8(sp)
; CHECK-NEXT: lw ra, 12(sp)
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
br i1 %a, label %iftrue, label %tail

Expand All @@ -35,13 +28,9 @@ tail:
define i32 @relax_jal(i1 %a) {
; CHECK-LABEL: relax_jal:
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw ra, 12(sp)
; CHECK-NEXT: sw s0, 8(sp)
; CHECK-NEXT: addi s0, sp, 16
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: bnez a0, .LBB1_1
; CHECK-NEXT: # %bb.4:
; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: lui a0, %hi(.LBB1_2)
; CHECK-NEXT: jalr zero, a0, %lo(.LBB1_2)
; CHECK-NEXT: .LBB1_1: # %iftrue
Expand All @@ -50,15 +39,12 @@ define i32 @relax_jal(i1 %a) {
; CHECK-NEXT: #APP
; CHECK-NEXT: .space 1048576
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: j .LBB1_3
; CHECK-NEXT: addi a0, zero, 1
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB1_2: # %jmp
; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB1_3: # %tail
; CHECK-NEXT: addi a0, zero, 1
; CHECK-NEXT: lw s0, 8(sp)
; CHECK-NEXT: lw ra, 12(sp)
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
br i1 %a, label %iftrue, label %jmp

Expand Down
7 changes: 0 additions & 7 deletions llvm/test/CodeGen/RISCV/branch.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,10 +5,6 @@
define void @foo(i32 %a, i32 *%b, i1 %c) {
; RV32I-LABEL: foo:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lw a3, 0(a1)
; RV32I-NEXT: beq a3, a0, .LBB0_12
; RV32I-NEXT: # %bb.1: # %test2
Expand Down Expand Up @@ -45,9 +41,6 @@ define void @foo(i32 %a, i32 *%b, i1 %c) {
; RV32I-NEXT: # %bb.11: # %test12
; RV32I-NEXT: lw a0, 0(a1)
; RV32I-NEXT: .LBB0_12: # %end
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret

%val1 = load volatile i32, i32* %b
Expand Down
115 changes: 32 additions & 83 deletions llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,20 +15,13 @@ declare i32 @llvm.ctpop.i32(i32)
define i16 @test_bswap_i16(i16 %a) nounwind {
; RV32I-LABEL: test_bswap_i16:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a1, 4080
; RV32I-NEXT: mv a1, a1
; RV32I-NEXT: slli a2, a0, 8
; RV32I-NEXT: and a1, a2, a1
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: srli a0, a0, 16
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%tmp = call i16 @llvm.bswap.i16(i16 %a)
ret i16 %tmp
Expand All @@ -37,10 +30,6 @@ define i16 @test_bswap_i16(i16 %a) nounwind {
define i32 @test_bswap_i32(i32 %a) nounwind {
; RV32I-LABEL: test_bswap_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi a1, a1, -256
; RV32I-NEXT: srli a2, a0, 8
Expand All @@ -54,9 +43,6 @@ define i32 @test_bswap_i32(i32 %a) nounwind {
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%tmp = call i32 @llvm.bswap.i32(i32 %a)
ret i32 %tmp
Expand All @@ -65,10 +51,6 @@ define i32 @test_bswap_i32(i32 %a) nounwind {
define i64 @test_bswap_i64(i64 %a) nounwind {
; RV32I-LABEL: test_bswap_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a2, 16
; RV32I-NEXT: addi a3, a2, -256
; RV32I-NEXT: srli a2, a1, 8
Expand All @@ -92,9 +74,6 @@ define i64 @test_bswap_i64(i64 %a) nounwind {
; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: or a1, a0, a1
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%tmp = call i64 @llvm.bswap.i64(i64 %a)
ret i64 %tmp
Expand All @@ -105,8 +84,6 @@ define i8 @test_cttz_i8(i8 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: andi a1, a0, 255
; RV32I-NEXT: beqz a1, .LBB3_2
; RV32I-NEXT: # %bb.1: # %cond.false
Expand Down Expand Up @@ -139,7 +116,6 @@ define i8 @test_cttz_i8(i8 %a) nounwind {
; RV32I-NEXT: .LBB3_2:
; RV32I-NEXT: addi a0, zero, 8
; RV32I-NEXT: .LBB3_3: # %cond.end
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -152,8 +128,6 @@ define i16 @test_cttz_i16(i16 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: and a1, a0, a1
Expand Down Expand Up @@ -188,7 +162,6 @@ define i16 @test_cttz_i16(i16 %a) nounwind {
; RV32I-NEXT: .LBB4_2:
; RV32I-NEXT: addi a0, zero, 16
; RV32I-NEXT: .LBB4_3: # %cond.end
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -201,8 +174,6 @@ define i32 @test_cttz_i32(i32 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: beqz a0, .LBB5_2
; RV32I-NEXT: # %bb.1: # %cond.false
; RV32I-NEXT: addi a1, a0, -1
Expand Down Expand Up @@ -234,7 +205,6 @@ define i32 @test_cttz_i32(i32 %a) nounwind {
; RV32I-NEXT: .LBB5_2:
; RV32I-NEXT: addi a0, zero, 32
; RV32I-NEXT: .LBB5_3: # %cond.end
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -247,8 +217,6 @@ define i32 @test_ctlz_i32(i32 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: beqz a0, .LBB6_2
; RV32I-NEXT: # %bb.1: # %cond.false
; RV32I-NEXT: srli a1, a0, 1
Expand Down Expand Up @@ -288,7 +256,6 @@ define i32 @test_ctlz_i32(i32 %a) nounwind {
; RV32I-NEXT: .LBB6_2:
; RV32I-NEXT: addi a0, zero, 32
; RV32I-NEXT: .LBB6_3: # %cond.end
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -301,16 +268,14 @@ define i64 @test_cttz_i64(i64 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -48
; RV32I-NEXT: sw ra, 44(sp)
; RV32I-NEXT: sw s0, 40(sp)
; RV32I-NEXT: sw s1, 36(sp)
; RV32I-NEXT: sw s2, 32(sp)
; RV32I-NEXT: sw s3, 28(sp)
; RV32I-NEXT: sw s4, 24(sp)
; RV32I-NEXT: sw s5, 20(sp)
; RV32I-NEXT: sw s6, 16(sp)
; RV32I-NEXT: sw s7, 12(sp)
; RV32I-NEXT: sw s8, 8(sp)
; RV32I-NEXT: addi s0, sp, 48
; RV32I-NEXT: sw s1, 40(sp)
; RV32I-NEXT: sw s2, 36(sp)
; RV32I-NEXT: sw s3, 32(sp)
; RV32I-NEXT: sw s4, 28(sp)
; RV32I-NEXT: sw s5, 24(sp)
; RV32I-NEXT: sw s6, 20(sp)
; RV32I-NEXT: sw s7, 16(sp)
; RV32I-NEXT: sw s8, 12(sp)
; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: addi a0, s3, -1
Expand Down Expand Up @@ -363,15 +328,14 @@ define i64 @test_cttz_i64(i64 %a) nounwind {
; RV32I-NEXT: srli a0, s1, 24
; RV32I-NEXT: .LBB7_3:
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: lw s8, 8(sp)
; RV32I-NEXT: lw s7, 12(sp)
; RV32I-NEXT: lw s6, 16(sp)
; RV32I-NEXT: lw s5, 20(sp)
; RV32I-NEXT: lw s4, 24(sp)
; RV32I-NEXT: lw s3, 28(sp)
; RV32I-NEXT: lw s2, 32(sp)
; RV32I-NEXT: lw s1, 36(sp)
; RV32I-NEXT: lw s0, 40(sp)
; RV32I-NEXT: lw s8, 12(sp)
; RV32I-NEXT: lw s7, 16(sp)
; RV32I-NEXT: lw s6, 20(sp)
; RV32I-NEXT: lw s5, 24(sp)
; RV32I-NEXT: lw s4, 28(sp)
; RV32I-NEXT: lw s3, 32(sp)
; RV32I-NEXT: lw s2, 36(sp)
; RV32I-NEXT: lw s1, 40(sp)
; RV32I-NEXT: lw ra, 44(sp)
; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: ret
Expand All @@ -384,8 +348,6 @@ define i8 @test_cttz_i8_zero_undef(i8 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: not a0, a0
; RV32I-NEXT: and a0, a0, a1
Expand All @@ -411,7 +373,6 @@ define i8 @test_cttz_i8_zero_undef(i8 %a) nounwind {
; RV32I-NEXT: addi a2, a2, %lo(__mulsi3)
; RV32I-NEXT: jalr a2
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -424,8 +385,6 @@ define i16 @test_cttz_i16_zero_undef(i16 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: not a0, a0
; RV32I-NEXT: and a0, a0, a1
Expand All @@ -451,7 +410,6 @@ define i16 @test_cttz_i16_zero_undef(i16 %a) nounwind {
; RV32I-NEXT: addi a2, a2, %lo(__mulsi3)
; RV32I-NEXT: jalr a2
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -464,8 +422,6 @@ define i32 @test_cttz_i32_zero_undef(i32 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: not a0, a0
; RV32I-NEXT: and a0, a0, a1
Expand All @@ -491,7 +447,6 @@ define i32 @test_cttz_i32_zero_undef(i32 %a) nounwind {
; RV32I-NEXT: addi a2, a2, %lo(__mulsi3)
; RV32I-NEXT: jalr a2
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -504,16 +459,14 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -48
; RV32I-NEXT: sw ra, 44(sp)
; RV32I-NEXT: sw s0, 40(sp)
; RV32I-NEXT: sw s1, 36(sp)
; RV32I-NEXT: sw s2, 32(sp)
; RV32I-NEXT: sw s3, 28(sp)
; RV32I-NEXT: sw s4, 24(sp)
; RV32I-NEXT: sw s5, 20(sp)
; RV32I-NEXT: sw s6, 16(sp)
; RV32I-NEXT: sw s7, 12(sp)
; RV32I-NEXT: sw s8, 8(sp)
; RV32I-NEXT: addi s0, sp, 48
; RV32I-NEXT: sw s1, 40(sp)
; RV32I-NEXT: sw s2, 36(sp)
; RV32I-NEXT: sw s3, 32(sp)
; RV32I-NEXT: sw s4, 28(sp)
; RV32I-NEXT: sw s5, 24(sp)
; RV32I-NEXT: sw s6, 20(sp)
; RV32I-NEXT: sw s7, 16(sp)
; RV32I-NEXT: sw s8, 12(sp)
; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: addi a0, s3, -1
Expand Down Expand Up @@ -566,15 +519,14 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
; RV32I-NEXT: srli a0, s1, 24
; RV32I-NEXT: .LBB11_3:
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: lw s8, 8(sp)
; RV32I-NEXT: lw s7, 12(sp)
; RV32I-NEXT: lw s6, 16(sp)
; RV32I-NEXT: lw s5, 20(sp)
; RV32I-NEXT: lw s4, 24(sp)
; RV32I-NEXT: lw s3, 28(sp)
; RV32I-NEXT: lw s2, 32(sp)
; RV32I-NEXT: lw s1, 36(sp)
; RV32I-NEXT: lw s0, 40(sp)
; RV32I-NEXT: lw s8, 12(sp)
; RV32I-NEXT: lw s7, 16(sp)
; RV32I-NEXT: lw s6, 20(sp)
; RV32I-NEXT: lw s5, 24(sp)
; RV32I-NEXT: lw s4, 28(sp)
; RV32I-NEXT: lw s3, 32(sp)
; RV32I-NEXT: lw s2, 36(sp)
; RV32I-NEXT: lw s1, 40(sp)
; RV32I-NEXT: lw ra, 44(sp)
; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: ret
Expand All @@ -587,8 +539,6 @@ define i32 @test_ctpop_i32(i32 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a1, 349525
; RV32I-NEXT: addi a1, a1, 1365
; RV32I-NEXT: srli a2, a0, 1
Expand All @@ -611,7 +561,6 @@ define i32 @test_ctpop_i32(i32 %a) nounwind {
; RV32I-NEXT: addi a2, a2, %lo(__mulsi3)
; RV32I-NEXT: jalr a2
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand Down
20 changes: 5 additions & 15 deletions llvm/test/CodeGen/RISCV/byval.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,14 +8,7 @@
define i32 @callee(%struct.Foo* byval %f) nounwind {
; RV32I-LABEL: callee:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lw a0, 0(a0)
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
entry:
%0 = getelementptr inbounds %struct.Foo, %struct.Foo* %f, i32 0, i32 0
Expand All @@ -29,29 +22,26 @@ define void @caller() nounwind {
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: addi s0, sp, 32
; RV32I-NEXT: lui a0, %hi(foo+12)
; RV32I-NEXT: addi a0, a0, %lo(foo+12)
; RV32I-NEXT: lw a0, 0(a0)
; RV32I-NEXT: sw a0, -12(s0)
; RV32I-NEXT: sw a0, 24(sp)
; RV32I-NEXT: lui a0, %hi(foo+8)
; RV32I-NEXT: addi a0, a0, %lo(foo+8)
; RV32I-NEXT: lw a0, 0(a0)
; RV32I-NEXT: sw a0, -16(s0)
; RV32I-NEXT: sw a0, 20(sp)
; RV32I-NEXT: lui a0, %hi(foo+4)
; RV32I-NEXT: addi a0, a0, %lo(foo+4)
; RV32I-NEXT: lw a0, 0(a0)
; RV32I-NEXT: sw a0, -20(s0)
; RV32I-NEXT: sw a0, 16(sp)
; RV32I-NEXT: lui a0, %hi(foo)
; RV32I-NEXT: addi a0, a0, %lo(foo)
; RV32I-NEXT: lw a0, 0(a0)
; RV32I-NEXT: sw a0, -24(s0)
; RV32I-NEXT: sw a0, 12(sp)
; RV32I-NEXT: lui a0, %hi(callee)
; RV32I-NEXT: addi a1, a0, %lo(callee)
; RV32I-NEXT: addi a0, s0, -24
; RV32I-NEXT: addi a0, sp, 12
; RV32I-NEXT: jalr a1
; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
Expand Down
117 changes: 0 additions & 117 deletions llvm/test/CodeGen/RISCV/calling-conv-sext-zext.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,13 +5,6 @@
define zeroext i8 @uint8_arg_to_uint8_ret(i8 zeroext %a) nounwind {
; RV32I-LABEL: uint8_arg_to_uint8_ret:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
ret i8 %a
}
Expand All @@ -23,12 +16,9 @@ define void @pass_uint8_as_uint8(i8 zeroext %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a1, %hi(receive_uint8)
; RV32I-NEXT: addi a1, a1, %lo(receive_uint8)
; RV32I-NEXT: jalr a1
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -43,12 +33,9 @@ define zeroext i8 @ret_callresult_uint8_as_uint8() nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a0, %hi(return_uint8)
; RV32I-NEXT: addi a0, a0, %lo(return_uint8)
; RV32I-NEXT: jalr a0
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -59,15 +46,8 @@ define zeroext i8 @ret_callresult_uint8_as_uint8() nounwind {
define signext i8 @uint8_arg_to_sint8_ret(i8 zeroext %a) nounwind {
; RV32I-LABEL: uint8_arg_to_sint8_ret:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
ret i8 %a
}
Expand All @@ -79,14 +59,11 @@ define void @pass_uint8_as_sint8(i8 zeroext %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a1, %hi(receive_sint8)
; RV32I-NEXT: addi a1, a1, %lo(receive_sint8)
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: jalr a1
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -100,14 +77,11 @@ define signext i8 @ret_callresult_uint8_as_sint8() nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a0, %hi(return_uint8)
; RV32I-NEXT: addi a0, a0, %lo(return_uint8)
; RV32I-NEXT: jalr a0
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -118,13 +92,6 @@ define signext i8 @ret_callresult_uint8_as_sint8() nounwind {
define signext i32 @uint8_arg_to_anyint32_ret(i8 zeroext %a) nounwind {
; RV32I-LABEL: uint8_arg_to_anyint32_ret:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = zext i8 %a to i32
ret i32 %1
Expand All @@ -137,12 +104,9 @@ define void @pass_uint8_as_anyint32(i8 zeroext %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a1, %hi(receive_anyint32)
; RV32I-NEXT: addi a1, a1, %lo(receive_anyint32)
; RV32I-NEXT: jalr a1
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -156,12 +120,9 @@ define signext i32 @ret_callresult_uint8_as_anyint32() nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a0, %hi(return_uint8)
; RV32I-NEXT: addi a0, a0, %lo(return_uint8)
; RV32I-NEXT: jalr a0
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -173,14 +134,7 @@ define signext i32 @ret_callresult_uint8_as_anyint32() nounwind {
define zeroext i8 @sint8_arg_to_uint8_ret(i8 signext %a) nounwind {
; RV32I-LABEL: sint8_arg_to_uint8_ret:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: andi a0, a0, 255
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
ret i8 %a
}
Expand All @@ -190,13 +144,10 @@ define void @pass_sint8_as_uint8(i8 signext %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: andi a0, a0, 255
; RV32I-NEXT: lui a1, %hi(receive_uint8)
; RV32I-NEXT: addi a1, a1, %lo(receive_uint8)
; RV32I-NEXT: jalr a1
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -211,13 +162,10 @@ define zeroext i8 @ret_callresult_sint8_as_uint8() nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a0, %hi(return_sint8)
; RV32I-NEXT: addi a0, a0, %lo(return_sint8)
; RV32I-NEXT: jalr a0
; RV32I-NEXT: andi a0, a0, 255
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -228,13 +176,6 @@ define zeroext i8 @ret_callresult_sint8_as_uint8() nounwind {
define signext i8 @sint8_arg_to_sint8_ret(i8 signext %a) nounwind {
; RV32I-LABEL: sint8_arg_to_sint8_ret:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
ret i8 %a
}
Expand All @@ -244,12 +185,9 @@ define void @pass_sint8_as_sint8(i8 signext %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a1, %hi(receive_sint8)
; RV32I-NEXT: addi a1, a1, %lo(receive_sint8)
; RV32I-NEXT: jalr a1
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -262,12 +200,9 @@ define signext i8 @ret_callresult_sint8_as_sint8() nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a0, %hi(return_sint8)
; RV32I-NEXT: addi a0, a0, %lo(return_sint8)
; RV32I-NEXT: jalr a0
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -278,13 +213,6 @@ define signext i8 @ret_callresult_sint8_as_sint8() nounwind {
define signext i32 @sint8_arg_to_anyint32_ret(i8 signext %a) nounwind {
; RV32I-LABEL: sint8_arg_to_anyint32_ret:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = sext i8 %a to i32
ret i32 %1
Expand All @@ -295,12 +223,9 @@ define void @pass_sint8_as_anyint32(i8 signext %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a1, %hi(receive_anyint32)
; RV32I-NEXT: addi a1, a1, %lo(receive_anyint32)
; RV32I-NEXT: jalr a1
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -314,12 +239,9 @@ define signext i32 @ret_callresult_sint8_as_anyint32() nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a0, %hi(return_sint8)
; RV32I-NEXT: addi a0, a0, %lo(return_sint8)
; RV32I-NEXT: jalr a0
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -331,14 +253,7 @@ define signext i32 @ret_callresult_sint8_as_anyint32() nounwind {
define zeroext i8 @anyint32_arg_to_uint8_ret(i32 signext %a) nounwind {
; RV32I-LABEL: anyint32_arg_to_uint8_ret:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: andi a0, a0, 255
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = trunc i32 %a to i8
ret i8 %1
Expand All @@ -349,13 +264,10 @@ define void @pass_anyint32_as_uint8(i32 signext %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: andi a0, a0, 255
; RV32I-NEXT: lui a1, %hi(receive_uint8)
; RV32I-NEXT: addi a1, a1, %lo(receive_uint8)
; RV32I-NEXT: jalr a1
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -371,13 +283,10 @@ define zeroext i8 @ret_callresult_anyint32_as_uint8() nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a0, %hi(return_anyint32)
; RV32I-NEXT: addi a0, a0, %lo(return_anyint32)
; RV32I-NEXT: jalr a0
; RV32I-NEXT: andi a0, a0, 255
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -389,15 +298,8 @@ define zeroext i8 @ret_callresult_anyint32_as_uint8() nounwind {
define signext i8 @anyint32_arg_to_sint8_ret(i32 signext %a) nounwind {
; RV32I-LABEL: anyint32_arg_to_sint8_ret:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = trunc i32 %a to i8
ret i8 %1
Expand All @@ -408,14 +310,11 @@ define void @pass_anyint32_as_sint8(i32 signext %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a1, %hi(receive_sint8)
; RV32I-NEXT: addi a1, a1, %lo(receive_sint8)
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: jalr a1
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -429,14 +328,11 @@ define signext i8 @ret_callresult_anyint32_as_sint8() nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a0, %hi(return_anyint32)
; RV32I-NEXT: addi a0, a0, %lo(return_anyint32)
; RV32I-NEXT: jalr a0
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -448,13 +344,6 @@ define signext i8 @ret_callresult_anyint32_as_sint8() nounwind {
define signext i32 @anyint32_arg_to_anyint32_ret(i32 signext %a) nounwind {
; RV32I-LABEL: anyint32_arg_to_anyint32_ret:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
ret i32 %a
}
Expand All @@ -464,12 +353,9 @@ define void @pass_anyint32_as_anyint32(i32 signext %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a1, %hi(receive_anyint32)
; RV32I-NEXT: addi a1, a1, %lo(receive_anyint32)
; RV32I-NEXT: jalr a1
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -482,12 +368,9 @@ define signext i32 @ret_callresult_anyint32_as_anyint32() nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a0, %hi(return_anyint32)
; RV32I-NEXT: addi a0, a0, %lo(return_anyint32)
; RV32I-NEXT: jalr a0
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand Down
1,409 changes: 911 additions & 498 deletions llvm/test/CodeGen/RISCV/calling-conv.ll
View file

Large diffs are not rendered by default.

65 changes: 13 additions & 52 deletions llvm/test/CodeGen/RISCV/calls.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9,12 +9,9 @@ define i32 @test_call_external(i32 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a1, %hi(external_function)
; RV32I-NEXT: addi a1, a1, %lo(external_function)
; RV32I-NEXT: jalr a1
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -25,14 +22,7 @@ define i32 @test_call_external(i32 %a) nounwind {
define i32 @defined_function(i32 %a) nounwind {
; RV32I-LABEL: defined_function:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: addi a0, a0, 1
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = add i32 %a, 1
ret i32 %1
Expand All @@ -43,12 +33,9 @@ define i32 @test_call_defined(i32 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a1, %hi(defined_function)
; RV32I-NEXT: addi a1, a1, %lo(defined_function)
; RV32I-NEXT: jalr a1
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -61,12 +48,9 @@ define i32 @test_call_indirect(i32 (i32)* %a, i32 %b) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: mv a2, a0
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: jalr a2
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -80,14 +64,7 @@ define i32 @test_call_indirect(i32 (i32)* %a, i32 %b) nounwind {
define fastcc i32 @fastcc_function(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: fastcc_function:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = add i32 %a, %b
ret i32 %1
Expand All @@ -98,17 +75,14 @@ define i32 @test_call_fastcc(i32 %a, i32 %b) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: sw s1, 4(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: sw s1, 8(sp)
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lui a0, %hi(fastcc_function)
; RV32I-NEXT: addi a2, a0, %lo(fastcc_function)
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: jalr a2
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: lw s1, 4(sp)
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw s1, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -121,11 +95,9 @@ declare i32 @external_many_args(i32, i32, i32, i32, i32, i32, i32, i32, i32, i32
define i32 @test_call_external_many_args(i32 %a) nounwind {
; RV32I-LABEL: test_call_external_many_args:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: addi s0, sp, 32
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s1, 8(sp)
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: sw s1, 4(sp)
; RV32I-NEXT: sw s1, 0(sp)
Expand All @@ -141,10 +113,9 @@ define i32 @test_call_external_many_args(i32 %a) nounwind {
; RV32I-NEXT: mv a7, s1
; RV32I-NEXT: jalr t0
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: lw s1, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = call i32 @external_many_args(i32 %a, i32 %a, i32 %a, i32 %a, i32 %a,
i32 %a, i32 %a, i32 %a, i32 %a, i32 %a)
Expand All @@ -154,15 +125,8 @@ define i32 @test_call_external_many_args(i32 %a) nounwind {
define i32 @defined_many_args(i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 %j) nounwind {
; RV32I-LABEL: defined_many_args:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lw a0, 4(s0)
; RV32I-NEXT: lw a0, 4(sp)
; RV32I-NEXT: addi a0, a0, 1
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%added = add i32 %j, 1
ret i32 %added
Expand All @@ -171,10 +135,8 @@ define i32 @defined_many_args(i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 %
define i32 @test_call_defined_many_args(i32 %a) nounwind {
; RV32I-LABEL: test_call_defined_many_args:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: addi s0, sp, 32
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw a0, 4(sp)
; RV32I-NEXT: sw a0, 0(sp)
; RV32I-NEXT: lui a1, %hi(defined_many_args)
Expand All @@ -187,9 +149,8 @@ define i32 @test_call_defined_many_args(i32 %a) nounwind {
; RV32I-NEXT: mv a6, a0
; RV32I-NEXT: mv a7, a0
; RV32I-NEXT: jalr t0
; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = call i32 @defined_many_args(i32 %a, i32 %a, i32 %a, i32 %a, i32 %a,
i32 %a, i32 %a, i32 %a, i32 %a, i32 %a)
Expand Down
38 changes: 0 additions & 38 deletions llvm/test/CodeGen/RISCV/div.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,12 +7,9 @@ define i32 @udiv(i32 %a, i32 %b) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a2, %hi(__udivsi3)
; RV32I-NEXT: addi a2, a2, %lo(__udivsi3)
; RV32I-NEXT: jalr a2
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -25,13 +22,10 @@ define i32 @udiv_constant(i32 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a1, %hi(__udivsi3)
; RV32I-NEXT: addi a2, a1, %lo(__udivsi3)
; RV32I-NEXT: addi a1, zero, 5
; RV32I-NEXT: jalr a2
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -42,14 +36,7 @@ define i32 @udiv_constant(i32 %a) nounwind {
define i32 @udiv_pow2(i32 %a) nounwind {
; RV32I-LABEL: udiv_pow2:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: srli a0, a0, 3
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = udiv i32 %a, 8
ret i32 %1
Expand All @@ -60,12 +47,9 @@ define i64 @udiv64(i64 %a, i64 %b) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a4, %hi(__udivdi3)
; RV32I-NEXT: addi a4, a4, %lo(__udivdi3)
; RV32I-NEXT: jalr a4
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -78,14 +62,11 @@ define i64 @udiv64_constant(i64 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a2, %hi(__udivdi3)
; RV32I-NEXT: addi a4, a2, %lo(__udivdi3)
; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: jalr a4
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -98,12 +79,9 @@ define i32 @sdiv(i32 %a, i32 %b) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a2, %hi(__divsi3)
; RV32I-NEXT: addi a2, a2, %lo(__divsi3)
; RV32I-NEXT: jalr a2
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -116,13 +94,10 @@ define i32 @sdiv_constant(i32 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a1, %hi(__divsi3)
; RV32I-NEXT: addi a2, a1, %lo(__divsi3)
; RV32I-NEXT: addi a1, zero, 5
; RV32I-NEXT: jalr a2
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -133,17 +108,10 @@ define i32 @sdiv_constant(i32 %a) nounwind {
define i32 @sdiv_pow2(i32 %a) nounwind {
; RV32I-LABEL: sdiv_pow2:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: srai a1, a0, 31
; RV32I-NEXT: srli a1, a1, 29
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: srai a0, a0, 3
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = sdiv i32 %a, 8
ret i32 %1
Expand All @@ -154,12 +122,9 @@ define i64 @sdiv64(i64 %a, i64 %b) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a4, %hi(__divdi3)
; RV32I-NEXT: addi a4, a4, %lo(__divdi3)
; RV32I-NEXT: jalr a4
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -172,14 +137,11 @@ define i64 @sdiv64_constant(i64 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a2, %hi(__divdi3)
; RV32I-NEXT: addi a4, a2, %lo(__divdi3)
; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: jalr a4
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand Down
66 changes: 30 additions & 36 deletions llvm/test/CodeGen/RISCV/fp128.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,48 +13,45 @@ define i32 @test_load_and_cmp() nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -48
; RV32I-NEXT: sw ra, 44(sp)
; RV32I-NEXT: sw s0, 40(sp)
; RV32I-NEXT: addi s0, sp, 48
; RV32I-NEXT: lui a0, %hi(y+12)
; RV32I-NEXT: addi a0, a0, %lo(y+12)
; RV32I-NEXT: lw a0, 0(a0)
; RV32I-NEXT: sw a0, -28(s0)
; RV32I-NEXT: sw a0, 20(sp)
; RV32I-NEXT: lui a0, %hi(y+8)
; RV32I-NEXT: addi a0, a0, %lo(y+8)
; RV32I-NEXT: lw a0, 0(a0)
; RV32I-NEXT: sw a0, -32(s0)
; RV32I-NEXT: sw a0, 16(sp)
; RV32I-NEXT: lui a0, %hi(y+4)
; RV32I-NEXT: addi a0, a0, %lo(y+4)
; RV32I-NEXT: lw a0, 0(a0)
; RV32I-NEXT: sw a0, -36(s0)
; RV32I-NEXT: sw a0, 12(sp)
; RV32I-NEXT: lui a0, %hi(y)
; RV32I-NEXT: addi a0, a0, %lo(y)
; RV32I-NEXT: lw a0, 0(a0)
; RV32I-NEXT: sw a0, -40(s0)
; RV32I-NEXT: sw a0, 8(sp)
; RV32I-NEXT: lui a0, %hi(x+12)
; RV32I-NEXT: addi a0, a0, %lo(x+12)
; RV32I-NEXT: lw a0, 0(a0)
; RV32I-NEXT: sw a0, -12(s0)
; RV32I-NEXT: sw a0, 36(sp)
; RV32I-NEXT: lui a0, %hi(x+8)
; RV32I-NEXT: addi a0, a0, %lo(x+8)
; RV32I-NEXT: lw a0, 0(a0)
; RV32I-NEXT: sw a0, -16(s0)
; RV32I-NEXT: sw a0, 32(sp)
; RV32I-NEXT: lui a0, %hi(x+4)
; RV32I-NEXT: addi a0, a0, %lo(x+4)
; RV32I-NEXT: lw a0, 0(a0)
; RV32I-NEXT: sw a0, -20(s0)
; RV32I-NEXT: sw a0, 28(sp)
; RV32I-NEXT: lui a0, %hi(x)
; RV32I-NEXT: addi a0, a0, %lo(x)
; RV32I-NEXT: lw a0, 0(a0)
; RV32I-NEXT: sw a0, -24(s0)
; RV32I-NEXT: sw a0, 24(sp)
; RV32I-NEXT: lui a0, %hi(__netf2)
; RV32I-NEXT: addi a2, a0, %lo(__netf2)
; RV32I-NEXT: addi a0, s0, -24
; RV32I-NEXT: addi a1, s0, -40
; RV32I-NEXT: addi a0, sp, 24
; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: jalr a2
; RV32I-NEXT: xor a0, a0, zero
; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: lw s0, 40(sp)
; RV32I-NEXT: lw ra, 44(sp)
; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: ret
Expand All @@ -70,59 +67,56 @@ define i32 @test_add_and_fptosi() nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -80
; RV32I-NEXT: sw ra, 76(sp)
; RV32I-NEXT: sw s0, 72(sp)
; RV32I-NEXT: addi s0, sp, 80
; RV32I-NEXT: lui a0, %hi(y+12)
; RV32I-NEXT: addi a0, a0, %lo(y+12)
; RV32I-NEXT: lw a0, 0(a0)
; RV32I-NEXT: sw a0, -44(s0)
; RV32I-NEXT: sw a0, 36(sp)
; RV32I-NEXT: lui a0, %hi(y+8)
; RV32I-NEXT: addi a0, a0, %lo(y+8)
; RV32I-NEXT: lw a0, 0(a0)
; RV32I-NEXT: sw a0, -48(s0)
; RV32I-NEXT: sw a0, 32(sp)
; RV32I-NEXT: lui a0, %hi(y+4)
; RV32I-NEXT: addi a0, a0, %lo(y+4)
; RV32I-NEXT: lw a0, 0(a0)
; RV32I-NEXT: sw a0, -52(s0)
; RV32I-NEXT: sw a0, 28(sp)
; RV32I-NEXT: lui a0, %hi(y)
; RV32I-NEXT: addi a0, a0, %lo(y)
; RV32I-NEXT: lw a0, 0(a0)
; RV32I-NEXT: sw a0, -56(s0)
; RV32I-NEXT: sw a0, 24(sp)
; RV32I-NEXT: lui a0, %hi(x+12)
; RV32I-NEXT: addi a0, a0, %lo(x+12)
; RV32I-NEXT: lw a0, 0(a0)
; RV32I-NEXT: sw a0, -28(s0)
; RV32I-NEXT: sw a0, 52(sp)
; RV32I-NEXT: lui a0, %hi(x+8)
; RV32I-NEXT: addi a0, a0, %lo(x+8)
; RV32I-NEXT: lw a0, 0(a0)
; RV32I-NEXT: sw a0, -32(s0)
; RV32I-NEXT: sw a0, 48(sp)
; RV32I-NEXT: lui a0, %hi(x+4)
; RV32I-NEXT: addi a0, a0, %lo(x+4)
; RV32I-NEXT: lw a0, 0(a0)
; RV32I-NEXT: sw a0, -36(s0)
; RV32I-NEXT: sw a0, 44(sp)
; RV32I-NEXT: lui a0, %hi(x)
; RV32I-NEXT: addi a0, a0, %lo(x)
; RV32I-NEXT: lw a0, 0(a0)
; RV32I-NEXT: sw a0, -40(s0)
; RV32I-NEXT: sw a0, 40(sp)
; RV32I-NEXT: lui a0, %hi(__addtf3)
; RV32I-NEXT: addi a3, a0, %lo(__addtf3)
; RV32I-NEXT: addi a0, s0, -24
; RV32I-NEXT: addi a1, s0, -40
; RV32I-NEXT: addi a2, s0, -56
; RV32I-NEXT: addi a0, sp, 56
; RV32I-NEXT: addi a1, sp, 40
; RV32I-NEXT: addi a2, sp, 24
; RV32I-NEXT: jalr a3
; RV32I-NEXT: lw a0, -12(s0)
; RV32I-NEXT: sw a0, -60(s0)
; RV32I-NEXT: lw a0, -16(s0)
; RV32I-NEXT: sw a0, -64(s0)
; RV32I-NEXT: lw a0, -20(s0)
; RV32I-NEXT: sw a0, -68(s0)
; RV32I-NEXT: lw a0, -24(s0)
; RV32I-NEXT: sw a0, -72(s0)
; RV32I-NEXT: lw a0, 68(sp)
; RV32I-NEXT: sw a0, 20(sp)
; RV32I-NEXT: lw a0, 64(sp)
; RV32I-NEXT: sw a0, 16(sp)
; RV32I-NEXT: lw a0, 60(sp)
; RV32I-NEXT: sw a0, 12(sp)
; RV32I-NEXT: lw a0, 56(sp)
; RV32I-NEXT: sw a0, 8(sp)
; RV32I-NEXT: lui a0, %hi(__fixtfsi)
; RV32I-NEXT: addi a1, a0, %lo(__fixtfsi)
; RV32I-NEXT: addi a0, s0, -72
; RV32I-NEXT: addi a0, sp, 8
; RV32I-NEXT: jalr a1
; RV32I-NEXT: lw s0, 72(sp)
; RV32I-NEXT: lw ra, 76(sp)
; RV32I-NEXT: addi sp, sp, 80
; RV32I-NEXT: ret
Expand Down
62 changes: 41 additions & 21 deletions llvm/test/CodeGen/RISCV/frame.ll
View file
Original file line number Diff line number Diff line change
@@ -1,30 +1,50 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: | FileCheck -check-prefix=RV32I-FPELIM %s
; RUN: llc -mtriple=riscv32 -disable-fp-elim -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I-WITHFP %s

%struct.key_t = type { i32, [16 x i8] }

define i32 @test() nounwind {
; RV32I-LABEL: test:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: addi s0, sp, 32
; RV32I-NEXT: sw zero, -16(s0)
; RV32I-NEXT: sw zero, -20(s0)
; RV32I-NEXT: sw zero, -24(s0)
; RV32I-NEXT: sw zero, -28(s0)
; RV32I-NEXT: sw zero, -32(s0)
; RV32I-NEXT: lui a0, %hi(test1)
; RV32I-NEXT: addi a1, a0, %lo(test1)
; RV32I-NEXT: addi a0, s0, -28
; RV32I-NEXT: jalr a1
; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
; RV32I-FPELIM-LABEL: test:
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -32
; RV32I-FPELIM-NEXT: sw ra, 28(sp)
; RV32I-FPELIM-NEXT: sw zero, 24(sp)
; RV32I-FPELIM-NEXT: sw zero, 20(sp)
; RV32I-FPELIM-NEXT: sw zero, 16(sp)
; RV32I-FPELIM-NEXT: sw zero, 12(sp)
; RV32I-FPELIM-NEXT: sw zero, 8(sp)
; RV32I-FPELIM-NEXT: lui a0, %hi(test1)
; RV32I-FPELIM-NEXT: addi a1, a0, %lo(test1)
; RV32I-FPELIM-NEXT: addi a0, sp, 12
; RV32I-FPELIM-NEXT: jalr a1
; RV32I-FPELIM-NEXT: mv a0, zero
; RV32I-FPELIM-NEXT: lw ra, 28(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 32
; RV32I-FPELIM-NEXT: ret
;
; RV32I-WITHFP-LABEL: test:
; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -32
; RV32I-WITHFP-NEXT: sw ra, 28(sp)
; RV32I-WITHFP-NEXT: sw s0, 24(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 32
; RV32I-WITHFP-NEXT: sw zero, -16(s0)
; RV32I-WITHFP-NEXT: sw zero, -20(s0)
; RV32I-WITHFP-NEXT: sw zero, -24(s0)
; RV32I-WITHFP-NEXT: sw zero, -28(s0)
; RV32I-WITHFP-NEXT: sw zero, -32(s0)
; RV32I-WITHFP-NEXT: lui a0, %hi(test1)
; RV32I-WITHFP-NEXT: addi a1, a0, %lo(test1)
; RV32I-WITHFP-NEXT: addi a0, s0, -28
; RV32I-WITHFP-NEXT: jalr a1
; RV32I-WITHFP-NEXT: mv a0, zero
; RV32I-WITHFP-NEXT: lw s0, 24(sp)
; RV32I-WITHFP-NEXT: lw ra, 28(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 32
; RV32I-WITHFP-NEXT: ret
%key = alloca %struct.key_t, align 4
%1 = bitcast %struct.key_t* %key to i8*
call void @llvm.memset.p0i8.i64(i8* %1, i8 0, i64 20, i32 4, i1 false)
Expand Down
7 changes: 0 additions & 7 deletions llvm/test/CodeGen/RISCV/frameaddr-returnaddr.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -67,14 +67,7 @@ define i8* @test_frameaddress_3_alloca() nounwind {
define i8* @test_returnaddress_0() nounwind {
; RV32I-LABEL: test_returnaddress_0:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: mv a0, ra
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = call i8* @llvm.returnaddress(i32 0)
ret i8* %1
Expand Down
70 changes: 0 additions & 70 deletions llvm/test/CodeGen/RISCV/i32-icmp.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,15 +8,8 @@
define i32 @icmp_eq(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_eq:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = icmp eq i32 %a, %b
%2 = zext i1 %1 to i32
Expand All @@ -26,15 +19,8 @@ define i32 @icmp_eq(i32 %a, i32 %b) nounwind {
define i32 @icmp_ne(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_ne:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = icmp ne i32 %a, %b
%2 = zext i1 %1 to i32
Expand All @@ -44,14 +30,7 @@ define i32 @icmp_ne(i32 %a, i32 %b) nounwind {
define i32 @icmp_ugt(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_ugt:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: sltu a0, a1, a0
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = icmp ugt i32 %a, %b
%2 = zext i1 %1 to i32
Expand All @@ -61,15 +40,8 @@ define i32 @icmp_ugt(i32 %a, i32 %b) nounwind {
define i32 @icmp_uge(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_uge:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: sltu a0, a0, a1
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = icmp uge i32 %a, %b
%2 = zext i1 %1 to i32
Expand All @@ -79,14 +51,7 @@ define i32 @icmp_uge(i32 %a, i32 %b) nounwind {
define i32 @icmp_ult(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_ult:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: sltu a0, a0, a1
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = icmp ult i32 %a, %b
%2 = zext i1 %1 to i32
Expand All @@ -96,15 +61,8 @@ define i32 @icmp_ult(i32 %a, i32 %b) nounwind {
define i32 @icmp_ule(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_ule:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: sltu a0, a1, a0
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = icmp ule i32 %a, %b
%2 = zext i1 %1 to i32
Expand All @@ -114,14 +72,7 @@ define i32 @icmp_ule(i32 %a, i32 %b) nounwind {
define i32 @icmp_sgt(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_sgt:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: slt a0, a1, a0
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = icmp sgt i32 %a, %b
%2 = zext i1 %1 to i32
Expand All @@ -131,15 +82,8 @@ define i32 @icmp_sgt(i32 %a, i32 %b) nounwind {
define i32 @icmp_sge(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_sge:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: slt a0, a0, a1
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = icmp sge i32 %a, %b
%2 = zext i1 %1 to i32
Expand All @@ -149,14 +93,7 @@ define i32 @icmp_sge(i32 %a, i32 %b) nounwind {
define i32 @icmp_slt(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_slt:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: slt a0, a0, a1
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = icmp slt i32 %a, %b
%2 = zext i1 %1 to i32
Expand All @@ -166,15 +103,8 @@ define i32 @icmp_slt(i32 %a, i32 %b) nounwind {
define i32 @icmp_sle(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_sle:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: slt a0, a1, a0
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = icmp sle i32 %a, %b
%2 = zext i1 %1 to i32
Expand Down
35 changes: 0 additions & 35 deletions llvm/test/CodeGen/RISCV/imm.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,76 +7,41 @@
define i32 @zero() nounwind {
; RV32I-LABEL: zero:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
ret i32 0
}

define i32 @pos_small() nounwind {
; RV32I-LABEL: pos_small:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: addi a0, zero, 2047
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
ret i32 2047
}

define i32 @neg_small() nounwind {
; RV32I-LABEL: neg_small:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: addi a0, zero, -2048
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
ret i32 -2048
}

define i32 @pos_i32() nounwind {
; RV32I-LABEL: pos_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a0, 423811
; RV32I-NEXT: addi a0, a0, -1297
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
ret i32 1735928559
}

define i32 @neg_i32() nounwind {
; RV32I-LABEL: neg_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a0, 912092
; RV32I-NEXT: addi a0, a0, -273
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
ret i32 -559038737
}
6 changes: 0 additions & 6 deletions llvm/test/CodeGen/RISCV/indirectbr.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,12 +7,9 @@ define i32 @indirectbr(i8* %target) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: jr a0
; RV32I-NEXT: .LBB0_1: # %ret
; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -28,12 +25,9 @@ define i32 @indirectbr_with_offset(i8* %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: jalr zero, a0, 1380
; RV32I-NEXT: .LBB1_1: # %ret
; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand Down
28 changes: 0 additions & 28 deletions llvm/test/CodeGen/RISCV/inline-asm.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,19 +7,12 @@
define i32 @constraint_r(i32 %a) {
; RV32I-LABEL: constraint_r:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a1, %hi(gi)
; RV32I-NEXT: addi a1, a1, %lo(gi)
; RV32I-NEXT: lw a1, 0(a1)
; RV32I-NEXT: #APP
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: #NO_APP
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = load i32, i32* @gi
%2 = tail call i32 asm "add $0, $1, $2", "=r,r,r"(i32 %a, i32 %1)
Expand All @@ -29,16 +22,9 @@ define i32 @constraint_r(i32 %a) {
define i32 @constraint_i(i32 %a) {
; RV32I-LABEL: constraint_i:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, a0, 113
; RV32I-NEXT: #NO_APP
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = load i32, i32* @gi
%2 = tail call i32 asm "addi $0, $1, $2", "=r,r,i"(i32 %a, i32 113)
Expand All @@ -48,15 +34,8 @@ define i32 @constraint_i(i32 %a) {
define void @constraint_m(i32* %a) {
; RV32I-LABEL: constraint_m:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: #APP
; RV32I-NEXT: #NO_APP
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
call void asm sideeffect "", "=*m"(i32* %a)
ret void
Expand All @@ -65,16 +44,9 @@ define void @constraint_m(i32* %a) {
define i32 @constraint_m2(i32* %a) {
; RV32I-LABEL: constraint_m2:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: #APP
; RV32I-NEXT: lw a0, 0(a0)
; RV32I-NEXT: #NO_APP
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = tail call i32 asm "lw $0, $1", "=r,*m"(i32* %a) nounwind
ret i32 %1
Expand Down
13 changes: 3 additions & 10 deletions llvm/test/CodeGen/RISCV/jumptable.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,10 +5,6 @@
define void @jt(i32 %in, i32* %out) {
; RV32I-LABEL: jt:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: blt a2, a0, .LBB0_4
; RV32I-NEXT: # %bb.1: # %entry
Expand All @@ -19,7 +15,7 @@ define void @jt(i32 %in, i32* %out) {
; RV32I-NEXT: # %bb.3: # %bb2
; RV32I-NEXT: addi a0, zero, 3
; RV32I-NEXT: sw a0, 0(a1)
; RV32I-NEXT: j .LBB0_9
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB0_4: # %entry
; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: beq a0, a3, .LBB0_8
Expand All @@ -29,17 +25,14 @@ define void @jt(i32 %in, i32* %out) {
; RV32I-NEXT: # %bb.6: # %bb4
; RV32I-NEXT: addi a0, zero, 1
; RV32I-NEXT: sw a0, 0(a1)
; RV32I-NEXT: j .LBB0_9
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB0_7: # %bb1
; RV32I-NEXT: addi a0, zero, 4
; RV32I-NEXT: sw a0, 0(a1)
; RV32I-NEXT: j .LBB0_9
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB0_8: # %bb3
; RV32I-NEXT: sw a2, 0(a1)
; RV32I-NEXT: .LBB0_9: # %exit
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
entry:
switch i32 %in, label %exit [
Expand Down
223 changes: 136 additions & 87 deletions llvm/test/CodeGen/RISCV/large-stack.ll
View file
Original file line number Diff line number Diff line change
@@ -1,38 +1,50 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: | FileCheck -check-prefix=RV32I-FPELIM %s
; RUN: llc -mtriple=riscv32 -verify-machineinstrs -disable-fp-elim < %s \
; RUN: | FileCheck -check-prefix=RV32I-WITHFP %s

; TODO: the quality of the generated code is poor

define void @test() nounwind {
; RV32I-LABEL: test:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a0, 74565
; RV32I-NEXT: addi a0, a0, 1680
; RV32I-NEXT: sub sp, sp, a0
; RV32I-NEXT: lui a0, 74565
; RV32I-NEXT: addi a0, a0, 1676
; RV32I-NEXT: add a0, sp, a0
; RV32I-NEXT: sw ra, 0(a0)
; RV32I-NEXT: lui a0, 74565
; RV32I-NEXT: addi a0, a0, 1672
; RV32I-NEXT: add a0, sp, a0
; RV32I-NEXT: sw s0, 0(a0)
; RV32I-NEXT: lui a0, 74565
; RV32I-NEXT: addi a0, a0, 1680
; RV32I-NEXT: add s0, sp, a0
; RV32I-NEXT: lui a0, 74565
; RV32I-NEXT: addi a0, a0, 1672
; RV32I-NEXT: add a0, sp, a0
; RV32I-NEXT: lw s0, 0(a0)
; RV32I-NEXT: lui a0, 74565
; RV32I-NEXT: addi a0, a0, 1676
; RV32I-NEXT: add a0, sp, a0
; RV32I-NEXT: lw ra, 0(a0)
; RV32I-NEXT: lui a0, 74565
; RV32I-NEXT: addi a0, a0, 1680
; RV32I-NEXT: add sp, sp, a0
; RV32I-NEXT: ret
; RV32I-FPELIM-LABEL: test:
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: lui a0, 74565
; RV32I-FPELIM-NEXT: addi a0, a0, 1664
; RV32I-FPELIM-NEXT: sub sp, sp, a0
; RV32I-FPELIM-NEXT: lui a0, 74565
; RV32I-FPELIM-NEXT: addi a0, a0, 1664
; RV32I-FPELIM-NEXT: add sp, sp, a0
; RV32I-FPELIM-NEXT: ret
;
; RV32I-WITHFP-LABEL: test:
; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: lui a0, 74565
; RV32I-WITHFP-NEXT: addi a0, a0, 1680
; RV32I-WITHFP-NEXT: sub sp, sp, a0
; RV32I-WITHFP-NEXT: lui a0, 74565
; RV32I-WITHFP-NEXT: addi a0, a0, 1676
; RV32I-WITHFP-NEXT: add a0, sp, a0
; RV32I-WITHFP-NEXT: sw ra, 0(a0)
; RV32I-WITHFP-NEXT: lui a0, 74565
; RV32I-WITHFP-NEXT: addi a0, a0, 1672
; RV32I-WITHFP-NEXT: add a0, sp, a0
; RV32I-WITHFP-NEXT: sw s0, 0(a0)
; RV32I-WITHFP-NEXT: lui a0, 74565
; RV32I-WITHFP-NEXT: addi a0, a0, 1680
; RV32I-WITHFP-NEXT: add s0, sp, a0
; RV32I-WITHFP-NEXT: lui a0, 74565
; RV32I-WITHFP-NEXT: addi a0, a0, 1672
; RV32I-WITHFP-NEXT: add a0, sp, a0
; RV32I-WITHFP-NEXT: lw s0, 0(a0)
; RV32I-WITHFP-NEXT: lui a0, 74565
; RV32I-WITHFP-NEXT: addi a0, a0, 1676
; RV32I-WITHFP-NEXT: add a0, sp, a0
; RV32I-WITHFP-NEXT: lw ra, 0(a0)
; RV32I-WITHFP-NEXT: lui a0, 74565
; RV32I-WITHFP-NEXT: addi a0, a0, 1680
; RV32I-WITHFP-NEXT: add sp, sp, a0
; RV32I-WITHFP-NEXT: ret
%tmp = alloca [ 305419896 x i8 ] , align 4
ret void
}
Expand All @@ -41,64 +53,101 @@ define void @test() nounwind {
; use of the emergency spill slot.

define void @test_emergency_spill_slot(i32 %a) nounwind {
; RV32I-LABEL: test_emergency_spill_slot:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 98
; RV32I-NEXT: addi a1, a1, -1376
; RV32I-NEXT: sub sp, sp, a1
; RV32I-NEXT: lui a1, 98
; RV32I-NEXT: addi a1, a1, -1380
; RV32I-NEXT: add a1, sp, a1
; RV32I-NEXT: sw ra, 0(a1)
; RV32I-NEXT: lui a1, 98
; RV32I-NEXT: addi a1, a1, -1384
; RV32I-NEXT: add a1, sp, a1
; RV32I-NEXT: sw s0, 0(a1)
; RV32I-NEXT: lui a1, 98
; RV32I-NEXT: addi a1, a1, -1388
; RV32I-NEXT: add a1, sp, a1
; RV32I-NEXT: sw s1, 0(a1)
; RV32I-NEXT: lui a1, 98
; RV32I-NEXT: addi a1, a1, -1392
; RV32I-NEXT: add a1, sp, a1
; RV32I-NEXT: sw s2, 0(a1)
; RV32I-NEXT: lui a1, 98
; RV32I-NEXT: addi a1, a1, -1376
; RV32I-NEXT: add s0, sp, a1
; RV32I-NEXT: lui a1, 78
; RV32I-NEXT: addi a1, a1, 512
; RV32I-NEXT: lui a2, 1048478
; RV32I-NEXT: addi a2, a2, 1388
; RV32I-NEXT: add a2, s0, a2
; RV32I-NEXT: mv a2, a2
; RV32I-NEXT: add a1, a2, a1
; RV32I-NEXT: #APP
; RV32I-NEXT: nop
; RV32I-NEXT: #NO_APP
; RV32I-NEXT: sw a0, 0(a1)
; RV32I-NEXT: #APP
; RV32I-NEXT: nop
; RV32I-NEXT: #NO_APP
; RV32I-NEXT: lui a0, 98
; RV32I-NEXT: addi a0, a0, -1392
; RV32I-NEXT: add a0, sp, a0
; RV32I-NEXT: lw s2, 0(a0)
; RV32I-NEXT: lui a0, 98
; RV32I-NEXT: addi a0, a0, -1388
; RV32I-NEXT: add a0, sp, a0
; RV32I-NEXT: lw s1, 0(a0)
; RV32I-NEXT: lui a0, 98
; RV32I-NEXT: addi a0, a0, -1384
; RV32I-NEXT: add a0, sp, a0
; RV32I-NEXT: lw s0, 0(a0)
; RV32I-NEXT: lui a0, 98
; RV32I-NEXT: addi a0, a0, -1380
; RV32I-NEXT: add a0, sp, a0
; RV32I-NEXT: lw ra, 0(a0)
; RV32I-NEXT: lui a0, 98
; RV32I-NEXT: addi a0, a0, -1376
; RV32I-NEXT: add sp, sp, a0
; RV32I-NEXT: ret
; RV32I-FPELIM-LABEL: test_emergency_spill_slot:
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: lui a1, 98
; RV32I-FPELIM-NEXT: addi a1, a1, -1392
; RV32I-FPELIM-NEXT: sub sp, sp, a1
; RV32I-FPELIM-NEXT: lui a1, 98
; RV32I-FPELIM-NEXT: addi a1, a1, -1396
; RV32I-FPELIM-NEXT: add a1, sp, a1
; RV32I-FPELIM-NEXT: sw s1, 0(a1)
; RV32I-FPELIM-NEXT: lui a1, 98
; RV32I-FPELIM-NEXT: addi a1, a1, -1400
; RV32I-FPELIM-NEXT: add a1, sp, a1
; RV32I-FPELIM-NEXT: sw s2, 0(a1)
; RV32I-FPELIM-NEXT: lui a1, 78
; RV32I-FPELIM-NEXT: addi a1, a1, 512
; RV32I-FPELIM-NEXT: addi a2, sp, 8
; RV32I-FPELIM-NEXT: add a1, a2, a1
; RV32I-FPELIM-NEXT: #APP
; RV32I-FPELIM-NEXT: nop
; RV32I-FPELIM-NEXT: #NO_APP
; RV32I-FPELIM-NEXT: sw a0, 0(a1)
; RV32I-FPELIM-NEXT: #APP
; RV32I-FPELIM-NEXT: nop
; RV32I-FPELIM-NEXT: #NO_APP
; RV32I-FPELIM-NEXT: lui a0, 98
; RV32I-FPELIM-NEXT: addi a0, a0, -1400
; RV32I-FPELIM-NEXT: add a0, sp, a0
; RV32I-FPELIM-NEXT: lw s2, 0(a0)
; RV32I-FPELIM-NEXT: lui a0, 98
; RV32I-FPELIM-NEXT: addi a0, a0, -1396
; RV32I-FPELIM-NEXT: add a0, sp, a0
; RV32I-FPELIM-NEXT: lw s1, 0(a0)
; RV32I-FPELIM-NEXT: lui a0, 98
; RV32I-FPELIM-NEXT: addi a0, a0, -1392
; RV32I-FPELIM-NEXT: add sp, sp, a0
; RV32I-FPELIM-NEXT: ret
;
; RV32I-WITHFP-LABEL: test_emergency_spill_slot:
; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: lui a1, 98
; RV32I-WITHFP-NEXT: addi a1, a1, -1376
; RV32I-WITHFP-NEXT: sub sp, sp, a1
; RV32I-WITHFP-NEXT: lui a1, 98
; RV32I-WITHFP-NEXT: addi a1, a1, -1380
; RV32I-WITHFP-NEXT: add a1, sp, a1
; RV32I-WITHFP-NEXT: sw ra, 0(a1)
; RV32I-WITHFP-NEXT: lui a1, 98
; RV32I-WITHFP-NEXT: addi a1, a1, -1384
; RV32I-WITHFP-NEXT: add a1, sp, a1
; RV32I-WITHFP-NEXT: sw s0, 0(a1)
; RV32I-WITHFP-NEXT: lui a1, 98
; RV32I-WITHFP-NEXT: addi a1, a1, -1388
; RV32I-WITHFP-NEXT: add a1, sp, a1
; RV32I-WITHFP-NEXT: sw s1, 0(a1)
; RV32I-WITHFP-NEXT: lui a1, 98
; RV32I-WITHFP-NEXT: addi a1, a1, -1392
; RV32I-WITHFP-NEXT: add a1, sp, a1
; RV32I-WITHFP-NEXT: sw s2, 0(a1)
; RV32I-WITHFP-NEXT: lui a1, 98
; RV32I-WITHFP-NEXT: addi a1, a1, -1376
; RV32I-WITHFP-NEXT: add s0, sp, a1
; RV32I-WITHFP-NEXT: lui a1, 78
; RV32I-WITHFP-NEXT: addi a1, a1, 512
; RV32I-WITHFP-NEXT: lui a2, 1048478
; RV32I-WITHFP-NEXT: addi a2, a2, 1388
; RV32I-WITHFP-NEXT: add a2, s0, a2
; RV32I-WITHFP-NEXT: mv a2, a2
; RV32I-WITHFP-NEXT: add a1, a2, a1
; RV32I-WITHFP-NEXT: #APP
; RV32I-WITHFP-NEXT: nop
; RV32I-WITHFP-NEXT: #NO_APP
; RV32I-WITHFP-NEXT: sw a0, 0(a1)
; RV32I-WITHFP-NEXT: #APP
; RV32I-WITHFP-NEXT: nop
; RV32I-WITHFP-NEXT: #NO_APP
; RV32I-WITHFP-NEXT: lui a0, 98
; RV32I-WITHFP-NEXT: addi a0, a0, -1392
; RV32I-WITHFP-NEXT: add a0, sp, a0
; RV32I-WITHFP-NEXT: lw s2, 0(a0)
; RV32I-WITHFP-NEXT: lui a0, 98
; RV32I-WITHFP-NEXT: addi a0, a0, -1388
; RV32I-WITHFP-NEXT: add a0, sp, a0
; RV32I-WITHFP-NEXT: lw s1, 0(a0)
; RV32I-WITHFP-NEXT: lui a0, 98
; RV32I-WITHFP-NEXT: addi a0, a0, -1384
; RV32I-WITHFP-NEXT: add a0, sp, a0
; RV32I-WITHFP-NEXT: lw s0, 0(a0)
; RV32I-WITHFP-NEXT: lui a0, 98
; RV32I-WITHFP-NEXT: addi a0, a0, -1380
; RV32I-WITHFP-NEXT: add a0, sp, a0
; RV32I-WITHFP-NEXT: lw ra, 0(a0)
; RV32I-WITHFP-NEXT: lui a0, 98
; RV32I-WITHFP-NEXT: addi a0, a0, -1376
; RV32I-WITHFP-NEXT: add sp, sp, a0
; RV32I-WITHFP-NEXT: ret
%data = alloca [ 100000 x i32 ] , align 4
%ptr = getelementptr inbounds [100000 x i32], [100000 x i32]* %data, i32 0, i32 80000
%1 = tail call { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } asm sideeffect "nop", "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r"()
Expand Down
84 changes: 0 additions & 84 deletions llvm/test/CodeGen/RISCV/mem.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,15 +7,8 @@
define i32 @lb(i8 *%a) nounwind {
; RV32I-LABEL: lb:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lb a1, 0(a0)
; RV32I-NEXT: lb a0, 1(a0)
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = getelementptr i8, i8* %a, i32 1
%2 = load i8, i8* %1
Expand All @@ -28,15 +21,8 @@ define i32 @lb(i8 *%a) nounwind {
define i32 @lh(i16 *%a) nounwind {
; RV32I-LABEL: lh:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lh a1, 0(a0)
; RV32I-NEXT: lh a0, 4(a0)
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = getelementptr i16, i16* %a, i32 2
%2 = load i16, i16* %1
Expand All @@ -49,15 +35,8 @@ define i32 @lh(i16 *%a) nounwind {
define i32 @lw(i32 *%a) nounwind {
; RV32I-LABEL: lw:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lw a1, 0(a0)
; RV32I-NEXT: lw a0, 12(a0)
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = getelementptr i32, i32* %a, i32 3
%2 = load i32, i32* %1
Expand All @@ -68,16 +47,9 @@ define i32 @lw(i32 *%a) nounwind {
define i32 @lbu(i8 *%a) nounwind {
; RV32I-LABEL: lbu:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lbu a1, 0(a0)
; RV32I-NEXT: lbu a0, 4(a0)
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = getelementptr i8, i8* %a, i32 4
%2 = load i8, i8* %1
Expand All @@ -91,16 +63,9 @@ define i32 @lbu(i8 *%a) nounwind {
define i32 @lhu(i16 *%a) nounwind {
; RV32I-LABEL: lhu:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lhu a0, 10(a0)
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = getelementptr i16, i16* %a, i32 5
%2 = load i16, i16* %1
Expand All @@ -116,15 +81,8 @@ define i32 @lhu(i16 *%a) nounwind {
define void @sb(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: sb:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: sb a1, 6(a0)
; RV32I-NEXT: sb a1, 0(a0)
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
store i8 %b, i8* %a
%1 = getelementptr i8, i8* %a, i32 6
Expand All @@ -135,15 +93,8 @@ define void @sb(i8 *%a, i8 %b) nounwind {
define void @sh(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: sh:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: sh a1, 14(a0)
; RV32I-NEXT: sh a1, 0(a0)
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
store i16 %b, i16* %a
%1 = getelementptr i16, i16* %a, i32 7
Expand All @@ -154,15 +105,8 @@ define void @sh(i16 *%a, i16 %b) nounwind {
define void @sw(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: sw:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: sw a1, 32(a0)
; RV32I-NEXT: sw a1, 0(a0)
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
store i32 %b, i32* %a
%1 = getelementptr i32, i32* %a, i32 8
Expand All @@ -174,17 +118,10 @@ define void @sw(i32 *%a, i32 %b) nounwind {
define i32 @load_sext_zext_anyext_i1(i1 *%a) nounwind {
; RV32I-LABEL: load_sext_zext_anyext_i1:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lb a1, 0(a0)
; RV32I-NEXT: lbu a1, 1(a0)
; RV32I-NEXT: lbu a0, 2(a0)
; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; sextload i1
%1 = getelementptr i1, i1* %a, i32 1
Expand All @@ -203,17 +140,10 @@ define i32 @load_sext_zext_anyext_i1(i1 *%a) nounwind {
define i16 @load_sext_zext_anyext_i1_i16(i1 *%a) nounwind {
; RV32I-LABEL: load_sext_zext_anyext_i1_i16:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lb a1, 0(a0)
; RV32I-NEXT: lbu a1, 1(a0)
; RV32I-NEXT: lbu a0, 2(a0)
; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; sextload i1
%1 = getelementptr i1, i1* %a, i32 1
Expand All @@ -236,10 +166,6 @@ define i32 @lw_sw_global(i32 %a) nounwind {
; TODO: the addi should be folded in to the lw/sw operations
; RV32I-LABEL: lw_sw_global:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a1, %hi(G)
; RV32I-NEXT: addi a2, a1, %lo(G)
; RV32I-NEXT: lw a1, 0(a2)
Expand All @@ -249,9 +175,6 @@ define i32 @lw_sw_global(i32 %a) nounwind {
; RV32I-NEXT: lw a3, 0(a2)
; RV32I-NEXT: sw a0, 0(a2)
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = load volatile i32, i32* @G
store i32 %a, i32* @G
Expand All @@ -266,18 +189,11 @@ define i32 @lw_sw_constant(i32 %a) nounwind {
; TODO: the addi should be folded in to the lw/sw
; RV32I-LABEL: lw_sw_constant:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a1, 912092
; RV32I-NEXT: addi a2, a1, -273
; RV32I-NEXT: lw a1, 0(a2)
; RV32I-NEXT: sw a0, 0(a2)
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = inttoptr i32 3735928559 to i32*
%2 = load volatile i32, i32* %1
Expand Down
22 changes: 0 additions & 22 deletions llvm/test/CodeGen/RISCV/mul.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,13 +7,10 @@ define i32 @square(i32 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a1, %hi(__mulsi3)
; RV32I-NEXT: addi a2, a1, %lo(__mulsi3)
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: jalr a2
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -26,12 +23,9 @@ define i32 @mul(i32 %a, i32 %b) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a2, %hi(__mulsi3)
; RV32I-NEXT: addi a2, a2, %lo(__mulsi3)
; RV32I-NEXT: jalr a2
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -44,13 +38,10 @@ define i32 @mul_constant(i32 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a1, %hi(__mulsi3)
; RV32I-NEXT: addi a2, a1, %lo(__mulsi3)
; RV32I-NEXT: addi a1, zero, 5
; RV32I-NEXT: jalr a2
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -61,14 +52,7 @@ define i32 @mul_constant(i32 %a) nounwind {
define i32 @mul_pow2(i32 %a) nounwind {
; RV32I-LABEL: mul_pow2:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: slli a0, a0, 3
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%1 = mul i32 %a, 8
ret i32 %1
Expand All @@ -79,12 +63,9 @@ define i64 @mul64(i64 %a, i64 %b) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a4, %hi(__muldi3)
; RV32I-NEXT: addi a4, a4, %lo(__muldi3)
; RV32I-NEXT: jalr a4
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -97,14 +78,11 @@ define i64 @mul64_constant(i64 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a2, %hi(__muldi3)
; RV32I-NEXT: addi a4, a2, %lo(__muldi3)
; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: jalr a4
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand Down
6 changes: 0 additions & 6 deletions llvm/test/CodeGen/RISCV/rem.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,12 +7,9 @@ define i32 @urem(i32 %a, i32 %b) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a2, %hi(__umodsi3)
; RV32I-NEXT: addi a2, a2, %lo(__umodsi3)
; RV32I-NEXT: jalr a2
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -25,12 +22,9 @@ define i32 @srem(i32 %a, i32 %b) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a2, %hi(__modsi3)
; RV32I-NEXT: addi a2, a2, %lo(__modsi3)
; RV32I-NEXT: jalr a2
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand Down
14 changes: 0 additions & 14 deletions llvm/test/CodeGen/RISCV/rotl-rotr.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,18 +8,11 @@
define i32 @rotl(i32 %x, i32 %y) {
; RV32I-LABEL: rotl:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: addi a2, zero, 32
; RV32I-NEXT: sub a2, a2, a1
; RV32I-NEXT: sll a1, a0, a1
; RV32I-NEXT: srl a0, a0, a2
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%z = sub i32 32, %y
%b = shl i32 %x, %y
Expand All @@ -31,18 +24,11 @@ define i32 @rotl(i32 %x, i32 %y) {
define i32 @rotr(i32 %x, i32 %y) {
; RV32I-LABEL: rotr:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: addi a2, zero, 32
; RV32I-NEXT: sub a2, a2, a1
; RV32I-NEXT: srl a1, a0, a1
; RV32I-NEXT: sll a0, a0, a2
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%z = sub i32 32, %y
%b = lshr i32 %x, %y
Expand Down
7 changes: 0 additions & 7 deletions llvm/test/CodeGen/RISCV/select-cc.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,10 +5,6 @@
define i32 @foo(i32 %a, i32 *%b) {
; RV32I-LABEL: foo:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lw a2, 0(a1)
; RV32I-NEXT: beq a0, a2, .LBB0_2
; RV32I-NEXT: # %bb.1:
Expand Down Expand Up @@ -59,9 +55,6 @@ define i32 @foo(i32 %a, i32 *%b) {
; RV32I-NEXT: # %bb.19:
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: .LBB0_20:
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
%val1 = load volatile i32, i32* %b
%tst1 = icmp eq i32 %a, %val1
Expand Down
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