254 changes: 94 additions & 160 deletions llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1216,19 +1216,19 @@ define <vscale x 1 x i64> @cttz_nxv1i64(<vscale x 1 x i64> %va) {
; RV32F-LABEL: cttz_nxv1i64:
; RV32F: # %bb.0:
; RV32F-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; RV32F-NEXT: vmseq.vx v0, v8, zero
; RV32F-NEXT: vrsub.vi v9, v8, 0
; RV32F-NEXT: vand.vv v8, v8, v9
; RV32F-NEXT: vand.vv v9, v8, v9
; RV32F-NEXT: fsrmi a0, 1
; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; RV32F-NEXT: vfncvt.f.xu.w v9, v8
; RV32F-NEXT: vsrl.vi v8, v9, 23
; RV32F-NEXT: vfncvt.f.xu.w v10, v9
; RV32F-NEXT: vsrl.vi v9, v10, 23
; RV32F-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV32F-NEXT: vzext.vf2 v9, v8
; RV32F-NEXT: vzext.vf2 v10, v9
; RV32F-NEXT: li a1, 127
; RV32F-NEXT: vsub.vx v8, v9, a1
; RV32F-NEXT: vsub.vx v9, v10, a1
; RV32F-NEXT: vmseq.vi v0, v8, 0
; RV32F-NEXT: li a1, 64
; RV32F-NEXT: vmerge.vxm v8, v8, a1, v0
; RV32F-NEXT: vmerge.vxm v8, v9, a1, v0
; RV32F-NEXT: fsrm a0
; RV32F-NEXT: ret
;
Expand All @@ -1250,39 +1250,22 @@ define <vscale x 1 x i64> @cttz_nxv1i64(<vscale x 1 x i64> %va) {
; RV64F-NEXT: fsrm a0
; RV64F-NEXT: ret
;
; RV32D-LABEL: cttz_nxv1i64:
; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; RV32D-NEXT: vmseq.vx v0, v8, zero
; RV32D-NEXT: vrsub.vi v9, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v9
; RV32D-NEXT: fsrmi a0, 1
; RV32D-NEXT: vfcvt.f.xu.v v8, v8
; RV32D-NEXT: li a1, 52
; RV32D-NEXT: vsrl.vx v8, v8, a1
; RV32D-NEXT: li a1, 1023
; RV32D-NEXT: vsub.vx v8, v8, a1
; RV32D-NEXT: li a1, 64
; RV32D-NEXT: vmerge.vxm v8, v8, a1, v0
; RV32D-NEXT: fsrm a0
; RV32D-NEXT: ret
;
; RV64D-LABEL: cttz_nxv1i64:
; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v9, v8, v9
; RV64D-NEXT: fsrmi a0, 1
; RV64D-NEXT: vfcvt.f.xu.v v9, v9
; RV64D-NEXT: li a1, 52
; RV64D-NEXT: vsrl.vx v9, v9, a1
; RV64D-NEXT: li a1, 1023
; RV64D-NEXT: vsub.vx v9, v9, a1
; RV64D-NEXT: vmseq.vi v0, v8, 0
; RV64D-NEXT: li a1, 64
; RV64D-NEXT: vmerge.vxm v8, v9, a1, v0
; RV64D-NEXT: fsrm a0
; RV64D-NEXT: ret
; CHECK-D-LABEL: cttz_nxv1i64:
; CHECK-D: # %bb.0:
; CHECK-D-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; CHECK-D-NEXT: vrsub.vi v9, v8, 0
; CHECK-D-NEXT: vand.vv v9, v8, v9
; CHECK-D-NEXT: fsrmi a0, 1
; CHECK-D-NEXT: vfcvt.f.xu.v v9, v9
; CHECK-D-NEXT: li a1, 52
; CHECK-D-NEXT: vsrl.vx v9, v9, a1
; CHECK-D-NEXT: li a1, 1023
; CHECK-D-NEXT: vsub.vx v9, v9, a1
; CHECK-D-NEXT: vmseq.vi v0, v8, 0
; CHECK-D-NEXT: li a1, 64
; CHECK-D-NEXT: vmerge.vxm v8, v9, a1, v0
; CHECK-D-NEXT: fsrm a0
; CHECK-D-NEXT: ret
;
; CHECK-ZVBB-LABEL: cttz_nxv1i64:
; CHECK-ZVBB: # %bb.0:
Expand Down Expand Up @@ -1378,19 +1361,19 @@ define <vscale x 2 x i64> @cttz_nxv2i64(<vscale x 2 x i64> %va) {
; RV32F-LABEL: cttz_nxv2i64:
; RV32F: # %bb.0:
; RV32F-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; RV32F-NEXT: vmseq.vx v0, v8, zero
; RV32F-NEXT: vrsub.vi v10, v8, 0
; RV32F-NEXT: vand.vv v8, v8, v10
; RV32F-NEXT: vand.vv v10, v8, v10
; RV32F-NEXT: fsrmi a0, 1
; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; RV32F-NEXT: vfncvt.f.xu.w v10, v8
; RV32F-NEXT: vsrl.vi v8, v10, 23
; RV32F-NEXT: vfncvt.f.xu.w v12, v10
; RV32F-NEXT: vsrl.vi v10, v12, 23
; RV32F-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; RV32F-NEXT: vzext.vf2 v10, v8
; RV32F-NEXT: vzext.vf2 v12, v10
; RV32F-NEXT: li a1, 127
; RV32F-NEXT: vsub.vx v8, v10, a1
; RV32F-NEXT: vsub.vx v10, v12, a1
; RV32F-NEXT: vmseq.vi v0, v8, 0
; RV32F-NEXT: li a1, 64
; RV32F-NEXT: vmerge.vxm v8, v8, a1, v0
; RV32F-NEXT: vmerge.vxm v8, v10, a1, v0
; RV32F-NEXT: fsrm a0
; RV32F-NEXT: ret
;
Expand All @@ -1412,39 +1395,22 @@ define <vscale x 2 x i64> @cttz_nxv2i64(<vscale x 2 x i64> %va) {
; RV64F-NEXT: fsrm a0
; RV64F-NEXT: ret
;
; RV32D-LABEL: cttz_nxv2i64:
; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; RV32D-NEXT: vmseq.vx v0, v8, zero
; RV32D-NEXT: vrsub.vi v10, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v10
; RV32D-NEXT: fsrmi a0, 1
; RV32D-NEXT: vfcvt.f.xu.v v8, v8
; RV32D-NEXT: li a1, 52
; RV32D-NEXT: vsrl.vx v8, v8, a1
; RV32D-NEXT: li a1, 1023
; RV32D-NEXT: vsub.vx v8, v8, a1
; RV32D-NEXT: li a1, 64
; RV32D-NEXT: vmerge.vxm v8, v8, a1, v0
; RV32D-NEXT: fsrm a0
; RV32D-NEXT: ret
;
; RV64D-LABEL: cttz_nxv2i64:
; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; RV64D-NEXT: vrsub.vi v10, v8, 0
; RV64D-NEXT: vand.vv v10, v8, v10
; RV64D-NEXT: fsrmi a0, 1
; RV64D-NEXT: vfcvt.f.xu.v v10, v10
; RV64D-NEXT: li a1, 52
; RV64D-NEXT: vsrl.vx v10, v10, a1
; RV64D-NEXT: li a1, 1023
; RV64D-NEXT: vsub.vx v10, v10, a1
; RV64D-NEXT: vmseq.vi v0, v8, 0
; RV64D-NEXT: li a1, 64
; RV64D-NEXT: vmerge.vxm v8, v10, a1, v0
; RV64D-NEXT: fsrm a0
; RV64D-NEXT: ret
; CHECK-D-LABEL: cttz_nxv2i64:
; CHECK-D: # %bb.0:
; CHECK-D-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; CHECK-D-NEXT: vrsub.vi v10, v8, 0
; CHECK-D-NEXT: vand.vv v10, v8, v10
; CHECK-D-NEXT: fsrmi a0, 1
; CHECK-D-NEXT: vfcvt.f.xu.v v10, v10
; CHECK-D-NEXT: li a1, 52
; CHECK-D-NEXT: vsrl.vx v10, v10, a1
; CHECK-D-NEXT: li a1, 1023
; CHECK-D-NEXT: vsub.vx v10, v10, a1
; CHECK-D-NEXT: vmseq.vi v0, v8, 0
; CHECK-D-NEXT: li a1, 64
; CHECK-D-NEXT: vmerge.vxm v8, v10, a1, v0
; CHECK-D-NEXT: fsrm a0
; CHECK-D-NEXT: ret
;
; CHECK-ZVBB-LABEL: cttz_nxv2i64:
; CHECK-ZVBB: # %bb.0:
Expand Down Expand Up @@ -1540,19 +1506,19 @@ define <vscale x 4 x i64> @cttz_nxv4i64(<vscale x 4 x i64> %va) {
; RV32F-LABEL: cttz_nxv4i64:
; RV32F: # %bb.0:
; RV32F-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; RV32F-NEXT: vmseq.vx v0, v8, zero
; RV32F-NEXT: vrsub.vi v12, v8, 0
; RV32F-NEXT: vand.vv v8, v8, v12
; RV32F-NEXT: vand.vv v12, v8, v12
; RV32F-NEXT: fsrmi a0, 1
; RV32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32F-NEXT: vfncvt.f.xu.w v12, v8
; RV32F-NEXT: vsrl.vi v8, v12, 23
; RV32F-NEXT: vfncvt.f.xu.w v16, v12
; RV32F-NEXT: vsrl.vi v12, v16, 23
; RV32F-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; RV32F-NEXT: vzext.vf2 v12, v8
; RV32F-NEXT: vzext.vf2 v16, v12
; RV32F-NEXT: li a1, 127
; RV32F-NEXT: vsub.vx v8, v12, a1
; RV32F-NEXT: vsub.vx v12, v16, a1
; RV32F-NEXT: vmseq.vi v0, v8, 0
; RV32F-NEXT: li a1, 64
; RV32F-NEXT: vmerge.vxm v8, v8, a1, v0
; RV32F-NEXT: vmerge.vxm v8, v12, a1, v0
; RV32F-NEXT: fsrm a0
; RV32F-NEXT: ret
;
Expand All @@ -1574,39 +1540,22 @@ define <vscale x 4 x i64> @cttz_nxv4i64(<vscale x 4 x i64> %va) {
; RV64F-NEXT: fsrm a0
; RV64F-NEXT: ret
;
; RV32D-LABEL: cttz_nxv4i64:
; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; RV32D-NEXT: vmseq.vx v0, v8, zero
; RV32D-NEXT: vrsub.vi v12, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v12
; RV32D-NEXT: fsrmi a0, 1
; RV32D-NEXT: vfcvt.f.xu.v v8, v8
; RV32D-NEXT: li a1, 52
; RV32D-NEXT: vsrl.vx v8, v8, a1
; RV32D-NEXT: li a1, 1023
; RV32D-NEXT: vsub.vx v8, v8, a1
; RV32D-NEXT: li a1, 64
; RV32D-NEXT: vmerge.vxm v8, v8, a1, v0
; RV32D-NEXT: fsrm a0
; RV32D-NEXT: ret
;
; RV64D-LABEL: cttz_nxv4i64:
; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; RV64D-NEXT: vrsub.vi v12, v8, 0
; RV64D-NEXT: vand.vv v12, v8, v12
; RV64D-NEXT: fsrmi a0, 1
; RV64D-NEXT: vfcvt.f.xu.v v12, v12
; RV64D-NEXT: li a1, 52
; RV64D-NEXT: vsrl.vx v12, v12, a1
; RV64D-NEXT: li a1, 1023
; RV64D-NEXT: vsub.vx v12, v12, a1
; RV64D-NEXT: vmseq.vi v0, v8, 0
; RV64D-NEXT: li a1, 64
; RV64D-NEXT: vmerge.vxm v8, v12, a1, v0
; RV64D-NEXT: fsrm a0
; RV64D-NEXT: ret
; CHECK-D-LABEL: cttz_nxv4i64:
; CHECK-D: # %bb.0:
; CHECK-D-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; CHECK-D-NEXT: vrsub.vi v12, v8, 0
; CHECK-D-NEXT: vand.vv v12, v8, v12
; CHECK-D-NEXT: fsrmi a0, 1
; CHECK-D-NEXT: vfcvt.f.xu.v v12, v12
; CHECK-D-NEXT: li a1, 52
; CHECK-D-NEXT: vsrl.vx v12, v12, a1
; CHECK-D-NEXT: li a1, 1023
; CHECK-D-NEXT: vsub.vx v12, v12, a1
; CHECK-D-NEXT: vmseq.vi v0, v8, 0
; CHECK-D-NEXT: li a1, 64
; CHECK-D-NEXT: vmerge.vxm v8, v12, a1, v0
; CHECK-D-NEXT: fsrm a0
; CHECK-D-NEXT: ret
;
; CHECK-ZVBB-LABEL: cttz_nxv4i64:
; CHECK-ZVBB: # %bb.0:
Expand Down Expand Up @@ -1702,19 +1651,19 @@ define <vscale x 8 x i64> @cttz_nxv8i64(<vscale x 8 x i64> %va) {
; RV32F-LABEL: cttz_nxv8i64:
; RV32F: # %bb.0:
; RV32F-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; RV32F-NEXT: vmseq.vx v0, v8, zero
; RV32F-NEXT: vrsub.vi v16, v8, 0
; RV32F-NEXT: vand.vv v8, v8, v16
; RV32F-NEXT: vand.vv v16, v8, v16
; RV32F-NEXT: fsrmi a0, 1
; RV32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; RV32F-NEXT: vfncvt.f.xu.w v16, v8
; RV32F-NEXT: vsrl.vi v8, v16, 23
; RV32F-NEXT: vfncvt.f.xu.w v24, v16
; RV32F-NEXT: vsrl.vi v16, v24, 23
; RV32F-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV32F-NEXT: vzext.vf2 v16, v8
; RV32F-NEXT: vzext.vf2 v24, v16
; RV32F-NEXT: li a1, 127
; RV32F-NEXT: vsub.vx v8, v16, a1
; RV32F-NEXT: vsub.vx v16, v24, a1
; RV32F-NEXT: vmseq.vi v0, v8, 0
; RV32F-NEXT: li a1, 64
; RV32F-NEXT: vmerge.vxm v8, v8, a1, v0
; RV32F-NEXT: vmerge.vxm v8, v16, a1, v0
; RV32F-NEXT: fsrm a0
; RV32F-NEXT: ret
;
Expand All @@ -1736,39 +1685,22 @@ define <vscale x 8 x i64> @cttz_nxv8i64(<vscale x 8 x i64> %va) {
; RV64F-NEXT: fsrm a0
; RV64F-NEXT: ret
;
; RV32D-LABEL: cttz_nxv8i64:
; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; RV32D-NEXT: vmseq.vx v0, v8, zero
; RV32D-NEXT: vrsub.vi v16, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v16
; RV32D-NEXT: fsrmi a0, 1
; RV32D-NEXT: vfcvt.f.xu.v v8, v8
; RV32D-NEXT: li a1, 52
; RV32D-NEXT: vsrl.vx v8, v8, a1
; RV32D-NEXT: li a1, 1023
; RV32D-NEXT: vsub.vx v8, v8, a1
; RV32D-NEXT: li a1, 64
; RV32D-NEXT: vmerge.vxm v8, v8, a1, v0
; RV32D-NEXT: fsrm a0
; RV32D-NEXT: ret
;
; RV64D-LABEL: cttz_nxv8i64:
; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; RV64D-NEXT: vrsub.vi v16, v8, 0
; RV64D-NEXT: vand.vv v16, v8, v16
; RV64D-NEXT: fsrmi a0, 1
; RV64D-NEXT: vfcvt.f.xu.v v16, v16
; RV64D-NEXT: li a1, 52
; RV64D-NEXT: vsrl.vx v16, v16, a1
; RV64D-NEXT: li a1, 1023
; RV64D-NEXT: vsub.vx v16, v16, a1
; RV64D-NEXT: vmseq.vi v0, v8, 0
; RV64D-NEXT: li a1, 64
; RV64D-NEXT: vmerge.vxm v8, v16, a1, v0
; RV64D-NEXT: fsrm a0
; RV64D-NEXT: ret
; CHECK-D-LABEL: cttz_nxv8i64:
; CHECK-D: # %bb.0:
; CHECK-D-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-D-NEXT: vrsub.vi v16, v8, 0
; CHECK-D-NEXT: vand.vv v16, v8, v16
; CHECK-D-NEXT: fsrmi a0, 1
; CHECK-D-NEXT: vfcvt.f.xu.v v16, v16
; CHECK-D-NEXT: li a1, 52
; CHECK-D-NEXT: vsrl.vx v16, v16, a1
; CHECK-D-NEXT: li a1, 1023
; CHECK-D-NEXT: vsub.vx v16, v16, a1
; CHECK-D-NEXT: vmseq.vi v0, v8, 0
; CHECK-D-NEXT: li a1, 64
; CHECK-D-NEXT: vmerge.vxm v8, v16, a1, v0
; CHECK-D-NEXT: fsrm a0
; CHECK-D-NEXT: ret
;
; CHECK-ZVBB-LABEL: cttz_nxv8i64:
; CHECK-ZVBB: # %bb.0:
Expand Down Expand Up @@ -3343,4 +3275,6 @@ define <vscale x 8 x i64> @cttz_zero_undef_nxv8i64(<vscale x 8 x i64> %va) {
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; RV32: {{.*}}
; RV32D: {{.*}}
; RV64: {{.*}}
; RV64D: {{.*}}