170 changes: 85 additions & 85 deletions llvm/lib/Target/AVR/AVRInstrInfo.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -648,46 +648,46 @@ let isCommutable = 1, Defs = [R1, R0, SREG] in {
let usesCustomInserter = 1 in {
def MULRdRr : FRdRr<0b1001, 0b11, (outs),
(ins GPR8
: $lhs, GPR8
: $rhs),
"mul\t$lhs, $rhs",
[/*(set R1, R0, (smullohi i8:$lhs, i8:$rhs))*/]>,
: $rd, GPR8
: $rr),
"mul\t$rd, $rr",
[/*(set R1, R0, (smullohi i8:$rd, i8:$rr))*/]>,
Requires<[SupportsMultiplication]>;

def MULSRdRr : FMUL2RdRr<0, (outs),
(ins LD8
: $lhs, LD8
: $rhs),
"muls\t$lhs, $rhs", []>,
: $rd, LD8
: $rr),
"muls\t$rd, $rr", []>,
Requires<[SupportsMultiplication]>;
}

def MULSURdRr : FMUL2RdRr<1, (outs),
(ins LD8lo
: $lhs, LD8lo
: $rhs),
"mulsu\t$lhs, $rhs", []>,
: $rd, LD8lo
: $rr),
"mulsu\t$rd, $rr", []>,
Requires<[SupportsMultiplication]>;

def FMUL : FFMULRdRr<0b01, (outs),
(ins LD8lo
: $lhs, LD8lo
: $rhs),
"fmul\t$lhs, $rhs", []>,
: $rd, LD8lo
: $rr),
"fmul\t$rd, $rr", []>,
Requires<[SupportsMultiplication]>;

def FMULS : FFMULRdRr<0b10, (outs),
(ins LD8lo
: $lhs, LD8lo
: $rhs),
"fmuls\t$lhs, $rhs", []>,
: $rd, LD8lo
: $rr),
"fmuls\t$rd, $rr", []>,
Requires<[SupportsMultiplication]>;

def FMULSU : FFMULRdRr<0b11, (outs),
(ins LD8lo
: $lhs, LD8lo
: $rhs),
"fmulsu\t$lhs, $rhs", []>,
: $rd, LD8lo
: $rr),
"fmulsu\t$rd, $rr", []>,
Requires<[SupportsMultiplication]>;
}

Expand Down Expand Up @@ -948,9 +948,9 @@ def : InstAlias<"sbr\t$rd, $k",
let isBarrier = 1, isBranch = 1, isTerminator = 1 in {
def RJMPk : FBRk<0, (outs),
(ins brtarget_13
: $target),
"rjmp\t$target", [(br bb
: $target)]>;
: $k),
"rjmp\t$k", [(br bb
: $k)]>;

let isIndirectBranch = 1,
Uses = [R31R30] in def IJMP
Expand Down Expand Up @@ -1095,27 +1095,27 @@ let isBranch = 1, isTerminator = 1 in {
let isBarrier = 1 in {
def SBRCRrB : FRdB<0b10, (outs),
(ins GPR8
: $rr, i8imm
: $rd, i8imm
: $b),
"sbrc\t$rr, $b", []>;
"sbrc\t$rd, $b", []>;

def SBRSRrB : FRdB<0b11, (outs),
(ins GPR8
: $rr, i8imm
: $rd, i8imm
: $b),
"sbrs\t$rr, $b", []>;
"sbrs\t$rd, $b", []>;

def SBICAb : FIOBIT<0b01, (outs),
(ins imm_port5
: $a, i8imm
: $addr, i8imm
: $b),
"sbic\t$a, $b", []>;
"sbic\t$addr, $b", []>;

def SBISAb : FIOBIT<0b11, (outs),
(ins imm_port5
: $a, i8imm
: $addr, i8imm
: $b),
"sbis\t$a, $b", []>;
"sbis\t$addr, $b", []>;
}

// Relative branches on status flag bits.
Expand Down Expand Up @@ -1186,51 +1186,51 @@ def : InstAlias<"brid\t$k", (BRBCsk 7, relbrtarget_7 : $k)>;
let isBranch = 1, isTerminator = 1, Uses = [SREG] in {
def BREQk : FBRsk<0, 0b001, (outs),
(ins relbrtarget_7
: $target),
"breq\t$target", [(AVRbrcond bb
: $target, AVR_COND_EQ)]>;
: $k),
"breq\t$k", [(AVRbrcond bb
: $k, AVR_COND_EQ)]>;

def BRNEk : FBRsk<1, 0b001, (outs),
(ins relbrtarget_7
: $target),
"brne\t$target", [(AVRbrcond bb
: $target, AVR_COND_NE)]>;
: $k),
"brne\t$k", [(AVRbrcond bb
: $k, AVR_COND_NE)]>;

def BRSHk : FBRsk<1, 0b000, (outs),
(ins relbrtarget_7
: $target),
"brsh\t$target", [(AVRbrcond bb
: $target, AVR_COND_SH)]>;
: $k),
"brsh\t$k", [(AVRbrcond bb
: $k, AVR_COND_SH)]>;

def BRLOk : FBRsk<0, 0b000, (outs),
(ins relbrtarget_7
: $target),
"brlo\t$target", [(AVRbrcond bb
: $target, AVR_COND_LO)]>;
: $k),
"brlo\t$k", [(AVRbrcond bb
: $k, AVR_COND_LO)]>;

def BRMIk : FBRsk<0, 0b010, (outs),
(ins relbrtarget_7
: $target),
"brmi\t$target", [(AVRbrcond bb
: $target, AVR_COND_MI)]>;
: $k),
"brmi\t$k", [(AVRbrcond bb
: $k, AVR_COND_MI)]>;

def BRPLk : FBRsk<1, 0b010, (outs),
(ins relbrtarget_7
: $target),
"brpl\t$target", [(AVRbrcond bb
: $target, AVR_COND_PL)]>;
: $k),
"brpl\t$k", [(AVRbrcond bb
: $k, AVR_COND_PL)]>;

def BRGEk : FBRsk<1, 0b100, (outs),
(ins relbrtarget_7
: $target),
"brge\t$target", [(AVRbrcond bb
: $target, AVR_COND_GE)]>;
: $k),
"brge\t$k", [(AVRbrcond bb
: $k, AVR_COND_GE)]>;

def BRLTk : FBRsk<0, 0b100, (outs),
(ins relbrtarget_7
: $target),
"brlt\t$target", [(AVRbrcond bb
: $target, AVR_COND_LT)]>;
: $k),
"brlt\t$k", [(AVRbrcond bb
: $k, AVR_COND_LT)]>;
}

//===----------------------------------------------------------------------===//
Expand All @@ -1246,10 +1246,10 @@ let hasSideEffects = 0 in {
"mov\t$rd, $rr", []>;

def MOVWRdRr : FMOVWRdRr<(outs DREGS
: $dst),
: $rd),
(ins DREGS
: $src),
"movw\t$dst, $src", []>,
: $rr),
"movw\t$rd, $rr", []>,
Requires<[HasMOVW]>;
}

Expand Down Expand Up @@ -1657,20 +1657,20 @@ let canFoldAsLoad = 1, isReMaterializable = 1, mayLoad = 1,

def LPMRdZ : FLPMX<0, 0,
(outs GPR8
: $dst),
: $rd),
(ins ZREG
: $z),
"lpm\t$dst, $z", []>,
"lpm\t$rd, $z", []>,
Requires<[HasLPMX]>;

// Load program memory, while postincrementing the Z register.
let Defs = [R31R30] in {
def LPMRdZPi : FLPMX<0, 1,
(outs GPR8
: $dst),
: $rd),
(ins ZREG
: $z),
"lpm\t$dst, $z+", []>,
"lpm\t$rd, $z+", []>,
Requires<[HasLPMX]>;

def LPMWRdZ : Pseudo<(outs DREGS
Expand All @@ -1696,13 +1696,13 @@ let mayLoad = 1, hasSideEffects = 0 in {
: F16<0b1001010111011000, (outs), (ins), "elpm", []>,
Requires<[HasELPM]>;

def ELPMRdZ : FLPMX<1, 0, (outs GPR8:$dst), (ins ZREG:$z),
"elpm\t$dst, $z", []>,
def ELPMRdZ : FLPMX<1, 0, (outs GPR8:$rd), (ins ZREG:$z),
"elpm\t$rd, $z", []>,
Requires<[HasELPMX]>;

let Defs = [R31R30] in {
def ELPMRdZPi : FLPMX<1, 1, (outs GPR8:$dst), (ins ZREG:$z),
"elpm\t$dst, $z+", []>,
def ELPMRdZPi : FLPMX<1, 1, (outs GPR8:$rd), (ins ZREG:$z),
"elpm\t$rd, $z+", []>,
Requires<[HasELPMX]>;
}

Expand Down Expand Up @@ -1742,12 +1742,12 @@ let Uses = [R1, R0] in {
// Read data from IO location operations.
let canFoldAsLoad = 1, isReMaterializable = 1 in {
def INRdA : FIORdA<(outs GPR8
: $dst),
: $rd),
(ins imm_port6
: $src),
"in\t$dst, $src", [(set i8
: $dst, (load ioaddr8
: $src))]>;
: $A),
"in\t$rd, $A", [(set i8
: $rd, (load ioaddr8
: $A))]>;

def INWRdA : Pseudo<(outs DREGS
: $dst),
Expand All @@ -1761,11 +1761,11 @@ let canFoldAsLoad = 1, isReMaterializable = 1 in {
// Write data to IO location operations.
def OUTARr : FIOARr<(outs),
(ins imm_port6
: $dst, GPR8
: $src),
"out\t$dst, $src", [(store i8
: $src, ioaddr8
: $dst)]>;
: $A, GPR8
: $rr),
"out\t$A, $rr", [(store i8
: $rr, ioaddr8
: $A)]>;

def OUTWARr : Pseudo<(outs),
(ins imm_port6
Expand All @@ -1781,8 +1781,8 @@ let Defs = [SP], Uses = [SP], hasSideEffects = 0 in {
let mayStore = 1 in {
def PUSHRr : FRd<0b1001, 0b0011111, (outs),
(ins GPR8
: $reg),
"push\t$reg", []>,
: $rd),
"push\t$rd", []>,
Requires<[HasSRAM]>;

def PUSHWRr : Pseudo<(outs),
Expand All @@ -1796,8 +1796,8 @@ let Defs = [SP], Uses = [SP], hasSideEffects = 0 in {
let mayLoad = 1 in {
def POPRd : FRd<0b1001, 0b0001111,
(outs GPR8
: $reg),
(ins), "pop\t$reg", []>,
: $rd),
(ins), "pop\t$rd", []>,
Requires<[HasSRAM]>;

def POPWRd : Pseudo<(outs DREGS
Expand Down Expand Up @@ -2060,22 +2060,22 @@ let Constraints =
def SBIAb : FIOBIT<0b10, (outs),
(ins imm_port5
: $addr, i8imm
: $bit),
"sbi\t$addr, $bit", [(store(or(i8(load lowioaddr8
: $b),
"sbi\t$addr, $b", [(store(or(i8(load lowioaddr8
: $addr)),
iobitpos8
: $bit),
: $b),
lowioaddr8
: $addr)]>;

def CBIAb : FIOBIT<0b00, (outs),
(ins imm_port5
: $addr, i8imm
: $bit),
"cbi\t$addr, $bit", [(store(and(i8(load lowioaddr8
: $b),
"cbi\t$addr, $b", [(store(and(i8(load lowioaddr8
: $addr)),
iobitposn8
: $bit),
: $b),
lowioaddr8
: $addr)]>;

Expand Down
4 changes: 1 addition & 3 deletions llvm/lib/Target/Lanai/Lanai.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -21,9 +21,7 @@ include "LanaiRegisterInfo.td"
include "LanaiCallingConv.td"
include "LanaiInstrInfo.td"

def LanaiInstrInfo : InstrInfo {
let useDeprecatedPositionallyEncodedOperands = 1;
}
def LanaiInstrInfo : InstrInfo;

//===----------------------------------------------------------------------===//
// Lanai processors supported.
Expand Down
12 changes: 6 additions & 6 deletions llvm/lib/Target/Lanai/LanaiInstrFormats.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -197,8 +197,8 @@ class InstRM<bit S, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstLanai<outs, ins, asmstr, pattern> {
bits<5> Rd;
bits<5> Rs1;
bit P;
bit Q;
bits<1> P;
bits<1> Q;
bits<16> imm16;
// Dummy variables to allow multiclass definition of RM and RRM
bits<2> YL;
Expand Down Expand Up @@ -259,8 +259,8 @@ class InstRRM<bit S, dag outs, dag ins, string asmstr,
bits<5> Rd;
bits<5> Rs1;
bits<5> Rs2;
bit P;
bit Q;
bits<1> P;
bits<1> Q;
bits<3> BBB;
bits<5> JJJJJ;
bits<2> YL;
Expand Down Expand Up @@ -504,8 +504,8 @@ class InstSPLS<dag outs, dag ins, string asmstr,
bit Y;
bit S;
bit E;
bit P;
bit Q;
bits<1> P;
bits<1> Q;
bits<10> imm10;

let Opcode = 0b1111;
Expand Down
87 changes: 85 additions & 2 deletions llvm/test/MC/AVR/inst-family-cond-branch.s
View file
Original file line number Diff line number Diff line change
@@ -1,4 +1,6 @@
; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
; RUN: llvm-mc -filetype=obj -triple avr < %s \
; RUN: | llvm-objdump -d - | FileCheck --check-prefix=INST %s


foo:
Expand All @@ -17,6 +19,12 @@ foo:
; CHECK: brbs 1, baz ; encoding: [0bAAAAA001,0b111100AA]
; CHECK: ; fixup A - offset: 0, value: baz, kind: fixup_7_pcrel

; INST-LABEL: <foo>:
; INST: breq .+0
; INST: breq .+0
; INST: breq .+0
; INST: breq .+0

; BRNE
brne .+10
brne .+2
Expand All @@ -32,6 +40,11 @@ foo:
; CHECK: brbc 1, bar ; encoding: [0bAAAAA001,0b111101AA]
; CHECK: ; fixup A - offset: 0, value: bar, kind: fixup_7_pcrel

; INST: brne .+0
; INST: brne .+0
; INST: brne .+0
; INST: brne .+0

bar:
; BRCS
brcs .+8
Expand All @@ -48,6 +61,12 @@ bar:
; CHECK: brcs end ; encoding: [0bAAAAA000,0b111100AA]
; CHECK: ; fixup A - offset: 0, value: end, kind: fixup_7_pcrel

; INST-LABEL: <bar>:
; INST: brlo .+0
; INST: brlo .+0
; INST: brlo .+0
; INST: brlo .+0

; BRCC
brcc .+66
brcc .-22
Expand All @@ -63,7 +82,12 @@ bar:
; CHECK: brcc baz ; encoding: [0bAAAAA000,0b111101AA]
; CHECK: ; fixup A - offset: 0, value: baz, kind: fixup_7_pcrel

; BRSH
; INST: brsh .+0
; INST: brsh .+0
; INST: brsh .+0
; INST: brsh .+0

; BRSH
brsh .+32
brsh .+70
brsh car
Expand All @@ -75,6 +99,10 @@ bar:
; CHECK: brsh car ; encoding: [0bAAAAA000,0b111101AA]
; CHECK: ; fixup A - offset: 0, value: car, kind: fixup_7_pcrel

; INST: brsh .+0
; INST: brsh .+0
; INST: brsh .+0

baz:

; BRLO
Expand All @@ -89,6 +117,11 @@ baz:
; CHECK: brlo car ; encoding: [0bAAAAA000,0b111100AA]
; CHECK: ; fixup A - offset: 0, value: car, kind: fixup_7_pcrel

; INST-LABEL: <baz>:
; INST: brlo .+0
; INST: brlo .+0
; INST: brlo .+0

; BRMI
brmi .+66
brmi .+58
Expand All @@ -101,6 +134,10 @@ baz:
; CHECK: brmi car ; encoding: [0bAAAAA010,0b111100AA]
; CHECK: ; fixup A - offset: 0, value: car, kind: fixup_7_pcrel

; INST: brmi .+0
; INST: brmi .+0
; INST: brmi .+0

; BRPL
brpl .-12
brpl .+18
Expand All @@ -113,7 +150,11 @@ baz:
; CHECK: brpl car ; encoding: [0bAAAAA010,0b111101AA]
; CHECK: ; fixup A - offset: 0, value: car, kind: fixup_7_pcrel

; BRGE
; INST: brpl .+0
; INST: brpl .+0
; INST: brpl .+0

; BRGE
brge .+50
brge .+42
brge car
Expand All @@ -125,6 +166,10 @@ baz:
; CHECK: brge car ; encoding: [0bAAAAA100,0b111101AA]
; CHECK: ; fixup A - offset: 0, value: car, kind: fixup_7_pcrel

; INST: brge .+0
; INST: brge .+0
; INST: brge .+0

car:
; BRLT
brlt .+16
Expand All @@ -138,6 +183,11 @@ car:
; CHECK: brlt end ; encoding: [0bAAAAA100,0b111100AA]
; CHECK: ; fixup A - offset: 0, value: end, kind: fixup_7_pcrel

; INST-LABEL: <car>:
; INST: brlt .+0
; INST: brlt .+0
; INST: brlt .+0

; BRHS
brhs .-66
brhs .+14
Expand All @@ -150,6 +200,10 @@ car:
; CHECK: brhs just_another_label ; encoding: [0bAAAAA101,0b111100AA]
; CHECK: ; fixup A - offset: 0, value: just_another_label, kind: fixup_7_pcrel

; INST: brhs .+0
; INST: brhs .+0
; INST: brhs .+0

; BRHC
brhc .+12
brhc .+14
Expand All @@ -162,6 +216,10 @@ car:
; CHECK: brhc just_another_label ; encoding: [0bAAAAA101,0b111101AA]
; CHECK: ; fixup A - offset: 0, value: just_another_label, kind: fixup_7_pcrel

; INST: brhc .+0
; INST: brhc .+0
; INST: brhc .+0

; BRTS
brts .+18
brts .+22
Expand All @@ -174,6 +232,10 @@ car:
; CHECK: brts just_another_label ; encoding: [0bAAAAA110,0b111100AA]
; CHECK: ; fixup A - offset: 0, value: just_another_label, kind: fixup_7_pcrel

; INST: brts .+0
; INST: brts .+0
; INST: brts .+0

just_another_label:
; BRTC
brtc .+52
Expand All @@ -187,6 +249,11 @@ just_another_label:
; CHECK: brtc end ; encoding: [0bAAAAA110,0b111101AA]
; CHECK: ; fixup A - offset: 0, value: end, kind: fixup_7_pcrel

; INST-LABEL: <just_another_label>:
; INST: brtc .+0
; INST: brtc .+0
; INST: brtc .+0

; BRVS
brvs .+18
brvs .+32
Expand All @@ -199,6 +266,10 @@ just_another_label:
; CHECK: brvs end ; encoding: [0bAAAAA011,0b111100AA]
; CHECK: ; fixup A - offset: 0, value: end, kind: fixup_7_pcrel

; INST: brvs .+0
; INST: brvs .+0
; INST: brvs .+0

; BRVC
brvc .-28
brvc .-62
Expand All @@ -211,6 +282,10 @@ just_another_label:
; CHECK: brvc end ; encoding: [0bAAAAA011,0b111101AA]
; CHECK: ; fixup A - offset: 0, value: end, kind: fixup_7_pcrel

; INST: brvc .+0
; INST: brvc .+0
; INST: brvc .+0

; BRIE
brie .+20
brie .+40
Expand All @@ -223,6 +298,10 @@ just_another_label:
; CHECK: brie end ; encoding: [0bAAAAA111,0b111100AA]
; CHECK: ; fixup A - offset: 0, value: end, kind: fixup_7_pcrel

; INST: brie .+0
; INST: brie .+0
; INST: brie .+0

; BRID
brid .+42
brid .+62
Expand All @@ -235,4 +314,8 @@ just_another_label:
; CHECK: brid end ; encoding: [0bAAAAA111,0b111101AA]
; CHECK: ; fixup A - offset: 0, value: end, kind: fixup_7_pcrel

; INST: brid .+0
; INST: brid .+0
; INST: brid .+0

end:
7 changes: 7 additions & 0 deletions llvm/test/MC/AVR/inst-mul.s
View file
Original file line number Diff line number Diff line change
@@ -1,4 +1,6 @@
; RUN: llvm-mc -triple avr -mattr=mul -show-encoding < %s | FileCheck %s
; RUN: llvm-mc -filetype=obj -triple avr -mattr=mul < %s \
; RUN: | llvm-objdump -d --mattr=mul - | FileCheck --check-prefix=INST %s


foo:
Expand All @@ -11,3 +13,8 @@ foo:
; CHECK: mul r15, r0 ; encoding: [0xf0,0x9c]
; CHECK: mul r16, r31 ; encoding: [0x0f,0x9f]
; CHECK: mul r31, r16 ; encoding: [0xf0,0x9f]

; INST: mul r0, r15
; INST: mul r15, r0
; INST: mul r16, r31
; INST: mul r31, r16
11 changes: 11 additions & 0 deletions llvm/test/MC/AVR/inst-rjmp.s
View file
Original file line number Diff line number Diff line change
@@ -1,4 +1,6 @@
; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
; RUN: llvm-mc -filetype=obj -triple avr < %s \
; RUN: | llvm-objdump -d - | FileCheck --check-prefix=INST %s


foo:
Expand Down Expand Up @@ -29,3 +31,12 @@ end:
; CHECK: ; fixup A - offset: 0, value: .Ltmp4-4, kind: fixup_13_pcrel
; CHECK: rjmp .Ltmp5-6 ; encoding: [A,0b1100AAAA]
; CHECK: ; fixup A - offset: 0, value: .Ltmp5-6, kind: fixup_13_pcrel

; INST: rjmp .+0
; INST: rjmp .+0
; INST: rjmp .+0
; INST: rjmp .+0
; INST: rjmp .+0
; INST: rjmp .+0
; INST: rjmp .+0
; INST: rjmp .+0
4 changes: 4 additions & 0 deletions llvm/test/MC/AVR/inst-sbrc.s
View file
Original file line number Diff line number Diff line change
@@ -1,4 +1,6 @@
; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
; RUN: llvm-mc -filetype=obj -triple avr < %s \
; RUN: | llvm-objdump -d - | FileCheck --check-prefix=INST %s


foo:
Expand All @@ -9,3 +11,5 @@ foo:
; CHECK: sbrc r2, 3 ; encoding: [0x23,0xfc]
; CHECK: sbrc r0, 7 ; encoding: [0x07,0xfc]

; INST: sbrc r2, 3
; INST: sbrc r0, 7
4 changes: 4 additions & 0 deletions llvm/test/MC/AVR/inst-sbrs.s
View file
Original file line number Diff line number Diff line change
@@ -1,4 +1,6 @@
; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
; RUN: llvm-mc -filetype=obj -triple avr < %s \
; RUN: | llvm-objdump -d - | FileCheck --check-prefix=INST %s


foo:
Expand All @@ -9,3 +11,5 @@ foo:
; CHECK: sbrs r2, 3 ; encoding: [0x23,0xfe]
; CHECK: sbrs r0, 7 ; encoding: [0x07,0xfe]

; INST: sbrs r2, 3
; INST: sbrs r0, 7