384 changes: 384 additions & 0 deletions llvm/test/CodeGen/RISCV/signbit-test.ll
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Original file line number Diff line number Diff line change
@@ -0,0 +1,384 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s | FileCheck -check-prefixes=RV32 %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck -check-prefixes=RV64 %s

define i64 @test_clear_mask_i64_i32(i64 %x) nounwind {
; RV32-LABEL: test_clear_mask_i64_i32:
; RV32: # %bb.0: # %entry
; RV32-NEXT: bltz a0, .LBB0_2
; RV32-NEXT: # %bb.1: # %t
; RV32-NEXT: li a1, 0
; RV32-NEXT: li a0, 42
; RV32-NEXT: .LBB0_2: # %f
; RV32-NEXT: ret
;
; RV64-LABEL: test_clear_mask_i64_i32:
; RV64: # %bb.0: # %entry
; RV64-NEXT: slli a1, a0, 32
; RV64-NEXT: bltz a1, .LBB0_2
; RV64-NEXT: # %bb.1: # %t
; RV64-NEXT: li a0, 42
; RV64-NEXT: .LBB0_2: # %f
; RV64-NEXT: ret
entry:
%a = and i64 %x, 2147483648
%r = icmp eq i64 %a, 0
br i1 %r, label %t, label %f
t:
br label %f
f:
%ret = phi i64 [ %x, %entry], [ 42, %t]
ret i64 %ret
}

define i64 @test_set_mask_i64_i32(i64 %x) nounwind {
; RV32-LABEL: test_set_mask_i64_i32:
; RV32: # %bb.0: # %entry
; RV32-NEXT: bgez a0, .LBB1_2
; RV32-NEXT: # %bb.1: # %t
; RV32-NEXT: li a1, 0
; RV32-NEXT: li a0, 42
; RV32-NEXT: .LBB1_2: # %f
; RV32-NEXT: ret
;
; RV64-LABEL: test_set_mask_i64_i32:
; RV64: # %bb.0: # %entry
; RV64-NEXT: slli a1, a0, 32
; RV64-NEXT: bgez a1, .LBB1_2
; RV64-NEXT: # %bb.1: # %t
; RV64-NEXT: li a0, 42
; RV64-NEXT: .LBB1_2: # %f
; RV64-NEXT: ret
entry:
%a = and i64 %x, 2147483648
%r = icmp ne i64 %a, 0
br i1 %r, label %t, label %f
t:
br label %f
f:
%ret = phi i64 [ %x, %entry], [ 42, %t]
ret i64 %ret
}

define i64 @test_clear_mask_i64_i16(i64 %x) nounwind {
; RV32-LABEL: test_clear_mask_i64_i16:
; RV32: # %bb.0: # %entry
; RV32-NEXT: slli a2, a0, 16
; RV32-NEXT: bltz a2, .LBB2_2
; RV32-NEXT: # %bb.1: # %t
; RV32-NEXT: li a1, 0
; RV32-NEXT: li a0, 42
; RV32-NEXT: .LBB2_2: # %f
; RV32-NEXT: ret
;
; RV64-LABEL: test_clear_mask_i64_i16:
; RV64: # %bb.0: # %entry
; RV64-NEXT: slli a1, a0, 48
; RV64-NEXT: bltz a1, .LBB2_2
; RV64-NEXT: # %bb.1: # %t
; RV64-NEXT: li a0, 42
; RV64-NEXT: .LBB2_2: # %f
; RV64-NEXT: ret
entry:
%a = and i64 %x, 32768
%r = icmp eq i64 %a, 0
br i1 %r, label %t, label %f
t:
br label %f
f:
%ret = phi i64 [ %x, %entry], [ 42, %t]
ret i64 %ret
}

define i64 @test_set_mask_i64_i16(i64 %x) nounwind {
; RV32-LABEL: test_set_mask_i64_i16:
; RV32: # %bb.0: # %entry
; RV32-NEXT: slli a2, a0, 16
; RV32-NEXT: bgez a2, .LBB3_2
; RV32-NEXT: # %bb.1: # %t
; RV32-NEXT: li a1, 0
; RV32-NEXT: li a0, 42
; RV32-NEXT: .LBB3_2: # %f
; RV32-NEXT: ret
;
; RV64-LABEL: test_set_mask_i64_i16:
; RV64: # %bb.0: # %entry
; RV64-NEXT: slli a1, a0, 48
; RV64-NEXT: bgez a1, .LBB3_2
; RV64-NEXT: # %bb.1: # %t
; RV64-NEXT: li a0, 42
; RV64-NEXT: .LBB3_2: # %f
; RV64-NEXT: ret
entry:
%a = and i64 %x, 32768
%r = icmp ne i64 %a, 0
br i1 %r, label %t, label %f
t:
br label %f
f:
%ret = phi i64 [ %x, %entry], [ 42, %t]
ret i64 %ret
}

define i64 @test_clear_mask_i64_i8(i64 %x) nounwind {
; RV32-LABEL: test_clear_mask_i64_i8:
; RV32: # %bb.0: # %entry
; RV32-NEXT: andi a2, a0, 128
; RV32-NEXT: bnez a2, .LBB4_2
; RV32-NEXT: # %bb.1: # %t
; RV32-NEXT: li a1, 0
; RV32-NEXT: li a0, 42
; RV32-NEXT: .LBB4_2: # %f
; RV32-NEXT: ret
;
; RV64-LABEL: test_clear_mask_i64_i8:
; RV64: # %bb.0: # %entry
; RV64-NEXT: andi a1, a0, 128
; RV64-NEXT: bnez a1, .LBB4_2
; RV64-NEXT: # %bb.1: # %t
; RV64-NEXT: li a0, 42
; RV64-NEXT: .LBB4_2: # %f
; RV64-NEXT: ret
entry:
%a = and i64 %x, 128
%r = icmp eq i64 %a, 0
br i1 %r, label %t, label %f
t:
br label %f
f:
%ret = phi i64 [ %x, %entry], [ 42, %t]
ret i64 %ret
}

define i64 @test_set_mask_i64_i8(i64 %x) nounwind {
; RV32-LABEL: test_set_mask_i64_i8:
; RV32: # %bb.0: # %entry
; RV32-NEXT: andi a2, a0, 128
; RV32-NEXT: beqz a2, .LBB5_2
; RV32-NEXT: # %bb.1: # %t
; RV32-NEXT: li a1, 0
; RV32-NEXT: li a0, 42
; RV32-NEXT: .LBB5_2: # %f
; RV32-NEXT: ret
;
; RV64-LABEL: test_set_mask_i64_i8:
; RV64: # %bb.0: # %entry
; RV64-NEXT: andi a1, a0, 128
; RV64-NEXT: beqz a1, .LBB5_2
; RV64-NEXT: # %bb.1: # %t
; RV64-NEXT: li a0, 42
; RV64-NEXT: .LBB5_2: # %f
; RV64-NEXT: ret
entry:
%a = and i64 %x, 128
%r = icmp ne i64 %a, 0
br i1 %r, label %t, label %f
t:
br label %f
f:
%ret = phi i64 [ %x, %entry], [ 42, %t]
ret i64 %ret
}

define i32 @test_clear_mask_i32_i16(i32 %x) nounwind {
; RV32-LABEL: test_clear_mask_i32_i16:
; RV32: # %bb.0: # %entry
; RV32-NEXT: slli a1, a0, 16
; RV32-NEXT: bltz a1, .LBB6_2
; RV32-NEXT: # %bb.1: # %t
; RV32-NEXT: li a0, 42
; RV32-NEXT: .LBB6_2: # %f
; RV32-NEXT: ret
;
; RV64-LABEL: test_clear_mask_i32_i16:
; RV64: # %bb.0: # %entry
; RV64-NEXT: slli a1, a0, 48
; RV64-NEXT: bltz a1, .LBB6_2
; RV64-NEXT: # %bb.1: # %t
; RV64-NEXT: li a0, 42
; RV64-NEXT: .LBB6_2: # %f
; RV64-NEXT: ret
entry:
%a = and i32 %x, 32768
%r = icmp eq i32 %a, 0
br i1 %r, label %t, label %f
t:
br label %f
f:
%ret = phi i32 [ %x, %entry], [ 42, %t]
ret i32 %ret
}

define i32 @test_set_mask_i32_i16(i32 %x) nounwind {
; RV32-LABEL: test_set_mask_i32_i16:
; RV32: # %bb.0: # %entry
; RV32-NEXT: slli a1, a0, 16
; RV32-NEXT: bgez a1, .LBB7_2
; RV32-NEXT: # %bb.1: # %t
; RV32-NEXT: li a0, 42
; RV32-NEXT: .LBB7_2: # %f
; RV32-NEXT: ret
;
; RV64-LABEL: test_set_mask_i32_i16:
; RV64: # %bb.0: # %entry
; RV64-NEXT: slli a1, a0, 48
; RV64-NEXT: bgez a1, .LBB7_2
; RV64-NEXT: # %bb.1: # %t
; RV64-NEXT: li a0, 42
; RV64-NEXT: .LBB7_2: # %f
; RV64-NEXT: ret
entry:
%a = and i32 %x, 32768
%r = icmp ne i32 %a, 0
br i1 %r, label %t, label %f
t:
br label %f
f:
%ret = phi i32 [ %x, %entry], [ 42, %t]
ret i32 %ret
}

define i32 @test_clear_mask_i32_i8(i32 %x) nounwind {
; RV32-LABEL: test_clear_mask_i32_i8:
; RV32: # %bb.0: # %entry
; RV32-NEXT: andi a1, a0, 128
; RV32-NEXT: bnez a1, .LBB8_2
; RV32-NEXT: # %bb.1: # %t
; RV32-NEXT: li a0, 42
; RV32-NEXT: .LBB8_2: # %f
; RV32-NEXT: ret
;
; RV64-LABEL: test_clear_mask_i32_i8:
; RV64: # %bb.0: # %entry
; RV64-NEXT: andi a1, a0, 128
; RV64-NEXT: bnez a1, .LBB8_2
; RV64-NEXT: # %bb.1: # %t
; RV64-NEXT: li a0, 42
; RV64-NEXT: .LBB8_2: # %f
; RV64-NEXT: ret
entry:
%a = and i32 %x, 128
%r = icmp eq i32 %a, 0
br i1 %r, label %t, label %f
t:
br label %f
f:
%ret = phi i32 [ %x, %entry], [ 42, %t]
ret i32 %ret
}

define i32 @test_set_mask_i32_i8(i32 %x) nounwind {
; RV32-LABEL: test_set_mask_i32_i8:
; RV32: # %bb.0: # %entry
; RV32-NEXT: andi a1, a0, 128
; RV32-NEXT: beqz a1, .LBB9_2
; RV32-NEXT: # %bb.1: # %t
; RV32-NEXT: li a0, 42
; RV32-NEXT: .LBB9_2: # %f
; RV32-NEXT: ret
;
; RV64-LABEL: test_set_mask_i32_i8:
; RV64: # %bb.0: # %entry
; RV64-NEXT: andi a1, a0, 128
; RV64-NEXT: beqz a1, .LBB9_2
; RV64-NEXT: # %bb.1: # %t
; RV64-NEXT: li a0, 42
; RV64-NEXT: .LBB9_2: # %f
; RV64-NEXT: ret
entry:
%a = and i32 %x, 128
%r = icmp ne i32 %a, 0
br i1 %r, label %t, label %f
t:
br label %f
f:
%ret = phi i32 [ %x, %entry], [ 42, %t]
ret i32 %ret
}

define i16 @test_clear_mask_i16_i8(i16 %x) nounwind {
; RV32-LABEL: test_clear_mask_i16_i8:
; RV32: # %bb.0: # %entry
; RV32-NEXT: andi a1, a0, 128
; RV32-NEXT: bnez a1, .LBB10_2
; RV32-NEXT: # %bb.1: # %t
; RV32-NEXT: li a0, 42
; RV32-NEXT: .LBB10_2: # %f
; RV32-NEXT: ret
;
; RV64-LABEL: test_clear_mask_i16_i8:
; RV64: # %bb.0: # %entry
; RV64-NEXT: andi a1, a0, 128
; RV64-NEXT: bnez a1, .LBB10_2
; RV64-NEXT: # %bb.1: # %t
; RV64-NEXT: li a0, 42
; RV64-NEXT: .LBB10_2: # %f
; RV64-NEXT: ret
entry:
%a = and i16 %x, 128
%r = icmp eq i16 %a, 0
br i1 %r, label %t, label %f
t:
br label %f
f:
%ret = phi i16 [ %x, %entry], [ 42, %t]
ret i16 %ret
}

define i16 @test_set_mask_i16_i8(i16 %x) nounwind {
; RV32-LABEL: test_set_mask_i16_i8:
; RV32: # %bb.0: # %entry
; RV32-NEXT: andi a1, a0, 128
; RV32-NEXT: beqz a1, .LBB11_2
; RV32-NEXT: # %bb.1: # %t
; RV32-NEXT: li a0, 42
; RV32-NEXT: .LBB11_2: # %f
; RV32-NEXT: ret
;
; RV64-LABEL: test_set_mask_i16_i8:
; RV64: # %bb.0: # %entry
; RV64-NEXT: andi a1, a0, 128
; RV64-NEXT: beqz a1, .LBB11_2
; RV64-NEXT: # %bb.1: # %t
; RV64-NEXT: li a0, 42
; RV64-NEXT: .LBB11_2: # %f
; RV64-NEXT: ret
entry:
%a = and i16 %x, 128
%r = icmp ne i16 %a, 0
br i1 %r, label %t, label %f
t:
br label %f
f:
%ret = phi i16 [ %x, %entry], [ 42, %t]
ret i16 %ret
}

define i16 @test_set_mask_i16_i7(i16 %x) nounwind {
; RV32-LABEL: test_set_mask_i16_i7:
; RV32: # %bb.0: # %entry
; RV32-NEXT: andi a1, a0, 64
; RV32-NEXT: beqz a1, .LBB12_2
; RV32-NEXT: # %bb.1: # %t
; RV32-NEXT: li a0, 42
; RV32-NEXT: .LBB12_2: # %f
; RV32-NEXT: ret
;
; RV64-LABEL: test_set_mask_i16_i7:
; RV64: # %bb.0: # %entry
; RV64-NEXT: andi a1, a0, 64
; RV64-NEXT: beqz a1, .LBB12_2
; RV64-NEXT: # %bb.1: # %t
; RV64-NEXT: li a0, 42
; RV64-NEXT: .LBB12_2: # %f
; RV64-NEXT: ret
entry:
%a = and i16 %x, 64
%r = icmp ne i16 %a, 0
br i1 %r, label %t, label %f
t:
br label %f
f:
%ret = phi i16 [ %x, %entry], [ 42, %t]
ret i16 %ret
}
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/X86/btq.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -27,8 +27,8 @@ if.end:
define void @test2(i64 %foo) nounwind {
; CHECK-LABEL: test2:
; CHECK: # %bb.0:
; CHECK-NEXT: testl $-2147483648, %edi # imm = 0x80000000
; CHECK-NEXT: jne .LBB1_2
; CHECK-NEXT: testl %edi, %edi
; CHECK-NEXT: js .LBB1_2
; CHECK-NEXT: # %bb.1: # %if.end
; CHECK-NEXT: retq
; CHECK-NEXT: .LBB1_2: # %if.then
Expand Down
124 changes: 62 additions & 62 deletions llvm/test/CodeGen/X86/masked_compressstore.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -273,8 +273,8 @@ define void @compressstore_v16f64_v16i1(ptr %base, <16 x double> %V, <16 x i1> %
; SSE-NEXT: testb $64, %al
; SSE-NEXT: jne LBB1_13
; SSE-NEXT: LBB1_14: ## %else17
; SSE-NEXT: testb $-128, %al
; SSE-NEXT: jne LBB1_15
; SSE-NEXT: testb %al, %al
; SSE-NEXT: js LBB1_15
; SSE-NEXT: LBB1_16: ## %else20
; SSE-NEXT: testl $256, %eax ## imm = 0x100
; SSE-NEXT: jne LBB1_17
Expand Down Expand Up @@ -334,8 +334,8 @@ define void @compressstore_v16f64_v16i1(ptr %base, <16 x double> %V, <16 x i1> %
; SSE-NEXT: LBB1_13: ## %cond.store16
; SSE-NEXT: movlps %xmm3, (%rdi)
; SSE-NEXT: addq $8, %rdi
; SSE-NEXT: testb $-128, %al
; SSE-NEXT: je LBB1_16
; SSE-NEXT: testb %al, %al
; SSE-NEXT: jns LBB1_16
; SSE-NEXT: LBB1_15: ## %cond.store19
; SSE-NEXT: movhps %xmm3, (%rdi)
; SSE-NEXT: addq $8, %rdi
Expand Down Expand Up @@ -416,8 +416,8 @@ define void @compressstore_v16f64_v16i1(ptr %base, <16 x double> %V, <16 x i1> %
; AVX1OR2-NEXT: vextractf128 $1, %ymm1, %xmm0
; AVX1OR2-NEXT: jne LBB1_13
; AVX1OR2-NEXT: ## %bb.14: ## %else17
; AVX1OR2-NEXT: testb $-128, %al
; AVX1OR2-NEXT: jne LBB1_15
; AVX1OR2-NEXT: testb %al, %al
; AVX1OR2-NEXT: js LBB1_15
; AVX1OR2-NEXT: LBB1_16: ## %else20
; AVX1OR2-NEXT: testl $256, %eax ## imm = 0x100
; AVX1OR2-NEXT: jne LBB1_17
Expand Down Expand Up @@ -472,8 +472,8 @@ define void @compressstore_v16f64_v16i1(ptr %base, <16 x double> %V, <16 x i1> %
; AVX1OR2-NEXT: LBB1_13: ## %cond.store16
; AVX1OR2-NEXT: vmovlps %xmm0, (%rdi)
; AVX1OR2-NEXT: addq $8, %rdi
; AVX1OR2-NEXT: testb $-128, %al
; AVX1OR2-NEXT: je LBB1_16
; AVX1OR2-NEXT: testb %al, %al
; AVX1OR2-NEXT: jns LBB1_16
; AVX1OR2-NEXT: LBB1_15: ## %cond.store19
; AVX1OR2-NEXT: vmovhps %xmm0, (%rdi)
; AVX1OR2-NEXT: addq $8, %rdi
Expand Down Expand Up @@ -1311,8 +1311,8 @@ define void @compressstore_v32f32_v32i32(ptr %base, <32 x float> %V, <32 x i32>
; SSE2-NEXT: testb $64, %al
; SSE2-NEXT: jne LBB6_13
; SSE2-NEXT: LBB6_14: ## %else17
; SSE2-NEXT: testb $-128, %al
; SSE2-NEXT: jne LBB6_15
; SSE2-NEXT: testb %al, %al
; SSE2-NEXT: js LBB6_15
; SSE2-NEXT: LBB6_16: ## %else20
; SSE2-NEXT: testl $256, %eax ## imm = 0x100
; SSE2-NEXT: jne LBB6_17
Expand All @@ -1335,8 +1335,8 @@ define void @compressstore_v32f32_v32i32(ptr %base, <32 x float> %V, <32 x i32>
; SSE2-NEXT: testl $16384, %eax ## imm = 0x4000
; SSE2-NEXT: jne LBB6_29
; SSE2-NEXT: LBB6_30: ## %else41
; SSE2-NEXT: testl $32768, %eax ## imm = 0x8000
; SSE2-NEXT: jne LBB6_31
; SSE2-NEXT: testw %ax, %ax
; SSE2-NEXT: js LBB6_31
; SSE2-NEXT: LBB6_32: ## %else44
; SSE2-NEXT: testl $65536, %eax ## imm = 0x10000
; SSE2-NEXT: jne LBB6_33
Expand Down Expand Up @@ -1429,8 +1429,8 @@ define void @compressstore_v32f32_v32i32(ptr %base, <32 x float> %V, <32 x i32>
; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
; SSE2-NEXT: movss %xmm0, (%rdi)
; SSE2-NEXT: addq $4, %rdi
; SSE2-NEXT: testb $-128, %al
; SSE2-NEXT: je LBB6_16
; SSE2-NEXT: testb %al, %al
; SSE2-NEXT: jns LBB6_16
; SSE2-NEXT: LBB6_15: ## %cond.store19
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; SSE2-NEXT: movss %xmm1, (%rdi)
Expand Down Expand Up @@ -1479,8 +1479,8 @@ define void @compressstore_v32f32_v32i32(ptr %base, <32 x float> %V, <32 x i32>
; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm3[1]
; SSE2-NEXT: movss %xmm0, (%rdi)
; SSE2-NEXT: addq $4, %rdi
; SSE2-NEXT: testl $32768, %eax ## imm = 0x8000
; SSE2-NEXT: je LBB6_32
; SSE2-NEXT: testw %ax, %ax
; SSE2-NEXT: jns LBB6_32
; SSE2-NEXT: LBB6_31: ## %cond.store43
; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3,3,3]
; SSE2-NEXT: movss %xmm3, (%rdi)
Expand Down Expand Up @@ -1635,8 +1635,8 @@ define void @compressstore_v32f32_v32i32(ptr %base, <32 x float> %V, <32 x i32>
; SSE42-NEXT: testb $64, %al
; SSE42-NEXT: jne LBB6_13
; SSE42-NEXT: LBB6_14: ## %else17
; SSE42-NEXT: testb $-128, %al
; SSE42-NEXT: jne LBB6_15
; SSE42-NEXT: testb %al, %al
; SSE42-NEXT: js LBB6_15
; SSE42-NEXT: LBB6_16: ## %else20
; SSE42-NEXT: testl $256, %eax ## imm = 0x100
; SSE42-NEXT: jne LBB6_17
Expand All @@ -1659,8 +1659,8 @@ define void @compressstore_v32f32_v32i32(ptr %base, <32 x float> %V, <32 x i32>
; SSE42-NEXT: testl $16384, %eax ## imm = 0x4000
; SSE42-NEXT: jne LBB6_29
; SSE42-NEXT: LBB6_30: ## %else41
; SSE42-NEXT: testl $32768, %eax ## imm = 0x8000
; SSE42-NEXT: jne LBB6_31
; SSE42-NEXT: testw %ax, %ax
; SSE42-NEXT: js LBB6_31
; SSE42-NEXT: LBB6_32: ## %else44
; SSE42-NEXT: testl $65536, %eax ## imm = 0x10000
; SSE42-NEXT: jne LBB6_33
Expand Down Expand Up @@ -1744,8 +1744,8 @@ define void @compressstore_v32f32_v32i32(ptr %base, <32 x float> %V, <32 x i32>
; SSE42-NEXT: LBB6_13: ## %cond.store16
; SSE42-NEXT: extractps $2, %xmm1, (%rdi)
; SSE42-NEXT: addq $4, %rdi
; SSE42-NEXT: testb $-128, %al
; SSE42-NEXT: je LBB6_16
; SSE42-NEXT: testb %al, %al
; SSE42-NEXT: jns LBB6_16
; SSE42-NEXT: LBB6_15: ## %cond.store19
; SSE42-NEXT: extractps $3, %xmm1, (%rdi)
; SSE42-NEXT: addq $4, %rdi
Expand Down Expand Up @@ -1784,8 +1784,8 @@ define void @compressstore_v32f32_v32i32(ptr %base, <32 x float> %V, <32 x i32>
; SSE42-NEXT: LBB6_29: ## %cond.store40
; SSE42-NEXT: extractps $2, %xmm3, (%rdi)
; SSE42-NEXT: addq $4, %rdi
; SSE42-NEXT: testl $32768, %eax ## imm = 0x8000
; SSE42-NEXT: je LBB6_32
; SSE42-NEXT: testw %ax, %ax
; SSE42-NEXT: jns LBB6_32
; SSE42-NEXT: LBB6_31: ## %cond.store43
; SSE42-NEXT: extractps $3, %xmm3, (%rdi)
; SSE42-NEXT: addq $4, %rdi
Expand Down Expand Up @@ -1920,8 +1920,8 @@ define void @compressstore_v32f32_v32i32(ptr %base, <32 x float> %V, <32 x i32>
; AVX1-NEXT: testb $64, %al
; AVX1-NEXT: jne LBB6_13
; AVX1-NEXT: LBB6_14: ## %else17
; AVX1-NEXT: testb $-128, %al
; AVX1-NEXT: jne LBB6_15
; AVX1-NEXT: testb %al, %al
; AVX1-NEXT: js LBB6_15
; AVX1-NEXT: LBB6_16: ## %else20
; AVX1-NEXT: testl $256, %eax ## imm = 0x100
; AVX1-NEXT: jne LBB6_17
Expand All @@ -1948,8 +1948,8 @@ define void @compressstore_v32f32_v32i32(ptr %base, <32 x float> %V, <32 x i32>
; AVX1-NEXT: testl $16384, %eax ## imm = 0x4000
; AVX1-NEXT: jne LBB6_29
; AVX1-NEXT: LBB6_30: ## %else41
; AVX1-NEXT: testl $32768, %eax ## imm = 0x8000
; AVX1-NEXT: jne LBB6_31
; AVX1-NEXT: testw %ax, %ax
; AVX1-NEXT: js LBB6_31
; AVX1-NEXT: LBB6_32: ## %else44
; AVX1-NEXT: testl $65536, %eax ## imm = 0x10000
; AVX1-NEXT: jne LBB6_33
Expand Down Expand Up @@ -2038,8 +2038,8 @@ define void @compressstore_v32f32_v32i32(ptr %base, <32 x float> %V, <32 x i32>
; AVX1-NEXT: LBB6_13: ## %cond.store16
; AVX1-NEXT: vextractps $2, %xmm0, (%rdi)
; AVX1-NEXT: addq $4, %rdi
; AVX1-NEXT: testb $-128, %al
; AVX1-NEXT: je LBB6_16
; AVX1-NEXT: testb %al, %al
; AVX1-NEXT: jns LBB6_16
; AVX1-NEXT: LBB6_15: ## %cond.store19
; AVX1-NEXT: vextractps $3, %xmm0, (%rdi)
; AVX1-NEXT: addq $4, %rdi
Expand Down Expand Up @@ -2074,8 +2074,8 @@ define void @compressstore_v32f32_v32i32(ptr %base, <32 x float> %V, <32 x i32>
; AVX1-NEXT: LBB6_29: ## %cond.store40
; AVX1-NEXT: vextractps $2, %xmm0, (%rdi)
; AVX1-NEXT: addq $4, %rdi
; AVX1-NEXT: testl $32768, %eax ## imm = 0x8000
; AVX1-NEXT: je LBB6_32
; AVX1-NEXT: testw %ax, %ax
; AVX1-NEXT: jns LBB6_32
; AVX1-NEXT: LBB6_31: ## %cond.store43
; AVX1-NEXT: vextractps $3, %xmm0, (%rdi)
; AVX1-NEXT: addq $4, %rdi
Expand Down Expand Up @@ -2192,8 +2192,8 @@ define void @compressstore_v32f32_v32i32(ptr %base, <32 x float> %V, <32 x i32>
; AVX2-NEXT: testb $64, %al
; AVX2-NEXT: jne LBB6_13
; AVX2-NEXT: LBB6_14: ## %else17
; AVX2-NEXT: testb $-128, %al
; AVX2-NEXT: jne LBB6_15
; AVX2-NEXT: testb %al, %al
; AVX2-NEXT: js LBB6_15
; AVX2-NEXT: LBB6_16: ## %else20
; AVX2-NEXT: testl $256, %eax ## imm = 0x100
; AVX2-NEXT: jne LBB6_17
Expand All @@ -2220,8 +2220,8 @@ define void @compressstore_v32f32_v32i32(ptr %base, <32 x float> %V, <32 x i32>
; AVX2-NEXT: testl $16384, %eax ## imm = 0x4000
; AVX2-NEXT: jne LBB6_29
; AVX2-NEXT: LBB6_30: ## %else41
; AVX2-NEXT: testl $32768, %eax ## imm = 0x8000
; AVX2-NEXT: jne LBB6_31
; AVX2-NEXT: testw %ax, %ax
; AVX2-NEXT: js LBB6_31
; AVX2-NEXT: LBB6_32: ## %else44
; AVX2-NEXT: testl $65536, %eax ## imm = 0x10000
; AVX2-NEXT: jne LBB6_33
Expand Down Expand Up @@ -2310,8 +2310,8 @@ define void @compressstore_v32f32_v32i32(ptr %base, <32 x float> %V, <32 x i32>
; AVX2-NEXT: LBB6_13: ## %cond.store16
; AVX2-NEXT: vextractps $2, %xmm0, (%rdi)
; AVX2-NEXT: addq $4, %rdi
; AVX2-NEXT: testb $-128, %al
; AVX2-NEXT: je LBB6_16
; AVX2-NEXT: testb %al, %al
; AVX2-NEXT: jns LBB6_16
; AVX2-NEXT: LBB6_15: ## %cond.store19
; AVX2-NEXT: vextractps $3, %xmm0, (%rdi)
; AVX2-NEXT: addq $4, %rdi
Expand Down Expand Up @@ -2346,8 +2346,8 @@ define void @compressstore_v32f32_v32i32(ptr %base, <32 x float> %V, <32 x i32>
; AVX2-NEXT: LBB6_29: ## %cond.store40
; AVX2-NEXT: vextractps $2, %xmm0, (%rdi)
; AVX2-NEXT: addq $4, %rdi
; AVX2-NEXT: testl $32768, %eax ## imm = 0x8000
; AVX2-NEXT: je LBB6_32
; AVX2-NEXT: testw %ax, %ax
; AVX2-NEXT: jns LBB6_32
; AVX2-NEXT: LBB6_31: ## %cond.store43
; AVX2-NEXT: vextractps $3, %xmm0, (%rdi)
; AVX2-NEXT: addq $4, %rdi
Expand Down Expand Up @@ -3659,8 +3659,8 @@ define void @compressstore_v16i8_v16i8(ptr %base, <16 x i8> %V, <16 x i8> %trigg
; SSE2-NEXT: movb %cl, (%rdi)
; SSE2-NEXT: incq %rdi
; SSE2-NEXT: LBB12_14: ## %else17
; SSE2-NEXT: testb $-128, %al
; SSE2-NEXT: je LBB12_16
; SSE2-NEXT: testb %al, %al
; SSE2-NEXT: jns LBB12_16
; SSE2-NEXT: ## %bb.15: ## %cond.store19
; SSE2-NEXT: movb %ch, (%rdi)
; SSE2-NEXT: incq %rdi
Expand Down Expand Up @@ -3765,8 +3765,8 @@ define void @compressstore_v16i8_v16i8(ptr %base, <16 x i8> %V, <16 x i8> %trigg
; SSE42-NEXT: testb $64, %al
; SSE42-NEXT: jne LBB12_13
; SSE42-NEXT: LBB12_14: ## %else17
; SSE42-NEXT: testb $-128, %al
; SSE42-NEXT: jne LBB12_15
; SSE42-NEXT: testb %al, %al
; SSE42-NEXT: js LBB12_15
; SSE42-NEXT: LBB12_16: ## %else20
; SSE42-NEXT: testl $256, %eax ## imm = 0x100
; SSE42-NEXT: jne LBB12_17
Expand Down Expand Up @@ -3826,8 +3826,8 @@ define void @compressstore_v16i8_v16i8(ptr %base, <16 x i8> %V, <16 x i8> %trigg
; SSE42-NEXT: LBB12_13: ## %cond.store16
; SSE42-NEXT: pextrb $6, %xmm0, (%rdi)
; SSE42-NEXT: incq %rdi
; SSE42-NEXT: testb $-128, %al
; SSE42-NEXT: je LBB12_16
; SSE42-NEXT: testb %al, %al
; SSE42-NEXT: jns LBB12_16
; SSE42-NEXT: LBB12_15: ## %cond.store19
; SSE42-NEXT: pextrb $7, %xmm0, (%rdi)
; SSE42-NEXT: incq %rdi
Expand Down Expand Up @@ -3898,8 +3898,8 @@ define void @compressstore_v16i8_v16i8(ptr %base, <16 x i8> %V, <16 x i8> %trigg
; AVX1OR2-NEXT: testb $64, %al
; AVX1OR2-NEXT: jne LBB12_13
; AVX1OR2-NEXT: LBB12_14: ## %else17
; AVX1OR2-NEXT: testb $-128, %al
; AVX1OR2-NEXT: jne LBB12_15
; AVX1OR2-NEXT: testb %al, %al
; AVX1OR2-NEXT: js LBB12_15
; AVX1OR2-NEXT: LBB12_16: ## %else20
; AVX1OR2-NEXT: testl $256, %eax ## imm = 0x100
; AVX1OR2-NEXT: jne LBB12_17
Expand Down Expand Up @@ -3959,8 +3959,8 @@ define void @compressstore_v16i8_v16i8(ptr %base, <16 x i8> %V, <16 x i8> %trigg
; AVX1OR2-NEXT: LBB12_13: ## %cond.store16
; AVX1OR2-NEXT: vpextrb $6, %xmm0, (%rdi)
; AVX1OR2-NEXT: incq %rdi
; AVX1OR2-NEXT: testb $-128, %al
; AVX1OR2-NEXT: je LBB12_16
; AVX1OR2-NEXT: testb %al, %al
; AVX1OR2-NEXT: jns LBB12_16
; AVX1OR2-NEXT: LBB12_15: ## %cond.store19
; AVX1OR2-NEXT: vpextrb $7, %xmm0, (%rdi)
; AVX1OR2-NEXT: incq %rdi
Expand Down Expand Up @@ -4031,8 +4031,8 @@ define void @compressstore_v16i8_v16i8(ptr %base, <16 x i8> %V, <16 x i8> %trigg
; AVX512F-NEXT: testb $64, %al
; AVX512F-NEXT: jne LBB12_13
; AVX512F-NEXT: LBB12_14: ## %else17
; AVX512F-NEXT: testb $-128, %al
; AVX512F-NEXT: jne LBB12_15
; AVX512F-NEXT: testb %al, %al
; AVX512F-NEXT: js LBB12_15
; AVX512F-NEXT: LBB12_16: ## %else20
; AVX512F-NEXT: testl $256, %eax ## imm = 0x100
; AVX512F-NEXT: jne LBB12_17
Expand Down Expand Up @@ -4092,8 +4092,8 @@ define void @compressstore_v16i8_v16i8(ptr %base, <16 x i8> %V, <16 x i8> %trigg
; AVX512F-NEXT: LBB12_13: ## %cond.store16
; AVX512F-NEXT: vpextrb $6, %xmm0, (%rdi)
; AVX512F-NEXT: incq %rdi
; AVX512F-NEXT: testb $-128, %al
; AVX512F-NEXT: je LBB12_16
; AVX512F-NEXT: testb %al, %al
; AVX512F-NEXT: jns LBB12_16
; AVX512F-NEXT: LBB12_15: ## %cond.store19
; AVX512F-NEXT: vpextrb $7, %xmm0, (%rdi)
; AVX512F-NEXT: incq %rdi
Expand Down Expand Up @@ -4164,8 +4164,8 @@ define void @compressstore_v16i8_v16i8(ptr %base, <16 x i8> %V, <16 x i8> %trigg
; AVX512VLDQ-NEXT: testb $64, %al
; AVX512VLDQ-NEXT: jne LBB12_13
; AVX512VLDQ-NEXT: LBB12_14: ## %else17
; AVX512VLDQ-NEXT: testb $-128, %al
; AVX512VLDQ-NEXT: jne LBB12_15
; AVX512VLDQ-NEXT: testb %al, %al
; AVX512VLDQ-NEXT: js LBB12_15
; AVX512VLDQ-NEXT: LBB12_16: ## %else20
; AVX512VLDQ-NEXT: testl $256, %eax ## imm = 0x100
; AVX512VLDQ-NEXT: jne LBB12_17
Expand Down Expand Up @@ -4225,8 +4225,8 @@ define void @compressstore_v16i8_v16i8(ptr %base, <16 x i8> %V, <16 x i8> %trigg
; AVX512VLDQ-NEXT: LBB12_13: ## %cond.store16
; AVX512VLDQ-NEXT: vpextrb $6, %xmm0, (%rdi)
; AVX512VLDQ-NEXT: incq %rdi
; AVX512VLDQ-NEXT: testb $-128, %al
; AVX512VLDQ-NEXT: je LBB12_16
; AVX512VLDQ-NEXT: testb %al, %al
; AVX512VLDQ-NEXT: jns LBB12_16
; AVX512VLDQ-NEXT: LBB12_15: ## %cond.store19
; AVX512VLDQ-NEXT: vpextrb $7, %xmm0, (%rdi)
; AVX512VLDQ-NEXT: incq %rdi
Expand Down Expand Up @@ -4296,8 +4296,8 @@ define void @compressstore_v16i8_v16i8(ptr %base, <16 x i8> %V, <16 x i8> %trigg
; AVX512VLBW-NEXT: testb $64, %al
; AVX512VLBW-NEXT: jne LBB12_13
; AVX512VLBW-NEXT: LBB12_14: ## %else17
; AVX512VLBW-NEXT: testb $-128, %al
; AVX512VLBW-NEXT: jne LBB12_15
; AVX512VLBW-NEXT: testb %al, %al
; AVX512VLBW-NEXT: js LBB12_15
; AVX512VLBW-NEXT: LBB12_16: ## %else20
; AVX512VLBW-NEXT: testl $256, %eax ## imm = 0x100
; AVX512VLBW-NEXT: jne LBB12_17
Expand Down Expand Up @@ -4357,8 +4357,8 @@ define void @compressstore_v16i8_v16i8(ptr %base, <16 x i8> %V, <16 x i8> %trigg
; AVX512VLBW-NEXT: LBB12_13: ## %cond.store16
; AVX512VLBW-NEXT: vpextrb $6, %xmm0, (%rdi)
; AVX512VLBW-NEXT: incq %rdi
; AVX512VLBW-NEXT: testb $-128, %al
; AVX512VLBW-NEXT: je LBB12_16
; AVX512VLBW-NEXT: testb %al, %al
; AVX512VLBW-NEXT: jns LBB12_16
; AVX512VLBW-NEXT: LBB12_15: ## %cond.store19
; AVX512VLBW-NEXT: vpextrb $7, %xmm0, (%rdi)
; AVX512VLBW-NEXT: incq %rdi
Expand Down
136 changes: 68 additions & 68 deletions llvm/test/CodeGen/X86/masked_expandload.ll
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16 changes: 8 additions & 8 deletions llvm/test/CodeGen/X86/masked_gather.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -650,8 +650,8 @@ define <16 x i8> @gather_v16i8_v16i32_v16i8(ptr %base, <16 x i32> %idx, <16 x i8
; SSE-NEXT: pinsrb $6, (%rcx), %xmm5
; SSE-NEXT: .LBB3_14: # %else17
; SSE-NEXT: pmovsxdq %xmm2, %xmm0
; SSE-NEXT: testb $-128, %al
; SSE-NEXT: je .LBB3_16
; SSE-NEXT: testb %al, %al
; SSE-NEXT: jns .LBB3_16
; SSE-NEXT: # %bb.15: # %cond.load19
; SSE-NEXT: pextrq $1, %xmm1, %rcx
; SSE-NEXT: pinsrb $7, (%rcx), %xmm5
Expand Down Expand Up @@ -789,8 +789,8 @@ define <16 x i8> @gather_v16i8_v16i32_v16i8(ptr %base, <16 x i32> %idx, <16 x i8
; AVX1-NEXT: vpinsrb $6, (%rcx), %xmm3, %xmm3
; AVX1-NEXT: .LBB3_14: # %else17
; AVX1-NEXT: vpaddq %xmm5, %xmm4, %xmm5
; AVX1-NEXT: testb $-128, %al
; AVX1-NEXT: je .LBB3_16
; AVX1-NEXT: testb %al, %al
; AVX1-NEXT: jns .LBB3_16
; AVX1-NEXT: # %bb.15: # %cond.load19
; AVX1-NEXT: vpextrq $1, %xmm0, %rcx
; AVX1-NEXT: vpinsrb $7, (%rcx), %xmm3, %xmm3
Expand Down Expand Up @@ -919,8 +919,8 @@ define <16 x i8> @gather_v16i8_v16i32_v16i8(ptr %base, <16 x i32> %idx, <16 x i8
; AVX2-NEXT: vpinsrb $6, (%rcx), %xmm3, %xmm3
; AVX2-NEXT: .LBB3_14: # %else17
; AVX2-NEXT: vpmovsxdq %xmm1, %ymm2
; AVX2-NEXT: testb $-128, %al
; AVX2-NEXT: je .LBB3_16
; AVX2-NEXT: testb %al, %al
; AVX2-NEXT: jns .LBB3_16
; AVX2-NEXT: # %bb.15: # %cond.load19
; AVX2-NEXT: vpextrq $1, %xmm0, %rcx
; AVX2-NEXT: vpinsrb $7, (%rcx), %xmm3, %xmm3
Expand Down Expand Up @@ -1034,8 +1034,8 @@ define <16 x i8> @gather_v16i8_v16i32_v16i8(ptr %base, <16 x i32> %idx, <16 x i8
; AVX512-NEXT: vpinsrb $6, (%rcx), %xmm2, %xmm2
; AVX512-NEXT: .LBB3_14: # %else17
; AVX512-NEXT: vpmovsxdq %ymm1, %zmm1
; AVX512-NEXT: testb $-128, %al
; AVX512-NEXT: je .LBB3_16
; AVX512-NEXT: testb %al, %al
; AVX512-NEXT: jns .LBB3_16
; AVX512-NEXT: # %bb.15: # %cond.load19
; AVX512-NEXT: vpextrq $1, %xmm0, %rcx
; AVX512-NEXT: vpinsrb $7, (%rcx), %xmm2, %xmm2
Expand Down
176 changes: 88 additions & 88 deletions llvm/test/CodeGen/X86/masked_load.ll
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220 changes: 110 additions & 110 deletions llvm/test/CodeGen/X86/masked_store.ll
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172 changes: 86 additions & 86 deletions llvm/test/CodeGen/X86/masked_store_trunc.ll
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184 changes: 92 additions & 92 deletions llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll
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172 changes: 86 additions & 86 deletions llvm/test/CodeGen/X86/masked_store_trunc_usat.ll
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8 changes: 4 additions & 4 deletions llvm/test/CodeGen/X86/omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -16,8 +16,8 @@
define i1 @p0_scalar_urem_by_const(i32 %x, i32 %y) {
; CHECK-LABEL: p0_scalar_urem_by_const:
; CHECK: # %bb.0:
; CHECK-NEXT: testb $-128, %dil
; CHECK-NEXT: sete %al
; CHECK-NEXT: testb %dil, %dil
; CHECK-NEXT: setns %al
; CHECK-NEXT: retq
%t0 = and i32 %x, 128 ; clearly a power-of-two or zero
%t1 = urem i32 %t0, 6 ; '6' is clearly not a power of two
Expand All @@ -28,8 +28,8 @@ define i1 @p0_scalar_urem_by_const(i32 %x, i32 %y) {
define i1 @p1_scalar_urem_by_nonconst(i32 %x, i32 %y) {
; CHECK-LABEL: p1_scalar_urem_by_nonconst:
; CHECK: # %bb.0:
; CHECK-NEXT: testb $-128, %dil
; CHECK-NEXT: sete %al
; CHECK-NEXT: testb %dil, %dil
; CHECK-NEXT: setns %al
; CHECK-NEXT: retq
%t0 = and i32 %x, 128 ; clearly a power-of-two or zero
%t1 = or i32 %y, 6 ; two bits set, clearly not a power of two
Expand Down
278 changes: 278 additions & 0 deletions llvm/test/CodeGen/X86/signbit-test.ll
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Original file line number Diff line number Diff line change
@@ -0,0 +1,278 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s

define i64 @test_clear_mask_i64_i32(i64 %x) nounwind {
; CHECK-LABEL: test_clear_mask_i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: js .LBB0_2
; CHECK-NEXT: # %bb.1: # %t
; CHECK-NEXT: movl $42, %eax
; CHECK-NEXT: .LBB0_2: # %f
; CHECK-NEXT: retq
entry:
%a = and i64 %x, 2147483648
%r = icmp eq i64 %a, 0
br i1 %r, label %t, label %f
t:
br label %f
f:
%ret = phi i64 [ %x, %entry], [ 42, %t]
ret i64 %ret
}

define i64 @test_set_mask_i64_i32(i64 %x) nounwind {
; CHECK-LABEL: test_set_mask_i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: jns .LBB1_2
; CHECK-NEXT: # %bb.1: # %t
; CHECK-NEXT: movl $42, %eax
; CHECK-NEXT: .LBB1_2: # %f
; CHECK-NEXT: retq
entry:
%a = and i64 %x, 2147483648
%r = icmp ne i64 %a, 0
br i1 %r, label %t, label %f
t:
br label %f
f:
%ret = phi i64 [ %x, %entry], [ 42, %t]
ret i64 %ret
}

define i64 @test_clear_mask_i64_i16(i64 %x) nounwind {
; CHECK-LABEL: test_clear_mask_i64_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: testw %ax, %ax
; CHECK-NEXT: js .LBB2_2
; CHECK-NEXT: # %bb.1: # %t
; CHECK-NEXT: movl $42, %eax
; CHECK-NEXT: .LBB2_2: # %f
; CHECK-NEXT: retq
entry:
%a = and i64 %x, 32768
%r = icmp eq i64 %a, 0
br i1 %r, label %t, label %f
t:
br label %f
f:
%ret = phi i64 [ %x, %entry], [ 42, %t]
ret i64 %ret
}

define i64 @test_set_mask_i64_i16(i64 %x) nounwind {
; CHECK-LABEL: test_set_mask_i64_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: testw %ax, %ax
; CHECK-NEXT: jns .LBB3_2
; CHECK-NEXT: # %bb.1: # %t
; CHECK-NEXT: movl $42, %eax
; CHECK-NEXT: .LBB3_2: # %f
; CHECK-NEXT: retq
entry:
%a = and i64 %x, 32768
%r = icmp ne i64 %a, 0
br i1 %r, label %t, label %f
t:
br label %f
f:
%ret = phi i64 [ %x, %entry], [ 42, %t]
ret i64 %ret
}

define i64 @test_clear_mask_i64_i8(i64 %x) nounwind {
; CHECK-LABEL: test_clear_mask_i64_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: js .LBB4_2
; CHECK-NEXT: # %bb.1: # %t
; CHECK-NEXT: movl $42, %eax
; CHECK-NEXT: .LBB4_2: # %f
; CHECK-NEXT: retq
entry:
%a = and i64 %x, 128
%r = icmp eq i64 %a, 0
br i1 %r, label %t, label %f
t:
br label %f
f:
%ret = phi i64 [ %x, %entry], [ 42, %t]
ret i64 %ret
}

define i64 @test_set_mask_i64_i8(i64 %x) nounwind {
; CHECK-LABEL: test_set_mask_i64_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jns .LBB5_2
; CHECK-NEXT: # %bb.1: # %t
; CHECK-NEXT: movl $42, %eax
; CHECK-NEXT: .LBB5_2: # %f
; CHECK-NEXT: retq
entry:
%a = and i64 %x, 128
%r = icmp ne i64 %a, 0
br i1 %r, label %t, label %f
t:
br label %f
f:
%ret = phi i64 [ %x, %entry], [ 42, %t]
ret i64 %ret
}

define i32 @test_clear_mask_i32_i16(i32 %x) nounwind {
; CHECK-LABEL: test_clear_mask_i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: testw %ax, %ax
; CHECK-NEXT: js .LBB6_2
; CHECK-NEXT: # %bb.1: # %t
; CHECK-NEXT: movl $42, %eax
; CHECK-NEXT: .LBB6_2: # %f
; CHECK-NEXT: retq
entry:
%a = and i32 %x, 32768
%r = icmp eq i32 %a, 0
br i1 %r, label %t, label %f
t:
br label %f
f:
%ret = phi i32 [ %x, %entry], [ 42, %t]
ret i32 %ret
}

define i32 @test_set_mask_i32_i16(i32 %x) nounwind {
; CHECK-LABEL: test_set_mask_i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: testw %ax, %ax
; CHECK-NEXT: jns .LBB7_2
; CHECK-NEXT: # %bb.1: # %t
; CHECK-NEXT: movl $42, %eax
; CHECK-NEXT: .LBB7_2: # %f
; CHECK-NEXT: retq
entry:
%a = and i32 %x, 32768
%r = icmp ne i32 %a, 0
br i1 %r, label %t, label %f
t:
br label %f
f:
%ret = phi i32 [ %x, %entry], [ 42, %t]
ret i32 %ret
}

define i32 @test_clear_mask_i32_i8(i32 %x) nounwind {
; CHECK-LABEL: test_clear_mask_i32_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: js .LBB8_2
; CHECK-NEXT: # %bb.1: # %t
; CHECK-NEXT: movl $42, %eax
; CHECK-NEXT: .LBB8_2: # %f
; CHECK-NEXT: retq
entry:
%a = and i32 %x, 128
%r = icmp eq i32 %a, 0
br i1 %r, label %t, label %f
t:
br label %f
f:
%ret = phi i32 [ %x, %entry], [ 42, %t]
ret i32 %ret
}

define i32 @test_set_mask_i32_i8(i32 %x) nounwind {
; CHECK-LABEL: test_set_mask_i32_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jns .LBB9_2
; CHECK-NEXT: # %bb.1: # %t
; CHECK-NEXT: movl $42, %eax
; CHECK-NEXT: .LBB9_2: # %f
; CHECK-NEXT: retq
entry:
%a = and i32 %x, 128
%r = icmp ne i32 %a, 0
br i1 %r, label %t, label %f
t:
br label %f
f:
%ret = phi i32 [ %x, %entry], [ 42, %t]
ret i32 %ret
}

define i16 @test_clear_mask_i16_i8(i16 %x) nounwind {
; CHECK-LABEL: test_clear_mask_i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: js .LBB10_2
; CHECK-NEXT: # %bb.1: # %t
; CHECK-NEXT: movw $42, %ax
; CHECK-NEXT: .LBB10_2: # %f
; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
; CHECK-NEXT: retq
entry:
%a = and i16 %x, 128
%r = icmp eq i16 %a, 0
br i1 %r, label %t, label %f
t:
br label %f
f:
%ret = phi i16 [ %x, %entry], [ 42, %t]
ret i16 %ret
}

define i16 @test_set_mask_i16_i8(i16 %x) nounwind {
; CHECK-LABEL: test_set_mask_i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jns .LBB11_2
; CHECK-NEXT: # %bb.1: # %t
; CHECK-NEXT: movw $42, %ax
; CHECK-NEXT: .LBB11_2: # %f
; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
; CHECK-NEXT: retq
entry:
%a = and i16 %x, 128
%r = icmp ne i16 %a, 0
br i1 %r, label %t, label %f
t:
br label %f
f:
%ret = phi i16 [ %x, %entry], [ 42, %t]
ret i16 %ret
}

define i16 @test_set_mask_i16_i7(i16 %x) nounwind {
; CHECK-LABEL: test_set_mask_i16_i7:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: testb $64, %al
; CHECK-NEXT: je .LBB12_2
; CHECK-NEXT: # %bb.1: # %t
; CHECK-NEXT: movw $42, %ax
; CHECK-NEXT: .LBB12_2: # %f
; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
; CHECK-NEXT: retq
entry:
%a = and i16 %x, 64
%r = icmp ne i16 %a, 0
br i1 %r, label %t, label %f
t:
br label %f
f:
%ret = phi i16 [ %x, %entry], [ 42, %t]
ret i16 %ret
}
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/X86/test-vs-bittest.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -640,8 +640,8 @@ define i16 @is_bit_clear_i16(i16 %x) {
; CHECK-LABEL: is_bit_clear_i16:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb $-128, %dil
; CHECK-NEXT: sete %al
; CHECK-NEXT: testb %dil, %dil
; CHECK-NEXT: setns %al
; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
; CHECK-NEXT: retq
%sh = lshr i16 %x, 7
Expand Down