diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFP.td b/llvm/lib/Target/SystemZ/SystemZInstrFP.td
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -255,7 +255,7 @@ let isCall = 1, Defs = [CC] in {
 }
 
 // Regular calls.
-let isCall = 1, Defs = [R14D, CC] in {
+let isCall = 1, Defs = [R14D, CC], Uses = [FPC] in {
   def CallBRASL : Alias<6, (outs), (ins pcrel32:$I2, variable_ops),
                         [(z_call pcrel32:$I2)]>;
   def CallBASR  : Alias<2, (outs), (ins ADDR64:$R2, variable_ops),

diff --git a/llvm/lib/Target/SystemZ/SystemZInstrVector.td b/llvm/lib/Target/SystemZ/SystemZInstrVector.td
diff --git a/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp b/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp
@@ -191,6 +191,9 @@ SystemZRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   Reserved.set(SystemZ::A0);
   Reserved.set(SystemZ::A1);
 
+  // FPC is the floating-point control register.
+  Reserved.set(SystemZ::FPC);
+
   return Reserved;
 }
 

diff --git a/llvm/lib/Target/SystemZ/SystemZRegisterInfo.td b/llvm/lib/Target/SystemZ/SystemZRegisterInfo.td
@@ -295,6 +295,13 @@ def CC : SystemZReg<"cc">;
 let isAllocatable = 0, CopyCost = -1 in
   def CCR : RegisterClass<"SystemZ", [i32], 32, (add CC)>;
 
+// The floating-point control register.
+// Note: We only model the current rounding modes and the IEEE masks.
+// IEEE flags and DXC are not modeled here.
+def FPC : SystemZReg<"fpc">;
+let isAllocatable = 0 in
+  def FPCRegs : RegisterClass<"SystemZ", [i32], 32, (add FPC)>;
+
 // Access registers.
 class ACR32<bits<16> num, string n> : SystemZReg<n> {
   let HWEncoding = num;

diff --git a/llvm/test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir b/llvm/test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir
@@ -181,11 +181,11 @@ body:             |
     J %bb.3
   
   bb.3:
-    WFCDB undef %46, %45, implicit-def $cc
+    WFCDB undef %46, %45, implicit-def $cc, implicit $fpc
     %48 = IPM implicit killed $cc
     %48 = AFIMux %48, 268435456, implicit-def dead $cc
     %6 = RISBMux undef %6, %48, 31, 159, 35
-    WFCDB undef %50, %45, implicit-def $cc
+    WFCDB undef %50, %45, implicit-def $cc, implicit $fpc
     BRC 15, 6, %bb.1, implicit killed $cc
     J %bb.4
   

diff --git a/llvm/test/CodeGen/SystemZ/clear-liverange-spillreg.mir b/llvm/test/CodeGen/SystemZ/clear-liverange-spillreg.mir
@@ -401,7 +401,7 @@ body:             |
     BRC 14, 6, %bb.29, implicit killed $cc
   
   bb.28:
-    %130 = CDFBR %60
+    %130 = CDFBR %60, implicit $fpc
     J %bb.30
   
   bb.29:

diff --git a/llvm/test/CodeGen/SystemZ/cond-move-regalloc-hints.mir b/llvm/test/CodeGen/SystemZ/cond-move-regalloc-hints.mir
@@ -237,7 +237,7 @@ body:             |
   
     %47:fp32bit = VL32 %64, 4, $noreg :: (load 4 from %ir.scevgep5)
     %25:gr64bit = LA %64, 4, $noreg
-    CEBR %47, undef %48:fp32bit, implicit-def $cc
+    CEBR %47, undef %48:fp32bit, implicit-def $cc, implicit $fpc
     %62:grx32bit = LOCRMux %62, %65, 15, 4, implicit $cc
     %61:grx32bit = LOCRMux %61, %10.subreg_l32, 15, 4, implicit killed $cc
     %65:grx32bit = AHIMux %65, 1, implicit-def dead $cc

diff --git a/llvm/test/CodeGen/SystemZ/debuginstr-02.mir b/llvm/test/CodeGen/SystemZ/debuginstr-02.mir
@@ -85,8 +85,8 @@ body:             |
     %6:fp32bit = SelectVR32 %3, %4, 15, 7, implicit $cc
     DBG_VALUE %6, $noreg, !7, !DIExpression(), debug-location !9
     %7:fp32bit = SelectVR32 %1, %4, 15, 7, implicit $cc
-    %8:fp32bit = AEBR %5, killed %6, implicit-def dead $cc
-    %9:fp32bit = AEBR %8, killed %7, implicit-def dead $cc
+    %8:fp32bit = AEBR %5, killed %6, implicit-def dead $cc, implicit $fpc
+    %9:fp32bit = AEBR %8, killed %7, implicit-def dead $cc, implicit $fpc
     $f0s = COPY %9
     Return implicit $f0s
 

diff --git a/llvm/test/CodeGen/SystemZ/fp-cmp-07.mir b/llvm/test/CodeGen/SystemZ/fp-cmp-07.mir
@@ -30,7 +30,7 @@ body:             |
   bb.0.entry:
     liveins: $f0s, $r2d
 
-    LTEBRCompare $f0s, $f0s, implicit-def $cc
+    LTEBRCompare $f0s, $f0s, implicit-def $cc, implicit $fpc
     $f2s = LER $f0s
     INLINEASM &"blah $0", 1, 9, $f2s
     CondReturn 15, 4, implicit $f0s, implicit $cc

diff --git a/llvm/test/CodeGen/SystemZ/fp-conv-17.mir b/llvm/test/CodeGen/SystemZ/fp-conv-17.mir
@@ -163,39 +163,39 @@ body:             |
     STE %16, %1, 0, $noreg :: (volatile store 4 into %ir.ptr2)
     STE %17, %1, 0, $noreg :: (volatile store 4 into %ir.ptr2)
     STE %18, %1, 0, $noreg :: (volatile store 4 into %ir.ptr2)
-    %19 = LDEBR %2
+    %19 = LDEBR %2, implicit $fpc
     STD %19, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
-    %20 = LDEBR %3
+    %20 = LDEBR %3, implicit $fpc
     STD %20, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
-    %21 = LDEBR %4
+    %21 = LDEBR %4, implicit $fpc
     STD %21, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
-    %22 = LDEBR %5
+    %22 = LDEBR %5, implicit $fpc
     STD %22, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
-    %23 = LDEBR %6
+    %23 = LDEBR %6, implicit $fpc
     STD %23, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
-    %24 = LDEBR %7
+    %24 = LDEBR %7, implicit $fpc
     STD %24, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
-    %25 = LDEBR %8
+    %25 = LDEBR %8, implicit $fpc
     STD %25, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
-    %26 = LDEBR %9
+    %26 = LDEBR %9, implicit $fpc
     STD %26, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
-    %27 = LDEBR %10
+    %27 = LDEBR %10, implicit $fpc
     STD %27, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
-    %28 = LDEBR %11
+    %28 = LDEBR %11, implicit $fpc
     STD %28, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
-    %29 = LDEBR %12
+    %29 = LDEBR %12, implicit $fpc
     STD %29, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
-    %30 = LDEBR %13
+    %30 = LDEBR %13, implicit $fpc
     STD %30, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
-    %31 = LDEBR %14
+    %31 = LDEBR %14, implicit $fpc
     STD %31, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
-    %32 = LDEBR %15
+    %32 = LDEBR %15, implicit $fpc
     STD %32, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
-    %33 = LDEBR %16
+    %33 = LDEBR %16, implicit $fpc
     STD %33, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
-    %34 = LDEBR %17
+    %34 = LDEBR %17, implicit $fpc
     STD %34, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
-    %35 = LDEBR %18
+    %35 = LDEBR %18, implicit $fpc
     STD %35, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
     Return